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5 4 3 2 1
Page Index
Pixie
01-COVER PAGE
02-BLOCK DIAGRAM
D
03-BLOCK DISTRIBUTION D
04-CPU M2-1 HyperTransport
MCP61PM-AM
05-CPU M2-1 DDR2
06-CPU M2-3 Miscellany
07-CPU M2-4 Power and Ground
08-DDR2 DIMM
09-DDR2 DIMM
10-DDR2 Termination
ET82 REV:A 11-MCP61 HT
PCB:15-V01-010010 12-MCP61 PCI-E X16
BOM:81-685-V01000 13-MCP61 PCI-E X1/RGMII/DAC
14-MCP61 PCI
C
REV:B 15-MCP61 SATA/IDE
C
PCB:15-V01-010020 16-MCP61 AUDIO/USB/MISC
BOM:81-685-V01010 MCP61-S 17-MCP61 PWR/GND
BOM:81-685-V01020 MCP61-P 18-MCP61 DECOUPLING/SPI
19-VGA
REV:1.0 20-1394(TI 23A)
PCB:15-V01-011000 21-LAN 88E8056
BOM:81-685-V01100 MCP61-S 22-PCI-E X16 CONN
BOM:81-685-V01101 MCP61-P 23-PCI1/PCI2
BOM:81-685-V01102 MCP61-S W/O 1394 24-PCI-E X1/TPM
B REV:1.0A 25-LPC SIO-ITE8726/FDD B
26-PS2/COM/LPT
PCB:15-V01-011010 27-USB
28-AUDIO ALC888/883
29-AUDIO ALC888/883(PANEL)
30-PWR CON/FNT PNL
31-CPU VCORE
32-DC-DC
Signature Date 33-ATTENTION
Designer Jeff Lee
A
Layout Elitegroup Computer Systems
A
Check Title
COVER PAGE
Approval Size
B
Date:
Document Number
MCP61PM-AM
Tuesday, October 03, 2006 Sheet 1 of 33
Rev
1.0A
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
POWER
D D
SUPPLY VREG
CONNECTOR
128-BIT 400/533/667/800MHZ
AM2 SOCKET 940 DDRII SDRAM CONN 0
THERM MONITOR
DDRII SDRAM CONN 1
HT 16X16 1GHZ
PCI EXPRESS
PEX X16
PCI EXPRESS
PEX X1
C PCI 33MHZ C
PCI EXPRESS PCI SLOT 1
PEX X1
NFORCE
MCP61 PCI SLOT 2
692 BGA
HDA
7.1 AUDIO
ATA 133
PRIMARY IDE
X10 USB2
INTEGRATED SATA CONTROLLERS (X2) BACK PANEL CONN
X4 - SATA CONN
USB2 PORTS 0-1
X2/GBIT LAN
B USB2 PORTS / 1394 conn 2-3 B
FLOPPY CONN FRONT PANEL HDR
PS2/KBRD CONN USB2 PORTS 4-5
SIO LPC BUS 33MHZ
PARALLEL CONN USB2 PORTS 6-7
ITE8726
BUF SIO CLK 24MHZ
USB2 PORTS 8-9
LPC HDR
SERIAL CONN
MII/RGMII MII/RGMII
4MB FLASH
A AC131 / RTL8110SC / RTL8211B A
Elitegroup Computer Systems
TPM
Title
BLOCK DIAGRAM
Size Document Number Rev
B
MCP61PM-AM 1.0A
Date: Tuesday, October 03, 2006 Sheet 2 of 33
5 4 3 2 1
5 4 3 2 1
M2 SOCKET 940
CHANNEL A0 0-63
HT_CPU_TXCLK0 MEMORY_A0_CLK[2:0] DIMM 0
D
HT_CPU_TXCLK0* MEMORY_A0_CLK[2:0]* D
HT_CPU_RXCLK0
HT_CPU_RXCLK0* MEMORY_B0_CLK[2:0]
MEMORY_B0_CLK[2:0]*
HT_CPU_TXCLK1
HT_CPU_TXCLK1* DIMM 1
HT_CPU_RXCLK1
HT_CPU_RXCLK1* CHANNEL B0 64-127
MEMORY_A1_CLK[2:0]
MEMORY_A1_CLK[2:0]*
CPUCLK_IN* MEMORY_B1_CLK[2:0]
CPUCLK_IN MEMORY_B1_CLK[2:0]*
CLKOUT_200MHZ PE0_REFCLK
C
CLKOUT_200MHZ* PE0_REFCLK* PE0 X16 C
HT_CPU_RXCLK1*
HT_CPU_RXCLK1 PE1_REFCLK
HT_CPU_TXCLK1* PE1_REFCLK* PE1 X1
HT_CPU_TXCLK1
HT_CPU_RXCLK0*
HT_CPU_RXCLK0
HT_CPU_TXCLK0*
HT_CPU_TXCLK0
14MHZ OR 24MHZ*
BUF_SIO
MCP61 SIO
LPC_CLK0
PCI_CLK0 PCI SLOT 1
B PCI_CLK1 B
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN PCI SLOT 2
LPC_CLK1
TPM
HDA_BITCLK HDA FLASH LPC
CODEC HEADER
RTC_XTAL
32.0 KHZ
XTAL_IN RGMII_TXCLK LAN
PHY
A RGMII_RXCLK A
25 MHZ
XTAL_OUT Elitegroup Computer Systems
BUF_25MHZ
Title
CLOCK DISTRIBUTION
Size Document Number Rev
B
MCP61PM-AM 1.0A
Date: Tuesday, October 03, 2006 Sheet 3 of 33
5 4 3 2 1
8 7 6 5 4 3 2 1
U9A
HYPERTRANSPORT
L0_CLKIN_H1 N6 AD5 L0_CLKOUT_H1
L0_CLKIN_H(1) L0_CLKOUT_H(1) L0_CLKOUT_H1 11
L0_CLKIN_L1 P6 AD4 L0_CLKOUT_L1
L0_CLKIN_L(1) L0_CLKOUT_L(1) L0_CLKOUT_L1 11
VLDT_B L0_CLKIN_H0 N3 AD1 L0_CLKOUT_H0
L0_CLKIN_H(0) L0_CLKOUT_H(0) L0_CLKOUT_H0 11
L0_CLKIN_L0 N2 AC1 L0_CLKOUT_L0
L0_CLKIN_L(0) L0_CLKOUT_L(0) L0_CLKOUT_L0 11
R182 51-04 L0_CTLIN_H1 V4 Y6 L0_CTLOUT_H1
D R176 51-04 L0_CTLIN_L1 V5
L0_CTLIN_H(1) L0_CTLOUT_H(1)
W6 L0_CTLOUT_L1
STP2
STP1
U9E D
L0_CTLIN_H0 L0_CTLIN_L(1) L0_CTLOUT_L(1) L0_CTLOUT_H0
U1 L0_CTLIN_H(0) L0_CTLOUT_H(0) W2 L0_CTLOUT_H0 11 INTERNAL MISC E
L0_CTLIN_L0 V1 W3 L0_CTLOUT_L0 L25 E20
L0_CTLIN_L(0) L0_CTLOUT_L(0) L0_CTLOUT_L0 11 RSVD1 RSVD17
L26 RSVD2 RSVD18 B19
L0_CADIN_H15 U6 Y5 L0_CADOUT_H15 L31
L0_CADIN_L15 L0_CADIN_H(15) L0_CADOUT_H(15) L0_CADOUT_L15 RSVD3
V6 L0_CADIN_L(15) L0_CADOUT_L(15) Y4 L30 RSVD4 RSVD19 AL4
L0_CADIN_H14 T4 AB6 L0_CADOUT_H14 AK4
L0_CADIN_L14 L0_CADIN_H(14) L0_CADOUT_H(14) L0_CADOUT_L14 RSVD20
T5 L0_CADIN_L(14) L0_CADOUT_L(14) AA6 W26 RSVD5 RSVD21 AK3
L0_CADIN_H13 R6 AB5 L0_CADOUT_H13 W25
L0_CADIN_L13 L0_CADIN_H(13) L0_CADOUT_H(13) L0_CADOUT_L13 RSVD6
T6 L0_CADIN_L(13) L0_CADOUT_L(13) AB4 AE27 RSVD7
L0_CADIN_H12 P4 AD6 L0_CADOUT_H12 U24 F2
L0_CADIN_L12 L0_CADIN_H(12) L0_CADOUT_H(12) L0_CADOUT_L12 RSVD8 RSVD22
P5 L0_CADIN_L(12) L0_CADOUT_L(12) AC6 V24 RSVD9 RSVD23 F3
L0_CADIN_H11 M4 AF6 L0_CADOUT_H11 AE28
L0_CADIN_L11 L0_CADIN_H(11) L0_CADOUT_H(11) L0_CADOUT_L11 RSVD10
M5 L0_CADIN_L(11) L0_CADOUT_L(11) AE6 RSVD24 G4
L0_CADIN_H10 L6 AF5 L0_CADOUT_H10 Y31 G3
L0_CADIN_L10 L0_CADIN_H(10) L0_CADOUT_H(10) L0_CADOUT_L10 RSVD11 RSVD25
M6 L0_CADIN_L(10) L0_CADOUT_L(10) AF4 Y30 RSVD12 RSVD26 G5
L0_CADIN_H9 K4 AH6 L0_CADOUT_H9 AG31
L0_CADIN_L9 L0_CADIN_H(9) L0_CADOUT_H(9) L0_CADOUT_L9 RSVD13
K5 L0_CADIN_L(9) L0_CADOUT_L(9) AG6 V31 RSVD14 RSVD27 AD25
L0_CADIN_H8 J6 AH5 L0_CADOUT_H8 W31 AE24
L0_CADIN_L8 L0_CADIN_H(8) L0_CADOUT_H(8) L0_CADOUT_L8 RSVD15 RSVD28
K6 L0_CADIN_L(8) L0_CADOUT_L(8) AH4 AF31 RSVD16 RSVD29 AE25
RSVD30 AJ18
L0_CADIN_H7 U3 Y1 L0_CADOUT_H7 AD18 AJ20
L0_CADIN_L7 L0_CADIN_H(7) L0_CADOUT_H(7) L0_CADOUT_L7 KEY1 RSVD31
U2 L0_CADIN_L(7) L0_CADOUT_L(7) W1 AD19 KEY2 RSVD32 C18
L0_CADIN_H6 R1 AA2 L0_CADOUT_H6 AE7 C20
C L0_CADIN_L6 T1
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADOUT_H(6)
L0_CADOUT_L(6) AA3 L0_CADOUT_L6 AE8
KEY3
KEY4
RSVD33
RSVD34 G24 C
L0_CADIN_H5 R3 AB1 L0_CADOUT_H5 H3 G25
L0_CADIN_L5 L0_CADIN_H(5) L0_CADOUT_H(5) L0_CADOUT_L5 KEY5 RSVD35
R2 L0_CADIN_L(5) L0_CADOUT_L(5) AA1 H4 KEY6 RSVD36 H25
L0_CADIN_H4 N1 AC2 L0_CADOUT_H4 H20 V29
L0_CADIN_L4 L0_CADIN_H(4) L0_CADOUT_H(4) L0_CADOUT_L4 KEY7 RSVD37
P1 L0_CADIN_L(4) L0_CADOUT_L(4) AC3 H21 KEY8 RSVD38 W30
L0_CADIN_H3 L1 AE2 L0_CADOUT_H3
L0_CADIN_L3 L0_CADIN_H(3) L0_CADOUT_H(3) L0_CADOUT_L3
M1 L0_CADIN_L(3) L0_CADOUT_L(3) AE3
L0_CADIN_H2 L3 AF1 L0_CADOUT_H2 ZIF-940PS-TYC
L0_CADIN_L2 L0_CADIN_H(2) L0_CADOUT_H(2) L0_CADOUT_L2
L2 L0_CADIN_L(2) L0_CADOUT_L(2) AE1
L0_CADIN_H1 J1 AG2 L0_CADOUT_H1
L0_CADIN_L1 L0_CADIN_H(1) L0_CADOUT_H(1) L0_CADOUT_L1
K1 L0_CADIN_L(1) L0_CADOUT_L(1) AG3
L0_CADIN_H0 J3 AH1 L0_CADOUT_H0
L0_CADIN_L0 L0_CADIN_H(0) L0_CADOUT_H(0) L0_CADOUT_L0 L0_CLKIN_H1
J2 L0_CADIN_L(0) L0_CADOUT_L(0) AG1 L0_CLKIN_H1 11
L0_CLKIN_L1
L0_CLKIN_L1 11
L0_CLKIN_H0
L0_CLKIN_H0 11
L0_CLKIN_L0
L0_CLKIN_L0 11
L0_CTLIN_H0
L0_CTLIN_H0 11
L0_CTLIN_L0
L0_CTLIN_L0 11
B B
L0_CADIN_L[0..15]
L0_CADIN_L[0..15] 11
L0_CADIN_H[0..15]
L0_CADIN_H[0..15] 11
L0_CADOUT_H[0..15]
L0_CADOUT_H[0..15] 11
L0_CADOUT_L[0..15]
L0_CADOUT_L[0..15] 11
A A
Elitegroup Computer Systems
Title
CPU M2-1 HyperTransport
Size Document Number Rev
B
MCP61PM-AM 1.0A
Date: Tuesday, October 03, 2006 Sheet 4 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U9B U9C
MEMORY INTERFACE A MEMORY INTERFACE B
MA0_CLK_H[2..0] MA0_CLK_H2 AG21 AE14 MA_DATA63 MB0_CLK_H2 AJ19 AH13 MB_DATA63
8,10 MA0_CLK_H[2..0] MA0_CLK_L2 MA0_CLK_H(2) MA_DATA(63) MA_DATA62 MB0_CLK_L2 MB0_CLK_H(2) MB_DATA(63) MB_DATA62
AG20 MA0_CLK_L(2) MA_DATA(62) AG14 AK19 MB0_CLK_L(2) MB_DATA(62) AL13
MA0_CLK_L[2..0] MA0_CLK_H1 G19 AG16 MA_DATA61 MB0_CLK_H1 A18 AL15 MB_DATA61
8,10 MA0_CLK_L[2..0] MA0_CLK_L1 MA0_CLK_H(1) MA_DATA(61) MA_DATA60 MB0_CLK_L1 MB0_CLK_H(1) MB_DATA(61) MB_DATA60
H19 MA0_CLK_L(1) MA_DATA(60) AD17 A19 MB0_CLK_L(1) MB_DATA(60) AJ15
MA0_CS_L[1..0] MA0_CLK_H0 U27 AD13 MA_DATA59 MB0_CLK_H0 U31 AF13 MB_DATA59
8,10 MA0_CS_L[1..0] MA0_CLK_L0 MA0_CLK_H(0) MA_DATA(59) MA_DATA58 MB0_CLK_L0 MB0_CLK_H(0) MB_DATA(59) MB_DATA58
U26 MA0_CLK_L(0) MA_DATA(58) AE13 U30 MB0_CLK_L(0) MB_DATA(58) AG13
MA0_ODT0 AG15 MA_DATA57 AL14 MB_DATA57
8,10 MA0_ODT0 MA0_CS_L1 MA_DATA(57) MA_DATA56 MB0_CS_L1 MB_DATA(57) MB_DATA56
AC25 MA0_CS_L(1) MA_DATA(56) AE16 AE30 MB0_CS_L(1) MB_DATA(56) AK15
MA1_CLK_H[2..0] MA0_CS_L0 AA24 AG17 MA_DATA55 MB0_CS_L0 AC31 AL16 MB_DATA55
D 9,10 MA1_CLK_H[2..0] MA0_CS_L(0) MA_DATA(55)
AE18 MA_DATA54 MB0_CS_L(0) MB_DATA(55)
AL17 MB_DATA54 D
MA1_CLK_L[2..0] MA0_ODT0 MA_DATA(54) MA_DATA53 MB0_ODT0 MB_DATA(54) MB_DATA53
9,10 MA1_CLK_L[2..0] AC28 MA0_ODT(0) MA_DATA(53) AD21 AD29 MB0_ODT(0) MB_DATA(53) AK21
AG22 MA_DATA52 AL21 MB_DATA52
MA1_CS_L[1..0] MA1_CLK_H2 MA_DATA(52) MA_DATA51 MB1_CLK_H2 MB_DATA(52) MB_DATA51
9,10 MA1_CS_L[1..0] AE20 MA1_CLK_H(2) MA_DATA(51) AE17 AL19 MB1_CLK_H(2) MB_DATA(51) AH15
MA1_CLK_L2 AE19 AF17 MA_DATA50 MB1_CLK_L2 AL18 AJ16 MB_DATA50
MA1_ODT0 MA1_CLK_H1 MA1_CLK_L(2) MA_DATA(50) MA_DATA49 MB1_CLK_H1 MB1_CLK_L(2) MB_DATA(50) MB_DATA49
9,10 MA1_ODT0 G20 MA1_CLK_H(1) MA_DATA(49) AF21 C19 MB1_CLK_H(1) MB_DATA(49) AH19
MA1_CLK_L1 G21 AE21 MA_DATA48 MB1_CLK_L1 D19 AL20 MB_DATA48
MA_CAS_L MA1_CLK_H0 MA1_CLK_L(1) MA_DATA(48) MA_DATA47 MB1_CLK_H0 MB1_CLK_L(1) MB_DATA(48) MB_DATA47
8,9,10 MA_CAS_L V27 MA1_CLK_H(0) MA_DATA(47) AF23 W29 MB1_CLK_H(0) MB_DATA(47) AJ22
MA_WE_L MA1_CLK_L0 W27 AE23 MA_DATA46 MB1_CLK_L0 W28 AL22 MB_DATA46
8,9,10 MA_WE_L MA_RAS_L MA1_CLK_L(0) MA_DATA(46) MA_DATA45 MB1_CLK_L(0) MB_DATA(46) MB_DATA45
8,9,10 MA_RAS_L MA_DATA(45) AJ26 MB_DATA(45) AL24
MA1_CS_L1 AD27 AG26 MA_DATA44 MB1_CS_L1 AE29 AK25 MB_DATA44
MA_BANK[2..0] MA1_CS_L0 MA1_CS_L(1) MA_DATA(44) MA_DATA43 MB1_CS_L0 MB1_CS_L(1) MB_DATA(44) MB_DATA43
8,9,10 MA_BANK[2..0] AA25 MA1_CS_L(0) MA_DATA(43) AE22 AB31 MB1_CS_L(0) MB_DATA(43) AJ21
AG23 MA_DATA42 AH21 MB_DATA42
MA_CKE1 MA1_ODT0 MA_DATA(42) MA_DATA41 MB1_ODT0 MB_DATA(42) MB_DATA41
9,10 MA_CKE1 AC27 MA1_ODT(0) MA_DATA(41) AH25 AD31 MB1_ODT(0) MB_DATA(41) AH23
MA_CKE0 AF25 MA_DATA40 AJ24 MB_DATA40
8,10 MA_CKE0 MA_DATA(40) MA_DATA39 MB_DATA(40) MB_DATA39
MA_DATA(39) AJ28 MB_DATA(39) AL27
MA_ADD[15..0] MA_CAS_L AB25 AJ29 MA_DATA38 MB_CAS_L AC29 AK27 MB_DATA38
8,9,10 MA_ADD[15..0] MA_WE_L MA_CAS_L MA_DATA(38) MA_DATA37 MB_WE_L MB_CAS_L MB_DATA(38) MB_DATA37
AB27 MA_WE_L MA_DATA(37) AF29 AC30 MB_WE_L MB_DATA(37) AH31
MA_DQS_H[8..0] MA_RAS_L AA26 AE26 MA_DATA36 MB_RAS_L AB29 AG30 MB_DATA36
8,9 MA_DQS_H[8..0] MA_RAS_L MA_DATA(36) MA_DATA35 MB_RAS_L MB_DATA(36) MB_DATA35
MA_DATA(35) AJ27 MB_DATA(35) AL25
MA_DQS_L[8..0] MA_BANK2 N25 AH27 MA_DATA34 MB_BANK2 N31 AL26 MB_DATA34
8,9 MA_DQS_L[8..0] MA_BANK1 MA_BANK(2) MA_DATA(34) MA_DATA33 MB_BANK1 MB_BANK(2) MB_DATA(34) MB_DATA33
Y27 MA_BANK(1) MA_DATA(33) AG29 AA31 MB_BANK(1) MB_DATA(33) AJ30
MA_DM[8..0] MA_BANK0 AA27 AF27 MA_DATA32 MB_BANK0 AA28 AJ31 MB_DATA32
8,9 MA_DM[8..0] MA_BANK(0) MA_DATA(32) MA_DATA31 MB_BANK(0) MB_DATA(32) MB_DATA31
E29 E31
C 8,9 MA_DATA[63..0]
MA_DATA[63..0] MA_CKE1 L27 MA_CKE(1)
MA_DATA(31)
MA_DATA(30) E28 MA_DATA30 MB_CKE1 M31 MB_CKE(1)
MB_DATA(31)
MB_DATA(30) E30 MB_DATA30 C
MA_CKE0 M25 D27 MA_DATA29 MB_CKE0 M29 B27 MB_DATA29
MA_CHECK[7..0] MA_CKE(0) MA_DATA(29) MA_DATA28 MB_CKE(0) MB_DATA(29) MB_DATA28
8,9 MA_CHECK[7..0] MA_DATA(28) C27 MB_DATA(28) A27
MA_ADD15 M27 G26 MA_DATA27 MB_ADD15 N28 F29 MB_DATA27
MA_ADD14 MA_ADD(15) MA_DATA(27) MA_DATA26 MB_ADD14 MB_ADD(15) MB_DATA(27) MB_DATA26
N24 MA_ADD(14) MA_DATA(26) F27 N29 MB_ADD(14) MB_DATA(26) F31
MB0_CLK_H[2..0] MA_ADD13 AC26 C28 MA_DATA25 MB_ADD13 AE31 A29 MB_DATA25
8,10 MB0_CLK_H[2..0] MA_ADD12 MA_ADD(13) MA_DATA(25) MA_DATA24 MB_ADD12 MB_ADD(13) MB_DATA(25) MB_DATA24
N26 MA_ADD(12) MA_DATA(24) E27 N30 MB_ADD(12) MB_DATA(24) A28
MB0_CLK_L[2..0] MA_ADD11 P25 F25 MA_DATA23 MB_ADD11 P29 A25 MB_DATA23
8,10 MB0_CLK_L[2..0] MA_ADD10 MA_ADD(11) MA_DATA(23) MA_DATA22 MB_ADD10 MB_ADD(11) MB_DATA(23) MB_DATA22
Y25 MA_ADD(10) MA_DATA(22) E25 AA29 MB_ADD(10) MB_DATA(22) A24
MB0_CS_L[1..0] MA_ADD9 N27 E23 MA_DATA21 MB_ADD9 P31 C22 MB_DATA21
8,10 MB0_CS_L[1..0] MA_ADD8 MA_ADD(9) MA_DATA(21) MA_DATA20 MB_ADD8 MB_ADD(9) MB_DATA(21) MB_DATA20
R24 MA_ADD(8) MA_DATA(20) D23 R29 MB_ADD(8) MB_DATA(20) D21
MB0_ODT0 MA_ADD7 P27 E26 MA_DATA19 MB_ADD7 R28 A26 MB_DATA19
8,10 MB0_ODT0 MA_ADD6 MA_ADD(7) MA_DATA(19) MA_DATA18 MB_ADD6 MB_ADD(7) MB_DATA(19) MB_DATA18
R25 MA_ADD(6) MA_DATA(18) C26 R31 MB_ADD(6) MB_DATA(18) B25
MB1_CLK_H[2..0] MA_ADD5 R26 G23 MA_DATA17 MB_ADD5 R30 B23 MB_DATA17
9,10 MB1_CLK_H[2..0] MA_ADD4 MA_ADD(5) MA_DATA(17) MA_DATA16 MB_ADD4 MB_ADD(5) MB_DATA(17) MB_DATA16
R27 MA_ADD(4) MA_DATA(16) F23 T31 MB_ADD(4) MB_DATA(16) A22
MB1_CLK_L[2..0] MA_ADD3 T25 E22 MA_DATA15 MB_ADD3 T29 B21 MB_DATA15
9,10 MB1_CLK_L[2..0] MA_ADD2 MA_ADD(3) MA_DATA(15) MA_DATA14 MB_ADD2 MB_ADD(3) MB_DATA(15) MB_DATA14
U25 MA_ADD(2) MA_DATA(14) E21 U29 MB_ADD(2) MB_DATA(14) A20
MB1_CS_L[1..0] MA_ADD1 T27 F17 MA_DATA13 MB_ADD1 U28 C16 MB_DATA13
9,10 MB1_CS_L[1..0] MA_ADD0 MA_ADD(1) MA_DATA(13) MA_DATA12 MB_ADD0 MB_ADD(1) MB_DATA(13) MB_DATA12
W24 MA_ADD(0) MA_DATA(12) G17 AA30 MB_ADD(0) MB_DATA(12) D15
MB1_ODT0 G22 MA_DATA11 C21 MB_DATA11
9,10 MB1_ODT0 MA_DQS_H7 MA_DATA(11) MA_DATA10 MB_DQS_H7 MB_DATA(11) MB_DATA10
AD15 MA_DQS_H(7) MA_DATA(10) F21 AK13 MB_DQS_H(7) MB_DATA(10) A21
MB_CAS_L MA_DQS_L7 AE15 G18 MA_DATA9 MB_DQS_L7 AJ13 A17 MB_DATA9
8,9,10 MB_CAS_L MB_WE_L MA_DQS_H6 MA_DQS_L(7) MA_DATA(9) MA_DATA8 MB_DQS_H6 MB_DQS_L(7) MB_DATA(9) MB_DATA8
8,9,10 MB_WE_L AG18 MA_DQS_H(6) MA_DATA(8) E17 AK17 MB_DQS_H(6) MB_DATA(8) A16
MB_RAS_L MA_DQS_L6 AG19 G16 MA_DATA7 MB_DQS_L6 AJ17 B15 MB_DATA7
8,9,10 MB_RAS_L MA_DQS_L(6) MA_DATA(7) MB_DQS_L(6) MB_DATA(7)
B MB_BANK[2..0]
MA_DQS_H5
MA_DQS_L5
AG24 MA_DQS_H(5) MA_DATA(6) E15 MA_DATA6
MA_DATA5
MB_DQS_H5
MB_DQS_L5
AK23 MB_DQS_H(5) MB_DATA(6) A14 MB_DATA6
MB_DATA5
B
8,9,10 MB_BANK[2..0] AG25 MA_DQS_L(5) MA_DATA(5) G13 AL23 MB_DQS_L(5) MB_DATA(5) E13
MA_DQS_H4 AG27 H13 MA_DATA4 MB_DQS_H4 AL28 F13 MB_DATA4
MB_CKE1 MA_DQS_L4 MA_DQS_H(4) MA_DATA(4) MA_DATA3 MB_DQS_L4 MB_DQS_H(4) MB_DATA(4) MB_DATA3
9,10 MB_CKE1 AG28 MA_DQS_L(4) MA_DATA(3) H17 AL29 MB_DQS_L(4) MB_DATA(3) C15
MB_CKE0 MA_DQS_H3 D29 E16 MA_DATA2 MB_DQS_H3 D31 A15 MB_DATA2
8,10 MB_CKE0 MA_DQS_L3 MA_DQS_H(3) MA_DATA(2) MA_DATA1 MB_DQS_L3 MB_DQS_H(3) MB_DATA(2) MB_DATA1
C29 MA_DQS_L(3) MA_DATA(1) E14 C31 MB_DQS_L(3) MB_DATA(1) A13
MB_ADD[15..0] MA_DQS_H2 C25 G14 MA_DATA0 MB_DQS_H2 C24 D13 MB_DATA0
8,9,10 MB_ADD[15..0] MA_DQS_L2 MA_DQS_H(2) MA_DATA(0) MB_DQS_L2 MB_DQS_H(2) MB_DATA(0)
D25 MA_DQS_L(2) C23 MB_DQS_L(2)
MB_DQS_H[8..0] MA_DQS_H1 E19 J28 MA_DQS_H8 MB_DQS_H1 D17 J31 MB_DQS_H8
8,9 MB_DQS_H[8..0] MA_DQS_L1 MA_DQS_H(1) MA_DQS_H(8) MA_DQS_L8 MB_DQS_L1 MB_DQS_H(1) MB_DQS_H(8) MB_DQS_L8
F19 MA_DQS_L(1) MA_DQS_L(8) J27 C17 MB_DQS_L(1) MB_DQS_L(8) J30
MB_DQS_L[8..0] MA_DQS_H0 F15 MB_DQS_H0 C14
8,9 MB_DQS_L[8..0] MA_DQS_L0 MA_DQS_H(0) MA_DM8 MB_DQS_L0 MB_DQS_H(0) MB_DM8
G15 MA_DQS_L(0) MA_DM(8) J25 C13 MB_DQS_L(0) MB_DM(8) J29
MB_DM[8..0]
8,9 MB_DM[8..0] MA_DM7 MA_CHECK7 MB_DM7 MB_CHECK7
AF15 MA_DM(7) MA_CHECK(7) K25 AJ14 MB_DM(7) MB_CHECK(7) K29
MB_DATA[63..0] MA_DM6 AF19 J26 MA_CHECK6 MB_DM6 AH17 K31 MB_CHECK6
8,9 MB_DATA[63..0] MA_DM5 MA_DM(6) MA_CHECK(6) MA_CHECK5 MB_DM5 MB_DM(6) MB_CHECK(6) MB_CHECK5
AJ25 MA_DM(5) MA_CHECK(5) G28 AJ23 MB_DM(5) MB_CHECK(5) G30
MB_CHECK[7..0] MA_DM4 AH29 G27 MA_CHECK4 MB_DM4 AK29 G29 MB_CHECK4
8,9 MB_CHECK[7..0] MA_DM3 MA_DM(4) MA_CHECK(4) MA_CHECK3 MB_DM3 MB_DM(4) MB_CHECK(4) MB_CHECK3
B29 MA_DM(3) MA_CHECK(3) L24 C30 MB_DM(3) MB_CHECK(3) L29
MA_DM2 E24 K27 MA_CHECK2 MB_DM2 A23 L28 MB_CHECK2
MA_DM1 MA_DM(2) MA_CHECK(2) MA_CHECK1 MB_DM1 MB_DM(2) MB_CHECK(2) MB_CHECK1
E18 MA_DM(1) MA_CHECK(1) H29 B17 MB_DM(1) MB_CHECK(1) H31
MA_DM0 H15 H27 MA_CHECK0 MB_DM0 B13 G31 MB_CHECK0
MA_DM(0) MA_CHECK(0) MB_DM(0) MB_CHECK(0)
ZIF-940PS-TYC ZIF-940PS-TYC
A A
Elitegroup Computer Systems
Title
CPU M2-2 DDR2
Size Document Number Rev
B
MCP61PM-AM 1.0A
Date: Tuesday, October 03, 2006 Sheet 5 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+2.5V_VDDA for CPU PLL
+12V VCC3
D VRD_VID[4..0]
VRD_VID[4..0] 31 D
VREF25 R168
D
8
10K-1-04 U7A
1 2 3 Q38 +2.5V_VDDA 16-100-300143(3A)
+
1 G 2N7002-S
U9D V_DIMM
2 Width:50mil and Long:500mil
S
-
L20 MISC V_DIMM
4 GS358SFS 1 2 CPU_VDDA C10
FB-30-S08 VDDA1
+2.5V_VDDA D10 VDDA2