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5 4 3 2 1
CONTENT SHEET
Cover Sheet, Block diagram
Intel LGA775 CPU - Signals/ Power/ GND
1-2
3-5
MS-7345 ATX Version: 1.2
D
Intel Bearlake - FSB, PCIE, DMI, VGA, MSIC 6 CPU: Intel Pentium 4, Pentium D, Core2 Duo, Wolfdale, Kentsfield
D
Intel Bearlake - Memory DDR2 7 and Yorkfield processors in LGA775 Package.
Intel Bearlake - Power / GND 8-9 System Chipset:
ICH9 - PCI, USB, DMI, PCIE 10 Intel Bearlake - Q/G/P (G33, P35, Q35/33North Bridge)
ICH9 - Host, DMI, SATA, Audio, SPI, RTC, MSIC 11 Intel ICH9 (South Bridge)
ICH9 - Power, GND 12 On Board Device:
DDR2 Chanel-A / Chanel-B 13-14 CLOCK Gen -- ICS 9LPRS906
Clock Gen ICS9LPRS906 15 LPC Super I/O -- Fintek F71882F
C
LAN -- Realtek 8111 (PCIE) C
Super I/O Fintek F71882 16
HD Audio Codec -- RTL888/888T
PS2 / COM / VGA Port 17 1394 Controller -- VT6308 (2-port)
SATA / e-SATA / FAN Control 18 PCIE to PATA/SATA Bridge -- Marvel 88SE6111
LAN Realtek RTL8111(PCIE) 19 Main Memory:
Audio Codec RTL888T/888 20 Dual-channel DDR-II * 4
PCIE x16, x4, x1 & Bus Switch 21
Expansion Slots:
PCI Slot 1 & 2 22
PCI EXPRESS X16 SLOT *1
Marvell 88SE6111 PCIE to IDE/ SATA 23 PCI EXPRESS X4 SLOT
B
Alternative B
USB Connectors 24 PCI EXPRESS X1 SLOT * 2
PCI SLOT * 2
IEEE1394 VT6308 25
System Power/ACPI Controller UPI 26 PWM: Intersil ISL6322 (4 Phases) w/ ISL6612 driver
DDR2 / NB-Core Switching Power 27
VRD 11 - ISL6322 (4 Phases) 28
ATX Power-Con. / F_Panel 29
Manual & Option Parts 30
A
Power Delivery 31 A
Reset & PWROK map 32
MICRO-STAR INT'L CO.,LTD
GPIO Setting & PCI Routing / Revision History 33-35
MSI MS-7345
Size Document Description Rev
Custom COVER SHEET 1.2
Date: Friday, May 18, 2007 Sheet 1 of 35
5 4 3 2 1
5 4 3 2 1
Block Diagram
Board Stack-up
(1080 Prepreg Considerations)
D D
1.9mils Cu plus plating
Solder Mask
VRD 11
ISL6322 Intel LGA775 Processor PREPREG 2.7mils
1 oz. (1.2mils)
Cu Power
4-Phase PWM FSB 800/1066/1333
DDR3 800/1066
Plane
FSB
CORE 50mils
1 oz. (1.2mils)
4 DDR II Cu GND
PCI_E X16 PCI EXPRESS X16 DIMM PREPREG 2.7mils Plane
Connector
Bearlake Modules Solder Mask
DDRII
G/Q/P 1.9mils Cu plus plating
GMCH
Analog RGB Single End 50ohm Top/Bottom : 4mils
Video Out USB2.0 - 90ohm : 15/4.5/7.5/4.5/15
SATA - 95ohm : 15/4/8/4/15
C C
LAN - 100ohm : 15/4/8/4/15
PCIE - 95ohm : 15/4/8/4/15
DMI IEEE1394 - 110ohm : 15/4/9/4/15
HD Audio Link HD Audio Codec IDE : 15/4/8/4/15
RTL888T/888 LAN
PCI_E x4
PCI-E RTL8111B
PCI_E x1 PCI_E x4
(2 PCI_E x1 option)
PCI_E x1
ICH9
SATA-II 0~4 SATA2
J1394_1
J1394_2
PCI 1394
VT6308
E-SATA SATA2
B B
PCI Slot 1
USB Port 0~11 USB2.0
LPC Bus
LPC SIO
PCI_E to PATA PCI_E x1 Fintek
Marvell
F71882
88SE6111 SPI
SATA-II IDE
A
Keyboard Floopy Serial A
SPI LPC
Flash ROM Debug Port Mouse
MICRO-STAR INT'L CO.,LTD
MSI MS-7345
Size Document Description Rev
Custom BLOCK DIAGRAM 1.2
Date: Friday, May 18, 2007 Sheet 2 of 35
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5 4 3 2 1
VCC_SENSE
VCC_SENSE 28
CPU SIGNAL BLOCK C71 PULL HIGHT PULL DOWN
X_10u/16V/12
VSS_SENSE
VSS_SENSE 28
VID[0..7] 28
6 H_A#[3..35]
D D
H_A#10
H_A#35
H_A#34
H_A#33
H_A#32
H_A#31
H_A#30
H_A#29
H_A#28
H_A#27
H_A#26
H_A#25
H_A#24
H_A#23
H_A#22
H_A#21
H_A#20
H_A#19
H_A#18
H_A#17
H_A#16
H_A#15
H_A#14
H_A#13
H_A#12
H_A#11
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
H_A#8
H_A#7
H_A#6
H_A#5
H_A#4
H_A#3
H_A#9
RN4 8P4R-680R
VID5 1 2 VTT_OUT_RIGHT
VID2 3 4
VTT_OUT_RIGHT VID4 5 6
AM7
AM5
AM3
AM2
AG5
AG4
AG6
AH5
AH4
AC5
AD6
AC2
AN3
AN4
AN5
AN6
AB4
AB5
AA5
AA4
AB6
AK3
AK4
AF4
AF5
AL4
AL6
AL5
AJ6
AJ5
AJ3
W6
W5
M4
M5
U4
U5
U6
R4
VID0 C73 C36
Y4
Y6
V4
V5
P6
T4
T5
L4
L5
7 8
U8A VID7 1 2 0.1u/16V/Y/4 0.1u/16V/Y/4
R54 VID3 3 4
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
DBR#
ITP_CLK1
ITP_CLK0
RSVD/VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC_SENSE
VSS_SENSE
VCC_MB_REGULATION
VSS_MB_REGULATION
1KR1%/2 VID6 5 6
H_DBI#0 A8 VID1 7 8
6 H_DBI#[0..3] DBI0#
H_DBI#1 G11 AN7 RN3 8P4R-680R
DBI1# VID_SELECT VRD_VIDSEL 28
H_DBI#2 D19 H1 CPU_GTLREF0
DBI2# GTLREF0 CPU_GTLREF0 4
H_DBI#3 C20 H2 CPU_GTLREF1
DBI3# GTLREF1 CPU_GTLREF1 4
H29 GTLREF_SEL
GTLREF_SEL CPU_MCH_GTLREF T14 X_TP
4 H_IERR# AB2 IERR# GTLREF2 E24 CPU_MCH_GTLREF 6
AB3 F2 CPU_GTLREF2
MCERR# FC5/CPU_GTLREF2 CPU_GTLREF2 4
R3 G10 CPU_GTLREF3 H_BPM#0 1 2 VTT_OUT_RIGHT
11 H_FERR# FERR#/PBE# RSVD/CPU_GTLREF3 CPU_GTLREF3 4
M3 H_BPM#1 3 4
11 H_STPCLK# STPCLK#
AD3 AG3 H_BPM#5 H_BPM#5 5 6
BINIT# BPM5# H_BPM#4 H_BPM#3
11 H_INIT# P3 INIT# BPM4# AF2 7 8
H4 AG2 H_BPM#3 RN5 8P4R-51R/2
RSP# BPM3# H_BPM#2
BPM2# AD2
B2 AJ1 H_BPM#1 H_TRST# 1 2
6 H_DBSY# DBSY# BPM1#
C1 AJ2 H_BPM#0 H_BPM#4 3 4
6 H_DRDY# DRDY# BPM0# H_BPM#0 5
E3 H_TDO 5 6
6 H_TRDY# TRDY#
J6 H_REQ#4 H_TCK 7 8
REQ4# H_REQ#[0..4] 6
D2 K6 H_REQ#3 RN6 8P4R-51R/2
6 H_ADS# ADS# REQ3#
C3 M6 H_REQ#2
6 H_LOCK# LOCK# REQ2#
C C2 J5 H_REQ#1 H_TDI 1 2 C
6 H_BNR# BNR# REQ1#
D4 K4 H_REQ#0 H_BPM#2 3 4
6 H_HIT# HIT# REQ0#
E4 H_TMS 5 6
6 H_HITM# HITM#
G8 W2 H_TESTHI12 7 8
6 H_BPRI# BPRI# TESTHI12 H_TESTHI12 5
G7 P1 H_TESTHI11 RN7 8P4R-51R/2
6 H_DEFER# DEFER# TESTHI11 Kentsfield
H5 H_TESTHI10
H_TDI TESTHI10 H_TESTHI9 R118 0/4 H_BPM#2
AD1 TDI TESTHI9 G4
H_TDO AF1 G3 H_TESTHI8 R140 0/4 H_BPM#3
H_TMS TDO TESTHI8
AC1 TMS TESTHI7 F24
H_TRST# AG1 G24 RN9 8P4R-51R/2
H_TCK TRST# TESTHI6 H_TESTHI10 VTT_OUT_LEFT
AE1 TCK TESTHI5 G26 1 2
PECI G5 G27 H_TESTHI12 3 4
11,16 PECI PECI TESTHI4
VTIN1 AL1 G25 H_TESTHI9 5 6
16 VTIN1 THERMDA TESTHI3
GNDHM AK1 F25 H_TESTHI2_7 R166 51R/2 V_FSB_VTT V_FSB_VTT H_TESTHI11 7 8 C94
16 GNDHM THERMDC TESTHI2
H_TRMTRIP# M2 W3 H_TESTHI1 0.1u/16V/Y/4
11 H_TRMTRIP# THERMTRIP# TESTHI1
AE8 F26 H_TESTHI0 R172 51R/2
H_PROCHOT# GND/SKTOCC# TESTHI0 FORCEPH R101 X_130R1%/2 VTT_OUT_RIGHT
4 H_PROCHOT# AL2 PROCHOT# FORCEPH AK6 VTT_OUT_RIGHT 4,5
N2 G6 RSVD_G6 R146 X_51R/2 VTT_OUT_LEFT H_TESTHI8 R143 51R/2
11 H_IGNNE# IGNNE# RSVD#G6
P2 H_TESTHI1 R123 51R/2
11 ICH_H_SMI# SMI#
K3 G28 CK_H_CPU_DN CK_H_CPU_DN 15 H_TESTHI13 R134 51R/2
11 H_A20M# A20M# BCLK1#
H_TESTHI13 L2 F28 CK_H_CPU_DP CK_H_CPU_DP 15
TESTI_13 BCLK0#
AH2 A3 H_RS#2
RSVD#AH2 RS2# H_RS#[0..2] 6
N5 F5 H_RS#1
RESERVED0 RS1# H_RS#0
AE6 RESERVED1 RS0# B3
H_BPM#1 R100 0/4 C9 RESERVED2 TEST-U3
D16 RESERVED4 AP1# U3 T8 X_TP
Kentsfield A20 U2 TEST-U2
RESERVED5 AP0# T7 X_TP
BR0# F3 H_BR#0 4,6
Y1 T2 H_COMP5 R130 49.9R1%/2
BOOTSELECT COMP5 H_COMP4 R135 49.9R1%/2
V2 LL_ID0 COMP4 J2 VTT_OUT_LEFT 4
B H_COMP3 R131 49.9R1%/2 B
AA2 LL_ID1 COMP3 R1
G2 H_COMP2 R144 49.9R1%/2
COMP2 H_COMP1 R126 49.9R1%/2 C95
15,16 CPU_BSEL0 G29 BSEL0 COMP1 T1
H30 A13 H_COMP0 R173 49.9R1%/2 0.1u/16V/Y/4
15,16 CPU_BSEL1 BSEL1 COMP0
15,16 CPU_BSEL2 G30 BSEL2
J17 TEST-J17 T9 X_TP
DP3# TEST-H16
4,11 H_PWRGD N1 PWRGOOD DP2# H16 T12 X_TP
TEST-H15
G23
DP1# H15
J16 TEST-J16
T11 X_TP
X_TP
Thermal TRIP
4,6 H_CPURST# RESET# DP0# T10
6 H_D#[0..63] ADSTB1# AD5 H_ADSTB#1 6
H_D#63 B22 R6
D63# ADSTB0# H_ADSTB#0 6
H_D#62 A22 C17 VCC3
D62# DSTBP3# H_DSTBP#3 6
H_D#61 A19 G19 VTT_OUT_RIGHT
D61# DSTBP2# H_DSTBP#2 6
H_D#60 B19 E12
D60# DSTBP1# H_DSTBP#1 6
H_D#59 B21 B9
D59# DSTBP0# H_DSTBP#0 6
H_D#58 C21 A16 R76 R89
D58# DSTBN3# H_DSTBN#3 6
H_D#57 B18 G20 X_10K/4 10KR/2
D57# DSTBN2# H_DSTBN#2 6
H_D#56 A17 G12
D56# DSTBN1# H_DSTBN#1 6
H_D#55 B16 C8 H_DSTBN#0 6
B
H_D#54 D55# DSTBN0# Q12
C18 D54# LINT1/NMI L1 H_NMI 11
K1 X_2N3904
LINT0/INTR H_INTR 11
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#