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DIGITAL CONTROLLED MULTI FREQUENCYMONITOR
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ST6369
DATA SHEET
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein :
1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
ST6369 DATASHEET INDEX
Pages
ST6369
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 4 6 9 15 19 21 22 23 26 29 30 39 40 40 42 43 48 52 53
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST6369 CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WAIT & STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-BIT PWM D/A CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST63E69 ST63T69
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55 56 58 60 61 67
GENERAL DESCRIPTION . . . . . . . . . . PIN DESCRIPTION . . . . . . . . . . . . . ST63E69,T69 EPROM/OTP DESCRIPTION. ABSOLUTE MAXIMUM RATINGS . . . . . . ORDERING INFORMATION . . . . . . . .
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ST6369
8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCY MONITOR
PRELIMINARY DATA
4.5 to 6V supply operating range 8MHz Maximum Clock Frequency User Program ROM: 7948 Reserved Test ROM: 244 Data ROM: user selectable size Data RAM: 256 Data EEPROM: 384 bytes bytes bytes bytes
40-Pin Dual in Line Plastic Package Up to 23 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs Two Timers each including an 8-bit counter with a 7-bit programmable prescaler Digital Watchdog Function Serial Peripheral Interface (SPI) supporting S-BUS/ I2C BUS and standard serial protocols One 14-Bit PWM D/A Converter Six 6-Bit PWM D/A Converters
ST6369 8K 256 384 7 (Ordering Information at the end of the datasheet)
1
PDIP40
DEVICE SUMMARY
DEVICE ROM (Bytes) RAM EEPROM (Bytes) (Bytes) D/A Conv.
One A/D converter with 0.5V resolution Five interrupt vectors (HSYNC/NMI, Timer 1 & 2, VSYNC, PWR INT.) On-chip clock oscillator ST6369 is supported by pin-to-pin EPROM and OTP versions. The development tool of the ST6369 microcontroller consists of the ST6369-EMU emulation and development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer.
February 1993
This is Preliminary information from SGS-THOMSON. Details are subject to change without notice.
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ST6369
Figure 1. ST6369 Pin Configuration
DA0 DA1 DA2 DA3 DA4 DA5 PB1 PB2 AD PB4 PB5 PB6 PA0 PA1 PA2 PA3 PA4 PA5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
40 39 38 37 36 35 34 33 32
VDD PC0 ( SCL ) PC1 ( SDA ) PC2 PC3 ( SEN ) PC4 ( PWRIN ) PC5 PC6 ( HSYNC ) PC7 HDA RESET OSCOUT OSCIN TEST VSYNC N.C. N.C. O0 O1 V SS
VR0G1375
ST6369
31 30 29 28 27 26 25 24 23 22 21
GENERAL DESCRIPTION The ST6369 microcontroller is member of the 8-bit HCMOS ST638x family, a series of devices specially oriented to Digital Controlled Multi Frequency Monitor applications. ST6369 members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to DCMF Monitor applications. The macrocells of the ST6369 are: two Timer peripherals each including an 8-bit counter with a 7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), six 6-bit PWM D/A converters, an A/D converter with 0.5V resolution, a 14-bit PWM D/A converter. In addition the following memory resources are available: program ROM (8K bytes), data RAM (256 bytes), EEPROM (384 bytes).
PA6 ( HD0 ) 19 PA7 ( HD1 ) 20
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Figure 2. ST6369 Block Diagram
* Refer To Pin Configuration For Additiona l Information TEST
HSYNC/PC6
TEST INTERRUPT Inputs PORT A PORT B PORT C
PA0 PB0
PA7 * PB7 *
VSYNC
USER PROGRAM ROM 8 kBytes
DATA ROM USER SELECTABLE DATA RAM 256 Bytes DATA EEPROM 384 Bytes
SERIAL PERIPHE RAL INTER FACE
PC2,PC4 PC7 * PC0 / SCL PC1 / SDA PC3 / SEN
TIMER 1
TIMER 2
PC
STACK STACK STACK STACK STACK STACK LEVEL LEVEL LEVEL LEVEL LEVEL LEVEL 1 2 3 4 5 6
DIGITAL WATCHDOG/TIMER
D / A Outputs
HDA,DA0 DA5 AD
8-BIT CORE
A/D Input
POWER SUPPLY
OSCILLATOR
RESET
VDD
VSS
OSCin
OSCout
RESET
VR 0B1 753
Table 1. Device Summary
DEVICE ST6369 ROM (Bytes) 8K RAM (Bytes) 256 EEPROM (Bytes) 384 A/D 1 14-bit D/A 1 6-bit D/A 6 EMULATING DEVICES ST63E69, ST63T69
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PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection. OSCIN, OSCOUT. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operation of the MCU with various stability/cost trade-offs. The OSCIN pin is the input pin, the OSCOUT pin is the output pin. RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be disabled when the RESET pin is low to reduce power consumption during reset phase. TEST. The TEST pin must be held at VSS for normal operation. PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input with or without pull-up resistor or as an output under software control of the data direction register. Pins PA4 to PA7 are configured as open-drain outputs (12V drive). On PA4-PA7 pins the input pull-up option is not available while PA6 and PA7 have additional current driving capability (25mA, VOL:1V). PA0 to PA3 pins are configured as pushpull. PB1-PB2, PB4-PB6. These 5 lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register.
PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. Pins PC0 to PC3 are configured as open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are "ANDed" with the SPI control signals and are all open-drain. PC0 is connected to the SPI clock signal (SCL), PC1 with the SPI data signal (SDA) while PC3 is connected with SPI enable signal (SEN, used in S-BUS protocol). Pin PC4 and PC6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; PC4 can be connected to Power Interrupt while PC6 can be connected to the HSYNC/NMI interrupt line. DA0-DA5. These pins are the six PWM D/A outputs of the 6-bit on-chip D/A converters. These lines have open-drain outputs with 12V drive. The output repetition rate is 31.25KHz (with 8MHz clock). AD. This is the input of the on-chip 10 levels comparator that can be used to implement the Analog Keyboard function. This pin is an high impedance input able to withstand signals with a peak amplitude up to 12V. VSYNC. This is the Vertical Synchronization pin. This pin is connected to an internal timer interrupt. O0, O1. These two lines are output open-drain pins with 12V drive. HDA. This is the output pin of the on-chip 14-bit PWM D/A Converter. This line is a push-pull output with standard drive.
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Table 2. Pin Summary
Pin Function DA0 to DA5 AD HDA VSYNC TEST OSCIN OSCOUT RESET PA0-PA3 PA4-PA5 PA6-PA7 PB1-PB2 PB4-PB6 PC0-PC3 PC4-PC7 O0, O1 VDD, VSS Description Output, Open-Drain, 12V Input, High Impedance, 12V Output, Push-Pull Input, Pull-up, Schmitt Trigger Input, Pull-Down Input, Resistive Bias, Schmitt Trigger to Reset Logic Only Output, Push-Pull Input, Pull-up, Schmitt Trigger Input I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input, High Drive I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 5V , Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input Output, Open-Drain, 12V Power Supply Pins
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ST6369 CORE The Core of the ST6369 is implemented independently from the I/O or memory configuration. Consequently, it can be treated as an independent centralprocessor communicating with I/O and memory via internal addresses, data, and control busses. The in-core communication is arranged as shown in the following block diagram figure; the controller being externally linked to both the reset and the oscillator, while the core is linked to the dedicated onchip macrocells peripherals via the serial data bus and indirectly for interrupt purposes through the control registers. Registers The ST6369 Core has five registers and three pairs of flags available to the programmer. They are shown in Figure 4 and are explained in the following paragraphs together with the program and data memory page registers. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator is addressed in the data space as RAM location at the FFH address. Accordingly, the ST6369 instruction set can use the accumulator as any other register of the data space.
Figure 4. Core Programming Model
INDEX REGISTER
b7 b7 b7 b7 b7
X REG. POINTER Y REG. POINTER
V REGISTER W REGISTER
b0
SHORT DIRECT ADDRESSING MODE b0
b0
b0 b0 b0
ACCUMULATOR
b11
PROGRAM COUNTER
SIX LEVELS STACK REGISTER
NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS
C C C
Z Z Z
VA000423
Figure 3. Core Block Diagram
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ST6369 CORE (Continued) Indirect Registers (X, Y). These two indirect registers are used as pointers to the memory locations in the data space. They are used in the register-indirect addressing mode.These registers can be addressed in the data space as RAM locations at the 80H (X) and 81H (Y) addresses. They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST638x instruction set can use the indirect registers as any other register of the data space. Short Direct Registers (V, W). These two registers are used to save one byte in short direct addressing mode. These registers can be addressed in the data space as RAM locations at the 82H (V) and 83H (W) addresses. They can also be accessed with the direct and bit direct addressing modes. Accordingly, the ST638x instruction set can use the short direct registers as any other register of the data space. Program Counter (PC) The program counter is a 12-bit register that contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or an address of operand. The 12-bit length allows the direct addressing of 4096 bytes in the program space. Nevertheless, if the program space contains more than 4096 locations, the further program space can be addressed by using the Program ROM Page Register. The PC value is incremented, after it is read for the address of the current instruction, by sending it through the ALU, so giving the address of the next byte in the program. To execute relative jumps the PC and the offset values are shifted through the ALU, where they will be added, and the result is shifted back into the PC. The program counter can be changed in the following ways: JP (Jump) instruction.... PC= Jump address CALL instruction ........... PC=Call address Relative Branch instructions ................... PC=PC+offset Interrupt........................ PC=Interrupt vector Reset............................ PC=Reset vector RET & RETI instructions............PC=Pop (stack) Normal instruction ........ PC= PC+1 Flags (C, Z) The ST6369 Core includes three pairs of flags that correspond to 3 different modes: normal mode, interrupt mode and Non-Maskable-Interrupt-Mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during normal operation, one pair is used during the interrupt mode (CI,ZI) and one is used during the not-maskable interrupt mode (CNMI, ZNMI). The ST6369 Core uses the pair of flags that corresponds to the actual mode: as soon as an interrupt (resp. a Non-Maskable-Interrupt) is generated, the ST6369 Core uses the interrupt flags (resp. the NMI flags) instead of the normal flags. When the RETI instruction is executed, the normal flags (resp. the interrupt flags) are restored if the MCU was in the normal mode (resp. in the interrupt mode) before the interrupt. Should be observed that each flag set can only be addressed in its own routine (Not-maskable interrupt, normal interrupt or main routine). The interrupt flags are not cleared during the context switching and so, they remain in the state they were at the exit of the last routine switching. The Carry flag is set when a carry or a borrow occurs during arithmetic operations, otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction, and participates in the rotate left instruction. The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero, otherwise it is cleared. The switching between these three sets is automatically performed when an NMI, an interrupt and a RETI instructions occur. As the NMI mode is automatically selected after the reset of the MCU, the ST6369 Core uses at first the NMI flags. Figure 5. Stack Operation
PROGRAM COUNTER
STACK LEVEL 1 WHEN RET OR RETI OCCURS STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6
WHEN CALL OR INTERRUPT REQUEST OCCURS
VA000424
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ST6369 CORE (Continued) Stack The ST6369 Core includes true LIFO hardware stack that eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level is shifted into the next level while the content of the PC is shifted into the first level (the value of the sixth level will be lost). When subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is shifted back into the previous level. These two operating modes are described in Figure 5. Since the accumulator, as all other data space registers, is not stored in this stack the handling of this registers shall be performed inside the subroutine. The stack pointer will remain in its deepest position, if more than 6 calls or interrupts are executed, so that the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. Memory Registers The PRPR can be addressed like a RAM location in the Data Space at the CAH address; nevertheless it is a write-only register that can not be accessed with single-bit operations. This register is used to select the 2-Kbyte ROM bank of the Program Space that will be addressed. The number of the page has to be loaded in the PRPR. The PRPR is not cleared during the MCU initialization and should therefore be defined before jumping out of the static page. Refer to the Program Space description for additional information concerning the use of this register. The PRPR is not modified when an interrupt or a subroutine occurs. Figure 6. Program ROM Page Register
PRPR Program ROM Page Register (CAH, Write Only)
The DRBR can be addressed like a RAM location in the Data Space at the E8H address, nevertheless it is write-only register that can not be accessed with single-bit operations. This register is used to select the desired 64-byte RAM/EEPROM bank of the Data Space. The number of the bank has to be loaded in the DRBR and the instruction has to point to the selected location as it was in the 0 bank (from 00H address to 3FH address). This register is undefined after Reset. Refer to the Data Space description for additional information. The DRBR register is not modified when a interrupt or a subroutine occurs. Figure 7. Data RAM Bank Register
DRBR Data RAM Bank Register (E8H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
The DRWR register can be addressedlike a RAM location in the Data Space at the C9H address, nevertheless it is write-only register that can not be accessed with single-bit operations. This register is used to move up and down the 64-byte read-only data window (from the 40H address to 7FH address of the Data Space) along the ROM of the MCU by step of 64 bytes. The effective address of the byte to be read as a data in the ROM is obtainedby the concatenationof the 6 less significant bits of the address given in the instruction (as less significant bits) and the content of the DRWR (as most significant bits). Refer to the Data Space description for additional information. Figure 8. Data ROM Window Register
DRWR
D7 D6 D5 D4 D3 D2 D1 D0
Data ROM Window Register (C9H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
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MEMORY SPACES The MCUs operate in three different memory spaces: Stack Space, Program Space and Data Space. A description of these spaces is shown in Figure 9. Stack Space The stack space consists of six 12 bit registers that are used for stacking subroutine and interrupt return addressesplus the current programcounterregister. Program Space The program space is physically implemented in the ROM and includes all the instructions that are to be executed, as well as the data required for the immediate addressing mode instructions, the reserved test area and user vectors. It is addressed thanks to the 12-bit Program Counter register (PC register) and so, the ST6369 Core can directly address up to 4K bytes of Program Space. Nevertheless, the Program Space can be extended by the addition of 2-Kbyte ROM banks as it is shown in Figure 11 in which a 8K bytes memory is described. These banks are addressed by pointing to the 000H-7FFH locations of the Program Space thanks to the Program Counter, and by writing the appropriate code in the Program ROM Page Register (PRPR) located at the CAH address of the Data Space. Because interrupts and common subFigure 9. Memory Addressing Description Diagram
STACK SPACE
routines should be available all the time only the lower 2K byte of the 4K program space are bank switched while the upper 2K byte can be seen as static space. Table 3 gives the different codes that allows the selection of the corresponding banks. Note that, from the memory point of view, the Page 1 and the Static Page represent the same physical memory: it is only a different way of addressing the same location. Figure 10. 8K Bytes Program Space Addressing Description
Program counter space 0FFFH Static Page Page 1 0800H 07FFH Page 0 0000H Page 1 Static Page Page 2 Page 3 0000H 1FFFH
PROGRAM SPACE
DATA SPACE
00 00h
PROGRAM COUNTER
000h
R AM / EEPR OM BAN KIN G AR EA
0-63
STACK LEVE L 1 STACK LEVE L 2 STACK LEVE L 3 STACK LEVE L 4 STACK LEVE L 5 STACK LEVE L 6
ROM
03Fh 040h
D ATA ROM W IN D OW
07FFh 08 00h
070h 080h 081h 082h 083h 084h
X R EGISTER Y R EGISTER V R EGISTER W R EGIST ER RA M
ROM
0C0h
DA TA R OM W IND OW SELE CT
0FF0h 0FFFh
IN TER R U PT & R ESET VEC TOR S
D ATA R AM BA N K S EL EC T
0FFh
AC C UMU L ATOR
VR001568
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MEMORY SPACES (Continued) Figure 11. Program ROM Page Register
PRPR Program ROM Page Register (CAH, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
PRPR0 PRPR1 UNUSED UNUSED UNUSED
D7-D2. These bits are not used but have to be written to "0". PRPR1-PRPR0. These are the program ROM banking bits and the value loaded selects the corresponding page to be addressed in the lower part of 4K program address space as specified in Table 3. This register is undefined on reset. Table 3. Program ROM Page Register Coding
PRPR1 X 0 0 1 1 PRPR0 X 0 1 0 1 PC11 1 0 0 0 0 Memory Page Static Page (Page 1) Page 0 Page 1 (Static Page) Page 2 Page 3
Note. Only the lower part of address space has been bankswitched because interrupt vectors and common subroutines should be available all the time. The reason of this structure is due to the fact that it is not possible to jump from a dynamic page to another, unless jumping back to the static page, changing contents of PRPR, and, then, jumping to a different dynamic page. Care is required when handling the PRPR as it is write only. For this reason, it is not allowed to change the PRPR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. Anyway, this operation may be necessary if the sum of common routines and interrupt drivers will take more than 2K bytes; in this case could be necessary to divide the interrupt driver in a (minor) part in the static page (start and end), and in the second (major) part in one dynamic page. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the PRPR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the PRPR is not affected.
Table 4. ST6369 Program ROM Map
ROM Page PAGE 0 Device Address 0000H-007FH 0080H-07FFH 0800H-0F9FH 0FA0H-0FEFH 0FF0H-0FF7H 0FF8H-0FFBH 0FFCH-0FFDH 0FFEH-0FFFH 0000H-000FH 0010H-07FFH 0000H-000FH 0010H-07FFH Description Reserved User ROM User ROM Reserved Interrupt Vectors Reserved NMI Vector Reset Vector Reserved User ROM Reserved User ROM
PAGE 1 "STATIC"
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MEMORY SPACES (Continued) Data Space The instruction set of the ST6369 Core operates on a specific space, named Data Space that contains all the data necessary for the processing of the program. The Data Space allows the adFigure 12. Data Space dressing of RAM (256 bytes), EEPROM (384 bytes), ST6369 Core/peripheral registers, and read-only data such as constants and the look-up tables. Figure 13. Data Space (Continued)
b7
b0 000H DATA RAM/EEPROM BANK AREA 03FH 040H DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM 07FH 080H 081H 082H 083H 084H 0BFH 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0D1H 0D2H 0D3H 0D4H 0D5H 0D7H 0D8H
b7
b0 RESERVED TIMER 2 PRESCALER REGISTER TIMER 2 COUNTER REGISTER TIMER 2 STATUS CONTROL REG. RESERVED
0D9H 0DAH 0DBH 0DCH 0DDH 0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H 0E8H 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH 0EFH 0F0H 0FEH 0FFH
PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DIRECTION REGISTER PORT B DIRECTION REGISTER PORT C DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA ROM WINDOW REGISTER PROGRAM ROM PAGE REGISTER RESERVED SPI DATA REGISTER RESERVED TIMER 1 PRESCALER REGISTER TIMER 1 COUNTER REGISTER TIMER 1 STATUS/CONTROL REG. RESERVED WATCHDOG REGISTER
DA0 DATA/CONTROL REGISTER DA1 DATA/CONTROL REGISTER DA2 DATA/CONTROL REGISTER DA3 DATA/CONTROL REGISTER AD, HSYNC RESULT REGISTER OUTPUTS CONTROL REGISTER DA4 DATA/CONTROL REGISTER DA5 DATA/CONTROL REGISTER DATA RAM BANK REGISTER DEDIC. LATCHES CONTROL REG. EEPROM CONTROL REGISTER SPI CONTROL REGISTER 1 SPI CONTROL REGISTER 2 RESERVED HDA DATA REGISTER 1 HDA DATA REGISTER 2 RESERVED ACCUMULATOR
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MEMORY SPACES (Continued) Data ROM Addressing. All the read-only data are physically implemented in the ROM in which the Program Space is also implemented. The ROM therefore contains the program to be executed and also the constants and the look-up tables needed for the program. The locations of Data Space in which the different constants and look-up tables are addressed by the ST6369 Core can be considered as being a 64-byte window through which it is possible to access to the read-only data stored in the ROM. This window is located from the 40H address to the 7FH address in the Data space and allows the direct reading of the bytes from the 000H address to the 03FH address in the ROM. All the bytes of the ROM can be used to store either instructions or read-only data. Indeed, the window can be moved by step of 64 bytes along the ROM in writing the appropriate code in the Write-only Data ROM Window register (DRWR, location C9H). The effective address of the byte to be read as a data in the ROM is obtained by the concatenation of the 6 less significant bits of the address in the Data Space (as less significant bits) and the content of the DRWR (as most significant bits). So when addressing location 40H of data space, and 0 is loaded in the DRWR, the physical addressed location in ROM is 00H. Figure 14. Data ROM Window Register
DWR Data ROM Window Register (C9H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
DWR0 = Data DWR1 = Data DWR2 = Data DWR3 = Data DWR4 = Data DWR5 = Data DWR6 = Data UNUSED ROM Window 0 ROM Window 1 ROM Window 2 ROM Window 3 ROM Window 4 ROM Window 5 ROM Window 6
DWR6-DWR0. These are the Data Rom Window bits that correspond to the upper bits of data ROM program space. This register is undefined after reset. Note. Care is required when handling the DRWR as it is write only. For this reason, it is not allowed to change the DRWR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRWR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRWR register is not affected.
Figure 15. Data ROM Window Memory Addressing
DATA ROM 13 12 6 11 5 10 4 9 3 8 2 7 1 6 0 5 0 1 4 3 2 1 5 4 3 2 1 0 PROGRAM SPACE ADDRESS READ 0 DATA SPACE ADDRESS 40h-7Fh IN INSTRUCTION
WINDOW REGISTER 7 CONTENTS (DWR)
Example:
DWR=28h 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 DATA SPACE ADDRESS 59h
ROM ADDRESS:A19h
0
0
1
0
1
0
0
0
0
1
1
0
0
1
VR01573B
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MEMORY SPACES (Continued) Data RAM/EEPROM In the ST6369 64 bytes of data RAM are directly addressable in the data space from 80H to BFH addresses. The additional 192 bytes of RAM, the 384 bytes of EEPROM can be addressed using the banks of 64 bytes located between addresses 00H and 3FH. The selection of the bank is done by programming the Data RAM Bank Register (DRBR) located at the E8H address of the Data Space. In this way each bank of RAM, EEPROM can select 64 bytes at a time. No more than one bank should be set at a time. Figure 16. Data RAM Bank Register
DRBR Data RAM Bank Register (E8H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
DRBR0 DRBR1 DRBR2 DRBR3 DRBR4 DRBR5 DRBR6 DRBR7
DRBR7,DRBR1,DRBR0. These bits select the EEPROM pages. DRBR4,DRBR3,DRBR2. Each of these bits, when set, will select one RAM page. This register is undefined after reset. Table 5 summarizes how to set the Data RAM Bank Register in order to select the various banks or pages. Note : Care is required when handling the DRBR as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRBR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. EEPROM Description The data space of ST6369 family from 00H to 3FH is paged as described in Table 5. 384 bytes of EEPROM located in six pages of 64 bytes (pages 0,1,2,3,4 and 5, see Table 5).
Table 5. Data RAM Bank Register Set-up
DRBR Value Hex. 01H 02H 03H 81H 82H 83H 04H 08H 10H Binary 0000 0001 0000 0010 0000 0011 1000 0001 1000 0010 1000 0011 0000 0100 0000 1000 0001 0000 EEPROM Page 0 EEPROM Page 1 EEPROM Page 2 EEPROM Page 3 EEPROM Page 4 EEPROM Page 5 RAM Page 2 RAM Page 3 RAM Page 4 Selection
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MEMORY SPACES (Continued) Through the programming of the Data RAM Bank Register (DRBR=E8H) the user can select the bank or page leaving unaffected the way to address the static registers. The way to address the "dynamic" page is to set the DRBR as described in Table 5 (e.g. to select EEPROM page 0, the DRBR has to be loaded with content 01H, see Data RAM/EEPROM addressing for additional information). Bits 0, 1 and 7 of the DRBR are dedicated to the EEPROM. The EEPROM pages do not require dedicated instructions to be accessed in reading or writing. The EEPROM is controlled by the EEPROM Control Register (EECR=EAH). Any EEPROM location can be read just like any other data location, also in terms of access time. To write an EEPROM location takes an average time of 5 ms (10ms max) and during this time the EEPROM is not accessible by the Core. A busy flag can be read by the Core to know the EEPROM status before trying any access. In writing the EEPROM can work in two modes: Byte Mode (BMODE) and Parallel Mode (PMODE). The BMODE is the normal way to use the EEPROM and consists in accessing one byte at a time. The PMODE consists in accessing 8 bytes per time. D7. Not used SB. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to the leakage values. Figure 17. EEPROM Control Register
EECR EEPROM Control Register (EAH, Read/Wr ite) D7 D6 D5 D4 D3 D2 D1 D0
EN = EEPROM Enable Bit BS = EEPROM Busy Bit PE = Parallel Mode Enable Bit PS = Parallel Start Bit Reserved (Must be set Low) Reserved (Must be set Low) SB = Stand-by Enable Bit Unused
D5, D4. Reserved for testing purposes, they must be set to zero. PS. SET ONLY. Once in Parallel Mode, as soon as the user software sets the PS bit the parallel writing of the 8 adjacent registers will start. PS is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written; after parallel programming the remaining undefined bytes will have no particular content. PE. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming (more bytes per time). If PE is set and the "parallel start bit" (PS) is low, up to 8 adjacent bytes can be written at the maximum speed, the content being stored in volatile registers. These 8 adjacent bytes can be considered as row, whose A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bytes. PE is automatically reset at the end of any parallel programming procedure. PE can be reset by the user software before starting the programming procedure, leaving unchanged the EEPROM registers. BS. READ ONLY. This bit will be automatically set by the CORE when the user program modifies an EEPROM register. The user program has to test it before any read or write EEPROM operation; any attempt to access the EEPROM while "busy bit" is set will be aborted and the writing procedure in progress completed. EN. WRITE ONLY. This bit MUST be set to one in order to write any EEPROM register. If the user program will attempt to write the EEPROM when EN= "0" the involved registers will be unaffected and the "busy bit" will not be set. AfterRESET thecontent of EECR registerwill be00H. Notes : When the EEPROM is busy (BS="1") the EECR can not be accessed in write mode, it is only possible to read BS status. This implies that as long as the EEPROM is busy it is not possible to change the status of the EEPROM control register. EECR bits 4 and 5 are reserved for test purposes, and must never be set to "1". Additional Notes on Parallel Mode. If the user wants to perform a parallel programming the first action should be the set to one the PE bit; from this moment the first time the EEPROM will be addressed in writing, the ROW address will be latched and it will be possible to change it only at the end of the programming procedure or by reset-
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MEMORY SPACES (Continued) ting PE without programming the EEPROM. After the ROW address latching the Core can "see" just one EEPROM row (the selected one) and any attempt to write or read other rows will produce errors. Do not read the EEPROM while PE is set. As soon as PE bit is set, the 8 volatile ROW latches are cleared. From this moment the user can load data in the whole ROW or just in a subset. PS setting will modify the EEPROM registers corresponding to the ROW latches accessed after PE. For example, if the software sets PE and accesses EEPROM in writing at addresses 18H,1AH,1BHand then sets PS, thesethree registers will be modified at the same time; the remaining bytes will have no particular content. Note that PE is internally reset at the end of the programming procedure. This implies that the user must set PE bit between two parallel programming procedures. Anyway the user can set and then reset PE without performing any EEPROMprogramming. PS is a set only bit and is internally reset at the end of the programming procedure. Note that if the user tries to set PS while PE is not set there will not be any programming procedure and the PS bit will be unaffected. Consequently PS bit can not be set if EN is low. PS can be affected by the user set if, and only if, EN and PE bits are also set to one.
INTERRUPT The ST6369 Core can manage 4 different maskable interrupt sources, plus one non-maskable interrupt source (top priority level interrupt). Each source is associated with a particular interrupt vector that contains a Jump instruction to the related interrupt service routine. Each vector is located in the Program Space at a particular address (see Table 6). When a source provides an interrupt request, and the request processing is also enabled by the ST6369 Core, then the PC register isloaded with the address of the interrupt vector (i.e. of the Jump instruction). Finally, the PC is loaded with the address of the Jump instruction and the interrupt routine is processed. The relationship between vector and source and the associated priority is hardware fixed for the different ST638x devices. For some interrupt sources it is also possible to select by software the kind of event that will generate the interrupt. All interrupts can be disabled by writing to the GEN bit (global interrupt enable) of the interrupt option register (address C8H). After a reset, ST6369 is in non maskable interrupt mode, so no interrupts will be accepted and NMI flags will be used, until a RETI instruction is executed. If an interrupt is executed, one special cycle is made by the core, during that the PC is set to the related interrupt vector address. A jump instruction at this address has to redirect program execution to the beginning of the related interrupt routine. The interrupt detecting cycle, also resets the related interrupt flag (not available to the user), so that another interrupt can be stored for this current vector, while its driver is under execution. If additional interrupts arrive from the same source, they will be lost. NMI can interrupt other interrupt routines at any time, while other interrupts cannot interrupt each other. If more than one interrupt is waiting for service, they are executed according to their priority. The lower the number, the higher the priority. Priority is, therefore, fixed. Interrupts are checked during the last cycle of an instruction (RETI included). Level sensitive interrupts have to be valid during this period. Table 6 details the different interrupt vectors/sources relationships. Interrupt Vectors/Sources The ST6369 Core includes 5 different interrupt vectors in order to branch to 5 different interrupt routines. The interrupt vectors are located in the fixed (or static) page of the Program Space.
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INTERRUPT (Continued) Table 6. Interrupt Vectors/Sources Relationships
Interrupt Source PC6/IRIN Pin (1) Timer 2 Vsync Timer 1 PC4/PWRIN Associated Vector Interrupt Vector # 0 (NMI) Interrupt Vector # 1 Interrupt Vector # 2 Interrupt Vector # 3 Interrupt Vector # 4 Vector Address 0FFCH-0FFDH 0FF6H-0FF7H 0FF4H-0FF5H 0FF2H-0FF3H 0FF0H-0FF1H
IOR Interr upt Option Register (C8H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Option Register The Interrupt Option Register (IOR register, location C8H) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register can be addressed in the Data Space as RAM location at the C8H address, nevertheless it is write-only register that can not be accessed with single-bit operations. The operating modes of the external interrupt inputs associated to interrupt vectors #1 and #2 are selected through bits 4 and 5 of the IOR register. Figure 18. Interrupt Option Register
Note: 1. This pin is associated with the NMI Interrupt Vector
The interrupt vector associated with the non-maskable interrupt source is named interrupt vector #0. It is located at the (FFCH,FFDH) addresses in the Program Space. This vector is associated with the PC6/IRIN pin. The interrupt vectors located at addresses (FF6H,FF7H), (FF4H,FF5H), (FF2H,FF3H), (FF0H,FF1H) are named interrupt vectors #1, #2, #3 and #4 respectively. These vectors are associated with TIMER 2 (#1), VSYNC (#2), TIMER 1 (#3) and PC4(PWRIN) (#4). Interrupt Priority The non-maskable interrupt request has the highest priority and can interrupt any other interrupt routines at any time, nevertheless the other interrupts cannot interrupt each other. If more than one interrupt request is pending, they are processed by the ST6369 Core according to their priority level: vector #1 has the higher priority while vector #4 the lower. The priority of each interrupt source is hardware fixed.
Unuse d GEN = Global Enab le Bit ES2 = Edge Selection Bit EL1 = Edge Level Selection Bit Unuse d
D7. Not used. EL1. This is the Edge/Level selection bit of interrupt #1. When set to one, the interrupt is generated on low level of the related signal; when cleared to zero, the interrupt is generated on falling edge. The bit is cleared to zero after reset. ES2. This is the edge selection bit on interrupt #2. This bit is used on the ST6369 devices with on-chip OSD generator for VSYNC detection. GEN. This is the global enable bit. When set to one all interrupts are globally enabled; when this bit is cleared to zero all interrupts are disabled (excluding NMI). D3 - D0. These bits are not used.
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INTERRUPT (Continued) Interrupt Procedure The interrupt procedure is very similar to a call procedure; the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event the user does not know about the context and the time at which it occurred. As a result the user should save all the data space registers which will be used inside the interrupt routines. There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes which are automatically switched and so these do not need to be saved. The following list summarizes the interrupt procedure (refer also to Figure 19. Interrupt Processing Flow Chart): - Interrupt detection C main are ex- The flagswithand Z of the and Z routineinterrupt changed the flags C of the routine (resp. the NMI flags) - The value of the PC is stored in the first level of the stack - The normal interrupt lines are inhibited (NMI still active) - The edge flip-flop is reset - The related interrupt vector is loaded in the PC. are saved inside the in- User selected registers(normally on a software terrupt service routine stack) the interrupt found by - The source ofone source isisassociated polling (if more than to the same vector) - Interrupt servicing - Return from interrupt (RETI) switches back - Automatically the ST63xx core interrupt flags) to the normal flags (resp the and pops the previous PC value from the stack The interrupt routine begins usually by the identification of the device that has generated the interrupt request. The user should save the registers which are used inside the interrupt routine (that holds relevant data) into a software stack. After the RETI instruction execution, the Core carries out the previous actions and the main routine can continue. ST6369 Interrupt Details IR Interrupt (#0). The IRIN/PC6 Interrupt is connected to the first interrupt #0 (NMI, 0FFCH). If the IRINT interrupt is disabled at the Latch circuitry, then it will be high. The #0 interrupt input detects a Figure 19. Interrupt Processing Flow-Chart
INSTRUCTION
FE TCH INST RUCTION
EX ECUTE INST RUCTION
WA S THE INST RUCTION A RETI YE S YES
NO
LOAD PC FROM INTERRUPT VECTOR ( FF C / FFD )
?
NO
IS THE CORE ALREADY IN NORMAL MODE ?
SET INTE RRUPT MAS K
CLEA R INTERRUPT MAS K
PUSH THE PC INTO THE STAC K
SELECT PROGRAM FLA GS
SEL ECT INTERNAL MODE FLAG
" POP " THE STACK ED PC CHECK IF THERE IS AN INTERRUPT REQUES T AND INTE RRUPT MASK YES
NO
?
VA000014
high to low level. Note that once #0 has been latched, then the only way to remove the latched #0 signal is to service the interrupt. #0 can interrupt the other interrupts. A simple latch is provided from the PC6(IRIN) pin in order to generate the IRINT signal. This latch can be triggered by either the positive or negative edge of IRIN signal. IRINT is inverted with respect to the latch. The latch can be read by software and reset by software.
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INTERRUPT (Continued) TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is connectedto the interrupt #1 (0FF6H). The TIMER 2 interrupt generates a low level (which is latched in the timer). Only the low level selection for #1 can be used. Bit 6 of the interrupt option register C8H has to be set. VSYNC Interrupt (#2). The VSYNC Interrupt is connected to the interrupt #2. When disabled the VSYNC INT signal is low. The VSYNC INT signal is inverted with respect to the signal applied to the VSYNC pin. Bit 5 of the interrupt option register C8H is used to select the negative edge (ES2=0) or the positive edge (ES2=1); the edge will depend on the application. Note that once an edge has been latched, then the only way to remove the latched signal is to service the interrupt. Care must be taken not to generate spurious interrupts. This interrupt may be used for synchronize to the VSYNC signal in order to change characters in the OSD only when the screen is on vertical blanking (if desired). This method may also be used to blink characters. TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is connected to the fourth interrupt #3 (0FF2H) which detects a low level (latched in the timer). PWR Interrupt (#4). The PWR Interrupt is connected to the fifth interrupt #4 (0FF0H). If the PWRINT is disabled at the PWR circuitry, then it will be high. The #4 interrupt input detects a low level. A simple latch is provided from the PC4 (PWRIN)pin in order to generate the PWRINT signal. This latch can be triggered by either the positive or negative edge of the PWRIN signal. PWRINT is inverted with respect to the latch. The latch can be reset by software. Notes Global disable does not reset edge sensitive interrupt flags. These edge sensitive interrupts become pending again when global disabling is released. Moreover, edge sensitive interrupts are stored in the related flags also when interrupts are globally disabled, unless each edge sensitive interrupt is also individually disabled before the interrupting event happens. Global disable is done by clearing the GEN bit of Interrupt option register, while any individual disable is done in the control register of the peripheral. The on-chip Timer peripherals have an interrupt requestflag bit (TMZ), this bit is set to one when the device wants to generate an interrupt request and a mask bit (ETI) that must be set to one to allow the transfer of the flag bit to the Core.
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RESET The ST6369 devices can be reset in two ways: by the external reset input (RESET) tied low and by the hardware activated digital watchdog peripheral. RESET Input The externalactive low reset pin is used to reset the ST6369 devices and provide an orderly software startup procedure. The activation of the Reset pin may occur at any time in the RUN or WAIT mode. Even short pulses at the reset pin will be accepted since the reset signal is latched internally and is only cleared after 2048 clocks at the oscillator pin. The clocks from the oscillator pin to the reset circuitry are bufferedby a schmitt trigger so that an oscillator in start-up conditions will not give spurious clocks. When the reset pin is held low, the external crystal oscillator is also disabled in order to reduce current consumption. The MCU is configured in the Reset mode as long as the signal of the RESET pin is low. The processing of the program is stopped and the standard Input/Output ports (port A, port B and port C) are in the input state. As soon as the level on the reset pin becomes high, the initialization sequenceis executed. Refer to the MCU initialization sequence for additional information.
Watchdog Reset The ST6369 devices are provided with an on-chip hardware activated digital watchdog function in order to provide a graceful recovery from a software upset. If the watchdog register is not refreshed and the end-of-count is reached, then the reset state will be latched into the MCU and an internal circuit pulls down the reset pin. This also resets the watchdog which subsequently turns off the pulldown and activates the pull-up device at the reset pin. This causes the positive transition at the reset pin. The MCU will then exit the reset state after 2048 clocks on the oscillator pin. Application Notes An external resistor between VDD and the reset pin is not required because an internal pull-up device is provided. The user may prefer to add an external pull-up resistor. An internal Power-on device does not guarantee that the MCU will exit the reset state when VDD is above 4.5V and therefore the RESET pin should be externally controlled.
Figure 20. Internal Reset Circuit
OSCILLATOR SIGNAL COUNTER
1.0k
ST6 INTERNAL RESET
TO ST6
RESET (ACTIVE LOW) VDD 300k
RESET
WATCHDOG RESET
VA000200
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RESET (Continued) Figure 21. Reset & Interrupt Processing Flow-Chart Figure 22. Restart Initialization Program Flow-Chart
RESET
RESET
JP
JP: 2 BYTES/4 CYCLES
RESET VECTOR
NMI MASK SET INT LATCH CLEARED ( IF PRESENT )
INITIALIZATION ROUTINE
SELECT NMI MODE FLAGS
RETI
RETI: 1BYTES/2 CYCLES
PUT FFEh ON ADDRESS BUS
VA00 0181
YES
IS RESET STILL PRESENT ?
NO
LOAD PC FROM RESET LOCATIONS FFE / FFF
FETCH INSTRUCTION
VA000427
MCU InitializationSequence When a reset occurs the stack is reset to program counter, the PC is loaded with the address of the reset vector (located in the program ROM at addresses FFEH & FFFH). A jump instruction to the
beginning of the program has to be written into these locations.After a reset the interrupt mask is automatically activated so that the Core is in nonmaskable interrupt mode to prevent false or ghost interrupts during the restart phase. Therefore the restart routine should be terminated by a RETI instruction to switch to normal mode and enable interrupts. If no pending interrupt is present at the end of the reset routine, the ST6369 will continue with the instruction after the RETI; otherwise the pending interrupt will be serviced. RESET Low Power Mode When the reset pin is low, the quartz oscillator is Disabled allowing reduced current consumption. When the reset pin is raised the quartz oscillator is enabled and oscillations will start to build up.The internal reset circuitry will count 2048 clocks on the oscillator pin before allowing the MCU to go out of the reset state;the clocks are after a schmitt trigger so that false or multiple counts are not possible.
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WAIT & STOP MODES The STOP and WAIT modes have been implemented in the ST6369 Core in order to reduce the consumption of the device when the latter has no instruction to execute. These two modes are described in the following paragraphs. On ST6369 as the hardware activated digital watchdog function is present the STOP instruction is de-activated and any attempt to execute it will cause the automatic execution of a WAIT instruction. WAIT Mode The configuration of the MCU in the WAIT mode occurs as soon as the WAIT instruction is executed. The microcontroller can also be considered as being in a "software frozen" state where the Core stops processing the instructions of the routine, the contents of the RAM locations and peripheral registers are saved as long as the power supply voltage is higher than the RAM retention voltage but where the peripheralsare still working. The WAIT mode is used when the user wants to reduce the consumption of the MCU when it is in idle, while not losing count of time or monitoring of external events. The oscillator is not stopped in order to provide clock signal to the peripherals. The timers counting may be enabled (writing the PSI bit in TSCR register) and the timer interrupt may be also enabled before entering the WAIT mode; this allows the WAIT mode to be left when timer interrupt occurs. If the exit from the WAIT mode is performed with a general RESET (either from the activation of the external pin or by watchdog reset) the MCU will enter a normal reset procedure as described in the RESET chapter. If an interrupt is generated during WAIT mode the MCU behaviour depends on the state of the ST6369 Core before the initialization of the WAIT sequence, but also of the kind of the interrupt request that is generated. This case will be described in the following paragraphs. In any case, the ST6369 Core does not generate any delay after the occurrence of the interrupt because the oscillator clock is still available. STOP Mode On ST6369 the hardware watchdog is present and the STOP instruction has been de-activated. Any attempt to execute a STOP will cause the automatic execution of a WAIT instruction. Exit from WAIT Mode The following paragraphs describe the output procedure of the ST6369 Core from WAIT mode when
an interrupt occurs. It must be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) before the start of the WAIT sequence, but also of the type of the interrupt request that is generated. In all cases the GEN bit of IOR has to be set to 1 in order to restart from WAIT mode. Contrary to the operation of NMI in the run mode, the NMI is masked in WAIT mode if GEN=0. Normal Mode. If the ST6369 Core was in the main routinewhen the WAIT instruction has been executed, the ST6369 Core outputsfrom the wait mode as soon as any interrupt occurs; the related interrupt routine is executedand at the end of the interruptservice routine the instruction that follows the WAIT instruction is executedif no other interrupts are pending. Non-maskable Interrupt Mode. If the WAIT instruction has been executed during the execution of the non-maskable interrupt routine, the ST6369 Core outputs from the wait mode as soon as any interrupt occurs: the instruction that follows the WAIT instruction is executed and the ST6369 Core is still in the non-maskable interrupt mode even if another interrupt has been generated. Normal Interrupt Mode. If the ST6369 Core was in the interrupt mode before the initialization of the WAIT sequence, it outputs from the wait mode as soon as any interrupt occurs. Nevertheless, two cases have to be considered: If the interrupt is a normal interrupt, the interrupt routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the ST6369 Core is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance to their priority. If the interrupt is a non-maskable interrupt, the non-maskable routine is processed at first. Then, the routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the ST6369 Core is still in the normal interrupt mode. Notes : If all the interrupt sources are disabled, the restart of the MCU can only be done by a Reset activation. The Wait instruction is not executed if an enabled interrupt request is pending. In the ST6369 the hardware activated digital watchdog function is present. As the watchdog is always activated the STOP instruction is de-activated and any attempt to execute the STOP instruction will cause an execution of a WAIT instruction.
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ON-CHIP CLOCK OSCILLATOR The internal oscillator circuit is designed to require a minimum of external components. A crystal quartz, a ceramic resonator, or an external signal (provided to the OSCIN pin) may be used to generate a system clock with various stability/cost tradeoffs. The typical clock frequency is 8MHz. Please note that different frequencies will affect the operation of those peripherals (D/As, SPI) whose reference frequencies are derived from the system clock. The different clock generator options connection methods are shown in Figures 23 and 24. One machine cycle takes 13 oscillator pulses; 12 clock pulses are needed to increment the PC while and additional 13th pulse is needed to stabilize the internal latches during memory addressing. This means that with a clock frequency of 8MHz the machine cycle is 1.625µSec. The crystal oscillator start-up time is a function of many variables: crystal parameters (especially RS), oscillator load capacitance (CL), IC parameters, ambient temperature, and supply voltage.It must be observed that the crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1 and CL2 are in the range of 15pF to 22pF but these should be chosen based on the crystal manufacturers specification. Typical input capacitance for OSCIN and OSCOUT pins is 5pF. The oscillator output frequency is internallydivided by 13 to produce the machine cycle and by 12 to produce the Timer and the Watchdog clock. A byte cycle is the smallest unit needed to execute any operation (i.e., increment the program counter). An instruction may need two, four, or five byte cycles to be executed (See Table 7). Table 7. Intructions Timing with 8MHz Clock
Instruction Type Branch if set/reset Branch & Subroutine Branch Bit Manipulation Load Instruction Arithmetic & Logic Conditional Branch Program Control Cycles 5 Cycles 4 Cycles 4 Cycles 4 Cycles 4 Cycles 2 Cycles 2 Cycles Execution Time 8.125µs 6.50µs 6.50µs 6.50µs 6.50µs 3.25µs 3.25µs
Figure 23. Clock Generator Option (1)
Figure 24. Clock Generator Option (2)
Figure 25. OSCIN, OSCOUT Diagram
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INPUT/OUTPUT PORTS The ST6369 microcontrollers use three standard I/O ports (A,B,C) with up to eight pins on each port; refer to the device pin configurations to see which pins are available. Each line can be individually programmed either in the input mode or the output mode as follows by software. - Output - Input with on-chip pull-up resistor (selected by software) - Input without on-chip pull-up resistor (selected by software) Note: pins with 12V open-drain capability do not have pull-up resistors. In output mode the following hardware configurations are available: - Open-drain output 12V (PA4-PA7, PC4-PC7) - Open-drain output 5V (PC0-PC3) - Push-pull output (PA0-PA3, PB0-PB6) The lines are organized in three ports (port A,B,C). The ports occupy 6 registers in the data space. Each bit of these registers is associated with a particular line (for instance, the bits 0 of the Port A Data and Direction registers are associated with the PA0 line of Port A). There are three Data registers (DRA, DRB, DRC), that are used to read the voltage level values of the lines programmed in the input mode, or to write the logic value of the signal to be output on the lines configured in the output mode. The port Data Registers can be read to get the effective logic levels of the pins, but they can be also written by the user software, in conjunction with the related Data Direction Register, to select the different input mode options. Single-bit operations on I/O registers (bit set/reset instructions) are possible but care is necessary because reading in input mode is made from I/O pins and therefore might be influenced by the external load, while writing will directly affect the Port data register causing an undesired changes of the input configuration. The three Data Direction registers (DDRA, DDRB, DDRC) allow the selection of the direction of each pin (input or output). All the I/O registers can be read or written as any other RAM location of the data space, so no extra RAM cell is needed for port data storing and manipulation. During the initialization of the MCU, all the I/O registers are cleared and the input mode with pull-up is selected on all the pins thusavoiding pin conflicts(with the exception of PC2 that is set in output mode and is set high ie. high impedance).
Details of I/O Ports When programmed as an input a pull-up resistor (if available) can be switched active under program control. When programmed as an output the I/O port will operate either in the push-pull mode or the open-drain mode according to the hardware fixed configuration as specified below. Port A. PA0-PA3 are available as push-pull when outputs. PA4-PA7 are available as open-drain (no push-pull programmability) capable of withstanding 12V (no resistive pull-up in input mode). PA6PA7 has been specially designed for higher driving capability and are able to sink 25mA with a maximum VOL of 1V. Port B. All lines are configured as push-pull when outputs. Port C. PC0-PC3 are available as open-drain capable of withstanding a maximum VDD+0.3V. PC4PC7 are available as open-drain capable of withstanding 12V (no resistive pull-up in input mode). Some lines are also used as I/O buffers for signals coming from the on-chip SPI. In this case the final signal on the output pin is equivalent to a wired AND with the programmed data output. If the user needs to use the serial peripheral, the I/O line should be set in output mode while the open-drain configuration is hardware fixed; the corresponding data bit must set to one. If the latchedinterrupt functionsare used (HSYNC, PWRIN) then the corresponding pins should be set to input mode. On ST6369 the I/O pins with double or special functions are: - PC0/SCL (connected to the SPI clock signal) - PC1/SDA (connected to the SPI data signal) - PC3/SEN (connected to the SPI enable signal) - PC4/PWRIN (connected to the PWRIN interrupt latch) - PC6/HSYNC (connected to the HSYNC interrupt latch) All the Port A,B and C I/O lines have Schmitt-trigger input configuration with a typical hysteresis of 1V.
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INPUT/OUTPUT PORTS (Continued) Table 8. I/O Port Options Selection
DDR 0 0 1 DR 0 1 X Mode Input Input Output Option With on-chip pull-up resistor Without on-chip pull-up resistor Open-drain or Push-Pull
I/O Pin Programming Each pin can be individually programmed as input or output with different input and output configurations. This is achieved by writing to the relevant bit in the data (DR) and data direction register (DDR). Table 8 shows all the port configurations that can be selected by the user software.
Note: X: Means don't care.
Figure 27. Port A, B, C Data Register
DDRA, DDRB,DDRC Port A, B, C Data Direction Register ( C4H PA, C5H PB, C6H PC Read/ Write ) D7 D6 D5 D4 D3 D2 D1 D0
Figure 26. Port A, B, C Data Register
DRA, DRB, DRC Port A, B, C Data Register ( C0H PA, C1H PB, C2H PC Read/ Write ) D7 D6 D5 D4 D3 D2 D1 D0
PA0 - PA7 = Data Bits PB0 - PB7 = Data Bits PC0 - PC7 = Data Bits
PA0 - PA7 = Data Direction Bits PB0 - PB7 = Data Direction Bits PC0 - PC7 = Data Direction Bits "0" Defines bit as Inpu t "1" Defines bit as Outpu t
PA7-PA0. These are the I/O port A data bits. Reset at power-on. PB7-PB0.These are the I/O port B data bits. Reset at power-on. PC7-PC0. Set to 04H at power-on. Bit 2 (PC2 pin) is set to one (open drain therefore high impedence).
PA7-PA0. These are the I/O port A data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Reset at power-on. PB7-PB0. These are the I/O port B data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Reset at power-on. PC7-PC0. These are the I/O port C data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Set to 04H at power-on. Bit 2 (PC2 pin) is set to one (output mode selected).
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INPUT/OUTPUT PORTS (Continued) Input/Output Configurations The following schematics show the I/O lines hardware configuration for the different options. Figure 28 shows the I/O configuration for an I/O pin with open-drain 12V capability (standard drive and high drive). Figure 29 shows the I/O configuration for an I/O pin with push-pull and with open drain 5V capability. Figure 28. I/O Configuration Diagram (Open Drain 12V) Notes : The WAIT instruction allows the ST6369 to be used in situations where low power consumption is needed. This can only be achieved however if the I/O pins either are programmed as inputs with well defined logic levels or have no power consuming resistive loads in output mode. The unavailable I/O lines PB0, PB3 and PB7 should be programmed in output mode. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is made from I/O pins while writing will directly affect the Port data register causing an undesired changes of the input configuration.
Figure 29. I/O Configuration Diagram (Open Drain 5V, Push-pull)
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TIMERS The ST6369 devices offer two on-chip Timer peripherals consisting of an 8-bit counter with a 7-bit programmable prescaler, thus giving a maximum count of 215, and a control logic that allows configuring the peripheral operating mode. Figure 30 shows the timer block diagram. The content of the 8-bit counters can be read/written in the Timer/Counter registers TCR that can be addressed in the data space as RAM location at addresses D3H (Timer 1) and DBH (Timer 2). The state of the 7-bit prescaler can be read in the PSC register at addresses D2H (Timer 1) and DAH (Timer 2). The control logic is managed by TSCR registers at D4H (Timer 1) and DCH (Timer