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LCD TV After Service Manual
MODEL:LCD20T5E
Notice: Please read this manual and the user's manual before repairment. This manual is just for reference.
After-sales Service manual
Model: LCD20T5E
Contents:
1Preparation before maintenance......................................................... 1 2Work Principle and Electric connection chart ..........................................2 3Block diagram of electric..................................................................8 4Circuit Principle Chart .....................................................................9 5IC Spec.......................................................................................34 6 Software initialzation Software version view and upgrade instruction ............60 7Exploded Views-Mechanical ............................................................78 8Installation Instruction ..................................................................79 9Maintenance spare part list ...............................................................82 10Trouble Shooting........................................................................84
NoteDisassembly Instructions 1. Preparation before maintenance: Common contents, it mainly expresses the information which need your attention, including the Safety instruction and the Protect measure.. 2. Electric connection chart: Identify the plug specification and the connection between the pins and the board by the unit of PCB. 3. Block diagram of electric: Show the signal processing of the unit in the unit of 1C or circuit. 4. Schematic Diagrams: Provide the circuit chart in the unit of PCB and provide the detailed principle chart with the simple signal processing and control instruction. 5. Software version view and upgrade instruction: The method of software
version view and the software upgrade instruction. 6. Maintenance spare part list: Including the Package, Accessory, PCB, Connector,, etc. and the material list that the service person can replace themselves.
1Preparation before maintenance
1.1Master basic information. Adequate communication with customers is required, to learn how the trouble happens and what the status is. This will help to promote effect and efficiency of the service. Learn if the trouble has conflict with technical standards. 1.2Reappearance of the trouble. Please assure: a. If the trouble exists as the customer described, and make initial judgment of the status, then decide what to do next; b. If any other trouble exists; c. May reset the machine under some instances. For example: when the picture and color could not satisfy the customer, could reset the machine first and then make amendment. Method: Press the "source"button for about five seconds, the" Factory setting" will be displayed, select the" factory reset" and enter, then select the" All Setting( Not include calibration)" and enter. d. Avoid the worse of trouble during the repair. 1.3 Judgment and Repair Judge the status of the trouble and find the reason, then repair. Please cut off the power before disassemble and welding. Read the manual carefully to learn security attentions. Please obey the requirement of Disassemble drawing and description strictly , use specified screw, take care not to make any scars on the machine especially on the LCD. Please wear anti-electrostatic gloves when welding. Please review the status of power, crystal, clock, input and output data. Please read Spare part list if need any change. Check the packing material and accessories when change the machine for the customer.
2
1
Working principle
Introduction
This machine adopts the most advanced Digital Video Processing Technology, using the SMT MST61510 COMS chip, intergrading SDTV, HDTV and PC-RGB Video Decoder, Interlace processor and Digital Video input port and so on. Due to the high integration of MST61510, all video signals can be digital processed within a COMS chip, displaying on LCD Panel in TTL or LVDS signals. The TV sound IF decoding is processed in UOC3, the digital audio will be sent to speaker after sound effect processing. This machine mainly realize the video signal processing display and the corresponding audio signal amplified output of RF(CATV)CVBS(composite video)S-VIDEO(Y/C signal)YPbPr YCbCrVGASCART_RGB,SCART_CVBS. Thereinto, S-VIDEO and CVBS. There is a TUNER in this machine, connecting to RF port. This machine supports an AV signal output and a earphone video output. The AV signal output will be effect when connecting to AV or RF(CATV). There will be no sound output when using earphone.. AV includes
. Audio signal flow
CATV Audio signal flow: TUNERUOC3AMPLIFIERLOUDSPEAKER
2
AV Audio signal flow: Mini I/OI/O UOC3AMPLIFIERLOUDSPEAKER YPbPrYcbCr Audio signal flow: I/OUOC3AMPLIFIERLOUDSPEAKER VGA Audio signal flow: I/OUOC3AMPLIFIERLOUDSPEAKER SCART_AVOUT output Audio signal flow: UOC3I/O output
. Video signal flow
CATV Video signal(TV) flow: TUNERI/OUOC3SCALARPANEL AV1 Video signal flow: I/OUOC3SCALARPANEL SCART_CVBS,SCART_RGB signal flow: I/OUOC3SCALARPANEL YPbPrYcbCr Video signal flow: I/OUOC3SCALARPANEL VGA Video signal flow: I/OSCALARPANEL AV output Video signal flow: Signal inputI/OUOC3I/0 output port
. External controlling signal flow
KEY: Key boardMCU IR: IR&LED boardMCU
Power
This machine adopts external adapter (MODEL:G60DD-SW)
Scalar PCB
The Scalar PCB includes SCALARMCU and sound effect processor. 1SCALAR processes all video signal and displays according with the PANEL requirement and supports OSD display and Menu function. It communicates with MCU, then receives and processes the Data from KEY and IR via MCU.
3
SCALAR PCB also can be called Zoomer. 2Flow of Video signal process The input of CVBS(including TUNER signal S-VIDEO signal of TUNER to U0C3 is via I/O PCB, and after processing it is transmitted to MST61510 and changed into TTL or LVDS, then it is displayed on LCD Panel. MST61510 will go on the in-phase switch of resolution and field, OSD overlapping of the input video signals, and switch it into the resolution required by the LCD PANEL. It transfers the image data of PANEL via LVDS and displays the right image in the PANEL. Note: The analog video signal input into MST61510 are mainly transferred
in difference transfer mode, When maintenance, don't check the `+'signal from all video channels only, please also check whether the `-`single is opened circuit. 3Main sound signal process signal One is SIF signal from TUNER, this is the sound signal without demodulation, and the other one is digital audio signal processed by ADC. SIF1 from TUNER1 will be sent to UOC3 for demodulation, DA transfer, Audio effect process, volume, balance process, then is amplified by amplifier IC (TD1517), and finally, it will be transferred to speaker. The sound process flow of other channels and TV are processed by the UOC3. 4Main system program flow
4
The loading program of MST61510 is saved in the 8M flash chip beside. If the flash chip is destroyed, the TV will can power on and the LOGO won't display. The program upgrade of FLSH chip must be processed via the upgrade port when the internal power supply and the FLASH and MST61510 are all working normally. 5 Some other controls
MST61510 transfers the LVDS to LCD Panel, additionally, it also do some
other controls. Firstly, the power supply and voltage to signal port of PANEL should be decided by the demand of the PANEL. ( 5V to AU LCD Panel, 12V to LG LCD Panel.) Secondly, control the backlight of PANEL. BKL-ON/OFF is controlling the backlight of LCD Panel. >1V means ON <1V means OFF while BRT-ADJ , controls the brightness of backlight. Note: the lower voltage of the BRT-ADJ, the brighter the LCD Panel of TVL1514 will be. General speaking, the voltage of BRT-ADJ is about 0.3V. When the TV display nothing, you should check whether the backlight is on, if not, then you should check whether there is voltage with LVDSVDD. If LVDSVDD is working normal, you should check whether there is some problem with LVDS Cord. Other PCB 1TUNER PCB: To receive TV signal and transfer the RF signal of CATV into CVBS Video signal.
5
The maintenance of TUNER PCB:
Check whether 31 V voltage is normal,
too high or too low voltage will affect the TV receiving. If there is no image display, please test it with AV signal first, if it works normally, then check the TUNER PCB; while if it works abnormally, it may be caused by mainboard. 2 KEY PCB: This machine use touch screen KEY PCB. The seven keys will be sent to coder after processing by touch key IC, the decoder will change the keys into corresponding high-low power level signal and send them to the MCU. 3IR PCB: LED display and remote control receiving. LED is mainly used for indicating the current working status of TV. When the remote control is out of effect, please check whether the connecting of IR and mainboard and the power supply are normal. Press the remote control in normal status, the IR PCB will output the pulse signal, if there is no pulse signal; it means there is some damage to the IR PCB.
6
I/O BOARD
XP5
AU panel pin_1 here XP702
LG panel pin_1 here
PIN 1 J3 XP501
INVERTER BOARD
(ORCAD) 1GND 2GND 3BRT1 4EN 512V 612V
1GND 25VS 3GND 4AV-RIN 5 GND 6AV-LIN 7GND 8. AV-CVBSIN 9. GND 10.AVIN-SC 11. GND 12. AVIN-SY
The European market used 1 to 6pins and 11 to 16pins of J1. 1AV-CVBSOUT 2GND 3AV-ALOUT 4GND 5AV--AROUT 6SGND 7CIN 8GND 9YIN 10GND 11AVIN-CVBS 12GND 13AVIN-L 14GND 15AVIN-R 16GND J8
J7
XP500
1Y 2GND 3PB 4GND 5PR 6GND 7HD-L 8GND 9HD-R 10GND 11NC 12GND 13VGA-HS 14GND 15VGA-VS 16GND 17NC 18GND 19PC5V 20#U5V 21VGAIN-B 22#U5V 23.VGAIN-G 24.GND 25.VGAIN-R 26.GND 27.VGA_ARIN 28.GND 29.VGA_ALIN 30.GND
XP901 1TXD-CPU 2RXD-CPU 3GND 4UOCIII_SCL 5UOCIII_SDA 65V 7GND 8KEY7
XP504
P1
P1
MAIN BOARD
1CARDIR/FDAT 2CARD-FCLK 3CARD-FCMD 4GND 5CARD-PR 6GND 7CARD-PB 8GND 9CARD-Y 10GND 11CARD-R 12GND 13CARD-L The 30pins lie type FPC next contact XP506 The 30pins lie type FPC next contact
CD driver
DVD-ROM/CARD
XP500 1GND 25V 3GND
SJR2 J8 1SC-CVBSIN 2GND 3SC-RIN 4GND 5SC-LIN 6GND 7S-BIN 8S-SW 9S-GIN 10GND 11S-RIN 12S-BLK XP502
1SPKL+ 2GND 3SP_LIN+ 4GND5 SP_RIN+ 6GND 7SPKR+
SIDE IO BOARD
SJR3
XP300
SJ4 XP200
XP502 FOR SCART IN OUT FOR EU 1SC-BLK 2SRGB-R 3SGND 4SRGB-G 5SC-SW 6SRGB-B 7SGND 8SC-AUDIO-LIN 9SGND 10SC-AUDIO-RIN 11SGND 12SC-CVBS-IN
XP503
XP904
XP300 XP400 1GND 212V 312V 4GND
TUNER BOARD TDQ-6F6/T116CW1
1CPU5V 2GND 3IR 4LED-BLUE1 5GND 6LED-R/G 7GND 85V
IR BOARD
SPEAKER
TUNER IF and control signal 1AGC 2GND 3GND 4UOC-SCL 5UOC-SDA 6GND 75VA 8GND 933V 10GND 11IF 12GND
1LED-STB 2BUZZER-CTL 3GND 4NC 5O1 602 7O3
J1
TOUCHKEY BOARD
SPEAKER
7
DVD/CARD-L/R
DVD-ROM OR CARD
DVD-IR
LCD PANNEL
VGA INPUTRGB/HSYNC/VSYNC
DVI
PC-AUDIO-L/R
PC INPUT
HD-AUDIO-L/R HD-Y/PB/PR
SWITCH circuit
IR
74HC04 (U5)
HD INPUT
AVIN_L/R
PI5V330Q 5V(U503) PI5V330Q 5V(U502)
R/G/B_IN1 4502 (U402) R/G/B_IN0 656 TV_HS TV_VS
SC_CVBSOUT SC_L/R_OUT
SC_CVBSOUT
MUTE
MST61510 (U801)
MDQ[0.31 MAD[0.11]
SC-CVBS_IN
SC_CVBSIN
SC_L/R_IN
MCLK MCLKE MDQM[1.2] MWE MCAS/MRAS MBA[0.1]
UOC III (U200)
AV2 INPUT SVIDEO INPUT
AV_CVBSIN
SIDE I/O BOARD
MUTE1
INVERTER BOARD
BKLon/off BKLsadj
AVIN_L/R AV_YCIN
I2C
MSC_RXD UOC_READY
MGND
HEADPHONE
TDA1517 U400
MOUT_L/R
MSC_READ
W79E632 (U701)
LED_R
P4.[3]
KEY6
P2.[6]
MUTE1 MUTE AMP CIRCUIT MUTE MUTE
PIC12F675 (U301)
P1.[1]
P2.[0,2]
P3.2(IR) P3.[3,4](LED)
P3.[0,1]
SPEAKER1
24C16(U201)
SAW_SW
MUTE1
IR
SW circuit
LED_ROout
SPEAKER2
SPEAKER GND
SIF1 SIF2 IF_OUT
RESET CIRCUIT
CTL&LED BOARD FROM ANTENNA TV RF SIGNAL INPUT TUNER BOARD
LED-ON BUZZER-CTL IO[1.3]
8
QT1080 KEY[1,7]
IR IR AND LED BOARD LED_R/B
KEY BOARD
5
4
3
2
1
100p C245 100p C246
L4
FB
0603 C355 4 88 110 90 5 7 9 94 118 100 117 124 3 69 15 47 82 U200 96 93 45
+8V
100p C247
+3.3VA
L3
+5VA1
+3.3VA
+1.8VA
+1.8VA
L201 L202 L203
2.7uH 2.7uH 2.7uH 100p C248 100p C249 100p C250 IF_OUT +5VA1 L200 R200 2.2K 0.56uH
TV_R_PIN85 TV_G_PIN86 TV_B_PIN87 1
5 5 5
T200 4 SAW 5 3 K3953M UOC_VIFIN1 UOC_VIFIN2
C17 100uF/16V
0.1uF
2
VDDA3 VDDA1 VDDP VREFAD VREF_SDAC1 VREF_SDAC2 VREF_SDAC3 VDDA2
VCOMB VP1 VP2 VP3
VADC VDDA
VDD18 VDDC2 VDDC1 VDDC3 VDDC4
VCC8V
R23 R254 NC C239 R255 C240 R256 NC C241 Y_OUT R201 1K C201 0.1uF D200 +5VA 1N4148 R203 R206 R207 100 100 100 1nF NC R204 C205 C206 4.7uF/16V C208 R208 27K R209 4.7K 680 C211 R214 C214 R215 R216 R218 R219 R222 R223 390 1uF C216 100 100 100 100 100 100 C219 1uF 10uF/16V SC_AUD_LOUT_PIN36 SC_AUD_ROUT_PIN37 M_LOUT_PIN60 4 M_ROUT_PIN61 4 5 5 2 10uF/16V C220 C212 10nF 0.1uF 3 0.01uF 1K 2 1 SAW R24 T201 0
0
D
D
NC
NC
R202 RGB
100
NC
5 5 5
NC
SCART_R_IN_PIN78 SCART_G_IN_PIN79 SCART_B_IN_PIN80 5 FBLIN_PIN77 1~3V
C202
C200 0.1uF 0.1uF C203 0.1uF
78 79 80 77 70 71 72 73 55 58 51 59 52 48
R3/Pr G3/Y B3/Pb INSSW3 V/R2/Pr U/B2/Pb Y/G2/Y YSYNC
YOUT UOUT/INSSW2 VOUT/SWO1 CVBSO/PIP ROUT GOUT BOUT BCLIN BLKIN SVM FBISO HOUT
74 75 76 64 85 86 87 83 84 65 66 67 31 43 44 41 42 46 36 37 60 61 62 63 106 105 104 103 102
4 5 3 K9656M
UOC_SIF1 UOC_SIF2
Y_OUT C237 C209
R205 0.1uF C207 0.1uF C210
0
C204
0.1uF
BA792????
5 CVBSIN_PIN55 5 DVD_Y2IN_PIN58 5 SC_CVBSIN_PIN51 5 DVD_C2IN_PIN59
0.1uF 0.1uF
CVBS2/Y2 CVBS3/Y3 CVBS4/Y4 C2/C3 C4 SVO/CVBSI VIFIN1 VIFIN2 SIF1 SIF2 AUDIO2_INL AUDIO2_INR AUDIO3_INL AUDIO3_INR SECPLL EWD/AVL AUDIO4_INL AUDIO4_INR AUDIO5_INL AUDIO5_INR SSIF VDRA VDRB DECBG IREF VSC EHTO GNDIF PH1LF PH2LF DECSDEM QSSO REFAD VGUARD DECDIG XIN XOUT
T202 TV_VOUT_PIN22 +5VA 8 TV_HOUT_PIN67 8 IF_OUT 4 SAW 5 3 2 K2974D UOC_VIFIN2 1 UOC_VIFIN1
5
SC_CVBSOUT_PIN48 C13 NC
R211
1K C14 NC UOC_VIFIN1 UOC_VIFIN2 UOC_SIF1 UOC_SIF2
R253 R212
24 25 29 30 53 54 56 57
AGC IFVO FMRO PLLIF
SAW K2974D: only for PAL
Q200 R210 1 MMBT3904 R213 1K 1K
C
C
6 6 4 4
PC_AUD_LIN_PIN53 PC_AUD_RIN_PIN54 DVD_AUD_LIN_PIN56 DVD_AUD_RIN_PIN57 +5VA1 R217 NC C242 0.22uF C221 0.22uF
UOC3
SIFAGC AGC2SIF AUDOUTSL AUDOUTSR AUDOUTLSL AUDOUTLSR AUDOUTHPL AUDOUTHPR P00/I2SDI1/O P01/I2SDO1 P02/I2SDO2 P03/I2SCLK P04/I2SWS
19 21 49 50 34 35 33 23 22 20
5 5 5 5
HD_AUD_LIN_PIN49 HD_AUD_RIN_PIN50 SC_AUD_LIN_PIN34 SC_AUD_RIN_PIN35 R227 R229 8 TV_VOUT_PIN22 R252 100 R232 C226 C227 10uF/16V R238 +3.3VA C228 0.1uF C229 1K C231 C16 C232 0.22uF/0.1uF 10uF/16V 3.3nF/1nF 2.2uF/16V R235 C230 4.7nF 8.2K 150nF R233 100K 39K NC 4.7K
TP204 TP203 R226 R228 R230 R231 INT0 P10/INT1 P11/T0 P12/INT2 P13/T1 P14/RX P15/TX P16/SCL P17/SDA P20/TPWM P21/PWM0 P22/PWM1 P23/PWM2 P24/PWM3 P25/PWM4 VSSC VSSC VSSC VSS_REF VSS_COMB VSSADC P30/ADC0 P31/ADC1 P32/ADC2 P33/ADC3 97 98 99 126 107 127 128 108 109 111 112 113 114 122 123 115 116 119 120 R251 R225 R234 R236 R237 R239 R240 R241 R242 NC 100 100 100 100 100 100 100 DVD_AUDIO_SW R224 100 R265 3.3K 100 100 100 3K NC +3.3VA IR 3,5,7 INT 7,8 UOC_READY NV_SCL NV_SDA I2S_DAT I2S_CLK I2S_WS TP200 TP201 TP202 R221 NC MUTE 7 UOC_SCL UOC_SDA DVD_AUDIO_SW 4 MSC_READ 7 R243 R244 R245 R246 R247 R248 R249 R220 3.3K 3.3K 3.3K 3.3K 3.3K NC NC 3.3K +3.3VA R250 100 STAT_AV_PIN115 R257 10K +5VA 1 12 6 8 101 121 125 89 68 95 92 2 R259 +5VA R258 C244 10uF/16V C252 0.1uF 39K C243 10uF/16V 5 AGC1 1 2 3 UOC_SCL 4 UOC_SDA 5 6 7 8 33V9 10 11 12 AGC 1 2 3 4 5 6 7 8 9 10 11 12 TP206 TP207 5,7 5,7 1 2 3 4 2mm +5VA
B
+3.3VA
27 26 32 28 17 16 38 39 91 13 14
3,4,7 TO J18 XP201
SAW_SW
B
R266
NC C233 47uF/16V C234 0.1uF +5VA1 24.576MHZ Z200
10 11
GREF_SDAC1 GREF_SDAC2
GNDA1 GNDA2 GNDA3
GNDA GNDA
C238 0.1uF U201 1 A0 2 A1 3 A2 4 GND 24C16
VCC WP SCL SDA
8 7 6 5
NC NV_SCL NV_SDA
NC
18 40 81
C235
C236
GNDA VSSC
TO J10 XP200
TP205
68K
+5VA
+33V R263 470 R22 0.56uH R261 4.7K 3 Q201 1 C388 2 R262 1K IF_OUT R290 4.7K 22 Size A3 Date: R21 0.56uH L205 100 C251 10uF/50V C253 0.1uF C254 10nF
TP208 2.0MM TP209 TP210
A
A
C255 10uF/16V
C256 0.01uF
C12
TO TUNER
0.1uF
Mstar semiconductor Co.,Ltd Shanghai Branch 021-54070188*21
Title
9
IF_OUT R264
UOC3+MST61510A BOARD
Document Number
2.UOC3
Monday, December 05, 2005 Sheet
1
Rev 1 2 of 9
5
4
3
2
5
4
3
2
1
XP300 1 2 3 4 4MM 12VU J7 FOR 12V POW IN
R300
R328 CUP_5V 27/2W R17 27/2W C364 C363 0.1uF R18 27/2W 10uF/16V L303 FB D306 12VU 2,5,7 IR LED_R R327 330 C321 12VA C307 0.22uF 5.1V C323 1uF/50V R309 4.7K R313 3 R307 4.7K 1 47uF/16V D305 100P R310 510 LEDR1 RTC_INT R325 0/NC 1 2 3 4 U301 VCC GP5 GP4 GP3 VSS AN0 GP1 GP2 8 7 6 5 NC C1 C2 0.1uF 1 VIN U309 1 VOUT 2 3 C365 RC317 10uF/16V C305 0.1uF C306 C309 C308 0.01uF 470uF/50V 470uF/50V C3 0.1uF 12VU GND
0 U303 LM2596 VIN ON/OFF GND TAB FB OUT 4 2 L300 Chock 47u/5A D300 SR34/5A C300 C302 0.1uF 5V L304 FB
D
PWM 5VPN
D
10uF/16V
L305 R301 NC
FB
3
TP300
CUP_5V
5
6
U5V L302FB
5V
R314 NC
470uF/25V
12VU KEY6 Stby KEY6 MUTE 7 R311 2,4,7 NC/0 R312 0 1
U304 LM2596 VIN ON/OFF GND TAB FB OUT 4 2
R318
L311 FB
DVD_5V
NC/PIC12F675 C322
0 L301 Chock 47u/5A D307 SR34/5A C301
L312 C303 0.1uF
FB
3
C304 0.1uF R316 NC
5
6
R317 NC
470uF/25V
C
C
1
100 Q303 3904 C313 3 1uF/50V
5V D301 C316 BAV99 1uF/50V R315 0 R322 10K R323 R320 7 D302 C317 +33V +5VA TP10 HOLE 33V 1 GND 3 33V D304 C330 C331 C320 1uF/50V 0.1uF 0.1uF 3 3 2 2 1 1 3 10uF/16V TP11 HOLE 4 D303 4 3 3 2 2 1 1 BAV99 1uF/50V STANDBY 0 4.7K R319 1 STn 3 STn 1 4.7K Q305 C328 0.1uF 3904 CUP_5V R321 10K L308 C327 0.1uF 3 NC
5VD
PWM 4.7K
1 2
Q302 3904
2
R308
3
2
C326 Q304 3904 C329 0.1uF 470uF/16V Q309 1 2 G D S Si2315 Q308 3
1
C314 3 1uF/50V 2 12VU 12VA L306 5V FB L307 L309 5V L310 FB C335C340C341C348 0.1uF 0.1uF 0.1uF 0.1uF 5V 12VA +8V U308 1 C345 10uF/16V C346 0.1uF VIN VOUT 2 3 C366 C347 RC317 10uF/16V C342 10uF/16V
A
4
9 6 7 8
9 8 12VU R302 10K
2
5V
2
5 5 6
1 2
G D S Si2315
3
C315 FB FB +5VA1 3
7
+5VA
1
C310 12VA Q307 Q300 3904 2 1 2 G D S Si2315 Q306 3
C318 BAV99 1uF/50V R306 1K
u574
B
2
1uF/50V 2
R303 9 8 4.7K 1
B
6 7
4 5 5 6
9 8
C336 10uF/16V
7
5VA 3 C324 470uF/16V C311 0.1uF
+5VA 3 1 IN GND
U305 VO VO 4 2
+3.3VA 3 3 2 2 1 1 R304 10K 9 8 R305 1 4.7K C332 10uF/16V C349C350C351C352C353C354 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF TP12 HOLE
C325 0.1uF 3
1 2
G D S
Si2315 C312 0.1uF
4
L2
NC
C333 10uF/16V
C334 0.1uF
RC1117/3.3V
6
7
6 7
4 5 5
9 8
Q301 3904 2
GND
+5VA1 U307 3 C343 0.1uF 1 IN GND VO VO 4 2
+1.8VA 3 3 2 2 1 1
CUP_5V C24 LED 3 9 8 C25 1 2 4.7K 4.7K Q1 3904 C356C357C358C359C361C360C362 C344 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF/16V TP13 HOLE
0.1uF
4
4
9 6 7 8
RC1117/1.8
5 5 6
A
+5VA : 5V for SYSTEM +3.3VA : 3.3V for UOC +1.8VA : 1.8V for UOC
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24
7
Mstar semiconductor Co.,Ltd Shanghai Branch 021-54070188*21
Title
10
Size A3 Date:
5 4 3 2
UOC3+MST61510A BOARD
Document Number
3.POWER
Monday, December 05, 2005 Sheet
1
Rev 1 3 of 9
5
4
3
2
1
5V XP400 1 2 3 4 5 6 7 2.0mm
D
L400 SPK_L TP401 SPK_L+ SPK_R+ MUTE1 TP405 TP402 TP403 TP404 5 DVD_R 5 AV_AUD_RIN 5 DVD_L 5 AV_AUD_LIN 12VA 12 14 15 11 1 5 2 4 6 DVD_AUDIO_SW R420 C402 0.1uF C403 470uF/16V 0 10 9 7 X0 X1 X2 X3 Y0 Y1 Y2 Y3 INH A B VEE R421 R422 R423 R424 16 4.7K 4.7K 4.7K 4.7K C422 0.01u C423 47uF/16V
5V 10uH
R416 1K R3 R5 NC
R417 1K
VCC
SPK_R
C10 NC 2
10uF/16V
DVD_AUD_LIN_PIN56
2
D
R418 X 13 0 R419 Y 3 0
1
Q404 3906 3 1
2 Q405 3906 3
C11
10uF/16V
DVD_AUD_RIN_PIN57
2
J8 FOR SPEAKER
10 11 12 13 14 15 16 17 18
FB400 FB0805 2 DVD_AUDIO_SW
R2 GND U402 74HCF4052 NC
R4 NC
IN1 SGND SVRR OUT1 GND OUT2 VPP MUTE IN2
8
U400
GND GND GND GND GND GND GND GND GND
2
M_LOUT_PIN60
C404 1uF C405 470uF/16V SPK_R+ 470uF/16V SPK_L+ C407 1uF C406 R404 10K R405 C408 10K 100uF/16V NC/1K 2 R19 3 MUTE1 R406 10K SPK_L 2 1 SPK_R 2 1
1 2 3 4 5 6 7 8 9
TDA1517-1 XP401 J19 CONN FLEX 2
R1 R6
0 0
2
C
M_ROUT_PIN61
FOR SPEAKER
XP402 J20 CONN FLEX 2
C
R407 1 Q401 1 3904 1K MUTE 2,3,7 TP1 1 TP2
High(>8.5V):On Low(<2V):Standby/Mute
R16 150K R15 MUTE1 15K
U401 1 2 3 4 S1 G1 S2 G2 D1B D1A D2B D2A SI9945DY 8 7 6 5 TP400
B
B
A
A
Mstar semiconductor Co.,Ltd Shanghai Branch 021-54070188*21
Title
11
Size A3 Date:
5 4 3 2
UOC3+MST61510A BOARD
Document Number
4.AUDIO
Monday, July 11, 2005 Sheet
1
Rev 1 4 of 9
5
4
3
2
1
TP516 TP517 TP518 XP501
TP519 R572 2.4K TP520 R575 2.4K 10uF/16V 10uF/16V R574 10K C9 C6 HD_AUD_RIN_PIN50 HD_AUD_LIN_PIN49 2 2 +5VA +5VA DVD_5V XP506 TO J15 XP507 TO J15 XP508 R573 DVD_RXD R584 DVD_TXD R585 0 0 0 DVD_IR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
R501 C501 22K R504 TP521 TP522 VGA_H_SYNC VGA_V_SYNC 6 6 TP523 75 15K R505 10uF/16V
+5VA
R571 10K +5VA
3
+5VA
R502
1 2
Q512 3904 R594 75 HD_Y TP536 TP537
1 2
Q510 3904 R590 75 Pr R508 C503
R503 +5VA
C502
22K
R593
22K R589 R509 10uF/16V 220 TP524 PC_5V 6 #U5V 6 VGAIN_B VGAIN_G VGAIN_R TP525 75 15K
1 2
Q511 3904 R592 75 Pb
R506
R507 10uF/16V 15K
220
TP538 7 7 SDA5 SCL5 R564 R563 R562 R561 R560 R559 R558 R557 TP539 0 0 0 0 0 0 0 0
75 R591
XP505
220 6 6 6 6 6 +5VA L500 10uH TP526 TP527 TP528 +5VA TP529 Pr HD_Y Pb R500 10K C500 6 6 6 PC_RIN PC_GIN PC_BIN U502 C505 J14 FOR KARD IN
#PC_AUD_RIN_PIN54 #PC_AUD_LIN_PIN53
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6 7 8 9 10 DVD_RXD 11 DVD_TXD 12 13 DVD_IR 14 15 16 DVD_FDAT 17 18 19 20 DVD_Y 21 22 23 DVD_PB 24 DVD_PR 25 26 27 DVD_R 28 29 DVD_L 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 DVD_PB 6 7 DVD_PR 8 9 10 DVD_Y 11 DVD_RXD R569 0 12 DVD_TXD R567 0 13 DVD_+1.8VA 14 15 16 DVD_+3.3VA 17 18 19 20 21 22 23 24 25 R568 0 26 DVD_IR 27 28 DVD_5V 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CON30
DVD_5V
DVD_+1.8VA
CON13 2MM TP540
CON30 J15 FOR DVD IN
CON30 FPC1MM
DVD_PB TP541 TP542 DVD_R DVD_L J16 FOR DVD OPEN/CLOSE XP504 CUP_5V DVD_R 4 4 DVD_Y DVD_PR DVD_L C19 47uF/16V
0.1u TP543 R595 R596 R597 R517 100 HD/PC_SW 7 100 100 100 C526 473 C527 473 C529 473 C528 102
+5VA
3
2 5 11 14 3 6 10 13
S1AIN S2AIN S3AIN S4AIN S1BIN S2BIN S3BIN S4BIN
VCC D1 D2 D3 D4 SEL /EN GND
16 4 7 9 12 1 15 8
RIN0 GIN0 BIN0 SOG0
8 8 8 8
R543 2.4K R545 2.4K AV_AUD_LIN AV_AUD_RIN
C
R514 4 4 15K 10uF/16V
1 2
Q500 3904 C504 0.01uF DVD_C2IN_PIN59 R513 2
PI5V330Q
1 2 3 4 5 6 7 8
2mm
MCU_TXD MCU_RXD UOC_SCL UOC_SDA
7 7 2,7 2,7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
3
3
D
CON45 KEY_DVD_OPEN/CLOSE
TP534 TP533 TP535 TP532 TP531 TP530 R570 0 C521 +5VA 10uF/16V C21 Q505 3904 DVD_5V 0.1uF R556 75 U501 DVD_+1.8VA C522 0.1uF DVD_5V U500 DVD_+3.3VA
3
R510 Q501 3904 C507 R511 DVD_Y2IN_PIN58 0.1uF R516 1.5K 2 75 10K
3 1
IN GND
VO VO
4 2
C520 10uF/16V
C
1
R547 10K 6.8K 10K R548 10uF/16V R515
2
C506
+5VA 1.8K C519 0.1u U503 CVBSIN_PIN55 2 DVD_PR DVD_Y DVD_PB R550 100 +5VA L501 10uH
RC1117/3.3V
1 2
3
3
RIN1 8 C523 C524 0.1uF
IN GND
VO VO
4 2
C525 10uF/16V
J1 FOR AV IN OUT
R542
R512 75 C518 100pF TP500 TP501 TP502
2 2 2
TV_R_PIN85 TV_G_PIN86 TV_B_PIN87
75
2 5 11 14 3 6 10 13
S1AIN S2AIN S3AIN S4AIN S1BIN S2BIN S3BIN S4BIN
VCC D1 D2 D3 D4 SEL /EN GND
16 4 7 9 12 1 15 8
R555 R552 100 100 +5VA
1
3
R551
10uF/16V Q506 3904 220 75 GIN1 8
RC1117/1.8
1 3 1 2
Q508 3904
2
R553 75 BIN1 8 220
C20 0.1uF R566
R554
NC/PI5V330Q
XP500
R565
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1AV_ACVBSout 2 AV_ALout 3 4 AV_ARout 5 6 7 8 9 10 11 12 AVin_L 13 14 AVin_R 15 16
220 R586 AVin_svideo_SC AVin_svideo_SY AVin_CVBS TP503 TP504 TP505 R531 TP506 220 TP507 2 12VA +12V_AUDIO 2 SC_CVBSOUT_PIN48 1 3 R519 4.7K 100uF/16V Q504 3906 2mm 100 R576 2,3,7 Q503 3904 C509 10uF/16V R523 6.8K 1K 1K 47K R524 R526 2 SC_AUD_ROUT_PIN37 C512 100pF C513 100pF 330 330 R525 R527 1K 1K 10uF/16V R535 R544 R546 R537 R536 C515 TP508 R539 R540 R538 75 75 75 TP509 TP510 XP502 TP512 75 75 100pF 100pF R541 3.3K 100pF
A
0 0 R549 0 100 DVD/TV_SW 7 CUP_5V
R587 +5VA R534 75 R588
J13 FOR KARD POW C514 XP503
DVD_5V R582 TP544 R583 4.7K R581 R580
CON16 1.25 FPC
3
1 2 3
B
4.7K
DVD_IR Q509 3904 100
1 2
3 1
Q507 3904 R577 22K
R518
3
2
SC_AUD_LOUT_PIN36
C508
4.7K R579 C510 R529 R533 100pF 47K 100pF C4 10uF/16V C5 SC_AUD_RIN_PIN35 SC_AUD_LIN_PIN34 STAT_AV_PIN115 FBLIN_PIN77 2 2 2 2 2 C511 7 DVD_IR_SW NC/100
2
R520 6.8K
R521 R522 10uF/16V
2
2
R578 100
1
Q502 3904
1
3
4.7K
IR
10K 100 100 C516 C517
2 2 2
SCART_B_IN_PIN80 SCART_G_IN_PIN79 SCART_R_IN_PIN78
R528 R530 R532
100 100 100
SC_CVBSIN_PIN51
A
J9 FOR SCART IN OUT
option for EU
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10 11 12
TP511 TP513 TP514 TP515 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40
Mstar semiconductor Co.,Ltd Shanghai Branch 021-54070188*21
Title
CON12 FPC 1.25MM
12
4 3 2
UOC3+MST61510A BOARD
Size A2 Date: Document Number
5.VIDEO Connector
Monday, July 11, 2005
1
Rev 1 Sheet 5 of 9
5
5
4
3
2
1
PC AUDIO INPUT
TO J4
D
D
5 5
VGA_H_SYNC VGA_V_SYNC
VGA_H_SYNC VGA_V_SYNC U5V L603 FB/0603 L601 FB/0603 L600 FB/0603 R625 75 C7 #PC_AUD_RIN_PIN54 #PC_AUD_LIN_PIN53 R638 5.1K R639 5.1K C617 R640 100P 5.1K 10uF/16V C618 100P C8 PC_AUD_RIN_PIN54 2 R637 5.1K 10uF/16V PC_AUD_LIN_PIN53 2 R617 100 R618 100 R619 100 C607 C608 C609 473 473 473 GNDR0 GNDG0 GNDB0 8 8 8 C604 R623 C606R624 NC 75 NC 75 C605 NC
5 5 5 5 5 5 5
PC_5V #U5V VGAIN_B VGAIN_G VGAIN_R
PC_5V #U5V VGAIN_B VGAIN_G VGAIN_R
PC_RIN PC_GIN PC_BIN
5 5 5
L610 FB/L0603
#PC_AUD_RIN_PIN54 #PC_AUD_LIN_PIN53
L609 NC
U5V
C
D613 5V6
D614 5V6 R13 2.2K/NC 3 D602 BAV99 2 1 2 1 U5V R7 0 3 R14 2.2K/NC
L602 FB/0603 L604 FB/0603
R628 100 R630 100
H_SYNC0 V_SYNC0
8 8
C
C610 C611 NC NC
D603 BAV99
U5 R8 0 R9 5.1K
B
L1 VCC A6 Y6 A5 Y5 A4 Y4 14 13 12 11 10 9 8 R12 R10 R11 0 0 0 C15 0.1u
CUP_5V 0603
1 2 3 4 5 6 7
A1 Y1 A2 Y2 A3 Y3 GND
TC74HCU04AF
B
PLUG-VGA
7
A
A
Mstar semiconductor Co.,Ltd Shanghai Branch 021-54070188*21
Title
13
Size A3 Date:
Document Number
UOC3+MST61510A BOARD 6.Vga_Dvi Connector
Sheet
1
Rev 1 9
Monday, July 11, 2005
6
of
5
4
3
2
5
4
3
2
1
CUP_5V KEY6 TP700
D
3
C707 1u/16V reset pulse Minimum 100us, active low R701 8K2 D700 4148 Z701 22.1184MHZ CUP_5V 1 2 3 4 RP705 R711 4.7K R710 8 7 6 5 4.7K 2,8 INT INT 8 7 6 5 RP706 C702 10P R707 NC C703 10P 1 2 3 4 R715 10K
C701 104
L700 FB C709 47U/16V 44 RP703
CUP_5V
RP704 TP701 CUP_5V 4 3 2 1 4 3 2 1
D
1 2 3 4 1 2 3 4
TP702 TP703 RP701 4.7K
U701 W79E632
35 21 20 10 EA/VP XTAL1 XTAL2 RESET
RP702 4.7K 5 6 7 8 5 6 7 8 BUD0 BUD1 BUD2 BUD3 ALE 8
8 7 6 5 8 7 6 5
4.7K
4.7K
IR1 R704 101 R703 100
14 15 16 17 2 3 4 5 6 7 8 9
INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
C
3 STANDBY 2,3,4 MUTE 5 DVD_IR_SW 5 HD/PC_SW 5 DVD/TV_SW 6 PLUG-VGA 2 MSC_READ CUP_5V R717 4.7K
P4.3
R724
470
P4.1
VSS
STANDBY MUTE RSTn HD/PC_SW DVD/TV_SW #PLUG-VGA MSC_READ
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P4.2 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P4.0 P3.7/RD P3.6/WR PSEN ALE/P P3.1/TXD P3.0/RXD
43 42 41 40 39 38 37 36 1 24 25 26 27 28 29 30 31 23 19 18 32 33 13 11
4.7K
10K
KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 PANEL_EN LED_G1 SCL_MST1 SDA_MST1 TP704 TP705 TP706
MBU0 MBU1 MBU2 MBU3 ALE UOC_READY UOC_SDA UOC_SCL XP701 1 LED 2 LED_Rout 3 4 5 KEY2 6 KEY1 7 CUP_5V KEY0 8 2.0mm
VCC
XP5 1 2 3 4 5 6 7 8 BUD[0..3] 8 UOC_READY 2 UOC_SDA 2,5 UOC_SCL 2,5
CUP_5V
J6 FOR KEY
PANEL_EN 9 CUP_5V R720 3.3K R719 3.3K R718 R705 NC
R702 4.7K RST_MST 8
C
22
12
34
CUP_5V R716 4.7K SCL5 SDA5 CUP_5V C706 104 1 2 3 4 A0 A1 A2 GND VCC WP SCL SDA 8 7 6 5 CUP_5V BKLon/off 9 LED_R R712 5.1K R713 5.1K K700 2 R722 CUP_5V 0 C708 47U/16V C704 104 3 8 1 PWMOUT0 PWMOUT0 WRZ 8 RDZ 8 BKLadj 9 CUP_5V R721 0 TP707 R723 NC TP708 TP709 R708 4.7K 5V R709 4.7K MCU_TXD MCU_RXD MCU_TXD 5 MCU_RXD 5 2,3,5 IR IR LED_G LED_Rout 5V U1 KEY3 KEY4 1 2 3 4 A0 A1 A2 GND 24C16 VCC WP SCL SDA 8 7 6 5 KEY5 KEY6 TP711 TP710 C705 22P 1 2 3 4 5 6 7 8 2mm XP702
B
CUP_5V R728 R714 R725 33 R726 33 R727 33 470
5 5
SCL5 SDA5
R706 4.7K
10K
LED_R 150
3
U702 24C16
B
J11 FOR REMOTE
A
A
Mstar semiconductor Co.,Ltd Shanghai Branch 021-54070188*21
Title
14
Size A3 Date:
5 4 3 2
UOC3+MST61510A BOARD
Document Number
7.Mcu
Monday, December 05, 2005 Sheet
1
Rev 1 7 of 9
5
4
3
2
1
+3.3AVDD
AVDD_DVI
+3.3V
VDDP +3.3AVDD AVDDPLL2
L800
FB0805
pin4,pin10 C811 C845 47uF/16V 0.1uF C812 0.1uF
+ 3 . 3 V V D D P
f o r
L807 FB0805 pin66,pin162,pin182 C813 C851 47uF/16V 0.1uF C814 0.1uF C815 0.1uF
V c c 3 . 3 f o r d i g i t a l
5VD
U803
+3.3V
3
C853 47uF/16V
VIN ADJ
VOUT TAB
2 4
C809 C844 47uF/16V 0.1uF
1
+ 3 . 3 A V D D A V D D _ D V I
f o r
3 . 3 V f o r A V D D _ P L L 2
L801
FB0805
pin109 C833 C808 47uF/16V 0.1uF
AIC1117-3.3CY/TO263
+3.3AVDD
D
AVDD_PLL
+ 3 . 3 M V D D ( S D R A M )
+3.3V MVDD33 pin12 C816
f o r V D D M 1 . 8 V V D D C f o r
V c c 3 . 3 f o r a n a l o g
5VD
U804
+3.3AVDD
3 1
C850 47uF/16V
VIN ADJ
VOUT TAB
2 4
C810 C848 47uF/16V 0.1uF
D
L802
FB0805
+ 3 . 3 A V D D A V D D _ P L L
f o r
AIC1117-3.3
C837 47uF/16V
0.1uF
L803
FB0805
pin86, pin102,pin113,pin125,pin139,pin154 C817 C849 47uF/16V 0.1uF C818 0.1uF C819 0.1uF C820 0.1uF C821 0.1uF C822 +1.8V 0.1uF VDDC
V c c 1 . 8
+3.3V U802 +1.8V
+3.3AVDD
AVDDA +3.3V L804 FB0805 C865 100uF/10V C832 0.1uF 0.1uF C840 47uF/16V 0.1uF pin63,pin79,pin131,pin49,pin156, pin173,pin185,pin195 C823 C824 C825 C826 C827 C828 C829 VDD_MPLL L806 FB0805 pin204 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C846 47uF/16V
3 1
VIN ADJ
VOUT TAB
2 4
C847 47uF/16V C807 0.1uF
L805
FB0805
pin17,pin34 C830 C839 47uF/16V C831
+ 3 . 3 A V D D A V D D A
f o r
+ 3 . 3 V f o r A V D D _ M P L L
AIC1117-1.8/TO263
VDDC AVDD_DVI MVDD33 AVDDA VDD_MPLL VDDP L808 0603
AVDD_PLL R821 R820 R819 R818 5 6 7 8 33 33 0 0 DHS DVS DRO7 DRO6 DRO5 DRO4 DRO3 DRO2 DHS 9 DVS 9 DRO7 9 DRO6 9 DRO5 9 DRO4 9 DRO3 9 DRO2 9
AVDDPLL2
VDDC
4 3 2 1
0
204
63 79 131 156 173 185 195
86 102 113 125 139 154
C
U801 AVDD_DVI
199 198 197 196 193 192 191 190 189 188
66 162 182
17 34
109
RN804
49
4 10
12
C
AVDD_DVI AVDD_DVI
VDDP VDDP VDDP
VDDM VDDM VDDM VDDM VDDM VDDM
AVDD_MPLL
AVDD_PLL
AVDD_PLL2
AVDD_ADC AVDD_ADC
VDDC
VDDC VDDC VDDC VDDC VDDC VDDC VDDC
NC NC LHS LVS R7 R6 R5 R4 R3 R2
C852
R802
390 1%
207 208 2 3 5 6 8 9 11 14 15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 36 37 38 39 40 41 42 43 44 45 46 47 48 51 52 53 54 55 56 57 58 59 60 61 77
DVI_R+ DVI_RDVI_G+ DVI_GDVI_B+ DVI_BDVI_CK+ DVI_CKREXT DDCD_DA DDCD_CK HSYNC1 VSYNC1 BIN1 BIN1M SOGIN1 GIN1 GIN1M RIN1 RIN1M BIN0M BIN0 GIN0M GIN0 SOGIN0 RIN0M RIN0 HSYNC0 VSYNC0 RMID REFP REFM
2 2 5
TV_HOUT_PIN67 TV_VOUT_PIN22 BIN1 GIN1 RIN1 R809 R810 R812 R813 R814
R806 R807
5 5
100 100 R805 100 C859 0.047u BIN1_PIN28 R808 100 C860 0.047u GND_BIN1 R811 100 C861 473 R815 100 C862 0.047u GIN1_PIN30 R816 C863 0.047u GND_GIN1 C864 RIN1_PIN33 100 R817 100 0.047u GND_RIN1 R804 100 C858 0.047u
I N P U T
SOG
LVB0M/R1 LVB0P/R0 LVB1M LVB1P LVB2M LVB2P LVBCKM LVBCKP LVB3M LVB3P LVA0M LVA0P LVA1M LVA1P LVA2M LVA2P LVACKM LVACKP LVA3M, LVA3P DQS[0] MDATA[0] MDATA[1] MDATA[2] MDATA[3] MDATA[4] MDATA[5] MDATA[6] MDATA[7] MDATA[8] MDATA[9] MDATA[10] MDATA[11] MDATA[12] MDATA[13] MDATA[14] MDATA[15] DQS[1] DQM[0] DQM[1] DQS[2] MDATA[16] MDATA[17] MDATA[18] MDATA[19] MDATA[20] MDATA[21] MDATA[22] MDATA[23] MDATA[24] MDATA[25] MDATA[26] MDATA[27] MDATA[28] MDATA[29] MDATA[30] MDATA[31] DQS[3] MADR[11] MADR[10] MADR[9] MADR[8] MADR[7] MADR[6] MADR[5] MADR[4] MADR[3] MADR[2] MADR[1] MADR[0] WEZ CASZ RASZ BADR[0] BADR[1] MCLK MCLKZ MCLKE MVREF
187 186 181 180 179 178 177 176 175 174 171 170 169 168 167 166 165 164 161 160 153 152 151 150 149 148 147 146 145 144 143 142 141 138 137 136 135 134 133 101 100 99 98 97 96 95 94 93 92 91 90 89 88 85 84 83 82 81 130 129 128 127 124 123 122 121 120 119 118 117 116 115 112 111 110 107 106 105 104
RN809
+3.3V +3.3V C857C854C855C856
5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8
RN808 33 RN807 33 RN806 33 RN805 33
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
DRO1/LB0M DRO0/LB0P DGO7/LB1M DGO6/LB1P DGO5/LB2M DGO4/LB2P DGO3/LBCKM DGO2/LBCKP DGO1/LB3M DGO0/LB3P DBO7/LA0M DBO6/LA0P DBO5/LA1M DBO4/LA1P DBO3/LA2M DBO2/LA2P DBO1/LACKM DBO0/LACKP DEN/LA3M DCLK/LA3P
C843 DRO1/LB0M 9 C834C835C836C838C841C842 DRO0/LB0P 9 0.1uF DGO7/LB1M 9 DGO6/LB1P 9 0.1uF 0.1uF 0.1uF DGO5/LB2M 9 0.1uF DGO4/LB2P 9 0.1uF DGO3/LBCKM 9 DGO2/LBCKP 9 DGO1/LB3M 9 MDQ0 DGO0/LB3P 9 DBO7/LA0M 9 MDQ1 DBO6/LA0P 9 MDQ2 DBO5/LA1M 9 DBO4/LA1P 9 MDQ3 DBO3/LA2M 9 MDQ4 DBO2/LA2P 9 DBO1/LACKM 9 MDQ5 DBO0/LACKP 9 MDQ6 DEN/LA3M 9 DCLK/LA3P 9 MDQ7 MDQM1 MWE MCAS MRAS MAD11 MBA0 MBA1 MAD10 MAD0 MAD1 MAD2 MDQM2 MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23
U800
0.1uF
0.1uF
C801 0.1u C800 0.1u
MST61510A(208Pin)
I N P U T
B
V G A
GNDB0 BIN0 GNDG0 GIN0 SOG0 6 GNDR0 5 RIN0 5 5 5 6 6 6 H_SYNC0 V_SYNC0
6
GNDB0 BIN0 GNDG0 GIN0 SOG0 GNDR0 RIN0 H_SYNC0 V_SYNC0
GNDB0 BIN0 GNDG0 GIN0 SOG0 GNDR0 RIN0 H_SYNC0 V_SYNC0
VI_DATA[8] VI_DATA[9] VI_DATA[10] VI_DATA[11] VI_DATA[12] VI_DATA[13] VI_DATA[14] VI_DATA[15] GPIO[5]/VHS GPIO[4]/VCLK2 VI_CK VI_DATA[0] VI_DATA[1] VI_DATA[2] VI_DATA[3] VI_DATA[4] VI_DATA[5] VI_DATA[6] VI_DATA[7] GPIO[2]/VVS HWRESET INT ALE RDZ WRZ DBUS[0] DBUS[1] DBUS[2] DBUS[3] PWM0 PWM1 VCTRL BYPASS GPIO[3]/VDE GPIO[1]/FIELD XOUT XIN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
MDQ15 33 MDQ14 MDQ13 MDQ12 MDQ11 MDQ10 MDQ9 MDQ8 MDQ0 MDQ1 MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 MDQM1 MDQM2 MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ31 MDQ30 MDQ29 MDQ28 MDQ27 MDQ26 MDQ25 MDQ24 MAD11 MAD10 MAD9 MAD8 MAD7 MAD6 MAD5 MAD4 MAD3 MAD2 MAD1 MAD0 MWE MCAS MRAS MBA0 MBA1 MCLK1 MCLKE1 R822 33 MCLKE C806 NC MVDD33 R824 NC R823
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD VQM0 /WE /CAS /RAS /CS CN BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
0.1uF MDQ15 MDQ14 MDQ13 MDQ12 MDQ11 MDQ10 MDQ9 MDQ8 MDQM1 MCLK MCLKE MAD9 MAD8 MAD7 MAD6 MAD5 MAD4 MAD3 MDQM2
B
Y , P b , P r
NC 4.7K 470 470 470
MDQ31 MDQ30 MDQ29 MDQ28 MDQ27 MDQ26 MDQ25 MDQ24
SDRAM_HY57V643220DT
#HRST R803 C802 NC NC
R801
33 #INT #ALE #RDZ #WRZ #BUD0 #BUD1 #BUD2 #BUD3 PWMOUT0
67 68 69 70 71 72 73 74 75 200 201 62 158 76 78 202 203
7
RST_MST
RST_MST INT ALE RDZ WRZ BUD0 BUD1 BUD2 BUD3
R800 RN801
33
#HRST #INT #ALE #RDZ #WRZ #BUD0 #BUD1 #BUD2 #BUD3
7
PWMOUT0
2,7 INT 7 ALE 7 RDZ 7 WRZ
A C E
5 6 7 8 5 6 7 8
RN800 33
4 3 2 1 4 3 2 1
C803 0.1u C804 22P
33
MCLK
A
A
33
I N T E R F
7
BUD[0..3]
OS201 14.318MHz C805 22P
u P
1 7 13 16 35 50 64 65 80 87 103 108 114 126 132 140 155 157 159 163 172 183 184 194 205 206
15
5 4 3 2
Title
UOC3+MST61510A BOARD
Size A2 Date: Document Number
8.Mst61510A
Monday, July 11, 2005
1
Rev 1 8 of 9
Sheet
5
4
3
2
1
DBOinterface swap DRO interface
PANEL_VCC1 XP903 XP901 C906 47U/16V + PANEL_VCC1 C903 104 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CON30 DCLK/LA3P DHS DVS DRO0/LB0P DRO1/LB0M DRO2 DRO3 DRO4 DRO5 DRO6 DRO7 DGO0/LB3P DGO1/LB3M DGO2/LBCKP DGO3/LBCKM DGO4/LB2P DGO5/LB2M DGO6/LB1P DGO7/LB1M DBO0/LACKP DBO1/LACKM DBO2/LA2P DBO3/LA2M DBO4/LA1P DBO5/LA1M DBO6/LA0P DBO7/LA0M PANEL_VCC1 DEN/LA3M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 XP902 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D
DBO0/LACKP DBO1/LACKM DBO2/LA2P DBO3/LA2M DBO4/LA1P DBO5/LA1M DBO6/LA0P DBO7/LA0M DGO0/LB3P DGO1/LB3M DGO2/LBCKP DGO3/LBCKM DGO4/LB2P DGO5/LB2M DGO6/LB1P DGO7/LB1M DRO0/LB0P DRO1/LB0M DRO2 DRO3 DRO4 DRO5 DRO6 DRO7 DCLK/LA3P DEN/LA3M DVS DHS
D
R909 NC/0
DCLK/LA3P DEN/LA3M 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
C
DRO1/LB0M DRO0/LB0P DGO7/LB1M DGO6/LB1P DGO5/LB2M DGO4/LB2P DGO3/LBCKM DGO2/LBCKP DGO1/LB3M DGO0/LB3P DBO7/LA0M DBO6/LA0P DBO5/LA1M DBO4/LA1P DBO3/LA2M DBO2/LA2P DBO1/LACKM DBO0/LACKP DEN/LA3M DCLK/LA3P DHS DVS DRO7 DRO6 DRO5 DRO4 DRO3 DRO2
DRO1/LB0M DRO0/LB0P DGO7/LB1M DGO6/LB1P DGO5/LB2M DGO4/LB2P DGO3/LBCKM DGO2/LBCKP DGO1/LB3M DGO0/LB3P DBO7/LA0M DBO6/LA0P DBO5/LA1M DBO4/LA1P DBO3/LA2M DBO2/LA2P DBO1/LACKM DBO0/LACKP DEN/LA3M DCLK/LA3P DHS DVS DRO7 DRO6 DRO5 DRO4 DRO3 DRO2 U5V
DBO0/LACKP DBO1/LACKM DBO2/LA2P DBO3/LA2M DBO4/LA1P DBO5/LA1M DBO6/LA0P DBO7/LA0M
8 8 8 8 8 8 8 8
PANEL_VCC F901 FUSE
C
PANEL_VCC1
CON42
R907 10K 2 3 R904 2K Q903 3906 3 TP900 TP901 TP902 1 Q900 1 R903 2K 3904
CON32 BKLon/off BKLon/off 7 +3.3VA 5VPN 12VU L900 NC/FB/0805 L901 FB/0805 L902 NC/FB/0805 R905 22K Q904
2
PANEL_VCC
Backlight
B
ON/OFF BKadj 12VU R906 4K7 7 C901 104 PANEL_EN
B
Q902
C907 104 C908 104
1 2 1 2
XP904 1 2 3 4 5 6 2mm R908 4.7K 1 2 3 4 5 6 C904 C900 104 C905 + 220U/16V + 220U/16V R901 1K U5V
G D 3 S Q905 Si2315 G D 3 S Si2315
MMBT3904
J5 FOR INVETOR
C909 2.2uF/10V
3
Q901 1 3904
R902 4K7 BKLadj 7
A
2
A
Mstar semiconductor Co.,Ltd Shanghai Branch 021-54070188*21
Title
16
Size A3 Date:
5 4 3 2
UOC3+MST61510A BOARD
Document Number
9.Panel Connector
Monday, December 05, 2005 Sheet
1
Rev 1 9 of 9
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
MST61510A
SXGA LCD Multi-Function Monitor Controller with TTL Output / Dual LVDS Transmitter Preliminary Data Sheet Version 0.1
PIN DIAGRAM (MST61510A)
DVI_RDVI_R+ GND GND AVDD_MPLL XIN XOUT PWM1 PWM0 NC NC LHSYNC LVSYNC VDDC GND R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] VDDC GND GND VDDP G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] VDDC GND B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] GND VDDP LDE OCLK GND BYPASS GND
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
GND DVI_G+ DVI_GAVDD_DVI DVI_B+ DVI_BGND DVI_CK+ DVI_CKAVDD_DVI REXT AVDD_PLL GND DDCD_DA DDCD_CK GND AVDD_ADC HSYNC1 VSYNC1 BIN1P BIN1M SOGIN1 GIN1P GIN1M RIN1P RIN1M BIN0M BIN0P GIN0M GIN0P SOGIN0 RIN0M RIN0P AVDD_ADC GND HSYNC0 VSYNC0 RMID REFP REFM VI_DATA[8] VI_DATA[9] VI_DATA[10] VI_DATA[11] VI_DATA[12] VI_DATA[13] VI_DATA[14] VI_DATA[15] VDDC GND GPO[5] GPO[4]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 100 101 102 103 104
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
Pin 1
VDDC GND VDDM DQS[0] MDATA[0] MDATA[1] MDATA[2] MDATA[3] MDATA[4] MDATA[5] MDATA[6] MDATA[7] MDATA[8] MDATA[9] MDATA[10] MDATA[11] GND VDDM MDATA[12] MDATA[13] MDATA[14] MDATA[15] DQS[1] DQM[0] GND VDDC MADR[11] MADR[10] MADR[9] MADR[8] GND VDDM MADR[7] MADR[6] MADR[5] MADR[4] MADR[3] MADR[2] MADR[1] MADR[0] WEZ CASZ GND VDDM RASZ BADR[0] BADR[1] AVDD_PLL2 GND MCLK MCLKZ MCLKE
xxxxxxxxxxx xxxxx
MST61510A
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Version 0.1
VI_CK VI_DATA[0] VI_DATA[1] VI_DATA[2] VI_DATA[3] VI_DATA[4] VI_DATA[5] VI_DATA[6] VI_DATA[7] VCTRL VDDC GND GND VDDP HWRESET INT ALE RDZ WRZ DBUS[0] DBUS[1] DBUS[2] DBUS[3] GPO[3] GPO[2] GPO[1] VDDC GND DQS[3] MDATA[31] MDATA[30] MDATA[29] MDATA[28] VDDM GND MDATA[27] MDATA[26] MDATA[25] MDATA[24] MDATA[23] MDATA[22] MDATA[21] MDATA[20] MDATA[19] MDATA[18] MDATA[17] MDATA[16] DQS[2] DQM[1] VDDM GND MVREF
-334 Copyright © 2005 MStar Semiconductor, Inc. All rights reserved.
99
4/15/2005
MST61510A
SXGA LCD Multi-Function Monitor Controller with TTL Output / Dual LVDS Transmitter Preliminary Data Sheet Version 0.1
PIN DESCRIPTION
MCU Interface
Pin Name HWRESET DBUS[3:0] ALE RDZ WRZ INT Pin Type Function Pin 67 75-72 69 70 71 68
Schmitt Trigger Input w/ Hardware Reset, active high 5V-tolerant I/O w/ 5V-tolerant I w/ 5V-tolerant I w/ 5V-tolerant I w/ 5V-tolerant Output MCU 4-bit DDR Direct bus; 4mA driving strength MCU Bus ALE, active high MCU Bus RDZ, active high MCU Bus WDZ, active high MCU Bus Interrupt; 4mA driving strength
Analog Interface
Pin Name RMID REFP REFM REXT HSYNC0 VSYNC0 BIN0M BIN0P GIN0M GIN0P SOGIN0 RIN0M RIN0P HSYNC1 VSYNC1 BIN1M BIN1P SOGIN1 GIN1M Analog Input 5V-tolerant Schmitt Trigger Input w/ Analog VSYNC Input from Channel 0 5V-tolerant Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input 5V-tolerant Schmitt Trigger Input w/ Analog VSYNC Input from Channel 1 5V-tolerant Analog Input Analog Input Analog Input Analog Input Reference Ground for Analog Blue Input from Channel 1 Analog Blue Input from Channel 1 Sync On Green Input from Channel 1 Reference Ground for Analog Green Input from Channel 1 21 20 22 24 19 Reference Ground for Analog Blue Input from Channel 0 Analog Blue Input from Channel 0 Reference Ground for Analog Green Input from Channel 0 Analog Green Input from Channel 0 Sync On Green Input from Channel 0 Reference Ground for Analog Red Input from Channel 0 Analog Red Input from Channel 0 27 28 29 30 31 32 33 18 37 Pin Type Function Mid-Scale Voltage Bypass Internal ADC Top De-coupling Pin Internal ADC Bottom De-coupling Pin External Resister 390 ohm to AVDD_DVI Pin 38 39 40 11 36
Schmitt Trigger Input w/ Analog HSYNC Input from Channel 0
Schmitt Trigger Input w/ Analog HSYNC Input from Channel 1
Version 0.1
-435 Copyright © 2005 MStar Semiconductor, Inc. All rights reserved.
4/15/2005
MST61510A
SXGA LCD Multi-Function Monitor Controller with TTL Output / Dual LVDS Transmitter Preliminary Data Sheet Version 0.1
Pin Name GIN1P RIN1M RIN1P
Pin Type Analog Input Analog Input Analog Input
Function Analog Green Input from Channel 1 Reference Ground for Analog Red Input from Channel 1 Analog Red Input from Channel 1
Pin 23 26 25
DVI Interface
Pin Name DVI_R+ DVI_RDVI_G+ DVI_GDVI_B+ DVI_BDVI_CK+ DVI_CKPin Type Input Input Input Input Input Input Input Input Function DVI Input Channel Red + DVI Input Channel Red DVI Input Channel Green + DVI Input Channel Green DVI Input Channel Blue + DVI Input Channel Blue DVI Input Clock + DVI Input Clock Pin 207 208 2 3 5 6 8 9
Video Interface
Pin Name VI_CK VI_DATA[15:0] Pin Type Input w/ 5V-tolerant Input w/ 5V-tolerant
Note 1
Function Digital Video Input Clock Digital Video Input Data[15:0]
Pin 53 48-41, 61-54
LCD Interface
Pin Name OCLK LDE LVSYNC LHSYNC R[7:4] R[3:0] G[7:0]
Pin Type Output w/ Pull-down Resistor Output w/ Pull-down Resistor Output w/ Pull-down Resistor Output w/ Pull-down Resistor Output w/ Pull-down Resistor Output w/ Pull-down Resistor Output w/ Pull-down Resistor
Function LCD Output Clock; 6mA driving strength LCD Display Enable; 6mA driving strength LCD VSYNC; 4mA driving strength LCD HSYNC; 4mA driving strength Red Channel Bit[7:4]; 6~12mA driving strength programmable Red Channel Bit[3:0]; 6mA driving strength Green Channel Bit[7:0]; 6mA driving strength
Pin 160 161 196 197 193-190 189-186 181-174
Version 0.1
-536 Copyright © 2005 MStar Semiconductor, Inc. All rights reserved.
4/15/2005
MST61510A
SXGA LCD Multi-Function Monitor Controller with TTL Output / Dual LVDS Transmitter Preliminary Data Sheet Version 0.1
Pin Name B[7:0]
Pin Type Output w/ Pull-down Resistor
Function Blue Channel Bit[7:0]; 6mA driving strength
Pin 171-164
Note 1: Please see the Output Type vs. Pin Configuration at the end of Pin Description section.
LVDS Interface
Pin Name LVA0M LVA0P LVA1M LVA1P LVA2M LVA2P LVA3M LVA3P LVACKM LVACKP LVB0M LVB0P LVB1M LVB1P LVB2M LVB2P LVB3M LVB3P LVBCKM LVBCKP
Note 1
Pin Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
Function A-Link Negative LVDS Differential Data Output A-Link Positive LVDS Differential Data Output A-Link Negative LVDS Differential Data Output A-Link Positive LVDS Differential Data Output A-Link Negative LVDS Differential Data Output A-Link Positive LVDS Differential Data Output A-Link Negative LVDS Differential Data Output A-Link Positive LVDS Differential Data Output A-Link Negative LVDS Differential Data Output A-Link Positive LVDS Differential Data Output B-Link Negative LVDS Differential Data Output B-Link Positive LVDS Differential Data Output B-Link Negative LVDS Differential Data Output B-Link Positive LVDS Differential Data Output B-Link Negative LVDS Differential Data Output B-Link Positive LVDS Differential Data Output B-Link Negative LVDS Differential Data Output B-Link Positive LVDS Differential Data Output B-Link Negative LVDS Differential Data Output B-Link Positive LVDS Differential Data Output
Pin 171 170 169 168 167 166 161 160 165 164 187 186 181 180 179 178 175 174 177 176
Note 1: Please see the Output Type vs. Pin Configuration at the end of Pin Description section.
GPO Interface
Pin Name PWM0 PWM1 GPO[1] GPO[2] GPO[3] GPO[4] Pin Type Output Output I/O I/O I/O I/O Function GPO with PWM Function; 4mA driving strength GPO with PWM Function; 4mA driving strength GPO / FIELD input; 4mA driving strength GPO / Digital VSYNC Input; 4mA driving strength GPO / DE Input; 4mA driving strength GPO / Secondary Video Clock Input; 4mA driving strength Pin 200 201 78 77 76 52
Version 0.1
-637 Copyright © 2005 MStar Semiconductor, Inc. All rights reserved.
4/15/2005
MST61510A
SXGA LCD Multi-Function Monitor Controller with TTL Output / Dual LVDS Transmitter Preliminary Data Sheet Version 0.1
Pin Name GPO[5]
Pin Type I/O
Function GPO / Digital HSYNC Input; 4mA driving strength
Pin 51
DRAM Interface
Pin Name MVREF MCLKE MCLKZ MCLK RASZ CASZ WEZ DQM[1:0] DQS[3:0] BADR[1:0] MADR[11:0] MDATA[31:0] Pin Type Input Output Output Output Output Output Output Output Output Output Output I/O Function Reference Voltage for DDR SDRAM Interface DRAM Memory Clock Enable DRAM Memory clock Complementary /Input (for differential clocks) DRAM Memory Clock Row Address Strobe, active low Column Address Strobe, active low Write Enable, active low Data Mask Byte Enable Data Strobe Memory Bank Address Memory Address Memory Data 107 112 115 116 133, 101 81, 100, 134, 153 110, 111 130-127, 124-117 82-85, 88-99, 135-138, 141-152 Pin 104 105 106
Misc. Interface
Pin Name XIN XOUT DDCD_DA DDCD_CK BYPASS VCTRL Output Pin Type Crystal Oscillator Input Function Crystal Oscillator Input Pin 203 202
Crystal Oscillator Output Crystal Oscillator Output I/O w/ 5V-tolerant Input w/ 5V-Tolerant strength HDCP Serial Bus Clock / DDC Clock of DVI Port For External Bypass Capacitor Regulator Control
HDCP Serial Bus Data / DDC data of DVI port; 4mA driving 14 15 158 62
Power Pins
Pin Name AVDD_DVI AVDD_ADC AVDD_PLL AVDD_PLL2 Pin Type 3.3V Power 3.3V Power 3.3V Power 3.3V Power Function DVI Power ADC Power PLL Power PLL Power Pin 4, 10 17, 34 12 109
Version 0.1
-738 Copyright © 2005 MStar Semiconductor, Inc. All rights reserved.
4/15/2005
MST61510A
SXGA LCD Multi-Function Monitor Controller with TTL Output / Dual LVDS Transmitter Preliminary Data Sheet Version 0.1
Pin Name AVDD_MPLL VDDM VDDP VDDC GND
Pin Type 3.3V Power 3.3V Power (SDR SDRAM) / 2.5V Power (DDR SDRAM) 3.3V Power 1.8V Power Ground
Function PLL Power DRAM Interface Power Digital Output Power Digital Core Power Ground
Pin 204 86, 102, 113, 125, 139, 154 66, 162, 182 49, 63, 79, 131, 156, 173, 185, 195 1, 7, 13, 16, 35, 50, 64, 65, 80, 87, 103, 108, 114, 126, 132, 140, 155, 157, 159, 163, 172, 183, 184, 194, 205, 206
No Connects
Pin Name NC
Note 2
Pin Type
Function No connect. Leave these pins floating.
Pin 198, 199
Note 2: This NC pin table is based on TTL output. Please see the Output Type vs. Pin Configuration at the end of Pin Description section.
Version 0.1
-839 Copyright © 2005 MStar Semiconductor, Inc. All rights reserved.
4/15/2005
MST61510A
SXGA LCD Multi-Function Monitor Controller with TTL Output / Dual LVDS Transmitter Preliminary Data Sheet Version 0.1
Output Type vs. Pin Configuration
Pin # 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 TTL OCLK LDE VDDP GND B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] GND VDDC G[0] G[1] G[2] G[3] G[4] G[5] LVDS LVA3P LVA3M VDDP GND LVACKP LVACKM LVA2P LVA2M LVA1P LVA1M LVA0P LVA0M GND VDDC LVB3P LVB3M LVBCKP LVBCKM LVB2P LVB2M Pin # 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 TTL G[6] G[7] VDDP GND GND VDDC R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] GND VDDC LVSYNC LHSYNC LVDS LVB1P LVB1M VDDP GND GND VDDC LVB0P LVB0M NC NC NC NC NC NC GND VDDC NC NC
Version 0.1
-940 Copyright © 2005 MStar Semiconductor, Inc. All rights reserved.
4/15/2005
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
9397 750 XXXXX
QSSO/AMOUT SCART/CINCH IN/OUT I2S L R L R LS-OUT HP-OUT
C
SOUND PLL DEEMPHASIS AM ADC/DAC
SSIF
Preliminary data sheet
REFO
om pa
A/D CONVERTER ALL-STANDARD STEREO DECODER AUDIO SELECT AUDIO CONTROL VOLUME TREBBLE/BASS FEATURES DACs
5. Block diagram
Philips Semiconductors
SIFIN/DVBIN
DVBO/IFVO/ FMRO DVBO/FMRO
SWITCH QSS SOUND IF AGC QSS MIXER AM DEMODULATOR
I/Os
RDS
AGCOUT BASE-BAND -PROCESSOR AND TELETEXT DECODER DIGITAL SIGNAL PROCESSING FEATURES SCAVEM ON TEXT BL R G CON.
VIFIN DECODER DELAY LINE REF
VISION IF/AGC/AFC PLL DEMOD. SOUND TRAP GROUP DELAY VIDEO AMP.
PAL/SECAM/NTSC
ny C
B CR RO GO BO WHITE-P. ADJ.
YUV IN/OUT
IFVO/SVO/ CVBS6 YSYNC CVBS2/Y2 PEAKING SCAN VELOCITY BRI
C
V-DRIVE EHTO BL G/Y R/PR B/PB EWD
ia l
GAMMA CONTROL SAT Ui Vi Vo Uo Yo Yi B/PB R/PR (CVBSx/Yx) (Cx) G/Y
en t
YUV SKIN TONE U/V TINT SATURATION
HOUT
SWO1 BL
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
UOCIII-TDA150XX series
O E O C C TR LL N N PY O U O ED O C C TR LL N N PY O U O ED O C C TR LL N N O U O ED C TR LL N N PY O U O O C C TR N N U O ED C LL N PY O U O C TR N O ED C LL O TR
Signal processor for low and mid-range LCD-TV
12 of 366
Fig 1. Block diagram of the "Stereo" TV processor
U
U
N
N
C
N O
Rev. 3.1 -- 8 July 2005
DIGITAL 2H/4H COMB FILTER MODULATION Y DELAY ADJ. U/V DELAY
41
VIDEO SWITCH VIDEO IDENT.
VIDEO FILTERS
on fid
RGB CONTROL OSD/TEXT INSERT CONTR/BRIGHTN CCC
CVBS3/Y3 C2/C3 CVBS4/Y4 C4 CVBSO/ PIP
Y
BCLIN BLKIN SVM
H/V VERTICAL & EAST-WEST GEOMETRY YUV INTERFACE RGB/YPBPR INSERT
H/V SYNC SEP. H-OSC. + PLL 2nd LOOP H-SHIFT H-DRIVE
RGB MATRIX BLUE STRETCH BLACK STRETCH
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6. Pinning information
QFP DESCRIPTION
9397 750 XXXXX
Table 5: "Face down" version
Pinning information
SYMBOL
C pa ny C on fid
AV Stereo No audio dsp
Preliminary data sheet
"Standard" version
Philips Semiconductors
Stereo + AV Stereo + AV Stereo AV stereo No stereo audio dsp
om
en t
O E O C C TR LL N N PY O U O ED O C C TR LL N N PY O U O ED O C C TR LL N N O U O ED C TR LL N N PY O U O O C C TR N N U O ED C LL N PY O U O C TR N O ED C LL O TR
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) VREF_POS_LSL VREF_NEG_LSL+ HPL VREF_POS_LSR+ HPR VREF_NEG_HPL+ HPR VREF_POS_HPR XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG EWD/AVL [1] VDRB VDRA VIFIN1 VIFIN2 VSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
ground ground digital supply to SDACs (1.8V) supply (3.3 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) negative reference voltage SDAC (0 V) positive reference voltage SDAC (3.3 V) crystal oscillator input crystal oscillator output ground V-guard input / I/O switch (e.g. 4 mA current sinking capability for direct drive of LEDs) decoupling digital supply 1st supply voltage TV-processor (+5 V) phase-2 filter phase-1 filter ground 1 for TV-processor SECAM PLL decoupling bandgap decoupling East-West drive output or AVL capacitor vertical drive B output vertical drive A output IF input 1 IF input 2 vertical sawtooth capacitor
ia l
UOCIII-TDA150XX series
Signal processor for low and mid-range LCD-TV
U
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
U
N
N
C
N O
Rev. 3.1 -- 8 July 2005
42
15 of 366
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QFP "Face down" version AV Stereo No audio dsp DESCRIPTION
Table 5:
Pinning information
9397 750 XXXXX
SYMBOL
Preliminary data sheet
"Standard" version
C
102 101 100 99 98 97 96
Philips Semiconductors
Stereo + AV Stereo + AV Stereo AV stereo No stereo audio dsp
om
102 101 100 99 98 97 96
27 28 29 30 31 32 33
27 28 29 30 31 32 33
pa ny C on fid
- 95 94 93 92 91 reference current input ground connection for IF amplifier SIF input 1 / DVB input 1 SIF input 2 / DVB input 2 tuner AGC output EHT/overvoltage protection input Automatic Volume Levelling / switch output / sound IF input / subcarrier reference output / external reference signal input for I signal mixer for DVB operation audio 5 input audio-5 input (left signal) audio-5 input (right signal) audio output for SCART/CINCH (left signal) audio output for SCART/CINCH (right signal) decoupling sound demodulator
en t
UOCIII-TDA150XX series
O E O C C TR LL N N PY O U O ED O C C TR LL N N PY O U O ED O C C TR LL N N O U O ED C TR LL N N PY O U O O C C TR N N U O ED C LL N PY O U O C TR N O ED C LL O TR
Signal processor for low and mid-range LCD-TV
GND2 PLLIF SIFAGC/DVBAGC [2] DVBO/IFVO/FMRO [2] DVBO/FMRO [2] VCC8V AGC2SIF VP2 IFVO/SVO/CVBS6 [2] AUDIOIN4 AUDIOIN4L AUDIOIN4R CVBS4/Y4
39 40 41 42 43 44 45 46 47 48 - 49 50 51
39 40 41 42 43 44 45 - 47 48 - 49 50 51
90 89 88 87 86 85 84 83 82 81 - 80 79 78
90 89 88 87 86 85 84 - 82 81 - 80 79 78
QSS intercarrier output / AM output / deemphasis (front-end audio out) ground 2 for TV processor IF-PLL loop filter AGC sound IF / internal-external AGC for DVB applications Digital Video Broadcast output / IF video output / FM radio output Digital Video Broadcast output / FM radio output 8 Volt supply for audio switches AGC capacitor second sound IF 2nd supply voltage TV processor (+5 V) IF video output / selected CVBS output / CVBS input audio 4 input audio-4 input (left signal) audio-4 input (right signal) CVBS4/Y4 input
ia l
U
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
U
N
N
C
N O
Rev. 3.1 -- 8 July 2005
43
- 34 35 36 37 38
- 34 35 36 37 38
- 95 94 93 92 91
IREF GNDIF SIFIN1/DVBIN1 [2] SIFIN2/DVBIN2 [2] AGCOUT EHTO AVL/SWO/SSIF/ REFO/REFIN [2] [3] AUDIOIN5 AUDIOIN5L AUDIOIN5R AUDOUTSL AUDOUTSR DECSDEM QSSO/AMOUT/ AUDEEM
[2]
16 of 366
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QFP "Face down" version AV Stereo No audio dsp DESCRIPTION
Table 5:
Pinning information
9397 750 XXXXX
SYMBOL
Preliminary data sheet
"Standard" version
C pa ny C on fid
Philips Semiconductors
Stereo + AV Stereo + AV Stereo AV stereo No stereo audio dsp
om
en t
O E O C C TR LL N N PY O U O ED O C C TR LL N N PY O U O ED O C C TR LL N N O U O ED C TR LL N N PY O U O O C C TR N N U O ED C LL N PY O U O C TR N O ED C LL O TR
C4 AUDIOIN2 AUDIOIN2L/SSIF [3] AUDIOIN2R CVBS2/Y2 AUDIOIN3 AUDIOIN3L AUDIOIN3R CVBS3/Y3 C2/C3 AUDOUTLSL AUDOUTLSR AUDOUT/AMOUT/ FMOUT AUDOUTHPL AUDOUTHPR CVBSO/PIP SVM FBISO/CSY HOUT VSScomb VDDcomb VIN (R/PRIN2/CX) UIN (B/PBIN2) YIN (G/YIN2/CVBS-YX) YSYNC YOUT UOUT (INSSW2) VOUT (SWO1)
52 - 53 54 55 - 56 57 58 59 60 61 - 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
52 - 53 54 55 - 56 57 58 59 62 63 - - - 64 65 66 67 68 69 70 71 72 73 74 75 76
77 - 76 75 74 - 73 72 71 70 69 68 - 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
77 - 76 75 74 - 73 72 71 70 67 66 - - - 65 64 63 62 61 60 59 58 57 56 55 54 53
chroma-4 input audio 2 input audio 2 input (left signal) / sound IF input audio 2 input (right signal) CVBS2/Y2 input audio 3 input audio 3 input (left signal) audio 3 input (right signal) CVBS3/Y3 input chroma-2/3 input audio output for audio power amplifier (left signal) audio output for audio power amplifier (right signal) audio output / AM output / FM output, volume controlled audio output for headphone channel (left signal) audio output for headphone channel (right signal) CVBS / PIP output scan velocity modulation output flyback input/sandcastle output or composite H/V timing output horizontal output ground connection for comb filter supply voltage for comb filter (5 V) V-input for YUV interface (2nd R input / PR input or CX input) U-input for YUV interface (2nd B input / PB input) Y-input for YUV interface (2nd G input / Y input or CVBS/YX input)) Y-input for sync separator Y-output (for YUV interface) U-output for YUV interface (2nd RGB / YPBPR insertion input) V-output for YUV interface (general purpose switch output)
ia l
UOCIII-TDA150XX series
Signal processor for low and mid-range LCD-TV
U
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
U
N
N
C
N O
Rev. 3.1 -- 8 July 2005
44
17 of 366
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QFP "Face down" version AV Stereo No audio dsp DESCRIPTION
Table 5:
Pinning information
9397 750 XXXXX
SYMBOL
Preliminary data sheet
"Standard" version
C pa ny C on fid
Philips Semiconductors
Stereo + AV Stereo + AV Stereo AV stereo No stereo audio dsp
om
en t
O E O C C TR LL N N PY O U O ED O C C TR LL N N PY O U O ED O C C TR LL N N O U O ED C TR LL N N PY O U O O C C TR N N U O ED C LL N PY O U O C TR N O ED C LL O TR
INSSW3 R/PRIN3 G/YIN3 B/PBIN3 GND3 VP3 BCLIN BLKIN RO GO BO VDDA1 VREFAD_NEG VREFAD_POS VREFAD GNDA VDDA(1.8V) VDDA2(3.3) VSSadc VDDadc(1.8) INT0/P0.5 P1.0/INT1 P1.1/T0 VDDC2 VSSC2 P0.4/I2SWS P0.4 P0.3/I2SCLK
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 - 103
77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 92 93 94 95 96 97 98 99 100 101 - 102 -
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 - 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 - 37 36 35 34 33 32 31 30 29 28 - 27 -
3rd RGB / YPBPR insertion input 3rd R input / PR input 3rd G input / Y input 3rd B input / PB input ground 3 for TV-processor 3rd supply for TV processor beam current limiter input black current input Red output Green output Blue output analog supply for TCG -Controller and digital supply for TV-processor (+3.3 V) negative reference voltage (0 V) positive reference voltage (3.3 V) reference voltage for audio ADCs (3.3/2 V) ground analogue supply for audio ADCs (1.8 V) supply voltage SDAC (3.3 V) ground for video ADC and PLL supply voltage video ADC and PLL external interrupt 0 or port 0.5 (4 mA current sinking capability for direct drive of LEDs) port 1.0 or external interrupt 1 port 1.1 or Counter/Timer 0 input digital supply to core (1.8 V) ground port 0.4 or I2S word select port 0.4 port 0.3 or I2S clock
ia l
UOCIII-TDA150XX series
Signal processor for low and mid-range LCD-TV
U
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
U
N
N
C
N O
Rev. 3.1 -- 8 July 2005
45
18 of 366
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QFP "Face down" version AV Stereo No audio dsp DESCRIPTION
Table 5:
Pinning information
9397 750 XXXXX
SYMBOL
Preliminary data sheet
"Standard" version
C pa ny C on fid
Philips Semiconductors
Stereo + AV Stereo + AV Stereo AV stereo No stereo audio dsp
om
en t
P0.3 P0.2/I2SDO2 P0.2 P0.1/I2SDO1 P0.1 P0.0/I2SDI1/O P0.0 P1.3/T1 P1.6/SCL P1.7/SDA VDDP(3.3V) P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P3.0/ADC0 P3.1/ADC1 VDDC1 DECV1V8 P3.2/ADC2 P3.3/ADC3 VSSC/P P2.4/PWM3 P2.5/PWM4 VDDC3 VSSC3
- 104 - 105 - 106 - 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 26 - 25 - 24 - 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 port 0.3 port 0.2 or I2S digital output 2 port 0.2 port 0.1 or I2S digital output 1 port 0.1 port 0.0 or I2S digital input 1 or I2S digital output port 0.0 port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line supply to periphery and on-chip voltage regulator (3.3V) port 2.0 or Tuning PWM output port 2.1 or PWM0 output port 2.2 or PWM1 output port 2.3 or PWM2 output port 3.0 or ADC0 input port 3.1 or ADC1 input digital supply to core (+1.8 V) decoupling 1.8 V supply port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for -Controller core and periphery port 2.4 or PWM3 output port 2.5 or PWM4 output digital supply to core (1.8V) ground
103 - 104 - 105 - 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
- 25 - 24 - 23 - 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
ia l
UOCIII-TDA150XX series
O E O C C TR LL N N PY O U O ED O C C TR LL N N PY O U O ED O C C TR LL N N O U O ED C TR LL N N PY O U O O C C TR N N U O ED C LL N PY O U O C TR N O ED C LL O TR
Signal processor for low and mid-range LCD-TV
U
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
U
N
N
C
N O
Rev. 3.1 -- 8 July 2005
46
19 of 366
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QFP "Face down" version AV Stereo No audio dsp port 1.2 or external interrupt 2 port 1.4 or UART bus port 1.5 or UART bus DESCRIPTION
Table 5:
Pinning information
9397 750 XXXXX
SYMBOL
Preliminary data sheet
"Standard" version
C
3 2 1
Philips Semiconductors
Stereo + AV Stereo + AV Stereo AV stereo No stereo audio dsp
om
3 2 1
P1.2/INT2 P1.4/RX P1.5/TX
126 127 128
126 127 128
pa ny C on fid
[1]
The function of this pin can be chosen by means of the AVLE bit.
[2]
The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in Table 6 "Pin functions for various mode