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PIC16C7X
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
· PIC16C72 · PIC16C73 · PIC16C73A · PIC16C74 · PIC16C74A · PIC16C76 · PIC16C77 · Wide operating voltage range: 2.5V to 6.0V · High Sink/Source Current 25/25 mA · Commercial, Industrial and Extended temperature ranges · Low-power consumption: · < 2 mA @ 5V, 4 MHz · 15 µA typical @ 3V, 32 kHz · < 1 µA typical standby current
PIC16C7X Microcontroller Core Features:
· High-performance RISC CPU · Only 35 single word instructions to learn · All single cycle instructions except for program branches which are two cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · Up to 8K x 14 words of Program Memory, up to 368 x 8 bytes of Data Memory (RAM) · Interrupt capability · Eight level deep hardware stack · Direct, indirect, and relative addressing modes · Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Programmable code-protection · Power saving SLEEP mode · Selectable oscillator options · Low-power, high-speed CMOS EPROM technology · Fully static design PIC16C7X Features Program Memory (EPROM) x 14 Data Memory (Bytes) x 8 I/O Pins Parallel Slave Port Capture/Compare/PWM Modules Timer Modules A/D Channels Serial Communication In-Circuit Serial Programming Brown-out Reset Interrupt Sources 72 2K 128 22 -- 1 3 5 SPI/I2C Yes Yes 8 73 4K 192 22 -- 2 3 5 SPI/I2C, USART Yes -- 11
PIC16C7X Peripheral Features:
· Timer0: 8-bit timer/counter with 8-bit prescaler · Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · Capture, Compare, PWM module(s) · Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM max. resolution is 10-bit · 8-bit multichannel analog-to-digital converter · Synchronous Serial Port (SSP) with SPITM and I2CTM · Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) · Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls · Brown-out detection circuitry for Brown-out Reset (BOR)
73A 4K 192 22 -- 2 3 5 SPI/I2C, USART Yes Yes 11
74 4K 192 33 Yes 2 3 8 SPI/I2C, USART Yes -- 12
74A 4K 192 33 Yes 2 3 8 SPI/I2C, USART Yes Yes 12
76 8K 368 22 -- 2 3 5 SPI/I2C, USART Yes Yes 11
77 8K 368 33 Yes 2 3 8 SPI/I2C, USART Yes Yes 12
© 1997 Microchip Technology Inc.
DS30390E-page 1
PIC16C7X
Pin Diagrams
SDIP, SOIC, Windowed Side Brazed Ceramic
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL ·1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL ·1 2 3 4 5 6 7 8 9 10 11 12 13 14
SSOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA
PIC16C72
PIC16C72
SDIP, SOIC, Windowed Side Brazed Ceramic
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL ·1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1
PDIP, Windowed CERDIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
PIC16C73 PIC16C73A PIC16C76
PIC16C74 PIC16C74A PIC16C77
DS30390E-page 2
© 1997 Microchip Technology Inc.
PIC16C7X
Pin Diagrams (Cont.'d)
MQFP
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16C74
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/SS/AN4 RA4/T0CKI
NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
PLCC
MQFP TQFP
6 5 4 3 2 1 44 43 42 41 40
RA4/T0CKI RA5/SS/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC
7 8 9 10 11 12 13 14 15 16 17
PIC16C74 PIC16C74A PIC16C77
18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16C74A PIC16C77
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/SS/AN4 RA4/T0CKI
RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
© 1997 Microchip Technology Inc.
NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
DS30390E-page 3
PIC16C7X
Table of Contents
1.0 General Description ....................................................................................................................................................................... 5 2.0 PIC16C7X Device Varieties ........................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................... 9 4.0 Memory Organization................................................................................................................................................................... 19 5.0 I/O Ports....................................................................................................................................................................................... 43 6.0 Overview of Timer Modules ......................................................................................................................................................... 57 7.0 Timer0 Module ............................................................................................................................................................................. 59 8.0 Timer1 Module ............................................................................................................................................................................. 65 9.0 Timer2 Module ............................................................................................................................................................................. 69 10.0 Capture/Compare/PWM Module(s).............................................................................................................................................. 71 11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 77 12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ...................................................................................... 99 13.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117 14.0 Special Features of the CPU ..................................................................................................................................................... 129 15.0 Instruction Set Summary............................................................................................................................................................ 147 16.0 Development Support ................................................................................................................................................................ 163 17.0 Electrical Characteristics for PIC16C72 ..................................................................................................................................... 167 18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183 19.0 Electrical Characteristics for PIC16C73A/74A ........................................................................................................................... 201 20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219 21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241 22.0 Packaging Information ............................................................................................................................................................... 251 Appendix A: ................................................................................................................................................................................... 263 Appendix B: Compatibility ............................................................................................................................................................. 263 Appendix C: What's New............................................................................................................................................................... 264 Appendix D: What's Changed ....................................................................................................................................................... 264 Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 265 Pin Compatibility ................................................................................................................................................................................ 271 Index .................................................................................................................................................................................................. 273 List of Examples................................................................................................................................................................................. 279 List of Figures..................................................................................................................................................................................... 280 List of Tables...................................................................................................................................................................................... 283 Reader Response .............................................................................................................................................................................. 286 PIC16C7X Product Identification System........................................................................................................................................... 287
For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and PIC16C74A devices. Applicable Devices 72 73 73A 74 74A 76 77
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30390E-page 4
© 1997 Microchip Technology Inc.
PIC16C7X
1.0 GENERAL DESCRIPTION
The PIC16C7X is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C72 has 128 bytes of RAM and 22 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/ PWM module and one serial port. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. Also a 5-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC16C73/73A devices have 192 bytes of RAM, while the PIC16C76 has 368 byes of RAM. Each device has 22 I/O pins. In addition, several peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. Also a 5-channel high-speed 8-bit A/ D is provided.The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC16C74/74A devices have 192 bytes of RAM, while the PIC16C77 has 368 bytes of RAM. Each device has 33 I/O pins. In addition several peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. An 8-bit Parallel Slave Port is provided. Also an 8-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC16C7X family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. A UV erasable CERDIP packaged version is ideal for code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume. The PIC16C7X family fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C7X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, serial communication, capture and compare, PWM functions and coprocessor applications).
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).
1.2
Development Support
PIC16C7X devices are supported by the complete line of Microchip Development tools. Please refer to Section 16.0 for more details about Microchip's development tools.
© 1997 Microchip Technology Inc.
DS30390E-page 5
PIC16C7X
TABLE 1-1: PIC16C7XX FAMILY OF DEVCES
PIC16C710 Clock Maximum Frequency of Operation (MHz) EPROM Program Memory (x14 words) Memory ROM Program Memory (14K words) Data Memory (bytes) Timer Module(s) 20 512 -- 36 TMR0 PIC16C71 20 1K -- 36 TMR0 PIC16C711 20 1K -- 68 TMR0 PIC16C715 20 2K -- 128 TMR0 PIC16C72 20 2K -- 128 TMR0, TMR1, TMR2 1 SPI/I2C -- 5 8 22 2.5-6.0 Yes Yes PIC16CR72(1) 20 -- 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C -- 5 8 22 3.0-5.5 Yes Yes
Capture/Compare/ Peripherals PWM Module(s) Serial Port(s) (SPI/I2C, USART) Parallel Slave Port Interrupt Sources I/O Pins Voltage Range (Volts) Features In-Circuit Serial Programming Brown-out Reset Packages
-- -- -- 4 13 3.0-6.0 Yes Yes
-- -- -- 4 4 13 3.0-6.0 Yes --
-- -- -- 4 4 13 3.0-6.0 Yes Yes
-- -- -- 4 4 13 3.0-5.5 Yes Yes
A/D Converter (8-bit) Channels 4
18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C73A PIC16C74A 20 4K 192 TMR0, TMR1, TMR2 2 SPI/I2C, USART Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP 20 8K 368 TMR0, TMR1, TMR2 2 SPI/I2C, USART -- 5 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC PIC16C76 20 8K 368 TMR0, TMR1, TMR2 2 SPI/I2C, USART Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP PIC16C77
Clock
Maximum Frequency of Oper- 20 ation (MHz) EPROM Program Memory (x14 words) Data Memory (bytes) Timer Module(s) 4K 192 TMR0, TMR1, TMR2
Memory
Capture/Compare/PWM Mod- 2 Peripherals ule(s) Serial Port(s) (SPI/I2C, US- SPI/I2C, USART ART) Parallel Slave Port Interrupt Sources I/O Pins Voltage Range (Volts) Features In-Circuit Serial Programming Brown-out Reset Packages -- 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC A/D Converter (8-bit) Channels 5
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices.
DS30390E-page 6
© 1997 Microchip Technology Inc.
PIC16C7X
2.0 PIC16C7X DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C7X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C7X family, there are two device "types" as indicated in the device number: 1. C, as in PIC16C74. These devices have EPROM type memory and operate over the standard voltage range. LC, as in PIC16LC74. These devices have EPROM type memory and operate over an extended voltage range.
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4
2.
Serialized Quick-Turnaround Production (SQTPSM) Devices
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PICSTART® Plus and PRO MATE® II programmers both support programming of the PIC16C7X.
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
© 1997 Microchip Technology Inc.
DS30390E-page 7
PIC16C7X
NOTES:
DS30390E-page 8
© 1997 Microchip Technology Inc.
PIC16C7X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) except for program branches. The table below lists program memory (EPROM) and data memory (RAM) for each PIC16C7X device. Device PIC16C72 PIC16C73 PIC16C73A PIC16C74 PIC16C74A PIC16C76 PIC16C77 Program Memory 2K x 14 4K x 14 4K x 14 4K x 14 4K x 14 8K x 14 8K x 14 Data Memory 128 x 8 192 x 8 192 x 8 192 x 8 192 x 8 368 x 8 386 x 8 PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
The PIC16CXX can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly.
© 1997 Microchip Technology Inc.
DS30390E-page 9
PIC16C7X
FIGURE 3-1: PIC16C72 BLOCK DIAGRAM
13 EPROM Program Memory 2K x 14 Program Bus 14 Instruction reg Direct Addr 7 8 Level Stack (13-bit) Program Counter Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 PORTB
RAM File Registers 128 x 8 RAM Addr(1) 9
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 PORTC
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
A/D
Synchronous Serial Port
CCP1
Note 1: Higher order bits are from the STATUS register.
DS30390E-page 10
© 1997 Microchip Technology Inc.
PIC16C7X
FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM
Device PIC16C73 PIC16C73A PIC16C76
Program Memory Data Memory (RAM) 4K x 14 4K x 14 8K x 14 192 x 8 192 x 8 368 x 8 13 Program Counter EPROM Program Memory 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) 9 PORTB Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) 8 W reg ALU PORTC
MUX
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
MCLR
VDD, VSS
Timer0
Timer1
Timer2
A/D
CCP1
CCP2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C73.
© 1997 Microchip Technology Inc.
DS30390E-page 11
PIC16C7X
FIGURE 3-3: PIC16C74/74A/77 BLOCK DIAGRAM
Device PIC16C74 PIC16C74A PIC16C77
Program Memory Data Memory (RAM) 4K x 14 4K x 14 8K x 14 192 x 8 192 x 8 368 x 8
13 Program Counter EPROM Program Memory 8 Level Stack (13-bit)
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 PORTB
RAM File Registers RAM Addr (1) 9
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD W reg RD7/PSP7:RD0/PSP0
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) 8
MUX
ALU
Parallel Slave Port MCLR VDD, VSS
PORTE RE0/RD/AN5 RE1/WR/AN6
Timer0
Timer1
Timer2
A/D
RE2/CS/AN7
CCP1
CCP2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C74.
DS30390E-page 12
© 1997 Microchip Technology Inc.
PIC16C7X
TABLE 3-1:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C72 PINOUT DESCRIPTION
DIP Pin# 9 10 SSOP Pin# 9 10 SOIC Pin# 9 10 I/O/P Type I O Buffer Type Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin.
MCLR/VPP
1
1
1
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
2 3 4 5 6 7
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 VSS VDD Legend: I = input
21 22 23 24 25 26 27 28 11 12 13 14 15
21 22 23 24 25 26 27 28 11 12 13 14 15
21 22 23 24 25 26 27 28 11 12 13 14 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) ST ST ST ST ST
16 16 16 I/O ST 17 17 17 I/O ST 18 18 18 I/O ST 8, 19 8, 19 8, 19 P -- Ground reference for logic and I/O pins. 20 20 20 P -- Positive supply for logic and I/O pins. O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode).
© 1997 Microchip Technology Inc.
DS30390E-page 13
PIC16C7X
TABLE 3-2:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C73/73A/76 PINOUT DESCRIPTION
DIP Pin# 9 10 SOIC Pin# 9 10 I/O/P Type I O Buffer Type Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin.
MCLR/VPP
1
1
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. VSS 8, 19 8, 19 P -- Ground reference for logic and I/O pins. VDD 20 20 P -- Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7
21 22 23 24 25 26 27 28
21 22 23 24 25 26 27 28
I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2)
DS30390E-page 14
© 1997 Microchip Technology Inc.
PIC16C7X
TABLE 3-3:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C74/74A/77 PINOUT DESCRIPTION
DIP Pin# 13 14 PLCC Pin# 14 15 QFP Pin# 30 31 I/O/P Type I O Buffer Type Description
ST/CMOS(4) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR/VPP
1
2
18
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
3 4 5 6 7 8
19 20 21 22 23 24
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 Legend: I = input Note 1: 2: 3: 4:
33 34 35 36 37 38 39
36 37 38 39 41 42 43
8 9 10 11 14 15 16
I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2)
RB0 can also be the external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock.
40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
© 1997 Microchip Technology Inc.
DS30390E-page 15
PIC16C7X
TABLE 3-3:
Pin Name
PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.'d)
DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
15 16 17 18 23 24 25 26
16 18 19 20 25 26 27 29
32 35 36 37 42 43 44 1
I/O I/O I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST ST ST
RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VSS VDD NC Legend: I = input Note 1: 2: 3: 4:
19 20 21 22 27 28 29 30 8 9 10 12,31 11,32 --
21 22 23 24 30 31 32 33 9 10 11 13,34 12,35 1,17,28, 40
38 39 40 41 2 3 4 5 25 26 27 6,29 7,28 12,13, 33,34
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P
ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) PORTE is a bi-directional I/O port. ST/TTL(3) ST/TTL(3) ST/TTL(3) -- -- -- RE0 can also be read control for the parallel slave port, or analog input5. RE1 can also be write control for the parallel slave port, or analog input6. RE2 can also be select control for the parallel slave port, or analog input7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected.
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30390E-page 16
© 1997 Microchip Technology Inc.
PIC16C7X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-4. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-4:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)
PC PC+1 PC+2 Internal phase clock
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
© 1997 Microchip Technology Inc.
DS30390E-page 17
PIC16C7X
NOTES:
DS30390E-page 18
© 1997 Microchip Technology Inc.
PIC16C7X
4.0 MEMORY ORGANIZATION
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 4-2:
PIC16C73/73A/74/74A PROGRAM MEMORY MAP AND STACK
PC<12:0>
4.1
Program Memory Organization
CALL, RETURN RETFIE, RETLW
The PIC16C7X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The amount of program memory available to each device is listed below: Device PIC16C72 PIC16C73 PIC16C73A PIC16C74 PIC16C74A PIC16C76 PIC16C77 Program Memory 2K x 14 4K x 14 4K x 14 4K x 14 4K x 14 8K x 14 8K x 14 Address Range
13
Stack Level 1
Stack Level 8 0000h-07FFh 0000h-0FFFh 0000h-0FFFh 0000h-0FFFh User Memory Space 0000h-0FFFh 0000h-1FFFh 0000h-1FFFh Interrupt Vector On-chip Program Memory (Page 0) 0004h 0005h 07FFh On-chip Program Memory (Page 1) 0800h Reset Vector 0000h
For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
FIGURE 4-1:
PIC16C72 PROGRAM MEMORY MAP AND STACK
PC<12:0>
0FFFh 1000h
1FFFh
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 Reset Vector
0000h
User Memory Space
Interrupt Vector
0004h 0005h
On-chip Program Memory 07FFh 0800h
1FFFh
© 1997 Microchip Technology Inc.
DS30390E-page 19
PIC16C7X
FIGURE 4-3: PIC16C76/77 PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
4.2
Data Memory Organization
Applicable Devices 72 73 73A 74 74A 76 77
13
Stack Level 1 Stack Level 2
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1:RP0 (STATUS<6:5>) = 00 Bank0 = 01 Bank1 = 10 Bank2 = 11 Bank3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some "high use" special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 4.2.1 GENERAL PURPOSE REGISTER FILE
Stack Level 8
Reset Vector
0000h
Interrupt Vector User Memory Space On-Chip Page 0
0004h 0005h 07FFh 0800h
On-Chip
Page 1 0FFFh 1000h
The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5).
On-Chip
Page 2 17FFh 1800h 1FFFh
On-Chip
Page 3
DS30390E-page 20
© 1997 Microchip Technology Inc.
PIC16C7X
FIGURE 4-4:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC
PIC16C72 REGISTER FILE MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
FIGURE 4-5:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
PIC16C73/73A/74/74A REGISTER FILE MAP
File Address
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON
PCLATH INTCON PIE1 PCON
PR2 SSPADD SSPSTAT
ADRES ADCON0 General Purpose Register
ADCON1 General Purpose Register
INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0
INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE(2) PCLATH INTCON PIE1 PIE2 PCON
PR2 SSPADD SSPSTAT
TXSTA SPBRG
ADCON1
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
BFh C0h
General Purpose Register
General Purpose Register
7Fh Bank 0 7Fh FFh Bank 0 Bank 1 Bank 1
FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not physically implemented on the PIC16C73/73A, read as '0'.
© 1997 Microchip Technology Inc.
DS30390E-page 21
PIC16C7X
FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) PORTE (1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD (1) TRISE (1) PCLATH INTCON PIE1 PIE2 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON
PCLATH INTCON
PR2 SSPADD SSPSTAT
TXSTA SPBRG
General Purpose Register 16 Bytes
General Purpose Register 16 Bytes
ADCON1
General Purpose Register 96 Bytes
EFh F0h FFh
16Fh 170h 17Fh
General Purpose Register 80 Bytes accesses 70h - 7Fh Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'.
Note:
The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require relocation of data memory usage in the user application code if upgrading to the PIC16C76/77.
DS30390E-page 22
© 1997 Microchip Technology Inc.
PIC16C7X
4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1:
Address Name
PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3)
Bank 0 00h(1) 01h 02h(1) 03h
(1)
INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON -- -- -- -- -- -- ADRES ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP
(4)
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- -- -- --
04h(1) 05h 06h 07h 08h 09h 0Ah(1,2) 0Bh(1) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read Unimplemented Unimplemented -- GIE -- -- PEIE ADIF -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE SSPIF T0IF CCP1IF INTF TMR2IF RBIF TMR1IF
---0 0000 ---0 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000 -- --
Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --uu uuuu 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON -- CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000 --00 0000 -- -- -- -- -- -- -- -- -- -- -- --
xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
© 1997 Microchip Technology Inc.
DS30390E-page 23
PIC16C7X
TABLE 4-1:
Address Name
PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3)
Bank 1 80h(1) 81h 82h(1) 83h(1) 84h(1) 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(1) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh PR2 SSPADD SSPSTAT -- -- -- -- -- -- -- -- -- -- ADCON1 INDF OPTION PCL STATUS FSR TRISA TRISB TRISC -- -- PCLATH INTCON PIE1 -- PCON -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 -- -- -- PEIE ADIE -- T0IE -- Write Buffer for the upper 5 bits of the PC INTE -- RBIE SSPIE T0IF CCP1IE INTF TMR2IE RBIF TMR1IE -- --
Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO
Indirect data memory address pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register PORTC Data Direction Register Unimplemented Unimplemented -- GIE --
---0 0000 ---0 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000 -- --
Unimplemented -- Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0 -- D/A P S R/W UA BF -- -- -- -- -- POR BOR
---- --qq ---- --uu -- -- -- -- -- --
1111 1111 1111 1111 0000 0000 0000 0000 --00 0000 --00 0000 -- -- -- -- -- -- -- -- -- -- ---- -000 -- -- -- -- -- -- -- -- -- -- ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
DS30390E-page 24
© 1997 Microchip Technology Inc.
PIC16C7X
TABLE 4-2:
Address Name
PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2)
Bank 0 00h(4) 01h 02h(4) 03h
(4)
INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP
(7)
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000
RP1
(7)
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
04h(4) 05h 06h 07h 08h(5) 09h
(5)
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(3) -- -- -- PEIE ADIF -- -- -- T0IE RCIF -- -- -- RE2 RE1 RE0
---- -xxx ---- -uuu ---0 0000 ---0 0000 0000 000x 0000 000u 0000 0000 0000 0000 ---- ---0 ---- ---0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
0Ah(1,4) 0Bh(4) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Write Buffer for the upper 5 bits of the Program Counter INTE TXIF RBIE SSPIF -- T0IF CCP1IF -- INTF TMR2IF -- RBIF TMR1IF CCP2IF
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000 --uu uuuu 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 -- CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
--00 0000 --00 0000 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- -- CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0
--00 0000 --00 0000 xxxx xxxx uuuu uuuu
A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 4: These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as `0'. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.
© 1997 Microchip Technology Inc.
DS30390E-page 25
PIC16C7X
TABLE 4-2:
Address Name
PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2)
Bank 1 80h(4) 81h 82h(4) 83h
(4)
INDF OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON -- -- -- PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- -- -- -- -- ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP
(7)
RP1
(7)
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
84h(4) 85h 86h 87h 88h(5) 89h
(5)
Indirect data memory address pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(3) -- -- Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register -- Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D -- D/A P S R/W UA BF OBF -- PEIE ADIE -- -- IBOV -- T0IE RCIE -- -- PSPMODE -- PORTE Data Direction Bits
0000 -111 0000 -111 ---0 0000 ---0 0000 0000 000x 0000 000u 0000 0000 0000 0000 ---- ---0 ---- ---0 ---- --qq ---- --uu -- -- -- -- -- --
8Ah(1,4) 8Bh(4) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
Write Buffer for the upper 5 bits of the Program Counter INTE TXIE -- -- RBIE SSPIE -- -- T0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE CCP2IE BOR(6)
1111 1111 1111 1111 0000 0000 0000 0000 --00 0000 --00 0000 -- -- -- -- -- --
0000 -010 0000 -010 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- ---- -000
Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 4: These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as `0'. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.
DS30390E-page 26
© 1997 Microchip Technology Inc.
PIC16C7X
TABLE 4-3:
Address Name
PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2)
Bank 0 00h(4) 01h 02h(4) 03h
(4)
INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
04h(4) 05h 06h 07h 08h(5) 09h
(5)
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(3) -- -- -- PEIE ADIF -- -- -- T0IE RCIF -- -- -- RE2 RE1 RE0
---- -xxx ---- -uuu ---0 0000 ---0 0000 0000 000x 0000 000u 0000 0000 0000 0000 ---- ---0 ---- ---0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
0Ah(1,4) 0Bh(4) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Write Buffer for the upper 5 bits of the Program Counter INTE TXIF RBIE SSPIF -- T0IF CCP1IF -- INTF TMR2IF -- RBIF TMR1IF CCP2IF
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000 --uu uuuu 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 -- CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
--00 0000 --00 0000 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- -- CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0
--00 0000 --00 0000 xxxx xxxx uuuu uuuu
A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as `0'.
© 1997 Microchip Technology Inc.
DS30390E-page 27
PIC16C7X
TABLE 4-3:
Address Name
PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2)
Bank 1 80h(4) 81h 82h(4) 83h
(4)
INDF OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON -- -- -- PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- -- -- -- -- ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
84h(4) 85h 86h 87h 88h(5) 89h
(5)
Indirect data memory address pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(3) -- -- Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF OBF -- PEIE ADIE -- -- IBOV -- T0IE RCIE -- -- PSPMODE -- PORTE Data Direction Bits
0000 -111 0000 -111 ---0 0000 ---0 0000 0000 000x 0000 000u 0000 0000 0000 0000 ---- ---0 ---- ---0 ---- --qq ---- --uu -- -- -- -- -- --
8Ah(1,4) 8Bh(4) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
Write Buffer for the upper 5 bits of the Program Counter INTE TXIE -- -- RBIE SSPIE -- -- T0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE CCP2IE BOR
1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D
0000 -010 0000 -010 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- ---- -000
Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and