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PIC16C9XX
8-Bit CMOS Microcontroller with LCD Driver
Devices included in this data sheet:
· PIC16C923 · PIC16C924
Available in Die Form
Microcontroller Core Features:
· · · · · · · · · High performance RISC CPU Only 35 single word instructions to learn 4K x 14 on-chip EPROM program memory 176 x 8 general purpose registers (SRAM) All single cycle instructions (500 ns) except for program branches which are two-cycle Operating speed: DC - 8 MHz clock input DC - 500 ns instruction cycle Interrupt capability Eight level deep hardware stack Direct, indirect and relative addressing modes
Peripheral Features:
· · · · 25 I/O pins with individual direction control 25-27 input only pins Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter, can be incremented during sleep via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · One pin that can be configured a capture input, PWM output, or compare output - Capture is 16-bit, max. resolution 31.25 ns - Compare is 16-bit, max. resolution 500 ns - PWM max resolution is 10-bits. Maximum PWM frequency @ 8-bit resolution = 32 kHz, @ 10-bit resolution = 8 kHz · Programmable LCD timing module - Multiple LCD timing sources available - Can drive LCD panel while in Sleep mode - Static, 1/2, 1/3, 1/4 multiplex - Static drive and 1/3 bias capability - 16 bytes of dedicated LCD RAM - Up to 32 segments, up to 4 commons
Common 1 2 3 4 Segment 32 31 30 29 Pixels 32 62 90 116
· Synchronous Serial Port (SSP) with SPITM and I2CTM · 8-bit multi-channel Analog to Digital converter (PIC16C924 only)
Special Microcontroller Features:
· Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Programmable code-protection · Power saving SLEEP mode · Selectable oscillator options · In-Circuit Serial ProgrammingTM (via two pins)
CMOS Technology
· Low-power, high-speed CMOS EPROM technology · Fully static design · Wide operating voltage range: 2.5V to 6.0V · Commercial and Industrial temperature ranges · Low-power consumption: - < 2 mA @ 5.5V, 4 MHz - 22.5 µA typical @ 4V, 32 kHz - < 1 µA typical standby current @ 3.0V
ICSP is a trademark of Microchip Technology Inc. I2C is a trademark of Philips Corporation. SPI is a trademark of Motorola Corporation.
© 1997 Microchip Technology Inc.
DS30444E - page 1
PIC16C9XX
Pin Diagrams
RA3 RA2 VSS RA1 RA0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
PLCC
RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
PIC16C923
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12
Shrink PDIP (750 mil)
MCLR/VPP RB3 RB2 RA0 RA1 VSS RA2 RA3 RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RE6/SEG11 RE5/SEG10 RE4/SEG09 RE3/SEG08 RE2/SEG07 RE1/SEG06 RE0/SEG05 RD4/SEG04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
RA3 RA2 VSS RA1 RA0 RB2 RB3 MCLR/VPP RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2
RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE7/SEG27 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin
DS30444E - page 2
RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIC16C923
TQFP
RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI
PIC16C923
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12
© 1997 Microchip Technology Inc.
PIC16C9XX
Pin Diagrams (Cont.'d)
RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 AVDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
PLCC
PIC16C924
Shrink PDIP (750 mil)
MCLR/VPP RB3 RB2 RA0/AN0 RA1/AN1 VSS RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12
RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RE6/SEG11 RE5/SEG10 RE4/SEG09 RE3/SEG08 RE2/SEG07 RE1/SEG06 RE0/SEG05 RD4/SEG04
TQFP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12
RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI
LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin
© 1997 Microchip Technology Inc.
RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2
RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE7/SEG27 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PIC16C924
PIC16C924
DS30444E - page 3
PIC16C9XX
Table of Contents
1.0 General Description..................................................................................................................................................................... 5 2.0 PIC16C9XX Device Varieties ...................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................ 9 4.0 Memory Organization ................................................................................................................................................................ 17 5.0 Ports .......................................................................................................................................................................................... 31 6.0 Overview of Timer Modules....................................................................................................................................................... 43 7.0 Timer0 Module .......................................................................................................................................................................... 45 8.0 Timer1 Module .......................................................................................................................................................................... 51 9.0 Timer2 Module .......................................................................................................................................................................... 55 10.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................... 57 11.0 Synchronous Serial Port (SSP) Module .................................................................................................................................... 63 12.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 79 13.0 LCD Module .............................................................................................................................................................................. 89 14.0 Special Features of the CPU ................................................................................................................................................... 103 15.0 Instruction Set Summary ......................................................................................................................................................... 119 16.0 Development Support.............................................................................................................................................................. 137 17.0 Electrical Characteristics ......................................................................................................................................................... 141 18.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 161 19.0 Packaging Information............................................................................................................................................................. 171 Appendix A: ................................................................................................................................................................................... 175 Appendix B: Compatibility ............................................................................................................................................................. 175 Appendix C: What's New................................................................................................................................................................ 176 Appendix D: What's Changed ........................................................................................................................................................ 176 Index .................................................................................................................................................................................................. 177 List of Equations And Examples ........................................................................................................................................................ 181 List of Figures..................................................................................................................................................................................... 181 List of Tables...................................................................................................................................................................................... 182 Reader Response .............................................................................................................................................................................. 186 PIC16C9XX Product Identification System ........................................................................................................................................ 187
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30444E - page 4
© 1997 Microchip Technology Inc.
PIC16C9XX
1.0 GENERAL DESCRIPTION
The PIC16C9XX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with an integrated LCD Driver module, in the PIC16CXXX mid-range family. All PICmicroTM microcontrollers employ an advanced RISC architecture. The PIC16CXXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C923 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The LCD module features programmable multiplex mode (static, 1/2, 1/3 and 1/4) and drive bias (static and 1/3). It is capable of driving up to 32 segments and up to 4 commons. It can also drive the LCD panel while in SLEEP mode. The PIC16C924 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The LCD module features programmable multiplex mode (static, 1/2, 1/3 and 1/4) and drive bias (static and 1/3). It is capable of driving up to 32 segments and up to 4 commons. It can also drive the LCD panel while in SLEEP mode. The PIC16C924 also has an 5-channel high-speed 8-bit A/D. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, and meters. The PIC16C9XX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and reset(s). A highly reliable Watchdog Timer with its own on-chip RC oscillator provides recovery in the event of a software lock-up. A UV erasable CERQUAD (compatible with PLCC) packaged version is ideal for code development while the cost-effective One-Time-Programmable (OTP) version is suitable for production in any volume. The PIC16C9XX family fits perfectly in applications ranging from handheld meters, thermostats, to home security products. The EPROM technology makes customization of application programs (LCD panels, calibration constants, sensor interfaces, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C9XX very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, capture and compare, PWM functions and coprocessor applications).
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXXX family of devices (Appendix B).
1.2
Development Support
PIC16C9XX devices are supported by the complete line of Microchip Development tools. Please refer to Section 16.0 for more details about Microchip's development tools.
© 1997 Microchip Technology Inc.
DS30444E- page 5
PIC16C9XX
TABLE 1-1: PIC16C9XX FAMILY OF DEVICES
PIC16C923 Clock Memory Maximum Frequency of Operation (MHz) EPROM Program Memory Data Memory (bytes) Timer Module(s) 8 4K 176 TMR0, TMR1, TMR2 1 SPI/I2C -- -- 4 Com, 32 Seg 8 25 27 2.5-6.0 Yes -- 64-pin SDIP, TQFP; 68-pin PLCC, Die 8 4K 176 TMR0, TMR1, TMR2 1 SPI/I2C -- 5 4 Com, 32 Seg 9 25 27 2.5-6.0 Yes -- 64-pin SDIP, TQFP; 68-pin PLCC, Die PIC16C924
Capture/Compare/PWM Module(s) Serial Port(s) Peripherals (SPI/I2C, USART) Parallel Slave Port A/D Converter (8-bit) Channels LCD Module Interrupt Sources I/O Pins Input Pins Voltage Range (Volts) Features In-Circuit Serial Programming Brown-out Reset Packages
All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30444E - page 6
© 1997 Microchip Technology Inc.
PIC16C9XX
2.0 PIC16C9XX DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C9XX Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C9XX family, there are two device "types" as indicated in the device number: 1. C, as in PIC16C924. These devices have EPROM type memory and operate over the standard voltage range. LC, as in PIC16LC924. These devices have EPROM type memory and operate over an extended voltage range.
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4
2.
Serialized Quick-Turnaround Production (SQTPSM) Devices
2.1
UV Erasable Devices
The UV erasable version, offered in CERQUAD package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Microchip's PICSTART® Plus and PRO MATE® II programmers both support the PIC16C9XX. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources.
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
© 1997 Microchip Technology Inc.
DS30444E - page 7
PIC16C9XX
NOTES:
DS30444E - page 8
© 1997 Microchip Technology Inc.
PIC16C9XX
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (500 ns @ 8 MHz) except for program branches. The PIC16C923 and PIC16C924 both address 4K x 14 of program memory and 176 x 8 of data memory. The PIC16CXXX can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXXX simple yet efficient, thus significantly reducing the learning curve. PIC16CXXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
© 1997 Microchip Technology Inc.
DS30444E - page 9
PIC16C9XX
FIGURE 3-1: PIC16C923 BLOCK DIAGRAM
13 EPROM Program Memory 4K x 14 Program Bus 14 Instruction reg Direct Addr 7 8 FSR reg STATUS reg 8 3 PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO PORTD W reg RD0-RD4/SEGnn 8 Level Stack (13-bit) Program Counter Data Bus 8 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS PORTB
RAM File Registers 176 x 8 RAM Addr 9
Addr MUX RB0/INT Indirect Addr RB1-RB7
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer 8
MUX
ALU
RD5-RD7/SEGnn/COMn MCLR VDD, VSS PORTE
RE0-RE7/SEGnn
PORTF
RF0-RF7/SEGnn
PORTG
RG0-RG7/SEGnn Timer0 Timer1, Timer2, CCP1
Synchronous Serial Port LCD
COM0 VLCD1 VLCD2 VLCD3 C1 C2 VLCDADJ
DS30444E - page 10
© 1997 Microchip Technology Inc.
PIC16C9XX
FIGURE 3-2: PIC16C924 BLOCK DIAGRAM
13 EPROM Program Memory 4K x 14 Program Bus 14 Instruction reg Direct Addr 7 8 FSR reg STATUS reg 8 3 PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO PORTD W reg RD0-RD4/SEGnn 8 Level Stack (13-bit) Program Counter Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB
RAM File Registers 176 x 8 RAM Addr 9
Addr MUX RB0/INT Indirect Addr RB1-RB7
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer 8
MUX
ALU
RD5-RD7/SEGnn/COMn MCLR VDD, VSS PORTE
RE0-RE7/SEGnn
PORTF
RF0-RF7/SEGnn
PORTG
RG0-RG7/SEGnn Timer0 A/D Timer1, Timer2, CCP1
Synchronous Serial Port LCD
COM0 VLCD1 VLCD2 VLCD3 C1 C2 VLCDADJ
© 1997 Microchip Technology Inc.
DS30444E - page 11
PIC16C9XX
TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION
Pin Name OSC1/CLKIN DIP Pin# 22 PLCC Pin# 24 TQFP Pin# 14 Pin Type I Buffer Type ST/CMOS Description Oscillator crystal input or external clock source input. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. The AN and VREF multiplexed functions are used by the PIC16C924 only. RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS 4 5 7 8 9 10 5 6 8 9 10 11 60 61 63 64 1 2 I/O I/O I/O I/O I/O I/O TTL TTL TTL TTL ST TTL RA0 can also be Analog input0. RA1 can also be Analog input1. RA2 can also be Analog input2. RA3 can also be Analog input3 or A/D Voltage Reference. RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. RA5 can be the slave select for the synchronous serial port or Analog input4. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT 12 13 4 I/O TTL/ST RB0 can also be the external interrupt pin. This buffer is a Schmitt Trigger input when configured as an external interrupt.
OSC2/CLKOUT
23
25
15
O
--
MCLR/VPP
1
2
57
I/P
ST
RB1 RB2 RB3 RB4 RB5 RB6
11 3 2 64 63 61
12 4 3 68 67 65
3 59 58 56 55 53
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL TTL TTL/ST Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. This buffer is a Schmitt Trigger input when used in serial programming mode. Interrupt on change pin. Serial programming data. This buffer is a Schmitt Trigger input when used in serial programming mode. PORTC is a bi-directional I/O port.
RB7
62
66
54
I/O
TTL/ST
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1
24 25 26 13 14 15 16
26 27 28 14 15 16 17
16 17 18 5 6 7 8 9
I/O I/O I/O I/O I/O I/O P
ST ST ST ST ST ST
RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input. RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). LCD Voltage Generation. LCD Voltage Generation. L = LCD Driver ST = Schmitt Trigger input
C2 17 18 Legend: I = input O = output -- = Not used
P P = power TTL = TTL input
DS30444E - page 12
© 1997 Microchip Technology Inc.
PIC16C9XX
TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.'d)
Pin Name COM0 DIP Pin# 59 PLCC Pin# 63 TQFP Pin# 51 Pin Type L Buffer Type Description Common Driver0 PORTD is a digital input/output port. These pins are also used as LCD Segment and/or Common Drivers. Segment Driver00/Digital Input/Output. Segment Driver01/Digital Input/Output. Segment Driver02/Digital Input/Output. Segment Driver03/Digital Input/Output. Segment Driver04/Digital Input/Output. Segment Driver29/Common Driver3/Digital Input. Segment Driver30/Common Driver2/Digital Input. Segment Driver31/Common Driver1/Digital Input. PORTE is a digital input or LCD Segment Driver port. Segment Driver05. Segment Driver06. Segment Driver07. Segment Driver08. Segment Driver09. Segment Driver10. Segment Driver11. Segment Driver27 (Not available on 64-pin devices). PORTF is a digital input or LCD Segment Driver port. Segment Driver12. Segment Driver13. Segment Driver14. Segment Driver15. Segment Driver16. Segment Driver17. Segment Driver18. Segment Driver19. PORTG is a digital input or LCD Segment Driver port. Segment Driver20. Segment Driver21. Segment Driver22. Segment Driver23. Segment Driver24. Segment Driver25. Segment Driver26. Segment Driver28 (Not available on 64-pin devices). LCD Voltage Generation. Analog Power (PIC16C924 only). Power (PIC16C923 only). LCD Voltage. -- LCD Voltage. L = LCD Driver ST = Schmitt Trigger input
RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RD5/SEG29/COM3 RD6/SEG30/COM2 RD7/SEG31/COM1
29 30 31 32 33 56 57 58
31 32 33 34 35 60 61 62
21 22 23 24 25 48 49 50
I/O/L I/O/L I/O/L I/O/L I/O/L I/L I/L I/L
ST ST ST ST ST ST ST ST
RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11 RE7/SEG27
34 35 36 37 38 39 40 -
37 38 39 40 41 42 43 36
26 27 28 29 30 31 32 -
I/L I/L I/L I/L I/L I/L I/L I/L
ST ST ST ST ST ST ST ST
RF0/SEG12 RF1/SEG13 RF2/SEG14 RF3/SEG15 RF4/SEG16 RF5/SEG17 RF6/SEG18 RF7/SEG19
41 42 43 44 45 46 47 48
44 45 46 47 48 49 50 51
33 34 35 36 37 38 39 40
I/L I/L I/L I/L I/L I/L I/L I/L
ST ST ST ST ST ST ST ST
RG0/SEG20 RG1/SEG21 RG2/SEG22 RG3/SEG23 RG4/SEG24 RG5/SEG25 RG6/SEG26 RG7/SEG28 VLCDADJ AVDD VDD VLCD1 VLCD2
49 50 51 52 53 54 55 -- 28 -- -- 27 18
53 54 55 56 57 58 59 52 30 21 21 29 19
41 42 43 44 45 46 47 -- 20 -- -- 19 10
I/L I/L I/L I/L I/L I/L I/L I/L P P P P P
ST ST ST ST ST ST ST ST
Legend: I = input O = output -- = Not used
P = power TTL = TTL input
© 1997 Microchip Technology Inc.
DS30444E - page 13
PIC16C9XX
TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.'d)
Pin Name VLCD3 VDD VSS NC DIP Pin# 19 20, 60 6, 21 -- PLCC Pin# 20 22, 64 7, 23 1 TQFP Pin# 11 12, 52 13, 62 -- Pin Type P P P -- Buffer Type -- -- -- -- Description LCD Voltage. Digital power. Ground reference. These pins are not internally connected. These pins should be left unconnected. L = LCD Driver ST = Schmitt Trigger input
Legend: I = input O = output -- = Not used
P = power TTL = TTL input
DS30444E - page 14
© 1997 Microchip Technology Inc.
PIC16C9XX
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-3. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)
PC PC+1 PC+2 Internal phase clock
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
© 1997 Microchip Technology Inc.
DS30444E - page 15
PIC16C9XX
NOTES:
DS30444E - page 16
© 1997 Microchip Technology Inc.
PIC16C9XX
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
4.2
Data Memory Organization
The PIC16C9XX family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 4K x 14 (0000h-0FFFh) is physically implemented. Accessing a location above the physically implemented addresses will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
The data memory is partitioned into four Banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1:RP0 (STATUS<6:5>) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. All four banks contain special function registers. Some "high use" special function registers are mirrored in other banks for code reduction and quicker access. 4.2.1 GENERAL PURPOSE REGISTER FILE
FIGURE 4-1:
PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 Reset Vector
The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5). The following General Purpose Registers are not physically implemented: 0000h · F0h-FFh of Bank 1 · 170h-17Fh of Bank 2 · 1F0h-1FFh of Bank 3 These locations are used for common access across banks.
User Memory Space
Interrupt Vector On-chip Program Memory (Page 0)
0004h 0005h 07FFh
On-chip Program Memory (Page 1)
0800h
0FFFh 1000h
1FFFh
© 1997 Microchip Technology Inc.
DS30444E - page 17
PIC16C9XX
FIGURE 4-2: REGISTER FILE MAP
File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(1) 80h 81h OPTION 82h PCL 83h STATUS 84h FSR 85h TRISA 86h TRISB 87h TRISC TRISD 88h TRISE 89h 8Ah PCLATH 8Bh INTCON 8Ch PIE1 8Dh 8Eh PCON 8Fh 90h 91h 92h PR2 93h SSPADD 94h SSPSTAT 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1(2) A0h General Purpose Register EFh Mapped in Bank 0 70h-7Fh Bank 1 F0h FFh Mapped in Bank 0 70h-7Fh Bank 2 16F 170 17F 1EFh Mapped in Bank 0 70h-7Fh Bank 3 1F0h 1FFh File Address Indirect addr.(1) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h PORTF 108h PORTG 109h 10Ah PCLATH 10Bh INTCON 10Ch 10Dh LCDSE 10Eh LCDPS 10Fh LCDCON 110h LCDD00 111h LCDD01 112h LCDD02 113h LCDD03 114h LCDD04 115h LCDD05 116h LCDD06 117h LCDD07 118h LCDD08 119h LCDD09 11Ah LCDD10 11Bh LCDD11 11Ch LCDD12 11Dh LCDD13 11Eh LCDD14 11Fh LCDD15 120h File Address Indirect addr.(1) OPTION PCL STATUS FSR TRISB TRISF TRISG PCLATH INTCON 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
ADRES(2) ADCON0(2)
General Purpose Register
7Fh Bank 0
Note
Unimplemented data memory locations, read as '0'. 1: Not a physical register. 2: These registers are not implemented on the PIC16C923.
DS30444E - page 18
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PIC16C9XX
4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh(1) 1Fh(1) Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON -- -- -- -- -- -- ADRES ADCON0 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu (4) (4) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read -- -- PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu 0000 0000 0000 0000 0000 0000 0000 0000
PORTD Data Latch when written: PORTD pins when read PORTE pins when read -- GIE LCDIF -- PEIE ADIF(2) -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE SSPIF T0IF CCP1IF INTF TMR2IF RBIF TMR1IF
---0 0000 ---0 0000 0000 000x 0000 000u 00-- 0000 00-- 0000 -- --
Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --uu uuuu 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000 xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
(5)
--
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000 -- -- -- -- -- -- -- -- -- -- -- --
xxxx xxxx uuuu uuuu ADON 0000 0000 0000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.
© 1997 Microchip Technology Inc.
DS30444E - page 19
PIC16C9XX
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Address Name Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh(1) Legend: Note 1: 2: 3: 4: 5: PR2 SSPADD SSPSTAT -- -- -- -- -- -- -- -- -- -- ADCON1 INDF OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 -- PCON -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 Write Buffer for the upper 5 bits of the PC INTE -- RBIE SSPIE T0IF CCP1IE INTF TMR2IE RBIF TMR1IE ---0 0000 ---0 0000 0000 000x 0000 000u 00-- 0000 00-- 0000 -- -- -- -- -- -- POR -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO
Indirect data memory address pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register -- -- PORTC Data Direction Register
PORTD Data Direction Register PORTE Data Direction Register -- GIE LCDIE -- PEIE ADIE(2) -- T0IE --
Unimplemented -- Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0 CKE D/A P S R/W UA BF
---- --0- ---- --u-- -- -- -- -- --
1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- ---- -000 -- -- -- -- -- -- -- -- -- -- ---- -000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.
DS30444E - page 20
© 1997 Microchip Technology Inc.
PIC16C9XX
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Address Name Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR -- PORTB PORTF PORTG -- PCLATH INTCON -- LCDSE LCDPS LCDCON LCDD00 LCDD01 LCDD02 LCDD03 LCDD04 LCDD05 LCDD06 LCDD07 LCDD08 LCDD09 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets
Indirect data memory address pointer Unimplemented PORTB Data Latch when written: PORTB pins when read PORTF pins when read PORTG pins when read Unimplemented -- GIE -- PEIE -- T0IE Write Buffer for the upper 5 bits of the PC INTE RBIE T0IF INTF RBIF
xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 -- --
---0 0000 ---0 0000 0000 000x 0000 000u -- --
Unimplemented SE29 -- LCDEN SEG07 COM0 SEG15 COM0 SEG23 COM0 SEG31 COM0 SEG07 COM1 SEG15 COM1 SEG23 COM1 SEG31 COM1(3) SEG07 COM2 SEG15 COM2 SEG23 COM2 SEG31 COM2(3) SEG07 COM3 SEG15 COM3 SEG23 COM3 SEG31 COM3(3) SE27 -- SLPEN SEG06 COM0 SEG14 COM0 SEG22 COM0 SEG30 COM0 SEG06 COM1 SEG14 COM1 SEG22 COM1 SEG30 COM1 SEG06 COM2 SEG14 COM2 SEG22 COM2 SEG30 COM2(3) SEG06 COM3 SEG14 COM3 SEG22 COM3 SEG30 COM3(3) SE20 -- -- SEG05 COM0 SEG13 COM0 SEG21 COM0 SEG29 COM0 SEG05 COM1 SEG13 COM1 SEG21 COM1 SEG29 COM1 SEG05 COM2 SEG13 COM2 SEG21 COM2 SEG29 COM2 SEG05 COM3 SEG13 COM3 SEG21 COM3 SEG29 COM3(3) SE16 -- VGEN SEG04 COM0 SEG12 COM0 SEG20 COM0 SEG28 COM0 SEG04 COM1 SEG12 COM1 SEG20 COM1 SEG28 COM1 SEG04 COM2 SEG12 COM2 SEG20 COM2 SEG28 COM2 SEG04 COM3 SEG12 COM3 SEG20 COM3 SEG28 COM3 SE12 LP3 CS1 SEG03 COM0 SEG11 COM0 SEG19 COM0 SEG27 COM0 SEG03 COM1 SEG11 COM1 SEG19 COM1 SEG27 COM1 SEG03 COM2 SEG11 COM2 SEG19 COM2 SEG27 COM2 SEG03 COM3 SEG11 COM3 SEG19 COM3 SEG27 COM3 SE9 LP2 CS0 SEG02 COM0 SEG10 COM0 SEG18 COM0 SEG26 COM0 SEG02 COM1 SEG10 COM1 SEG18 COM1 SEG26 COM1 SEG02 COM2 SEG10 COM2 SEG18 COM2 SEG26 COM2 SEG02 COM3 SEG10 COM3 SEG18 COM3 SEG26 COM3 SE5 LP1 LMUX1 SEG01 COM0 SEG09 COM0 SEG17 COM0 SEG25 COM0 SEG01 COM1 SEG09 COM1 SEG17 COM1 SEG25 COM1 SEG01 COM2 SEG09 COM2 SEG17 COM2 SEG25 COM2 SEG01 COM3 SEG09 COM3 SEG17 COM3 SEG25 COM3 SE0 LP0 LMUX0 SEG00 COM0 SEG08 COM0 SEG16 COM0 SEG24 COM0 SEG00 COM1 SEG08 COM1 SEG16 COM1 SEG24 COM1 SEG00 COM2 SEG08 COM2 SEG16 COM2 SEG24 COM2 SEG00 COM3 SEG08 COM3 SEG16 COM3 SEG24 COM3
1111 1111 1111 1111 ---- 0000 ---- 0000 00-0 0000 00-0 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.
© 1997 Microchip Technology Inc.
DS30444E - page 21
PIC16C9XX
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Address Name Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION PCL STATUS FSR -- TRISB TRISF TRISG -- PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO
Indirect data memory address pointer Unimplemented PORTB Data Direction Register PORTF Data Direction Register PORTG Data Direction Register Unimplemented -- GIE -- PEIE -- T0IE Write Buffer for the upper 5 bits of the PC INTE RBIE T0IF INTF RBIF
1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -- --
---0 0000 ---0 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.
DS30444E - page 22
© 1997 Microchip Technology Inc.
PIC16C9XX
4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 4-3:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 IRP bit7
R/W-0 RP1
R/W-0 RP0
R-1 TO
R-1 PD
R/W-x Z
R/W-x DC
R/W-x C bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
© 1997 Microchip Technology Inc.
DS30444E - page 23
PIC16C9XX
4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT pin interrupt, TMR0, and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
FIGURE 4-4:
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit7
R/W-1 INTEDG
R/W-1 T0CS
R/W-1 T0SE
R/W-1 PSA
R/W-1 PS2
R/W-1 PS1
R/W-1 PS0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS30444E - page 24
© 1997 Microchip Technology Inc.
PIC16C9XX
4.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
FIGURE 4-5:
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit7
R/W-0 PEIE
R/W-0 T0IE
R/W-0 INTE
R/W-0 RBIE
R/W-0 T0IF
R/W-0 INTF
R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear interrupt) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
© 1997 Microchip Technology Inc.
DS30444E - page 25
PIC16C9XX
4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
FIGURE 4-6:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 LCDIE bit7
R/W-0 ADIE(1)
U-0 --
U-0 --
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0 TMR2IE
R/W-0 TMR1IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
LCDIE: LCD Interrupt Enable bit 1 = Enables the LCD interrupt 0 = Disables the LCD interrupt ADIE: A/D Converter Interrupt Enable bit(1) 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 6:
bit 5-4: Unimplemented: Read as '0' bit 3:
bit 2:
bit 1:
bit 0:
Note 1: Bit ADIE is reserved on the PIC16C923, always maintain this bit clear.
DS30444E - page 26
© 1997 Microchip Technology Inc.
PIC16C9XX
4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 4-7:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 LCDIF bit7
R/W-0 ADIF(1)
U-0 --
U-0 --
R/W-0 SSPIF
R/W-0 CCP1IF
R/W-0 TMR2IF
R/W-0 TMR1IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
LCDIF: LCD Interrupt Flag bit 1 = LCD interrupt occurred (must be cleared in software) 0 = LCD interrupt did not occur ADIF: A/D Converter Interrupt Flag bit(1) 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 6:
bit 5-4: Unimplemented: Read as '0' bit 3:
bit 2:
bit 1:
bit 0:
Note 1: Bit ADIF is reserved on the PIC16C923, always maintain this bit clear.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
© 1997 Microchip Technology Inc.
DS30444E - page 27
PIC16C9XX
4.2.2.6 PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. For various reset conditions see Table 14-4 and Table 14-5.
FIGURE 4-8:
PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit7
U-0 --
U-0 --
U-0 --
U-0 --
U-0 --
R/W-0 POR
U-0 -- bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) Unimplemented: Read as '0'
bit 0:
DS30444E - page 28
© 1997 Microchip Technology Inc.
PIC16C9XX
4.3 PCL and PCLATH
Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address. The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-9 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).
4.4
Program Memory Paging
FIGURE 4-9:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU result
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
PIC16C9XX devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). Note: The PIC16C9XX ignores paging bit PCLATH<4>, which is used to access program memory pages 2 and 3. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556). 4.3.2 STACK
The PIC16CXXX family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
© 1997 Microchip Technology Inc.
DS30444E - page 29
PIC16C9XX
Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used).
4.5
Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register (FSR). Reading the INDF register itself indirectly (FSR = '0') will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-10. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.
EXAMPLE 4-1:
ORG 0x500 BSF PCLATH,3 CALL SUB1_P1 : : : ORG 0x900 SUB1_P1: : : RETURN
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh)
;called subroutine ;page 1 (800h-FFFh) ;return to Call subroutine ;in page 0 (000h-7FFh)
EXAMPLE 4-2:
movlw movwf clrf incf btfss goto :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 4-10: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0 6 from opcode 0 IRP
Indirect Addressing
7 FSR register 0
bank select
location select 00 00h 01 10 11
bank select 00h
location select
Data Memory
7Fh
7Fh
Bank 0 For memory map detail see Figure 4-2.
Bank 1
Bank 2
Bank 3
DS30444E - page 30
© 1997 Microchip Technology Inc.
PIC16C9XX
5.0 PORTS
FIGURE 5-1:
Data bus WR Port
Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
BLOCK DIAGRAM OF PINS RA3:RA0 AND RA5
Q VDD
D
5.1
PORTA and TRISA Register
CK
Q
The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All RA pins have data direction bits (TRISA register) which can configure these pins as output or input. Setting a bit in the TRISA register puts the corresponding output d