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GND
GND
10
8
50
49
48
52
*VDD
IC506 74HC4094 Vol Vol Vol Vol Vol Vol Mute PH D509 D510 D511 D512 D513 D514 D515 D516 R532 330R 4 R533 330R 5 R534 330R 6 R535 330R 7 R536 330R 14 R537 330R 13 R538 330R 12 R539 330R 11
*VDD
51
7
6
4
47
5
3
2
1
16
EXTAL
MODA
VRH
E
PE7
PE3
PE6
STRA/AS
VDD
Q1 Q2 Q3 Q4 Q5 Q6 Q7
STR CLK
1 2 3
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 12 13
IC504D
VCC
Q0
EN
15
IC502 27C256
MODB
VRL
R/W
VSS
PE2
28
GND
8
IC507 74HC4094 CD D517 D518 D519 D520 D521 D522 D523 S/BY R540 330R 4 R541 330R 5 R542 330R 6 R543 330R 7 R544 330R 14 R545 330R 13 R546 330R 12 R547 330R 11
16
PD1
PD2
PD3
PD4
PD5
PA7
PA6
PA5
PA4
PA3
PA2
VDD
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
EN STR CLK
15 1 2 3 11
74HC00 C527 1nF
PA1
A12 A13 A14 VPP CE OE
R503 10k
R502 10k
R501 10k C507 100n
VDD
21
22
23
24
25
26
27
28
29
30
31
32
VI AU SP Tape
DATA
*VDD 1 20 22
GND
IC504B
GND
Q Q
9
6
74HC00
4
1 5 *MC_IN 2
14
R514 1k8
*CCS_ON PROT_OUT *AMPIN
T502 BC846B
T501 BC846B
*VDD *VDD
33
14
8
7
HA7Z Micro controller diagram. c Cyrus Electronics Ltd 13-Aug-2001
S:\STUART\SERV1586.SCH
VR501
7805
*VDD
C502 C503 C509 C511 C510 C512 C513
*VDD *VDD
R562 10k R561 10k
*VIN *CCS_ON *FUSE *MAINS *OVER_C *AMPIN *PSXO *PSX_MOD
CONLIF15 R563 1k R550 1k R551 1k R552 1k R553 1k R554 1k R555 1k
CON501 R549 1k R556 1k R557 1k R558 1k R559 1k R560 1k
*VIN
C501 100nF
I/P O/P
*MC_IN *MC_OUT *SEL_CE *VOL_CE *DATA *CLK
G
*VDD
IC503 74HC373
20
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC
100nF
100nF
100nF
100nF
100nF
100nF
100nF
RE501
1 2 3
ROT_A ROT_B
2 5 *VDD
IC505 74HC4094 R524 330R 4 R525 330R 5 R526 330R 6 R527 330R 7 R528 330R 14 R529 330R 13 R530 330R 12 R531 330R 11
D0 D1 D2 D3 D4 D5 D6 D7 OE
3 4 7 8 13 14 17 18 1 11
X501 IR501 ROTARY_ENC
C521
C520
C519
C515
C514
C516
C526
C504
C518
C517
C522
C523
C524
C525
*VDD
6 9 EN 15 1 2 3
R564 1k
16
1nF
VDD
Vol Vol Vol Vol Vol Vol Vol Vol
D501 D502 D503 D504 D505 D506 D507 D508
12 /RESET DIS_CE *DATA *CLK 15 16 19
*VDD 1 2 3 IR 9 10
74HC00 R507 4k7 IC504C
1nF
1nF
1nF
1nF
1nF
1nF
100nF
1nF
1nF
1nF
1nF
1nF
1nF
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VDD OUT GND
REMOTE_EYE
STR CLK
8 *VDD
R506 4k7 R548 10R
DATA
SW501 C508 100n
Q Q
9
LE
R518 43k S/BY
8.00MHz Use guard tracks.
R508 10M C506 22pF
*MAINS *PSXO *PSX_MOD
SW502
R523 20k MUTE
C505 22pF
SW503
R521 10k BAL
8 11 12 13 15 16 17 18 19 /RESET 9 10 11 12 13 14 15 16 17 *VDD R504 4k7 18 19
R505 4k7 20
XTAL PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
PE5 PE1 PE4 PE0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0
46 45 44 43 42 41 40 39 38 37 36 35 34
*FUSE
SW504
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
D0 D1 D2 D3 D4 D5 D6 D7
DATA
*OVER_C
R517 43k PH
SW505
R522 20k CD
IC501
MC68HC11A8
Q Q
9
HA7Z Micro controller diagram.
68HC11 MICRO PROCESSOR
SW506
R520 10k TU
RESET XIRQ IRQ PD0
*VDD
SW507
R519 91k VI
*VDD
*VDD
*VDD
SW508
R516 43k AU
TU
IR ROT_A ROT_B *CLK *DATA DIS_CE *VOL_CE *SEL_CE
SW509
R515 20k SP
3
IC504A 74HC00
*MC_OUT
SW510
R512 10k TP
R511 10k Q501 Q502 Q503 Q504 Q505 Q506 Q507 Q508
C530 100n
R510 10k
C529 100n
R513 10k
C528 100n
MOUNTING HOLES