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Complete PCB Design Using OrCad Capture and Layout
By
Kraig Mitzner
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This eBook does not include ancillary media that was packaged with the printed version of the book.
Newnes is an imprint of Elsevier 30 Corporate Drive, Suite 400, Burlington, MA 01803, USA Linacre House, Jordan Hill, Oxford OX2 8DP, UK Copyright © 2007, Elsevier Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher. Permissions may be sought directly from Elsevier's Science & Technology Rights Department in Oxford, UK: phone: ( 44) 1865 843830, fax: ( 44) 1865 853333, e-mail: [email protected]. You may also complete your request on-line via the Elsevier homepage (http://elsevier.com), by selecting "Customer Support" and then "Obtaining Permissions." Recognizing the importance of preserving what has been written, Elsevier prints its books on acid-free paper whenever possible. Library of Congress Cataloging-in-Publication Data Mitzner, Kraig. Complete PCB design using OrCad capture and layout / Kraig Mitzner. p. cm. Includes bibliographical references and index. ISBN-13: 978-0-7506-8214-5 (pbk. : alk. paper) ISBN-10: 0-7506-8214-0 (pbk. : alk. paper) 1. Printed circuits--Design and construction. 2. OrCAD SDT. I. Title. TK7868.P7.M56 2007 621.3815'31--dc22 2006034059 British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. ISBN-13: 978-0-7506-8214-5 ISBN-10: 0-7506-8214-0 For information on all Newnes publications visit our Web site at www.books.elsevier.com Typeset by Charon Tec Ltd (A Macmillan Company), Chennai, India www.charontec.com Printed in China. 07 08 09 10 10 9 8 7 6 5 4 3 2 1
Table of Contents
INTRODUCTION XV ACKNOWLEDGMENTS
XIX
CHAPTER 1
INTRODUCTION TO PCB DESIGN AND CAD ............................................... 1
Computer-Aided Design and the OrCAD Design Suite ................................1 Printed Circuit Board Fabrication ...................................................................2 PCB cores and layer stack-up ...................................................................2 PCB fabrication process ............................................................................4 Photolithography and chemical etching .................................................5 Mechanical milling ....................................................................................8 Layer registration......................................................................................9 Function of OrCAD Layout in the PCB Design Process ...............................11 Design Files Created by Layout....................................................................14 Layout format files (.MAX).....................................................................14 Postprocess (Gerber) files .......................................................................14 PCB assembly layers and files ................................................................14
CHAPTER 2
INTRODUCTION TO THE PCB DESIGN FLOW BY EXAMPLE ............................. 17
Overview of the Design Flow ......................................................................17
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Creating a Circuit Design with Capture.......................................................17 Starting a new project ............................................................................17 Placing parts ............................................................................................20 Wiring (connecting) the parts ................................................................23 Creating the Layout netlist in Capture ..................................................23 Designing the PCB with Layout ...................................................................25 Starting Layout and importing the netlist ............................................25 Making a board outline ..........................................................................29 Placing the parts .....................................................................................31 Autorouting the board ...........................................................................32 Manual routing .......................................................................................32 Cleanup ....................................................................................................34 Locking traces..........................................................................................34 Performing a design rule check .............................................................35 Postprocessing the board design for manufacturing...........................35
CHAPTER 3
PROJECT STRUCTURES AND THE LAYOUT TOOL SET..................................... 39
Project Setup and Schematic Entry Details .................................................39 Capture projects explained ....................................................................39 Capture part libraries explained ............................................................42 Understanding the Layout Environment and Tool Set ..............................43 Board technology files............................................................................43 The AutoECO utility ................................................................................44 The session frame and Design window ................................................46 The toolbar ..............................................................................................47 Controlling the autorouter.....................................................................57 Postprocessing and layer details ...........................................................60
CHAPTER 4
INTRODUCTION TO INDUSTRY STANDARDS ................................................. 65
Introduction to the Standards Organizations.............................................66
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Institute for Printed Circuits (IPC-Association Connecting Electronics Industries) .......................................................................66 Electronic Industries Alliance (EIA) ........................................................66 Joint Electron Device Engineering Council (JEDEC) ..............................66 International Engineering Consortium (IEC) .........................................67 Military Standards ..................................................................................67 American National Standards Institute (ANSI) .....................................67 Institute of Electrical and Electronics Engineers (IEEE) ........................67 Classes and Types of PCBs ............................................................................68 Performance classes ................................................................................68 Producibility levels ..................................................................................68 Fabrication types and assembly subclasses ..........................................69 OrCAD Layout design complexity levels--IPC performance classes..........................................................................69 IPC land pattern density levels ..............................................................70 Introduction to Standard Fabrication Allowances .....................................70 Registration tolerances...........................................................................70 Breakout and annular ring control ........................................................70 PCB Dimensions and Tolerances ..................................................................71 Standard panel sizes ...............................................................................71 Tooling area allowances and effective panel usage .......................................................................................72 Standard finished PCB thickness............................................................72 Core thickness .........................................................................................73 Prepreg thickness ....................................................................................73 Copper thickness for PTHs and vias.......................................................73 Copper cladding/foil thickness ...............................................................74 Copper Trace and Etching Tolerances ..........................................................75 Standard Hole Dimensions ...........................................................................76 Soldermask Tolerance ...................................................................................77 End Note ........................................................................................................77 Suggested reading ..................................................................................77 Other items of interest ...........................................................................77
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CHAPTER 5
INTRODUCTION TO DESIGN FOR MANUFACTURING ...................................... 79
Introduction to PCB Assembly and Soldering Processes ............................79 Assembly Processes ......................................................................................79 Manual assembly processes ...................................................................79 Automated assembly processes (pick and place) .................................80 Soldering Processes ......................................................................................81 Manual soldering ....................................................................................81 Wave soldering .......................................................................................82 Reflow soldering .....................................................................................84 Component Placement and Orientation Guide ..........................................85 Component Spacing for Through-hole Devices..........................................86 Discrete THDs ..........................................................................................86 Integrated circuit through-hole devices................................................86 Mixed discrete and IC through-hole devices ........................................86 Holes and jumper wires..........................................................................86 Component Spacing for Surface-Mounted Devices .............................86 Discrete SMDs .........................................................................................86 Integrated-circuit SMDs..........................................................................86 Mixed discrete and IC SMDs...................................................................86 Mixed THD and SMD Spacing Requirements ..............................................86 Footprint and Padstack Design for PCB Manufacturability .......................94 Land Patterns for Surface-Mounted Devices ..............................................94 SMD padstack design .............................................................................96 SMD footprint design .............................................................................99 Land Patterns for Through-hole Devices ..................................................101 Footprint design for through-hole devices.........................................101 Padstack design for through-hole devices..........................................103 Hole-to-lead ratio .................................................................................103 PTH land dimension (annular ring width) ...........................................104 Clearance between plane layers and PTHs .........................................106 Soldermask and solder paste dimensions ...........................................107
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CHAPTER 6
PCB DESIGN FOR SIGNAL INTEGRITY .................................................... 109
Circuit Design Issues Not Related to PCB Layout......................................109 Noise ......................................................................................................109 Distortion...............................................................................................110 Frequency response ..............................................................................111 Issues Related to PBC Layout ...............................................................111 Electromagnetic Interference and Cross Talk ......................................111 Magnetic fields and inductive coupling ..............................................112 Loop inductance ....................................................................................115 Electric fields and capacitive coupling.................................................117 Ground Planes and Ground Bounce ..........................................................119 What ground is and what it is not ......................................................119 Ground (return) planes .........................................................................122 Ground bounce and rail collapse .........................................................123 Split power and ground planes ...........................................................125 PCB Electrical Characteristics ......................................................................127 Characteristic impedance .....................................................................127 Reflections .............................................................................................133 Ringing...................................................................................................137 Electrically long traces ..........................................................................139 Critical length ........................................................................................142 Transmission line terminations ............................................................143 PCB Routing Topics .....................................................................................144 Parts placement for electrical considerations .....................................145 PCB layer stack-up ................................................................................146 Bypass capacitors and fanout ..............................................................151 Trace width for current carrying capability ........................................151 Trace width for controlled impedance ................................................153 Trace spacing for voltage withstanding ..............................................163 Trace spacing to minimize cross talk (3w rule) ...................................163 Traces with acute and 90ș angles ........................................................164
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Contents
CHAPTER 7
MAKING AND EDITING CAPTURE PARTS ................................................. 167
The Capture Part Libraries ..........................................................................167 Types of Packaging .....................................................................................168 Homogeneous parts .............................................................................168 Heterogeneous parts ............................................................................169 Pins ...............................................................................................................169 Part Editing Tools ........................................................................................170 The Select tool and settings .................................................................170 The pin tools..........................................................................................170 The graphics tools .................................................................................171 The zoom tools......................................................................................171 Constructing Capture Parts ........................................................................171 Method 1: Constructing Parts Using the New Part Option (Design Menu).....................................................................................................172 Design example for a passive, homogeneous part ............................172 Design example for an active, multipart, homogeneous component ......................................................................................180 Assigning power pin visibility .............................................................183 Design example for a passive, heterogeneous part...........................184 Method 2: Constructing Parts with Capture Using the Design Spreadsheet...........................................................................................187 Method 3: Constructing Parts Using Generate Part from the Tools Menu ......................................................................................................190 Method 4: Generating Parts with the PSpice Model Editor.....................192 Generating a Capture part library from a PSpice model library...............................................................................................193 Making and/or Obtaining PSpice Libraries for Making New Capture Parts ...................................................................................194 Downloading libraries and/or models from the Internet ..................195 Making a PSpice model from a Capture project .................................196 Adding PSpice templates (models) to preexisting Capture parts .....206 Constructing Capture Symbols ..................................................................208
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CHAPTER 8
MAKING AND EDITING LAYOUT FOOTPRINTS ........................................... 211
Introduction to the Library Manager ........................................................211 Introduction to Layout's Footprint Libraries and Naming Conventions ....................................................................................212 Layout's footprint libraries...................................................................213 Naming conventions .............................................................................213 The Composition of Footprints ..................................................................217 Padstacks ...............................................................................................217 Obstacles ...............................................................................................218 Text ........................................................................................................220 Datums and insertion origins...............................................................220 The Basic Footprint Design Process ...........................................................221 Working with Padstacks .............................................................................226 Accessing existing padstacks ...............................................................227 Editing padstack properties from the spreadsheet ............................228 Saving footprints and padstacks .........................................................229 Footprint Design Examples ........................................................................231 Design example 1: a surface-mount footprint design .......................232 Design example 2: a modified through-hole footprint design ..............................................................................................237 Using the Pad Array Generator..................................................................243 Introduction...........................................................................................243 Footprint design for PGAs ....................................................................243 Footprint design for BGAs....................................................................248 Blind, buried, and microvias.................................................................258 Mounting holes .....................................................................................259 Printing a catalog of a footprint library ..............................................261
CHAPTER 9
PCB DESIGN EXAMPLES .................................................................... 263
Overview of the Design Flow ....................................................................264
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Example 1: Dual Power Supply, Analog Design .......................................266 Initial design concept and preparation ...............................................267 Project setup and design in Capture ...................................................268 Defining the board requirements ........................................................285 Importing the design into Layout........................................................288 Setting up the board ............................................................................289 Prerouting the board ............................................................................306 Autorouting the board .........................................................................316 Finalizing the design.............................................................................318 Example 2: Mixed Analog/Digital Design Using Split Power, Ground Planes .....................................................................................................322 Mixed-signal circuit design in Capture................................................322 Power and ground connections to digital and analog parts .............324 Connecting separate analog and digital grounds to a split plane ........................................................................................324 Using busses for digital nets ................................................................327 Defining the layer stack-up for split planes .......................................328 Establishing a primary power plane....................................................330 Creating split ground planes................................................................334 Creating nested power planes with copper pours .............................336 Using anti-copper on plane layers.......................................................338 Setting up and running the autorouter ..............................................340 Moving a routed trace to a different layer .........................................342 Adding ground planes and guard traces to routing layers ...............342 Defining vias for flood planes/pours ...................................................345 Setting the copper pour spacing .........................................................347 Stitching a ground plane manually .....................................................348 Using anti-copper obstacles on copper pours ....................................349 Routing guard traces and rings ...........................................................349 Example 3: Multipage, Multipower, and Multiground Mixed A/D PCB Design with PSpice ........................................................................352 Project setup for PSpice simulation and Layout .................................354 Adding schematic pages to the design ...............................................356
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Using off-page connectors with wires ................................................358 Using off-page connectors with busses ..............................................359 Setting up multiple-ground systems ...................................................359 Setting up PSpice sources.....................................................................360 Performing PSpice simulations ............................................................361 Preparing the simulated project for Layout........................................364 Assigning a new technology file .........................................................365 Placing parts on the bottom (back) of a board...................................365 Layer stack-up for a multiground system ...........................................365 Net layer assignments ..........................................................................367 Through-hole and blind via setup .......................................................367 Fanning out a board with multiple vias ..............................................367 Overriding known errors in Layout .....................................................370 Autorouting with the DRC/route box..................................................370 Using forced thermals to connect ground planes ..............................372 Using the AutoECO to update a board from Capture ........................372 Example 4: High-Speed Digital Design......................................................376 Layer setup for microstrip transmission lines .....................................380 Via design for heat spreaders ..............................................................381 Constructing a heat spreader with copper area obstacles ................382 Using free vias as heat pipes ...............................................................382 Determining critical trace length of transmission lines .....................387 Routing controlled impedance traces..................................................388 Moated ground areas for clock circuits ...............................................390 Routing curved traces ...........................................................................390 Gate and pin swapping ........................................................................392 Stitching a ground plane with the free via matrix.............................395 Miscellaneous Items....................................................................................397 Fixing bad pad exits..............................................................................397 Design cache--cleanup, replace, update.............................................398 Adding test points ................................................................................400 Types of AutoECOs ...............................................................................401
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Contents
Making a custom Capture template ....................................................403 Making a custom Layout technology/template file ...........................403 Using the Stackup Editor ............................................................................404 Using the Stackup Editor with an active board design......................404 Using the Stackup Editor to set up a custom technology or template file ....................................................................................407 Submitting stack-up drawings with Gerber files ...............................408 Adding solder thieves...........................................................................408 Printing a footprint catalog from a PCB design..................................409
CHAPTER 10
POSTPROCESSING AND BOARD FABRICATION............................................ 411
The Circuit Design with OrCAD..................................................................411 Schematic design in Capture ................................................................411 The board design with Layout .............................................................413 Postprocessing the design with Layout ..............................................414 Fabricating the Board .................................................................................417 Choosing a board house.......................................................................417 Setting up a user account.....................................................................417 Submitting Gerber files and requesting a quote................................418 Annotating the layer types and stack-up ...........................................419 Receipt inspection and testing.............................................................422 Nonstandard Gerber files .....................................................................422
CHAPTER 11
ADDITIONAL TOOLS .......................................................................... 423
Using PSpice to Simulate Transmission Lines ...........................................423 Simulating digital transmission lines ..................................................424 Simulating analog signals ....................................................................427 Using Microsoft Excel with a Bill of Materials Generated by Capture ..................................................................................................427 Using the SPECCTRA Autorouter with Layout ..........................................429
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Introduction to GerbTool............................................................................437 Opening a Layout-generated Gerber file with GerbTool ..................437 Making a .DRL file for a CNC machine.................................................438 Panelization ...........................................................................................443 Using the IPC-7351 Land Pattern Viewer ..................................................449 Using CAD Tools to 3-D Model a PCB ........................................................452
APPENDICES
Appendix A: Layout Technology Files .......................................................455 Appendix B: List of Design Standards .......................................................457 Appendix C: A Partial List of Packages and Footprints and Some of the Footprints Included in OrCAD Layout ............................459 Appendix D: Rise and Fall Times for Various Logic Families ....................471 Appendix E: Drill and Screw Dimensions ..................................................473 Appendix F: References by Subject ...........................................................475
BIBLIOGRAPHY AND REFERENCES .......................................................... 491 INDEX ............................................................................................ 495
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Introduction to Complete PCB Design Using OrCAD Capture and Layout
I did not write this book because I am an OrCAD guru. I wrote it because no up-to-date references were available when I was trying to learn how to use the software. This book is the one I wish I would have had. This book was born from notes I compiled as I learned (the hard way) to use the software. The initial intent of the book was to describe how to use OrCAD Layout specifically. Along the way, though, I realized also that I (and many of the engineers I talked to) had a lot to learn about the printed circuit board (PCB) design process itself. There was a significant amount of information available on PCB design from both the electrical and the manufacturing aspects, but there was not an easily accessible resource that covered those subjects with how to use the software. That is the intent of this book. Chapter 1 introduces the reader to the basics of PCB design. The chapter begins by introducing the concepts of computer-aided engineering, computer-aided design, and computer-aided manufacturing. The chapter then explains how these tools are used to design and manufacture multilayer PCBs. Many 3-D pictures are used to show the construction of PCBs. Topics such as PCB cores and layer stack-up, apertures, D-codes, photolithography, layer registration, plated through-holes, and Gerber files are explained. Chapter 2 leads new users of the software through a very simple design example. The purpose of the example is to paint a "big picture" of the design flow process. The example begins with a blank schematic page and ends with the Gerber files. The circuit is ridiculously simple so that it is not a distraction to understanding the process itself. Along the way some of Layout's routing tools are briefly introduced along with some of the other tools, which sets the stage for Chap. 3. Chapter 3 provides an overview of the OrCAD project files and structure and explains Layout's tool set in detail. The chapter revisits and explains some of the actions performed and tools used during the example in Chap. 2. Gerber files are also explained in detail. Chapter 4 introduces some of the industry standards organizations related to the design and fabrication of PCBs (e.g., IPC and JEDEC). PCB performance classes and producibility levels are also described along with the basic ideas behind standard fabrication allowances. These concepts are described here to help the reader realize some of the fabrication issues up front to help minimize board failures and to identify some of the guides and standards resources that are available for PCB design.
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Introduction Chapter 5 addresses the mechanical aspect of PCB design--design for manufacturability (DFM). The chapter explains where parts should be placed on the board, how far apart, and in what orientation from a manufacturing perspective. OrCAD Layout's design rule checker is then considered relative to the manufacturing concepts and IPC's courtyard concepts. To aid in understanding the design issues, manufacturing processes such as reflow and wave soldering, pick-and-place assembly, and thermal management are discussed. The information is then used as a guide in designing plated through-holes, surface-mount lands, and Layout footprints in general. Tables summarize the information and serve as a design guide during footprint design and PCB layout. Chapter 6 addresses the electrical aspect of PCB design. There are several good references available on signal integrity, electromagnetic interference, and electromagnetic compatibility. Chapter 6 provides an overview of those topics and applies them directly to PCB design. Topics such as loop inductance, ground bounce, ground planes, characteristic impedance, reflections, and ringing are discussed. The idea of "the unseen schematic" (the PCB layout) and its role in circuit operation on the PCB is introduced. Look-up tables and equations are provided to determine required trace widths for current handling and impedance as well as required trace spacing for high-voltage designs and high-frequency designs. Various layer stack-up topographies for analog, digital, and mixed-signal applications are also described. The design examples in Chap. 9 demonstrate how to apply the layer stack-ups described in this chapter. Chapter 7 explains how to construct Capture parts using the Capture Library Manager and Part Editor and the PSpice Model Editor. Heterogeneous and homogeneous parts are developed in examples using four different methods. Different methods are used depending on whether a part will be used for simple schematic entry, design projects intended for PCB layout, PSpice simulations, or all of the above. The chapter also demonstrates how to attach PSpice models to Capture's schematic parts using PSpice models downloaded from the Internet and basic PSpice models developed from functional Capture projects. The Capture parts can then be used for both PSpice simulations and PCB layout as demonstrated in Chap. 9. Detailed coverage of padstacks and footprints is covered in Chap. 8. The chapter introduces the Layout Library Manager, Layout's footprint naming conventions, and the basic composition of a footprint. Then a detailed description of the padstack (as it relates to PCB manufacturing described in Chaps. 1 and 5) is given, as it is the foundation of both footprint design and PCB routing. Design examples are provided to demonstrate how to design discrete through-hole and surface-mount devices and how to use the pad array generator to design footprints for pin grid arrays and ball grid arrays with dogbone fanouts included with the footprint. Chapter 9 provides four PCB design examples that use the material covered in the previous eight chapters. The first example is a simple analog design using a single op-amp. The design shows how to set up multiple plane layers for positive and negative power supplies and ground. The design also demonstrates several key concepts in Capture, such as how to connect global nets, how to assign footprints, how to perform design rule checks, how to
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Introduction use the Capture part libraries, how to generate a bill of materials (BOM), and how to use the BOM as an aid in the design process in Capture and Layout. The design also shows how to perform important tasks in Layout such as how to load board technology files, locate specific parts, and modify padstacks. Intertool communication (such as annotation and back annotation) between Capture and Layout is also demonstrated. The second design is a mixed digital/analog circuit. In addition to the tasks demonstrated in the first example, the design also demonstrates how to set up and use split planes to isolate analog and digital power supplies and grounds. Other tasks include using copper pours on routing layers to make partial ground planes, using copper pours on plane layers to make nested power and ground planes, and defining anti-copper areas on plane and routing layers. The third example uses the same mixed digital/analog circuit from the second example but demonstrates how to use multiple page schematics and off-page connectors to add PSpice simulations to a Capture project used for PCB layout, all within a single project design. It also demonstrates how to construct multiple, separated power and ground planes and a shield plane to completely isolate analog from digital circuitry. The use of guard rings and guard traces is also demonstrated. The fourth example is a high-speed digital design, which demonstrates how to design transmission lines, stitch multilayer ground planes, perform pin/gate swapping, place moated ground areas for clock circuitry, and design a heat spreader. Chapter 10 describes how to postprocess a PCB design and generate specific Gerber files. Through an example it is shown how to relate the OrCAD Layout design perspective and layer stack-up (including image polarity) to the board manufacturer's perspective by submitting Gerber files to an actual board manufacturer via the Internet. The discussion also provides an example fabrication quote. Nonstandard Gerber files are briefly discussed as well as Gerber files that are generated for PCBs with nonplated mounting holes. Chapter 11 introduces other tools that can be used with OrCAD Capture and Layout to enhance the PCB design process. The chapter provides examples of how to use Microsoft Excel with the bill of materials generated by Capture to create parts lists and various other tracking documents that can be used during the PCB layout process to minimize design errors. Other examples include how to use PSpice to simulate transmission lines to aid in circuit design and PCB layout, how to use the SPECCTRA autorouter with Layout to route high-density PCB designs faster and with less manual cleanup, how to use GerbTool to panelize a board design, and how to use Layout to generate a .DXF file that can be used by a graphics program to construct a 3-D image of your board design. The IPC Land Pattern Viewer is also introduced in this chapter. Kraig Mitzner [email protected]
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Acknowledgments
The author would like to thank the following: My wife Jody, son Stephen, and daughter Chelsey: thank you for your endless patience and understanding. This book is dedicated to you. Without your support this book could not have been completed. Cadence Design Systems, Inc. for allowing Elsevier to distribute OrCAD software with this book. Chuck Glaser (and everyone else) at Elsevier for enthusiastically taking on a first-time author. Advanced Circuits for allowing me to use their Web site to write Chap. 10. Dr. Jeff Will at Valparaiso University for his encouragement at "just the right time" and his invaluable feedback during the writing process. Dr. David Galipeau at South Dakota State University for teaching me about the writing process and for giving me the courage to face criticism: "Good writing is not written, it is rewritten." And most importantly God for giving me the gift of curiosity, the drive to figure things out, and the desire to share that knowledge with others.
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CHAPTER
1
Introduction to PCB Design and CAD
Computer-Aided Design and the OrCAD Design Suite
Before digging into the details of Layout, we will take a moment to discuss computer-aided engineering (CAE) tools in general. Computer-aided engineering tools cover all aspects of engineering design from drawings to analysis to manufacturing. Computer-aided design (CAD) is a category of CAE that is related to the physical layout and drawing development of a system design. CAD programs specific to the electronics industry are known as electronic CAD (ECAD) or electronic design automation (EDA). EDA tools reduce development time and cost because they allow designs to be simulated and analyzed prior to purchasing and manufacturing hardware. Once a design has been proven through drawings, simulations, and analysis, the system can be manufactured. Applications used in manufacturing are known as computer-aided manufacturing (CAM) tools. CAM tools use software programs and design data (generated by the CAE tools) to control automated manufacturing machinery to turn a design concept into reality. So how does OrCAD/Cadence fit into all of this? Cadence owns and manages many types of CAD/CAM products related to the electronics industry, including the OrCAD design suite. The OrCAD design suite can be purchased through resellers such as EMA Design Automation, Inc., who package different combinations of CAD/CAM applications, including Capture, PSpice, and Layout, to suit customers' needs. Although these applications can operate individually, bundling the individual tools into one suite allows for intertool communication. The OrCAD tools can also interact with other CAD/CAM tools such as GerbTool, SPECCTRA, or Allegro. Chapter 11 covers the use of these tools with OrCAD. Capture is the centerpiece of the package and acts as the prime EDA tool. Capture contains extensive parts libraries that may be used to generate schematics that stand alone or that interact with PSpice, or Layout, or both simultaneously. A representation of a Capture part is shown in Fig. 1-1. The pins on a Capture part can be mapped into the pins of a PSpice model and/or the pins of a physical package in Layout. PSpice is a CAE tool that contains the mathematical models for performing simulations, and Layout is a CAD tool that converts a symbolic schematic diagram into a physical representation of the design. Netlists are used to interconnect parts within a design and connect each of the parts with its model and footprint. In addition to being a CAD tool, Layout also functions as a front-end CAM tool by generating the data on which other CAM
1
Chapter 1
A"Part" [PSpice] Model (electrical/mathematical characteristics) Pin 3 Pin 1 Pin 2 Pin 4
Pin 1
Pin 2
[Capture]
OrCAD
Symbol (schematic appearance) Pin 1 Pin 2 Pin 3 Pin 4
Pin 3
Pin 4 [Layout] Footprint (physical interface)
Figure 1-1 The pieces of a "part."
tools operate when manufacturing the printed circuit board (PCB) (GerbTool, for example). By combining all three applications into one package you have a powerful set of tools to efficiently design, test, and build electronic circuits. The key to successful project design and production is in understanding the PCB itself and knowing how to use the tools that build the PCB.
Printed Circuit Board Fabrication
We now look at how PCBs are manufactured so that we will have a better understanding of what we are trying to accomplish with Layout and why. A PCB consists of two basic parts: a substrate (the board) and printed wires (the copper traces). The substrate provides a structure that physically holds the circuit components and printed wires in place and provides electrical insulation between conductive parts. A common type of substrate is FR4, which is a fiberglassepoxy laminate. It is similar to older types of fiberglass boards but is flame resistant. Substrates are also made from Teflon, ceramics, and special polymers.
PCB cores and layer stack-up
During manufacturing the PCB starts out as a copper clad substrate as shown in Fig. 1-2. A rigid substrate is a C-stage laminate (fully cured epoxy). The copper cladding may be copper that is plated onto the substrate or copper foil that is glued to the substrate. The thickness of the copper is measured in ounces (oz) of copper per square foot, where 1.0oz/ft2 of copper is approximately 1.21.4 mils (0.00120.0014 in.) thick. It is common to drop "/ft2" and refer to 1 the thickness only in oz. For example, you can order 1oz copper on a 8 -in.-thick FR4 substrate. A substrate can have copper on one or both sides. Multilayer boards are made up of one or more single- or double-sided substrates called cores. A core is a copper-plated epoxy laminate. The cores are glued together with one or more sheets of a partially cured epoxy as shown in
2
Introduction to PCB Design and CAD
FR4 Substrate (laminate) Copper cladding
Figure 1-2 A double-sided copper clad FR4 substrate.
Core Prepreg Core
{ { {
C-stage laminate B-stage laminate C-stage laminate Copper cladding
Figure 1-3 Cores and prepreg.
Fig. 1-3. The sheets are also referred to as prepreg or B-stage laminate. Once all of the cores are patterned (described below) and aligned, the entire assembly is fully cured in a heated press. There are three methods of assembling the cores when making a multilayer board. Figure 1-4 shows the first two methods in an example with four routing layers and two plane layers. Figure 1-4(a) shows three (double-sided) cores bonded together by two prepreg layers, while Fig. 1-4(b) shows the same six layers made of two cores, which make up the four inner layers, bonded together by one prepreg layer. The outer layers in 1-4(b) are copper foil sheets bonded to the assembly with prepreg.
(a) Clad Clad Clad Clad Clad Clad Core Prepreg Core Prepreg Core Top Inner1 GND plane PWR plane Inner2 Bottom (b) Foil Clad Clad Clad Clad Foil Prepreg Prepreg Core Prepreg Core Top Inner1 GND plane PWR plane Inner2 Bottom
Figure 1-4 Two stack-up methods for a six-layer board. (a) Multicore, outer clad. (b) Multicore, outer foil. 3
Chapter 1 The routing layers in Fig. 1-4 are shown as patterned copper segments and the plane layers are shown as solid lines. The inner layers are patterned prior to bonding the cores together. The outer layers are patterned later in the process after the cores have been bonded and cured and most of the holes have been drilled. Because the outer layers are etched later and because copper foil is typically less expensive than copper cladding, the stack-up shown in Fig. 1-4(b) is more widely used. The third method uses several fabrication techniques by which highly complex boards can be fabricated, as illustrated in Fig. 1-5. This circuit board may have a typical four-layer core stack-up at its center, but additional layers are built up layer by layer on the top and the bottom using sequential lamination techniques. The techniques can be used to produce blind and buried vias as well as typical plated through-hole vias and nonplated holes. Resistors and capacitors can also be embedded into the substrate. More will be discussed about blind vias in later chapters (8 and 9).
Top solder mask Plated through-hole (through-via) Top build-up (Core) Std core stack-up (Prepreg) (Core) Bottom build-up (Buried) (Blind) Laser micro-via (Buried via)
Plasma micro-via (Blind)
Paste filled micro-via (Blind)
Unplated hole
(Buried)
Bottom solder mask
Figure 1-5 A built-up, multitechnology, PCB stack-up.
PCB fabrication process
The copper traces and pads you see on a PCB are produced by selectively removing the copper cladding and foil. There are two common methods for removing the unwanted copper: wet acid etching and mechanical milling. Acid etching is more common when manufacturing large quantities of boards because many boards can be made simultaneously. One drawback to wet etching is that the chemicals are hazardous and must be replenished occasionally, and the depleted chemicals must be recycled or discarded. Milling is usually used for smaller production runs and prototype boards. During milling, the traces and pads are formed by a rotating bit that grinds the unwanted copper from the substrate. With either method, a digital map is made of the copper patterns. The purpose of CAD software like OrCAD Layout is to generate the digital maps.
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Introduction to PCB Design and CAD
Note Only one layer is considered in the following explanation of the fabrication process.
Photolithography and chemical etching
Selectively removing the copper with etching processes requires etching the unwanted copper while protecting the wanted copper from the etchant. This protection is provided by a polymer coating (called photoresist) that is deposited onto the surface of the copper cladding as shown in Fig. 1-6. The photoresist is patterned into the shape of the desired printed circuit through a process called photolithography. The patterned resist protects selected areas of the copper from the etchant and exposes the copper to be etched.
Resist
Cu
Substrate
Figure 1-6 A copper clad board coated with photoresist.
There are two steps to photolithography, patterning the photoresist--exposing the resist to light (typically ultraviolet (UV) light) and developing it (selective removal in a chemical bath). There are two types of photoresist: positive resist and negative resist. When positive resist is exposed to UV light, the polymer breaks down and can be removed from the copper. Conversely, negative resist that is shielded from UV light is removed. A mask is used to expose the desired part of the photoresist. A mask is a specialized black and white photographic film or glass photoplate on which a picture of the traces and pads is printed with a laser photoplotter. Two types of masks are shown in Fig. 1-7. The masks are examples of a trace connected to a pad. Figure 1-7(a) shows a positive mask used to expose positive photoresist, and Fig. 1-7(b) shows a negative mask used to expose negative photoresist. Masks that will be used repeatedly are sometimes produced on glass photoplates instead of film. The mask is placed on top of the photoresist as shown in Fig. 1-8, and the assembly is exposed to the UV light. The dark areas block UV light and the white (transparent) areas allow the UV light to hit the photoresist, which imprints the circuit image into the photoresist. A separate mask is used for each layer of a circuit board. OrCAD Layout generates the data that the photoplotter uses to make these masks.
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Chapter 1
(a) (b)
Figure 1-7 Photolithography masks. (a) A positive mask. (b) A negative mask.
Figure 1-8 Positive photomask on photoresist-coated board.
Another way of exposing the photoresist is by using a programmable laser to "draw" the pattern directly onto the photoresist. This is a newer technique called laser direct imaging (LDI). A benefit of the LDI process is that it uses the same data as the photoplotters but no masks are required. After the photoresist has been exposed (either with the mask and UV or with the laser) it is washed in a chemical called the developer. In the case of positive resist, the resist breaks down during exposure and is removed by the developer. In the case of negative resist, the UV light cures the resist, and only the unexposed resist is removed by the developer. Common developers are sodium hydroxide (NaOH) for positive resist and sodium carbonate (Na2CO3) for negative resist. Once the resist has been exposed and developed, a circuit image made of the photoresist is left on the copper as shown in Fig. 1-9.
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Introduction to PCB Design and CAD
Figure 1-9 Developed photoresist on copper.
Next, the board is etched in an acid solution such as ferric chloride (FeCl3) or sodium persulfate (Na2S2O8). The etching solution does not significantly affect the photoresist but attacks the bare copper and removes it from the substrate, leaving behind the resist-coated copper as shown in Fig. 1-10.
Figure 1-10 Unwanted copper removed after etching.
Some processes use a plated tin alloy as the etch resist. The tin alloy plating is more resistant to etchants and preprepares the copper surface for solder processes. In this case the photolithography processes are used to selectively plate the circuit pattern onto the copper surfaces prior to etching. When polymer etch resists are used the photoresist is cleaned from the copper with a resist stripper, leaving behind the copper traces. Fig. 1-11 shows the final patterned copper. When
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Figure 1-11 Copper pad and trace after etching and resist stripping.
metal etch resists are used the plating is typically left in place. Holes for the leads, etc., are not etched into the pads because they are drilled after all of the cores have been glued together (later in the process) to ensure proper alignment of the holes between board layers.
Mechanical milling
As mentioned above, milling is an alternative to etching. To mill the board, a computer numerical control (CNC) machine is programmed with the digital map of the board and grinds away the unwanted copper. The unwanted copper can be completely removed (like that in Fig. 1-11), or just enough copper may be removed to isolate the pads and traces from the bulk copper as shown in Fig. 1-12. Removing only enough copper to isolate the traces from the bulk copper reduces milling time but can affect the impedance of the traces.
Figure 1-12 A mechanically milled trace. 8
Introduction to PCB Design and CAD
Layer registration
After the inner layers have been patterned, the cores are aligned (called registration) and glued together. Registration is critical because the pads on each layer need to be properly aligned when the holes are drilled. Registration is accomplished using alignment patterns (called fiducials) and tooling holes in the board, which slide onto guide pins. With the cores in place and properly aligned, a heated press cures the assembly. After the assembly is cured, holes are drilled for through-hole component leads and vias. The drilling process inevitably heats the laminate due to friction between the laminate and the high-speed drill bit. This tends to soften the laminate and smear it across the walls of the drilled copper. After the drilling processes are finished, the assembly is placed into a bath to etchback the laminate slightly and clean the faces of the copper pad walls. This is called laminate etchback or desmear. Once the holes have been drilled and desmeared, a physical path exists between pads on different layers, but as Fig. 1-13(a) shows there is not an electrical connection between them. To make electrical connections between pads on different layers the board is placed into a plating bath that coats the insides of the holes with copper, which electrically connects the pads--hence the term "plated" through-holes. The plating thickness varies but is typically about 1 mil (0.001 in.) thick. The cutaway view of Fig. 1-13(b) shows a plated through-hole on an internal layer of a PCB. The top and bottom copper is actually patterned after the plating process is finished because the plating process would replate the areas where copper had been removed.
(a)
(b)
Figure 1-13 Holes are drilled into the board and then copper plated. (a) A nonplated through-hole. (b) A plated through-hole.
Not all layers have traces. Some layers are planes (see Fig. 1-14). Plane layers are typically used to provide low-impedance (resistance and inductance) connections to power and ground and to provide easy access to power and ground at any location on the board. Plane layers and impedance issues are discussed in Chap. 6. The leads of components are connected to ground or power by soldering them into plated through-holes. Since copper conducts heat well, soldering
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Chapter 1 to a plane layer could require an excessive amount of heat that could damage the components or the plating in the hole (called the barrel). Thermal reliefs are used as shown in Fig. 1-14 to reduce the path for heat conduction but maintain electrical continuity with the plane.
Figure 1-14 A connection to a plane layer through a thermal relief.
Since ground and power planes are often inner layers and signal layers will likely be above and below them, there will be instances in which a via will run through a plane layer but must not touch it. In this case a "clearance" area (shown in Fig. 1-15) is etched into the plane layer around the via to prevent a connection to the plane. The clearance is usually larger than the normal pad size to ensure that the plane stays isolated from the plated hole.
Figure 1-15 A clearance area provides isolation between a plated hole and a plane.
After the through-holes are plated, the top and bottom layers are patterned using the photolithography process as described for the inner layers. After the outer copper has been patterned, the exposed traces and plated through-holes can be tinned (although tinning is sometimes deferred until later). Nonplated holes (such as for mounting holes) may be drilled at this time.
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Introduction to PCB Design and CAD Next, a thin polymer layer is usually applied to the top and bottom of the board. This layer (shown in green in Fig. 1-16) is called the soldermask or solder resist. Holes are opened into the polymer using photolithography to expose the pads and holes where components will be soldered to the board. The soldermask protects the top and bottom copper from oxidation and helps prevent solder bridges from forming between closely spaced pads. Sometimes openings in the soldermask are not made over small or densely placed vias (called tenting a via). Tented vias are protected from having chemicals such as flux from becoming trapped inside the hole. Tenting also prevents solder migration into the hole, which could lead to poor solder joints on small components that are close to and connected to the via.
R2
Figure 1-16 Final layers are the soldermask (green) and silk screen (white).
Finally, markings (called the silk screen) are placed on the board to identify where components are to be placed. The silk screen is shown in white in Fig. 1-16.
Function of OrCAD Layout in the PCB Design Process
Layout is used to design the PCB by generating a digital description of the board layers for photoplotters and CNC machines, which are used to manufacture the boards. There are separate layers for routing copper traces on the top, bottom, and all inner layers; drill hole sizes and locations; soldermasks; silk screens; solder paste; part placement; and board dimensions. These layers are not all portrayed identically in Layout. Some of the layers are shown from a positive perspective, meaning what you see with the software is what is placed onto the board, while other layers are shown from a negative perspective, meaning what you see with the software is what is removed from the board. The layers represented in the positive view are the board outline, routed copper, silk screens, solder paste, and assembly instructions. The layers represented in the negative view are copper plane layers, drill holes, and soldermasks. Figure 1-17 shows routed layers (top and bottom and inner for example) that Layout shows in the positive perspective. The background is black and the traces and pads on each layer
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Chapter 1 are a different color to make it easier to keep track of visually. The drill holes are shown on a dedicated drill layer because, as mentioned above, the drilling process is a distinct step that is performed at a specific time during the manufacturing process.
1 2 3
1 2 3
14 13 12
Figure 1-17 Copper in routed layers (positive view).
Figures 1-18(a) and 1-18(b) show the difference between a physical copper plane layer with a thermal via and the negative representation used by Layout. In this view the black background is actually the copper plane, and the yellow areas indicate were the copper is removed. As with the routed layers, the drill holes are visible on the drill layer.
(a) (b)
Figure 1-18 Copper in a plane layer (negative view without drill info). (a) Copper plane with thermal relief. (b) Negative view in Layout.
Figure 1-19(a) shows the soldermask with the patterned holes that allow access to pads, and Fig. 1-19(b) shows the negative representation used by Layout. Here, as with the negative perspective of the ground plane, the black background is actually the polymer film and the green circles are the holes in the soldermask. Finally, Fig. 1-20 shows examples of drill patterns and silk-screen representations used by Layout (traces not shown). The dark red circles are the locations and sizes of the drill holes (a negative view) and the brighter red symbols are used in conjunction with a drill chart (see Fig. 1-21) to give ID numbers for the different drill tools. The white print is the silk screen discussed above.
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Introduction to PCB Design and CAD
(a) (b)
Figure 1-19 Soldermask layer and negative view. (a) Soldermask. (b) Negative view in Layout.
RC
1 1 2
1
RA
1 14 1 2 2
2
RB J1
R2
Figure 1-20 Circuit layout with drill identifiers and silk screen on a PCB.
1
3
2
U2
13
R1
3 12 1 2 4 11 1
4
5
10
6
9
DRILL CHART SYM DIAM 0.028 0.034 0.037 TOTAL TOL QTY 2 14 8 24 NOTE
Figure 1-21 Drill chart with drill IDs and specifications. 13
Chapter 1
Design Files Created by Layout
Layout format files (.MAX)
When you are designing your board, Layout works with and saves your design in a format that is efficient for your computer. The Layout design file has a .MAX extension. When you are ready to fabricate your board, Layout postprocesses the design and converts it into a format that the photoplotters and CNC machines can use. These files are called Gerber files.
Postprocess (Gerber) files
Postprocessing creates a separate Gerber file for each of the layers discussed above. There can be as many as 30 or so different layer files that Layout generates to describe various manufacturing aspects of your PCB. Some examples of these files, their extensions, and their functions are listed in Table 1-1. These and other files that Layout generates will be discussed in greater detail in the next two chapters.
File name and extension BoardName .AST BoardName .SPT BoardName .SST BoardName .SMT BoardName .TOP` BoardName .IN1 BoardName .IN2 BoardName .Inx BoardName .PWR BoardName .GND BoardName .BOT BoardName .SMB BoardName .SSB BoardName .SPB BoardName .ASB BoardName .DRD Throughhole .tap Function Top side assembly Top side solder paste Top side silk screen Top side soldermask Top side copper (usually routing) Inner layer 1 (routing or plane) Inner layer 2 (routing or plane) Inner layer x (routing or plane) Power layer (a plane layer) Ground layer (a plane layer) Bottom side copper (usually routing) Bottom side soldermask Bottom side silk screen Bottom side solder paste Bottom side assembly Board outline info Drill information
Table 1-1 Gerber (layer) files generated by layout
PCB assembly layers and files
There are several layer files generated by Layout that are not part of the actual fabrication process. These files are used for automated assembly of a finished board and are mentioned only briefly here. The first layer is the solder-paste layer. It is used to make a contact mask for selectively applying solder paste onto the PCB's pads so that components can be reflow soldered to the board. There may be a solder-paste layer for the top side of the board (.SPT) and one for the bottom side (.SPB) as shown in Table 1-1. The second layer file is the
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Introduction to PCB Design and CAD assembly layer, which contains information for automatic component placement machines (pick-and-place machines) as to the part type, its position, and its orientation on the board. As with the soldermask, there may be an assembly layer for the top side of the board (.AST) and one for the bottom side (.ASB). PCB design for the various soldering and assembly processes is discussed in Chap. 5. The purpose of this chapter has been to introduce you to the process by which PCBs are manufactured. The purpose of the next chapter is to show you how to use OrCAD Layout to design your board and generate the files needed to manufacture your PCB.
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