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MADE IN KOREA
2003.1 9017100200
SERVICE
MANUAL

2 4 / 9 6 M U L T I M O D E




EQUALIZER
MEQ-2000
CONTENTS
Electrical Adjustment Procedure 1
Micom Data 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
13, 14
Specifications 15, 16, 17, 18
Electrical Parts List 19, 20, 21
Top and Bottom View of P.C. Board 22, 23, 24, 25, 26
Wiring Diagram 27
Block Diagram 28
Schematic Diagram 29, 30, 31, 32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43, 44, 45, 46,
47, 48, 49, 50, 51, 52, 53, 54
Exploded View of Cabinet & Chassis / Mechanical Parts List 55, 56
Ass'y Drawing 57, 58
ELECTRICAL ADJUSTMENT PROCEDURE

1. ANALOG INPUT GAIN ADJUSTING
1) First, Connect Analog XLR input and Digital XLR output to test equipment (Inter-M use Audio Precision
System II Cascade , It support the AES3 in/out)
2) Put the Analog Input Potentiometer (Left below in Front Panel) to Max.
3) Analog input Level of the each channel is -20dBu,
And Adjust the P3 and P4 to Digital Output Level of the each channel is -20.5dBFS.
When you adjust this potentiometer, Tolerance is +/- 0.1 dBFS.

2. ANALOG OUTPUT GAIN ADJUSTING
1) First, Connect Analog XLR Output and Digital XLR input to test equipment.(Inter-M use Audio Precision
System II Cascade, It support the AES3 in/out)
2) Digital input Level of the each channel is -3dBFS,
And Adjust the P1 and P2 to Analog Output Level of the each channel is 21dBu.

3. ANALOG OUTPUT CMRR ADJUSTING
1) First, Connect the special cable for CMRR adjusting to Analog XLR Output.
The special CMRR adjusting cable is made with 300 ohm resistor that of tolerance is 0.01%.(+/- 0.03ohm)
2) Digital input Level of each channel is -3dBFS,
And, Adjust the P5 and P6 to Analog Output Level is below -35dBu.




1
MICOM DATA

ADSP-21065L DSP MICROCOMPUTER

SUMMARY

­ High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and
Industrial Applications
­ Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle
­ 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-Point Arithmetic
­ 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral
­ I2S Support, for Eight Simultaneous Receive and Transmit Channels

KEY FEATURES

­ 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance
­ User-Configurable 544 Kbits On-Chip SRAM Memory
­ Two External Port, DMA Channels and Eight Serial Port, DMA Channels
­ SDRAM Controller for Glueless Interface to Low Cost External Memory (@66 MHz)
­ 64M Words External Address Range
­ 12 Programmable I/O Pins and Two Timers with Event Capture Options
­ Code-Compatible with ADSP-2106x Family
­ 208-Lead MQFP or 196-Ball Mini-BGA Package
­ 3.3 Volt Operation

Flexible Data Formats and 40-Bit Extended Precision
­ 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats
­ 32-Bit Fixed-Point Data Format, Integer and Fractional, with Dual 80-Bit Accumulators

Parallel Computations
­ Single-Cycle Multiply and ALU Operations in Parallel with Dual Memory Read/Writes and Instruction
Fetch
­ Multiply with Add and Subtract for Accelerated FFT Butterfly Computation
­ 1024-Point Complex FFT Benchmark: 0.274 ms (18,221 Cycles)

544 Kbits Configurable On-Chip SRAM
­ Dual-Ported for Independent Access by Core Processor and DMA
­ Configurable in Combinations of 16-, 32-, 48-Bit Data and Program Words in Block 0 and Block 1

DMA Controller
­ Ten DMA Channels­Two Dedicated to the External Port and Eight Dedicated to the Serial Ports
­ Background DMA Transfers at up to 66 MHz, in Parallel with Full Speed Processor Execution
­ Performs Transfers Between:
Internal RAM and Host
Internal RAM and Serial Ports
Internal RAM and Master or Slave SHARC
Internal RAM and External Memory or I/O Devices
External Memory and External Devices

Host Processor Interface
­ Efficient Interface to 8-, 16-, and 32-Bit Microprocessors
­ Host Can Directly Read/Write ADSP-21065L IOP Registers




2
Multiprocessing
­ Distributed On-Chip Bus Arbitration for Glueless, Parallel Bus Connect Between Two ADSP-21065Ls
Plus Host
­ 132 Mbytes/s Transfer Rate Over Parallel Bus

Serial Ports
­ Independent Transmit and Receive Functions
­ Programmable 3-Bit to 32-Bit Serial Word Width
­ I2S Support Allowing Eight Transmit and Eight Receive Channels
­ Glueless Interface to Industry Standard Codecs
­ TDM Multichannel Mode with µ-Law/A-Law Hardware Companding
­ Multichannel Signaling Protocol

BLOCK DIAGRAM



CORE PROCESSOR DUAL-PORTED SRAM
JTAG 7




BLOCK 0
INSTRUCTION TWO INDEPENDENT
CACHE TEST &




BLOCK 1
DUAL-PORTED BLOCKS EMULATION
32 48 BIT
PROCESSOR PORT I/O PORT
ADDR DATA DATA ADDR
DAG1 DAG2
ADDR DATA ADDR DATA EXTERNAL
8 4 32 8 4 24 PROGRAM
SEQUENCER PORT
SDRAM
IOA IOD INTERFACE
24 PM ADDRESS BUS 17 48
24
ADDR BUS
32 DM ADDRESS BUS MUX

MULTIPROCESSOR
INTERFACE
48 PM DATA BUS
BUS 32
CONNECT DATA BUS
(PX) 40 DM DATA BUS MUX

HOST PORT


DATA DMA 4
REGISTER IOP CONTROLLER
FILE REGISTERS
(MEMORY MAPPED) (2 Rx, 2Tx)
16 40 BIT BARREL SPORT 0
MULTIPLIER SHIFTER ALU CONTROL, (I2S)
STATUS, TIMER
& (2 Rx, 2Tx)
DATA BUFFERS SPORT 1
(I2S)
I/O PROCESSOR




3
PIN DESCRIPTIONS
ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing
requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as
asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR23-0, DATA31-0, FLAG11-0, SW, and
inputs that have internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and
TDI)­these pins can be left floating. These pins have a logic-level hold circuit that prevents the input from
floating internally.
I=Input S=Synchronous P=Power Supply (O/D)=Open Drain
O=Output A=Asynchronous G=Ground (A/D)=Active Drive
T=Three-state (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
Pin Type Function
ADDR23-0 I/O/T External Bus Address. The ADSP-21065L outputs addresses for external
memory and peripherals on these pins. In a multiprocessor system the bus
master outputs addresses for read/writes of the IOP registers of the other
ADSP-21065L. The ADSP-21065L inputs addresses when a host processor
or multiprocessing bus master is reading or writing its IOP registers.
DATA31-0 I/O/T External Bus Data. The ADSP-21065L inputs and outputs data and
instructions on these pins. The external data bus transfers 32-bit single-
precision floating-point data and 32-bit fixed-point data over bits 31-0. 16-bit
short word data is transferred over bits 15-0 of the bus. Pull-up resistors on
unused DATA pins are not necessary.
MS3-0 I/O/T Memory Select Lines. These lines are asserted as chip selects for the
corresponding banks of external memory. Internal ADDR25-24 are decoded
into MS3-0. The MS3-0 lines are decoded memory address lines that change
at the same time as the other address lines. When no external memory
access is occurring the MS3-0 lines are inactive; they are active, however,
when a conditional memory access instruction is executed, whether or not
the condition is true. Additionally, an MS3-0 line which is mapped to SDRAM
may be asserted even when no SDRAM access is active. In a
multiprocessor system, the MS3-0 lines are output by the bus master.
RD I/O/T Memory Read Strobe. This pin is asserted when the ADSP-21065L reads
from external memory devices or from the IOP register of another ADSP-
21065L. External devices (including another ADSP-21065L) must assert RD
to read from the ADSP-21065L's IOP registers. In a multiprocessor system,
RD is output by the bus master and is input by another ADSP-21065L.
WR I/O/T Memory Write Strobe. This pin is asserted when the ADSP-21065L writes
to external memory devices or to the IOP register of another ADSP-21065L.
External devices must assert WR to write to the ADSP-21065L's IOP
registers. In a multiprocessor system, WR is output by the bus master and is
input by the other ADSP-21065L.
SW I/O/T Synchronous Write Select. This signal interfaces the ADSP-21065L to
synchronous memory devices (including another ADSP-21065L). The
ADSP-21065L asserts SW to provide an early indication of an impending
write cycle, which can be aborted if WR is not later asserted (e.g., in a
conditional write instruction). In a multiprocessor system, SW is output by the
bus master and is input by the other ADSP-21065L to determine if the
multiprocessor access is a read or write. SW is asserted at the same time as
the address output.
ACK I/O/S Memory Acknowledge. External devices can deassert ACK to add wait
states to an external memory access. ACK is used by I/O devices, memory
controllers, or other peripherals to hold off completion of an external memory


4
Pin Type Function
access. The ADSP-21065L deasserts ACK as an output to add wait states to
a synchronous access of its IOP registers. In a multiprocessor system, a
slave ADSP-21065L deasserts the bus master's ACK input to add wait
state(s) to an access of its IOP registers. The bus master has a keeper latch
on its ACK pin that maintains the input at the level to which it was last driven.
SBTS I/S Suspend Bus Three-State. External devices can assert SBTS to place the
external bus address, data, selects, and strobes­but not SDRAM control
pins­in a high impedance state for the following cycle. If the ADSP-21065L
attempts to access external memory while SBTS is asserted, the processor
will halt and the memory access will not finish until SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21065L
deadlock.
IRQ2-0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG11-0 I/O/A Flag Pins. Each is configured via control bits as either an input or an output.
As an input, it can be tested as a condition. As an output, it can be used to
signal external peripherals.
HBR I/A Host Bus Request. Must be asserted by a host processor to request control
of the ADSP-21065L's external bus. When HBR is asserted in a
multiprocessing system, the ADSP-21065L that is bus master will relinquish
the bus and assert HBG. To relinquish the bus, the ADSP-21065L places the
address, data, select, and strobe lines in a high impedance state. It does,
however, continue to drive the SDRAM control pins. HBR has priority over all
ADSP-21065L bus requests (BR2-1) in a multiprocessor system.
HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the
host processor may take control of the external bus. HBG is asserted by the
ADSP-21065L until HBR is released. In a multiprocessor system, HBG is
output by the ADSP-21065L bus master.
CS I/A Chip Select. Asserted by host processor to select the ADSP-21065L.
REDY(O/D) O Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait
states to an asynchronous access of its internal memory or IOP registers by
a host. Open drain output (O/D) by default; can be programmed in ADREDY
bit of SYSCON register to be active drive (A/D). REDY will only be output if
the CS and HBR inputs are asserted.
DMAR1 I/A DMA Request 1 (DMA Channel 9).
DMAR2 I/A DMA Request 2 (DMA Channel 8).
DMAG1 O/T DMA Grant 1 (DMA Channel 9).
DMAG2 O/T DMA Grant 2 (DMA Channel 8).
BR2-1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065L's
to arbitrate for bus mastership. An ADSP-21065L drives its own BRx line
(corresponding to the value of its ID2-0 inputs) only and monitors all others. In
a uniprocessor system, tie both BRx pins to VDD.
ID1-0 I Multiprocessing ID. Determines which multiprocessor bus request
(BR1­BR2) is used by ADSP-21065L. ID=01 corresponds to BR1, ID=10
corresponds to BR2. ID=00 in single-processor systems. These lines are a
system configuration selection which should be hard-wired or changed only
at reset.
CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an
ADSP-21065L bus slave to interrupt background DMA transfers and gain


5
Pin Type Function
access to the external bus. CPA is an open drain output that is connected to
both ADSP-21065Ls in the system. The CPA pin has an internal 5k pull-up
resistor. If core access priority is not required in a system, leave the CPA pin
unconnected.
DTxX O Data Transmit (Serial Ports 0, 1; Channels A, B). Each DTxX pin has a
50k internal pull-up resistor.
DRxX I Data Receive (Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50k
internal pull-up resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50k internal pull-
up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50k internal pull-
up resistor.
TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).
BSEL I EPROM Boot Select. When BSEL is high, the ADSP-21065L is configured
for booting from an 8-bit EPROM. When BSEL is low, the BSEL and BMS
inputs determine booting mode. See BMS for details. This signal is a system
configuration selection which should be hard-wired.
BMS I/O/T* Boot Memory Select. Output: used as chip select for boot EPROM devices
(when BSEL=1). In a multiprocessor system, BMS is output by the bus
master. Input: When low, indicates that no booting will occur and that the
ADSP-21065L will begin executing instructions from external memory. See
following table. This input is a system configuration selection which should
be hard-wired.
*Three-statable only in EPROM boot mode (when BMS is an output).
BSEL BMS Booting Mode
1 Output EPROM (connect BMS to EPROM chip select).
0 1 (Input) Host processor (HBW (SYSCON) bit selects host bus width).
0 0 (Input) No booting. Processor executes from external memory.
CLKIN I Clock In. Used in conjunction with XTAL, configures the ADSP-21065L to
use either its internal clock generator or an external clock source. The
external crystal should be rated at 1x frequency.

Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. The ADSP-21065L's internal clock generator
multiplies the 1x clock to generate 2x clock for its core and SDRAM. It drives
2x clock out on the SDCLKx pins for the SDRAM interface to use. See also
SDCLKx.
Connecting the 1x external clock to CLKIN while leaving XTAL unconnected
configures the ADSP-21065L to use the external clock source. The
instruction cycle rate is equal to 2x CLKIN. CLKIN may not be halted,
changed, or operated below the specified frequency.
RESET I/A Processor Reset. Resets the ADSP-21065L to a known state and begins
execution at the program memory location specified by the hardware reset
vector address. This input must be asserted at power-up.
TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary
scan.




6
Pin Type Function
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has
a 20k internal pull-up resistor.
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDI has a 20k internal pull-up resistor.
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-
21065L. TRST has a 20k internal pull-up resistor.
EMU (O/D) O Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target
board connector only.
BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the
ADSP-21065L is current bus master of the shared external bus. The ADSP-
21065L drives BMSTR high only while it is the bus master. In a single-
processor system (ID=00), the processor drives this pin high.
CAS I/O/T SDRAM Column Access Strobe. Provides the column address. In
conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,
defines the operation for the SDRAM to perform.
RAS I/O/T SDRAM Row Access Strobe. Provides the row address. In conjunction with
CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation
for the SDRAM to perform.
SDWE I/O/T SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx and
sometimes SDA10, defines the operation for the SDRAM to perform.
DQM O/T SDRAM Data Mask. In write mode, DQM has a latency of zero and is used
to block write operations.
SDCLK1-0 I/O/S/T SDRAM 2x Clock Output. In systems with multiple SDRAM devices
connected in parallel, supports the corresponding increased clock load
requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or
both SDCLKx pins can be three-stated.
SDCKE I/O/T SDRAM Clock Enable. Enables and disables the CLK signal. For details,
see the data sheet supplied with your SDRAM device.
SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with
a host access.
XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the
ADSP-21065L's internal clock generator or to disable it to use an external
clock source. See CLKIN.
PWM_EVENT1-0 I/O/A PWM Output/Event Capture. In PWMOUT mode, is an output pin and
functions as a timer counter. In WIDTH_CNT mode, is an input pin and
functions as a pulse counter/event capture.
VDD P Power Supply; nominally +3.3V dc. (33 pins)
GND G Power Supply Return. (37 pins)
NC Do Not Connect. Reserved pins that must be left open and unconnected. (7)




7
CLOCK SIGNALS

The ADSP-21065L can use an external clock or a crystal. See CLKIN pin description. You can configure the
ADSP-21065L to use its internal clock generator by connecting the necessary components to CLKIN and
XTAL. You can use either a crystal operating in the fundamental mode or a crystal operating at an overtone.
Figure shows the component connections used for a crystal operating in fundamental mode, and Figure 2
shows the component connections used for a crystal operating at an overtone.

CLKIN XTAL CLKIN XTAL


RS

X1 X1
C3

C1 C2 C1 C2
L1




SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
SUGGESTED COMPONENTS FOR 30 MHz OPERATION: ECLIPTEK EC2SM-T-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC2SM-33-30.000M (SURFACE MOUNT PACKAGE) ECLIPTEK ECT-30.000M (THRU-HOLE PACKAGE)
ECLIPTEK EC-33-30.000M (THRU-HOLE PACKAGE) C1=18pF
C1=33pF C2=27pF
C2=27pF C3=75pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR L1=3300nH
X1. Rs=SEE NOTE.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. NOTE: C1, C2, C3, Rs AND L1 ARE SPECIFIC TO CRYSTAL SPECIFIED
FOR X1.
CONTACT MANUFACTURER FOR DETAILS.
Figure 1. 30 MHz Operation (Fundamental Mode Crystal) Figure 2. 30 MHz Operation (3rd Overtone Crystal)



TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to
monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-
2106x's CLKIN, TMS, TCK, TRST, TDI, TDO, EMU and GND signals be made accessible on the target
system via a 14-pin connector (a 2 row x 7 pin strip header) such as that shown in Figure 3. The EZ-ICE
probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your
target board design if you, intend to use the ADSP-2106x EZ-ICE.
The total trace length between the EZ-ICE
connector and the furthest device sharing the EZ-
ICE JTAG pins should be limited to 15 inches GND
1 2

EMU

maximum for guaranteed operation. This restriction
3 4
on length must include EZ-ICE JTAG signals, which KEY (NO PIN) CLKIN (OPTIONAL)

are routed to one or more 2106x devices or to a 5 6


combination of 2106xs and other JTAG devices on BTMS TMS


the chain. 7 8

BTCK TCK

The 14-pin, 2-row pin strip header is keyed at the 9 10

Pin 3 location­you must remove Pin 3 from the BTRST 9 TRST


header. The pins must be 0.025 inch square and at 11 12


least 0.20 inch in length. Pin spacing should be BTDI TDI


0.1 0.1 inches. Pin strip headers are available from 13 14
GND TDO
vendors such as 3M, McKenzie and Samtec.
TOP VIEW




Figure 3. Target Board Connector for ADSP-2106x
EZ-ICE (JTAG Header)




8
208-LEAD MQFP PIN CONFIGURATION

Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
No. Name No. Name No. Name No. Name No. Name
1 VDD 43 CAS 85 VDD 127 DATA28 169 ADDR17
2 RFS0 44 SDWE 86 DATA3 128 DATA29 170 ADDR16
3 GND 45 VDD 87 DATA4 129 GND 171 ADDR15
4 RCLK0 46 DQM 88 DATA5 130 VDD 172 VDD
5 DR0A 47 SDCKE 89 GND 131 VDD 173 ADDR14
6 DR0B 48 SDA10 90 DATA6 132 DATA30 174 ADDR13
7 TFS0 49 GND 91 DATA7 133 DATA31 175 ADDR12
8 TCLK0 50 DMAG1 92 DATA8 134 FLAG7 176 VDD
9 VDD 51 DMAG2 93 VDD 135 GND 177 GND
10 GND 52 HBG 94 GND 136 FLAG6 178 ADDR11
11 DT0A 53 BMSTR 95 VDD 137 FLAG5 179 ADDR10
12 DT0B 54 VDD 96 DATA9 138 FLAG4 180 ADDR9
13 RFS1 55 CS 97 DATA10 139 GND 181 GND
14 GND 56 SBTS 98 DATA11 140 VDD 182 VDD
15 RCLK1 57 GND 99 GND 141 VDD 183 ADDR8
16 DR1A 58 WR 100 DATA12 142 NC 184 ADDR7
17 DR1B 59 RD 101 DATA13 143 ID1 185 ADDR6
18 TFS1 60 GND 102 NC 144 ID0 186 GND
19 TCLK1 61 VDD 103 NC 145 EMU 187 GND
20 VDD 62 GND 104 DATA14 146 TDO 188 ADDR5
21 VDD 63 REDY 105 VDD 147 TRST 189 ADDR4
22 DT1A 64 SW 106 GND 148 TDI 190 ADDR3
23 DT1B 65 CPA 107 DATA15 149 TMS 191 VDD
24 PWM_EVENT1 66 VDD 108 DATA16 150 GND 192 VDD
25 GND 67 VDD 109 DATA17 151 TCK 193 ADDR2
26 PWM_EVENT0 68 GND 110 VDD 152 BSEL 194 ADDR1
27 BR1 69 ACK 111 DATA18 153 BMS 195 ADDR0
28 BR2 70 MS0 112 DATA19 154 GND 196 GND
29 VDD 71 MS1 113 DATA20 155 GND 197 FLAG0
30 CLKIN 72 GND 114 GND 156 VDD 198 FLAG1
31 XTAL 73 GND 115 NC 157 RESET 199 FLAG2
32 VDD 74 MS2 116 DATA21 158 VDD 200 VDD
33 GND 75 MS3 117 DATA22 159 GND 201 FLAG3
34 SDCLK1 76 FLAG11 118 DATA23 160 ADDR23 202 NC
35 GND 77 VDD 119 GND 161 ADDR22 203 NC
36 VDD 78 FLAG10 120 VDD 162 ADDR21 204 GND
37 SDCLK0 79 FLAG9 121 DATA24 163 VDD 205 IRQ0
38 DMAR1 80 FLAG8 122 DATA25 164 ADDR20 206 IRQ1
39 DMAR2 81 GND 123 DATA26 165 ADDR19 207 IRQ2
40 HBR 82 DATA0 124 VDD 166 ADDR18 208 NC
41 GND 83 DATA1 125 GND 167 GND
42 RAS 84 DATA2 126 DATA27 168 GND


9
208-LEAD MQFP PIN




208-LEAD MQFP PIN




ADDR10
ADDR11


ADDR12
ADDR13
ADDR14

ADDR15
ADDR16
ADDR17


ADDR18
ADDR19
ADDR20

ADDR21
ADDR22
ADDR23
ADDR0
ADDR1
ADDR2


ADDR3
ADDR4
ADDR5


ADDR6
ADDR7
ADDR8


ADDR9
FLAG3

FLAG2
FLAG1
FLAG0
2
1
0




VDD
GND




VDD




GND




VDD
VDD




GND
GND




VDD
GND




GND
VDD




VDD




GND
GND




VDD




GND
NC




NC
NC
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190


188
187
186
185
184
183
182
181



178
177
176
175
174
173
172
171
170
189




180
179




169
168
167
166
165
164
163
162
161
160
159
158
157
VDD 1 156 VDD
RSF0 2 PIN 1 155 GND
GND 3 IDENTIFIER 154 GND
RCLK0 4 153
DR0A 5 152 BSEL
DR0B 6 151 TCK
TFS0 7 150 GND
TCLK0 8 149 TMS
VDD 9 148 TDI
GND 10 147
DT0A 11 146 TDO
DT0B 12 145
RFS1 13 144 ID0
GND 14 143 ID1
RCLK1 15 142 NC
DR1A 16 141 VDD
DR1B 17 140 VDD
TFS1 18 139 GND
TCLK1 19 138 FLAG4
VDD 20 137 FLAG5
VDD 21 136 FLAG6
DT1A 22 135 GND
DT1B 23 134 FLAG7
PWM EVENT1 24 133 DATA31
GND 25 132 DATA30
PWM EVENT0 26
OO
ADSP-21065L 131 VDD
27 TOP VIEW 130 VDD
28 (Not to Scale) 129 GND
VDD 29 128 DATA29
CLKIN 30 127 DATA28
XTAL 31 126 DATA27
VDD 32 125 GND
GND 33 124 VDD
SDCLK1 34 123 DATA26
GND 35 122 DATA25
VDD 36 121 DATA24
SDCLK0 37 120 VDD
1 38 119 GND
2 39 118 DATA23
40 117 DATA22
GND 41 116 DATA21
42 115 NC
43 114 GND
44 113 DATA20
VDD 45 112 DATA19
DQM 46 111 DATA18
SDCKE 47 110 VDD
SDA10 48 109 DATA17
GND 49 108 DATA16
1 50 107 DATA15
2 51 106 GND
52 105 VDD
100
101
102
103
104
73
74
75
76
77
78
79
80
81


83
84
85