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ANALOG 3v3 ir_out R146 12v 5v 3v3 75R 12v C256 C1 100nF C257 C2 100nF C3 100nF 12v 5v 3v3 gnd 5v 3v3 D12 LTL-907PK 12v 5v gnd gnda sda scl sda scl 12v 5v gnd gnda
D
ir_out txd rxd txd rxd
470uF 16V
D
470uF 16V
ANA gnd gnd gnd gnd gnd CPU /pld_cs /cpu_ready cpu_addr[0..18] cpu_data[0..7] pld_data nconfig dclk /vid_reset sda_1 sda scl MUX/GAMMA/OSD/HOST
/sdi_oe sdi_error pc_hsync pc_vsync pc_h_pol pc_v_pol /scs sclk s_mosi s_miso 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CON40 gnd 5v a_miso/ir a_mosi a_sclk/off a_reset /scs sclk s_mosi s_miso a_miso/ir a_mosi a_sclk/off a_reset
/pld_cs /cpu_ready cpu_addr[0..18] cpu_data[0..7] pld_data nconfig dclk /vid_reset
cpu_addr[0..18] cpu_data[0..7]
/pld_cs /cpu_ready cpu_addr[0..18] cpu_data[0..7] pld_data nconfig dclk
bolt_power /debug_plug dis_blue7 dis_red7
22RX4 1 3 5 7
R117 2 4 6 8
J1 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 CON_PDP gnd
dis_blue6 dis_red6 22RX4 1 3 5 7 R118 2 4 6 8
J4
bolt_power /debug_plug
sda_1 sda scl
dis_blue5 dis_red5
3v3
scl sda sda_1 txd rxd com_l com_16/9
pdp_hqen scl sda sda_1 txd rxd com_l com_16/9 5v gnd power_good
pdp_hqen power_good
gen1_sclk gen1_sdata gen2_sclk gen2_sdata /cs_frc2 /cs_dice2 /cs_frc1 /cs_dice1 /scs sclk s_mosi s_miso
gen1_sclk gen1_sdata gen2_sclk gen2_sdata /cs_frc2 /cs_dice2 /cs_frc1 /cs_dice1 /scs sclk s_mosi s_miso
dis_blue4 dis_red4 dis_clk dis_hs dis_vs dis_en dis_red[0..7] dis_green[0..7] dis_blue[0..7] 22RX4 1 3 5 7 R119 2 4 6 8
12v
d_miso d_mosi d_sclk d_reset
d_miso d_mosi d_sclk d_reset
dis_clk dis_hs dis_vs dis_en dis_red[0..7] dis_green[0..7] dis_blue[0..7]
dis_blue3 dis_red3
dis_blue2 dis_red2 22RX4 1 3 5 7 R120 2 4 6 8
dis_blue1 dis_red1
vid1_uv0 vid1_uv1 vid1_uv2 vid1_uv3 vid1_uv4 vid1_uv5 vid1_uv6 vid1_uv7 vid1_y0 vid1_y1 vid1_y2 vid1_y3 vid1_y4 vid1_y5 vid1_y6 vid1_y7 vid1_clk vid1_hs vid1_vs vid1_href vid1_odd
5v gnd
dis_blue0 CPU dice1_dv dice1_hblank dice1_vblank dice1_cref dice1_clk dice1_dv dice1_hblank dice1_vblank dice1_cref dice1_clk dis_red0 22RX4 1 3 5 7 R121 2 4 6 8
dis_vs dis_green7
dis_hs dis_green6 22RX4 1 3 5 7 R122 2 4 6 8
DICE 1 vid1_clk vid1_hs vid1_vs vid1_href vid1_odd vid1_y[0..7] vid1_uv[0..7] dice1_ref_clk dice1_clk dice1_hs dice1_vs dice1_dv dice1_hblank dice1_vblank dice1_red[0..7] dice1_green[0..7] dice1_blue[0..7] /cs_dice1 sclk s_mosi s_miso /vid_reset DICE1 dice1_ref_clk dice1_clk dice1_hs dice1_vs dice1_dv dice1_hblank dice1_vblank dice1_red[0..7] dice1_green[0..7] dice1_blue[0..7] /cs_dice1 sclk s_mosi s_miso /vid_reset 5v 3v3 gnd
FRAME RATE CONVERTER 1 dis_green5 dice1_clk dice1_hs dice1_vs dice1_cref frc1_ref_clk frc1_clk frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7] frc1_ref_clk frc1_clk frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]
dis_en
C
C
vid1_clk vid1_hs vid1_vs vid1_href vid1_odd vid1_y[0..7] vid1_uv[0..7]
frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]
frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]
dis_clk dis_green4
dice1_red[0..7] dice1_green[0..7] dice1_blue[0..7]
/frc1_lock /frc1_lreq frc1_dreq /frc1_sync /cs_frc1 sclk s_mosi s_miso
/frc1_lock /frc1_lreq frc1_dreq /frc1_sync /cs_frc1 sclk s_mosi s_miso /vid_reset fs1_ref_clk
/frc1_lock /frc1_lreq frc1_dreq /frc1_sync
/frc1_lock /frc1_lreq frc1_dreq /frc1_sync
dis_green3
power_good dis_green2 22RX4 1 3 5 7 R123 2 4 6 8
J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CON40 gnd a_miso/ir a_mosi a_sclk/off a_reset 3v3 gnd 3v3 gnd
dis_green1
scl sda sda_1
5v 3v3 gnd FRC1
/vid_reset fs1_ref_clk
dis_green0 pdp_cnt pdp_hqen
ir_out com_l com_16/9
5v
vid2_uv0 vid2_uv1 vid2_uv2 vid2_uv3 vid2_uv4 vid2_uv5 vid2_uv6 vid2_uv7 vid2_y0 vid2_y1 vid2_y2 vid2_y3 vid2_y4 vid2_y5 vid2_y6 vid2_y7 vid2_clk vid2_hs vid2_vs vid2_href vid2_odd
R1 3K3 dice2_dv dice2_hblank dice2_vblank dice2/pc_cref dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2_dv dice2_hblank dice2_vblank dice2/pc_cref dice2/pc_clk dice2/pc_hs dice2/pc_vs gnd
R2 6K8
DICE 2 vid2_clk vid2_hs vid2_vs vid2_href vid2_odd vid2_y[0..7] vid2_uv[0..7] dice2_ref_clk dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2_dv dice2_hblank dice2_vblank dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /dice2_oe /cs_dice2 sclk s_mosi s_miso /vid_reset DICE2 dice2_ref_clk dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2_dv dice2_hblank dice2_vblank dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /dice2_oe /cs_dice2 sclk s_mosi s_miso /vid_reset 5v 3v3 gnd
FRAME RATE CONVERTER 2
vid2_clk vid2_hs vid2_vs vid2_href vid2_odd vid2_y[0..7] vid2_uv[0..7]
B
dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2/pc_cref
frc2_ref_clk frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]
frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]
frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]
frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]
B
dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7]
/frc2_lock /frc2_lreq frc2_dreq /frc2_sync /cs_frc2 sclk s_mosi s_miso /vid_reset fs2_ref_clk
/frc2_lock /frc2_lreq frc2_dreq /frc2_sync /cs_frc2 sclk s_mosi s_miso /vid_reset fs2_ref_clk
/frc2_lock /frc2_lreq frc2_dreq /frc2_sync
/frc2_lock /frc2_lreq frc2_dreq /frc2_sync /cs_dis dis_sclk 3v3 5v J10 1 2 3 4 5 6 7 8 9 10 11 12 CON_DIS 5v 3v3 gnd 5v 3v3 gnd gnd
SDI
3v3 gnd vid2_clk vid2_y[0..7]
pc_clamp pc_hsync
3v3 gnd
/cs_dis dis_sclk
5v 3v3 gnd
5v 3v3 gnd
/sdi_oe sdi_error
5v 3v3 gnd
FRC2 SDI PC ADC pc_hsync_in pc_vsync_in pc_r_in pc_g_in pc_b_in dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /pc_oe pc_clamp /dice2_oe /pc_oe /clock_bypass /dice2_oe /pc_oe /clock_bypass
d_miso d_mosi d_sclk d_reset /cs_dis dis_sclk s_mosi sda scl
pc_hsync_in pc_vsync_in pc_r_in pc_g_in pc_b_in
sda scl 16 gnda gnda 6 1 7 2 8 3 9 4 10 5 J2 12v 5v 3v3 gnd gnda
sda scl 12v 5v 3v3 gnd gnda
dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /pc_oe pc_clamp
PLD
pc_r_in pc_g_in pc_b_in
11 12
pc_hsync pc_vsync pc_h_pol pc_v_pol dice1_ref_clk dice2_ref_clk gen1_sclk gen1_sdata
CLOCK frc2_clk frc1_clk frc1_ref_clk /clock_bypass fs1_ref_clk fs2_ref_clk frc2_ref_clk gen2_sclk gen2_sdata
A
PC_ADC 13 14 15 pc_hsync_in pc_vsync_in
dice1_ref_clk dice2_ref_clk gen1_sclk gen1_sdata
frc2_clk frc1_clk frc1_ref_clk /clock_bypass fs1_ref_clk fs2_ref_clk frc2_ref_clk
17
DB15-PC-F
A
gnd
5v 3v3 gnd
5v 3v3 gnd
gen2_sclk gen2_sdata
gnda CLOCK
BL1 110200C gnd gnd gnd gnd gnd A B C D E J I H G F gnd gnd gnd gnd gnd 208080B SIGLE AMITEK
Title PDE top level Size D Date: Document Number 208080B.SCH Thursday, December 30, 1999
1
Rev B Sheet 11 of 1
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