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SiS302LV/CH7019
+DVDD 13 14.318MHZ_TV R573 1 10K/NA 2 0603 R601 1 10K/NA 2 0603 R598 1 10K/NA 2 0603 R597 1 10K/NA 2 0603 R570 1 10K/NA 2 0603
D

CLOSE TO CH7017 R607 14.318MHZ_TV R572 1 357K/NA2 0603 R600 1 357K/NA2 0603 1 R599 1 357K/NA2 0603 R608 1 357K/NA2 0603 R571 1 357K/NA2 0603 AS VB_GPIO2 VB_GPIO3 VB_GPIO4 VB_GPIO5 PCIRST# R575 2 0/NA 2 0 0603 R566 1 2 2 1 0 0603 1 2 X501 2 1 MOD_XOUT

Spread Range Selection
FS0 SR0 Spreading Range 1 0 +/- 1.50% 1 1 +/- 2.50% 0 0 +/- 1.25% 0 1 +/- 2.00%
1

Input Frequency Modulation Rate
10 MHz to 20 MHz 10 MHz to 20 MHz 20 MHz to 35 MHz 20 MHz to 35 MHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz
D

14.318MHZ/NA C575 22P/NA 0603 5%

C585 22P/NA 0603 5%

R596 1 0/NA 1 2 3 4 R574 1M/NA 0603

2 0603

MOD_XOUT +DVDD

2

U505 XIN XOUT FS0 VSS P2010/NA SO8 +DAC_VDD 2 0 0603 R47 1 1 0 R50 75/NA 0603 2 2 0603 1 2 3 4 75*4 1206 RP3 8 7 6 5 VDD SR0 MODOUT SSON 8 7 6 5

FS0 and SR0 HAVE INTERNAL PULL_UP 100K Ohm

1

7,10,15,18,19,22,23 PCIRST#

1

R605 1M/NA 0603 2

R561 1 6 6 +3VS 1 VBCLK VBDE VBCLK VBDE

CLOSE TO CH7017 6 VBCTL1 R542 1 2 0 0603

L521 2 120Z/100M 2012 1 1 C576 0.1U 0603 50V C606 0.1U 0603 50V +TVPLL_VCC L518 1 2 120Z/100M 2012 1 2 JL13 +VDDV 1 1

TV_LUMA +TVPLL_VDD 1 1 1 1 C568 10U 1206 25V C573 0.1U 0603 2 2 C588 10U 1206 25V C579 0.1U 0603 TVPLL_GND 1 1 R612 75/NA 0603 2 R616 1 0/NA 1 2 0805 2 TP5 TV_CRMA TV_COMP

TV_LUMA 11,12 TV_CRMA 11,12 TV_COMP 11,12 U507 5 4 NC0 NC1 GND0 VIN VOUT 1 2 3 +5VS

+3VS

2

2

L13 1 2 120Z/100M 2012

2

JP_NET20

TVPLL_GND +VREF1 2 C37 0.1U/NA 0603 R30 2 10K/NA 0603 1 2 0 0603 10K CH7019 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

MOD_XOUT

C41 10U 1206 25V

C39 0.1U 0603 50V

C613 0.1U 0603 50V +DAC_VDD

2

+3VS +DAC_VDD 1 1 2 L17 1 1 C70 10U 1206 25V 2 120Z/100M 2012 JL14 1 2 JP_NET20 1 1 1 1 R81 L22 2 120Z/100M 2012 JL15 2 JP_NET20 +3VS AME8800AEEV/NA SOT25

1 C618 2.2U/NA 0805C

2

2

1

L11 1
C

R31 2 1

DVDD1 DE1 FLD/STL1 VREF1 VDDV P-OUT RESET* GPIO[5] GPIO[4] TVPLL_VDD TVPLL_VCC XO XI / FIN TVPLL_GND BCO/VSYNC C/HSYNC DAC_GND0 DACA[3] DACB[3] DACA[2[ DACB[2] DACA[1] DACB[1] DACA[0] DACB[0] DAC_GND1

120Z/100M/NA 2012 6 6 VBVSYNC VBHSYNC

140 CH7019 U7 SIS302LV R614 150 1% PQFP128A_0.5MM 1 2 0603D

C66 0.1U 0603 50V

C65 0.1U 0603 50V

2

2

2

C

VBVSYNC VBHSYNC R16 R15 1 FC_VBD[0..11] 1 2 0/NA 0603 FC_VBD0 FC_VBD1 FC_VBD2 FC_VBD3 FC_VBD4 FC_VBD5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102

DAC_GND R801 2 6.04K 2.4K CH7019 C87 2 0603 2

2

2

6 VBCTL0 6 FC_VBD[0..11]

2 0 0603

+DVDD 6 6 VBGCLK# VBGCLK

R540 1 VBGCLK# VBGCLK

2 0 0603

+DVDD 1 1 1 C554 10U/NA 1206 25V C557 0.1U/NA 0603 2 2

R552 1

2 0/NA 0603

1

1

CLOSE TO CH7017 DGND +DVDD 6 6 VAGCLK# VAGCLK R533 1 VAGCLK# VAGCLK 2 0 0603

FC_VAD0 FC_VAD1 FC_VAD2 FC_VAD3 FC_VAD4 FC_VAD5

1

C556 0.1U/NA 0603

FC_VBD6 FC_VBD7 FC_VBD8 FC_VBD9 FC_VBD10 FC_VBD11

FC_VAD6 FC_VAD7 FC_VAD8 FC_VAD9 FC_VAD10 FC_VAD11 FC_VAD[0..11]

B

6 FC_VAD[0..11] 6 VAHSYNC 6 VAVSYNC +3VS L9 1

V1 H1 DGND3 D1[0] D1[1] D1[2] D1[3] D1[4] D1[5] XCLK1* DGND2 XCLK1 D1[6] D1[7] D1[8] D1[9] D1[10] D1[11] DVDD3 DVDD2 D2[0] D2[1] D2[2] D2[3] D2[4] D2[5] XCLK2* DGND1 XCLK2 D2[6] D2[7] D2[8] D2[9] D2[10] D2[11] DGND0 H2 V2

SiS301LV/ Chrontel CH7019

ISET DAC_VDD VSWING LGND5 LDC0* LDC0 LVDD5 LDC1* LDC1 LGND4 LDC2* LDC2 LVDD4 LL1C* LL1C LGND3 LDC3* LDC3 LVDD3 LVDD2 LDC4* LDC4 LGND2 LDC5* LDC5 LVDD1 LDC6* LDC6 LGND1 LDC7* LDC7 LVDD0 LL2C* LL2C LGND0 LPLL_GND LPLLCAP LPLL_VDD

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

1 2K

2

1

0603 1U

C64 0.1U 0603 50V

C63 0.1U 0603 50V

C82 10U 1206 25V

1

TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKTXCLK+ R74

TXOUT0- 11,12 TXOUT0+ 11,12 +LVDD3 TXOUT1- 11,12 TXOUT1+ 11,12 TXOUT2- 11,12 TXOUT2+ 11,12 TXCLKTXCLK+ 2 0 0603 TX2OUT0- 11,12 TX2OUT0+ 11,12 2 TX2OUT1- 11,12 TX2OUT1+ 11,12 TX2OUT2- 11,12 TX2OUT2+ 11,12 11,12 11,12 LGND

R69 +LVDD2 C55 0.1U 0603 50V

1

2 0/NA 0603 1 C56 0.1U 0603 50V C81 10U 1206 25V

+LVDD0/1 L20 2 120Z/100M 2012 JL16 1 2 JP_NET20 L19 1 2 120Z/100M 2012 JL17 2 JP_NET20
B

+3VS

1

+LPLL_VDD

TX2OUT0TX2OUT0+ TX2OUT1TX2OUT1+ TX2OUT2TX2OUT2+

2

2

LGND1 +LVDD0/1 1 1 1

2

+3VS

TX2CLKTX2CLK+

2

2

2

TX2CLK- 11,12 TX2CLK+ 11,12

C57 0.1U 0603 50V

C58 0.1U 0603 50V

C86 10U 1206 25V

1 L15 1

LGND2 +LPLL_VDD 1 1 1 C52 100P 0603 10% C54 0.1U 0603 50V C76 10U 1206 25V

+3VS 2 1 C53 0.1U 0603 50V +5VS 2

DVDD0 DE2 FLD/STL2 AS SPD SPC HIN VIN VREF2 SDD SDC DD1 DC1 DD2 DC2 V5V HOUT VOUT HPD HPINT* GPIO[0] GPIO[1] GPIO[2] GPIO[3] ENAVDD ENABKL

+DVDD 2 1 1 1

120Z/100M 2012 JL18 1 2 JP_NET20

2

2

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

1

GPIOA GPIOB GPIOC GPIOD DD2 DC2

120Z/100M 2012 JL19 2 JP_NET20

C29 10U 1206 25V

C30 0.1U 0603 2 2

C31 0.1U 0603

14x20 LQFP

C44 1 0.1U R46 1 1 TP4

1

HPD

DGND VADE R33 AS 1 2 0 0603

100 R53 1 0603

2

6

VADE

ENABKL ENAVDD

VB_GPIO3 VB_GPIO2 R49 1 1 PCIRST# 2 0 0603

ENPBLT 11,25 ENAVDD 11,12 2

R595 4.7K/NA 0603 2

1 R592 4.7K/NA 0603 R569

2 50V 0603 2 0 0603

LPLLGND PCI_INTA# 7,10,15

2

2

PCIRST# 7,10,15,18,19,22,23

DD2

1 0/NA

+VREF2 +3VS +3VS 1 L520 2 120Z/100M 2012 1 1 R555 4.7K 0603 6 6 VBCAD VBHCLK VBCAD VBHCLK 2 2 R565 4.7K/NA 0603 1 R578 2 0 0603D_DFS 2 R42

1 2 10K/NA 0603 C42 0.1U 50V 0603 R40 1 0603 R32 2 10K/NA 0603 2 0 0603

C49 0.1U/NA 0603 50V

1

2 0603

R567

1

2 33/NA 0603

GPIOC

C50 0.1U/NA 0603 50V DC2 +5VS 1 1 R593 1 0/NA 2 0603 R594 1 2 33/NA 0603 GPIOD

2

2

VGA
C96 10U 1206 25V

YUV TV 0 1

SCART 1 0

Normal TV 1 1

1

2 0

2

2

+3VS

C43 0.1U 0603 50V

GPIOA GPIOB

0 0

1 1

+3VS GPIOA R35 R39 GPIOB 1 1 2 10K/NA 0603 2 4.7K/NA 0603 2 4.7K/NA 0603 2 4.7K/NA 0603

1

A

C559 27P/NA 0603 5%

1

C572 27P/NA 0603 5%

R36

GPIOC
+3VS

0 0 Normal PAL 525I

0 1 PAL-M 525P

1 0 PAL-N 750P

1
A

GPIOD Normal TV YUV TV

1 Normal NTSC 1080I

2

2

R589 1 R588 1

+3VS

Title SIS 302LV Size Date:
5 4 3 2

Document Number

8640 Sheet 9 of
1

Rev 01 32

Wednesday, August 28, 2002

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