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V772 CRT Monitor Service Guide
Circuit Operation Theory
ACER V772 DEFLECTION CIRCUIT OPERATION THEORY
1. The Block Diagram of Deflection:
H-sync Digital Tilt Rotation
V-sync Controller Circuit C il
I2C BUS
AutoSync Deflection
Controller
IC TDA4856
Vertical
Deflection
Output Step Up
IC TDA4866 for B+ G1 & Spot Dynamic
Killer Circuit
Focus
H-SIZE
Compensation
Shut down
Circuit
G1
Dynamic
Regulation
Feedback
Horizontal
Deflection Output
Circuit
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V772 CRT Monitor Service Guide
Circuit Operation Theory
2. Autosync Deflection Controller (TDA4856)
2.1 pin 1 is AFC feedback.
2.2 pin XRAY: if V XRAY > threshold (6.25V typical) switches the whole IC into protection mode.
2.3 pin 3,4,5,6,8 for B+ control function block.
2.4 pin 11(EWDRV) is a parabolic waveform used for pincushion correction
2.5 pin 16 generates video claming & blanking pulse.
2.6 pin 18,19 is I2C data.
2.7 pin 21 V-regulation.
2.8 the resistor from pin 28 (HREF) to ground determines the maximum oscillator frequency.
2.9 the resistor from pin 27 (HBUF) to pin 28 defines the frequency range.
2.10 pin 31 H-regulation.
2.11 pin 32 focus.
+48V
ZD204
+14V C205 + 30V
2.2U R205
50V 110K D201
(EL) 1N4148
R236
10 R203
1/2W 62K
(FS) VR201 R238 R257
HVADJ 12K 2.2K +14V
HDRV (OPEN)
+14V
EWDRV R206
C203 C226 + ZD201
R265 2200P 100U 12V
R267 JUMPER 100V 25V
V2 56K (PE) (EL)
100 HV-ADJ C222
V1 R204 1U
2.2K R222
R264 1/4W C202 50V 4.7K
100 0.01U (EL) C227 R221 1/4W
10K
PWM
+
VBL 100V 0.1U
R201 +C201 (PE) 50V
100 47U (D) Q201
HBL 50V H945
R202 (EL)
100 R237 R208
CLAMP 10K 1M
C204
+2.2U R216
15.8K
CLBL 16
HSYNC 15
VSYNC 14
VOUT1 13
VOUT2 12
EWDRV11
VCC10
50V (1%)
9
HDRV 8
GND 7
BDRV 6
BIN 5
BSENS 4
BOP 3
XRAY 2
HFLB 1
TP3 TP2
(EL)
i.c.
+48V
R217 R218
+14V IC201 100K 22.1K
TDA4856 R235 (1%) (1%)
17 HUNLOCK
10K
31 HSMOD
21 VSMOD
20 ASCOR
32 FOCUS
26 HPLL1
30 HPLL2
25 SGND
22 VAGC
29 HCAP
24 VCAP
27 HBUF
28 HREF
23 VREF
19 SDA
18 SCL
R270 HFLB
10K
R263
HULK 1K
FOCUS
SCL R214 HSMOD
R209 C207 1.27K R220
100 0.1U R213 (1%) JUMPER R262
SDA 100V 3.3K R215 (OPEN)
R210 C206 (PE) C208 2.67K C210 R268 R261
100 0.1U 0.1U C209 (1%) 0.01U C211 120K (OPEN) SC2
VSMOD 100V R212 8200P R266 2200P R260 D208
22.1K 100V 100V 100V 100V
R211 (PE) (1%) (PE) 8.2M (EPI) 390K (OPEN)
JUMPER (PE) (PE)
R258 SC1
(OPEN) D206
(OPEN)
SC0
D207
1N4148
Fig 2 Autosync Deflection Controller circuit
3. H-Driver & Output CKT:
3.1 HDRV signal comes from IC201 pin8, then goes into Q301, Q301 constitutes an inverting stage
and combines with T302 to drive Q302.
3.2 Q302, C306, C309, D305 constitute the H-output CKT with diode modulator mode.
3.3 Q324 & Q325 constitute a switch for lower frequency driver switching to cover the low hfe HOT
running under low frequency will occur poor-drive condition.
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V772 CRT Monitor Service Guide
Circuit Operation Theory
Fig 3 HDRV & output circuit
4. Dynamic focus CKT
According to the CRT spec
H dynamic focus Vpp = 300 V
V dynamic focus Vpp = 130 V
4-1 Vertical dynamic focus
The signal from IC201 (pin 32) is a vertical frequency parabolic waveform.
Q321: an inverting amplifier stage.
4-2 Horizontal dynamic focus:
The waveform of C313 (CS-2, CS-1) is a horizontal frequency parabolic waveform, and is amplified by
T304.
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V772 CRT Monitor Service Guide
Circuit Operation Theory
+14V
R391 DAF
1K
CS-2
+ C346 + C327 C329
22U R351 10U R373 0.033U
16V 68K 50V 150 R327 400V
(EL) (EL) 1/2W 10 (MPE)
1W
(FS)
R352 T304
3.9K
3 2 R379
FOCUS Q321 1K
BF423 2W
4 1
CS-1
19.20113.001
C328
R353 470P
560K 1KV
1/4W (D)
-190V
Fig 4 Dynamic Focus circuit
5. Brightness & spot killer CKT.
5.1 G1 CKT
The bright control signal from UC controller is about 0 ~ 5V, when the voltage of bright control signal
decreases, the current flow through R241 increases and the voltage of G1 increases.
5.2 Blanking CKT
To avoid the disturbed picture display on the screen, we have to blank the monitor in the following
situations.
(1) when display mode is changed.
(2) when the monitor enter the power saving mode.
(3) blank the vertical retrace line
when the " blank" signal becomes "high" Q208 "ON" , Q203 "OFF".G1 voltage is about ( -190 *
R271/(R271+R241)) ＋ -184V. The signal which is IC201 (pin 16) is inverted and amplified by Q202,
and coupling to G1.During the vertical retrace interval , the G1 voltage will be drop down about 48V.
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V772 CRT Monitor Service Guide
Circuit Operation Theory
+45V
+6.5V
R231 R232
100 5.6K
1/4W 1/2W
CLAMP
ZD203 R240
R254
5.1V 3.3K
2.7K
Q208 + C224
Q202
H945 0.22U
H945 C223
R255 250V
(EL) R239 0.01U
BLANK BRITE Q203
6.8K 50V
10K BF423
(D)
R256
G1
HULK
10K
R241 R271
R269
100K 1M
1K
1/2W 1/2W
-190V
Fig5 Brightness & Spot killer circuit
6. BDRV and step-up CKT
6.1 The "BDRV" signal from TDA4856 pin6 is a square waveform. It is inverted and amplified by
Q201, Q311 and Q312 constitute a buffer stage.
6.2 Q325, L301, D318, C323 is step-up circuit B+ = 45 * ( Ton + Toff ) / Toff.
B+ +45V
C334
R333 1000P C322
10 1KV (OPEN) L301
1W (D) 100V 900UH
(PE) 19.40195.001
+14V
A Q311
H945
D318
UG4D
+ C323
4.7U Q325
250V IRF630 R370
(EL) R371 47
PWM
10K
Q312
A733
Fig 6 BDRV & Step-up circuit
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Circuit Operation Theory
7. HV Shutdown Circuit
The IC201 pin2 (XRAY) provides a voltage detector with a threshold. If the voltage at pin XRAY
exceeds this threshold (6.25v typical) the pins HDRV, BDRV, VOUT1 and VOUT2 are floating.
When anode voltage increases, the voltage at FBT (pin3) increases, the voltage at IC201 pin2 increases.
The shutdown voltage is about 28KV.
C204
+2.2U R216
15.8K
50V (1%) TP3 TP2
CLBL 16
HSYNC 15
VSYNC 14
VOUT1 13
VOUT2 12
EWDRV11
VCC 10
9
HDRV 8
GND 7
BDRV 6
BIN 5
BSENS 4
BOP 3
XRAY 2
HFLB 1
(EL)
+48V
i.c.
R217 R218
IC201 100K 22.1K
TDA4856 (1%) (1%)
17 HUNLOCK
31 HSMOD
21 VSMOD
20 ASCOR
32 FOCUS
26 HPLL1
30 HPLL2
25 SGND
22 VAGC
29 HCAP
24 VCAP
27 HBUF
28 HREF
23 VREF
19 SDA
18 SCL
Fig 7 HV- shutdown CKT
8.Horizontal linearity CKT
V772 Cs control truth table
Frequency range SC0 SC1 SC2 Cs Capacitor
Fh》 36K 0 0 0 C310+C311+C312+C313
36K》 Fh》 40K 0 0 1 C310+C311+C312
40K》 Fh》 51K 1 0 1 C310+C312
51K 》 Fh》 62K 1 0 1 C310+C312
62K 》 Fh》 72K 1 1 1 C310
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V772 CRT Monitor Service Guide
Circuit Operation Theory
T301
19.70066.001
D
1
*
(RED)
DYH+
B+ A 15
2
DYH-
12
(WHT)
L304
10UH 16
B 19.50051.051
+6.5V
2 3 R322
10
2W D322 5
8
1N4148
R309 3
220
2W 5 4 Q322
H945
H-LIN 4
C321 R319
D312 560P Q324 10K 6
RGP10J 1KV C2235 C330
(OPEN) 9
50V
(D)
B
CS-2
C313 C312 C311
0.15U 0.33 1.0U +14V
250V 250V 250V
(MPP) (MPP) (MPP)
R316
C310 Q307 4.7K
0.3U Q308 IRF640
400V R338 IRF630 R320
(MPP) 100K 100K
1/4W 1/4W A D309
FR155
R317 C316
47K 0.047U
50V SC0
A (D) Q303 R315
H945 47K
R324 C317 D310
47K 0.047U FR155 SC1
50V Q304 R325
(D) R326 H945 47K
Q309 4.7K
IRF630
R321
100K A
1/4W +14V
D311 R312
C315 FR155 4.7K
R313 0.047U
47K 50V
(D) SC2
CS-1 Q305 R311
H945 47K
Fig 8 Linear circuit
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V772 CRT Monitor Service Guide
Circuit Operation Theory
9. ABL CIRCUIT
When the beam current is over the limited current, the ABL circuit will pull down the
voltage of the video preamp (pin 10) to reduce the gain of video amplifier.
T301
19.70066.001
1
(RED)
15
2
12
(WHT)
16
ABLADJ
8 R308 D306 R310
10K 1N4148 1.5K
5 C324 1/2W
3 1500P ABL
100V R314
(PE) D307 6.8K
1N4148
4
6
9
Fig 9 ABL circuit
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Circuit Operation Theory
10. TILT CKT
We can rotate raster clockwise or counterclockwise by changing the direction of the current flow
through the tilt coil.
When the voltage of MP202 (pin3) is larger than 8V, the current flows from Q205 to Tilt coil, other
wise, the current flows from tilt coil to Q206
+6.5V
+14V +14V
MP202
3P
Q207 1
R247 H945 R249
2.2K (OPEN) 2
+5V Q205 1/4W
H945 3
R246 R245 TILT-COIL
R243 10K 10K
(OPEN) + C228
Q206 2.2U
A733 50V
Q204 (EL)
TILT H945 + 2.2U
C225
R244 Q210
2.2K 50V A733
(EL)
Fig 10 TILT circuit
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Circuit Operation Theory
11. Vertical Output Circuit
This vertical driver IC circuit is a half bridge configuration
The signals from TDA4856 OSC IC to TDA4863AJ
IC202
TDA4863AJ
-8.5V +14V
V-OUT
GND
C217
VP2
VP3
VP1
INN
INP
470U R227
16V 0.22
+ 1/2W
7
6
5
4
3
2
1
R228 (EL)
(FS)
1K
V1
C213
V2 D202 + 1000U
1N4003 25V
R229 (EL)
1K (105C)
C219 C218 R224 + C214
5600P 5600P R253 5.6 100U
100V 100V 180 DYV+ 1/4W 35V ZD202
(PE) (PE) R250 1/4W R251 R252 (EL) 20V
1.8K 1.8K 180
DYV- C216
C220 1/4W 0.1U
0.1U 100V R226 R274
100V (PE) 270 33K
(PE)
V+
C215 R275
470U 27K
R225 16V
1 + (EL)
1/2W
TR201
100
Fig11 Vertical output circuit
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Circuit Operation Theory
Switching Power Supply Operation Theory
1. General Specification
Input Voltage: 90~264VAC (FULL RANGE)
Input Frequency: 47~63Hz
Output Requirement: Dc Output
+6V
+13V
+78V
+45V
-10V
2. Block Diagram
DEGAUSS
CIRCUIT
OUTPUT
RECTIFIER ISOLATION RECTIFIER
AC RFI SWITCHING AND
INPUT FILTER & ELEMENT TRANSFOR OUTPUT
FILTER -MER FILTER
FEEDBACK
CONTROL POWER
CIRCUIT SAVING
CONTROL
3. Circuit Operation Theorem
3.1 RFI FILTER
L
C603
L602 2200P L603
C601 250V
3 4 0.47U (Y)
R601
250V
(X) C602
1 2 2200P L604
250V
(Y)
N
FG
This circuit designed to inhibit electric and magnetic interference for meet FCC, VDE, VCCI standard
requirements.
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Circuit Operation Theory
3.2 Rectifier and filter
L D602~D605
3 20D6 * 4
~
4 1
AC INPUT - +
C612
~2 + 220U DC OUTPUT
400V
N (EL)
When power switch is turn on, the AC voltage is Rectifier and filter by D603~D606, C612. The DC
output voltage will be 1.4*(ac input)
3.3 switching Element and isolation transformer
T601 FR701 C53
B61 6 11 (SHORT)
R604 C613
82K 0.01U
2W 1KV ZD601
(D)
C50 (OPEN)
12
C614 D610 D613
(OPEN) UF4007 (OPEN)
FR702
10
C51 L606 1
(SHORT)
(BEAD)
D608 L608
C608
47U RGP10D (BEAD)
25V 8
(EL) C624
220P
Q602 1KV
FS14SM-12 (D)
L607 15
(BEAD) R619
R608 D614 470
20K UF4007 2W 18
R607 *
0.15
2W 16
FR704
9 13 (SHORT) EGP30B