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SERVICE MANUAL
CR-L600
CD Receiver
CONTENTS
1 SPECIFICATIONS 2
2 ADJUSTMENTS AND CHECKS 3
3 IC BLOCK DIAGRAMS AND PIN FUNCTIONS 6
4 EXPLODED VIEWS AND PARTS LIST 18
5 PC BOARDS AND PARTS LIST 22
6 INCLUDED ACCESSORIES 27
NOTES
PC boards shown are viewed from parts side.
The parts with no reference number or no parts number in the
exploded views are not supplied.
As regards the resistors and capacitors, refer to the circuit diagrams
contained in this manual.
£ Parts marked with this sign are safety critical components. They £
must be replaced with identical components - refer to the appropriate
parts list and ensure exact replacement.
Parts of [ ] mark can be used only with the version designated.
Effective : December, 2002
1 SPECIFICATIONS
AMPLIFIER Section
Output Power .............................. 30 W/ch (6 ohms, 0.5 %,1 kHz)
Input Sensitivity................................................ 350 mV/47k ohms
Frequency Response ...................... 20 Hz to 20,000 Hz (+1/-3 dB)
TUNER Section
FM Section
Frequency Range .......... 87.50 MHz to 108.00 MHz (50 kHz steps)
Signal-to-Noise Ratio .................... 65 dB (Mono) / 60 dB (Stereo)
AM Section
Frequency Range .................... 522 kHz to 1629 kHz (9 kHz steps)
Signal-to-Noise Ratio............................................................ 35 dB
CD PLAYER Section
Frequency Response .......................... 20 Hz to 20,000 Hz (±2 dB)
Signal-to-Noise Ratio .......................................... more than 85 dB
Wow and Flutter ...................................................... Unmeasurable
GENERAL
Power Requirements............................................ 230 V AC, 50 Hz
Power Consumption .............................................................. 40 W
Power Consumption (standby)................................................ 5 W
Dimension (W x H x D) ................................ 190 x 104 x 349 mm
Weight ................................................................................ 3.0 kg
Standard Accessories .............. Remote Control Unit (RC-864) x 1
Batteries (AA, R6, SUM-3) x 2
AM Loop Antenna x 1
FM Lead-type Antenna x 1
Owner's Manual x 1
Warranty Card x 1
· Design and specifications are subject to change without notice.
· Weight and dimensions are approximate.
2
2 ADJUSTMENTS AND CHECKS
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3 IC BLOCK DIAGRAMS AND PIN FUNCTIONS
TMP87PS71AF (IC31)
I PIN ASSIGNMENTS
(TOP VIEW)
P96 (S14)
P95 (S13)
P94 (S12)
P92 (S10)
P93 (S11)
P77 (G0)
P76 (G1)
P75 (G2)
P74 (G3)
P73 (G4)
P72 (G5)
P71 (G6)
P70 (G7)
P67 (G8)
P91 (S9)
P90 (S8)
P87 (S7)
P86 (S6)
P85 (S5)
P84 (S4)
P83 (S3)
P82 (S2)
P81 (S1)
P80 (S0)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
(SIS) P97 65 40 P66 (G9)
VKK 66 39 P65 (G10)
(KEY0) P40 67 38 P64 (G11)
(KEY1) P41 68 37 P63 (G12)
(KEY2) P42 69 36 P62 (G13)
(KEY3) P43 70 35 P61 (G14)
(KEY4) P44 71 34 P60 (G15)
(KEY5) P45 72 33 VDD
(CIN5/KEY6) P46 73 32 P07
(CIN4/KEY7) P47 74 31 P06
(CIN3) P50 75 30 P05
(CIN2) P51 76 29 P04
(CIN1) P52 77 28 P03
(CIN0) P53 78 27 P02
P54 79 26 P01
(PWM/PDO) P55 80 25 P00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
(INT0) P10
(INT1) P11
(INT2/TC1) P12
(DVO) P13
P14
(TC2) P15
P16
P17
TEST
(XTIN) P21
(XTIN) P22
RESET
XIN
XOUT
VSS
(INTS/STOP) P20
(INT3/TC3) P30
(TC4) P31
(SCK) P32
(SI) P33
(SO) P34
(HSCK) P35
P36
(HSO) P37
I BLOCK DIAGRAM
I/O Ports
I/O Ports Output Ports
P97 P87 P77 P67
to to to to
P90 P80 P70 P60
Power Supply VDD P9 P8 P7 P6
VSS
Key scan
VFT Power VKK VFT drive circuit (automatic display) control
Supply
P S W Stack Pointer Data Memory Program counter
Flags RBS (RAM)
ALU
Program Memory
Register banks (ROM)
Reset I/O RESET
System Controller
Test Pin TEST
Interrupt Controller
Standby Controller Inst.
Register
Inst.
Timing Generator Time Base 16-bit 8-bit Serial Decoder
Timer Timer/Counters Timer/Counters Interfaces
Resonator XIN High
connecting XOUT frequ. Clock TC1 TC2 TC3 TC4 SIO HSO 6-bit A/D
Pins Low Generator Watchdog Converter
frequ. Timer
P2 P0 P1 P3 P5 P4
P22 P07 P17 P37 P55 P47
to to to to to to
P20 P00 P10 P30 P50 P40
I/O Ports
6
PIN NO. SYMBOL I/O DESCRIPTION
1 F_MUTE O FUNCTION MUTE CONTROL PORT
2 REMO I REMOTE CONTROL SENSOR DATA INPUT
3 RDS CLK I
RDS CLOCK/DATA PORT
4 RDS DATA O
5 V_SDATA O
VOL.IC CONTROL PORT
6 V_SCLK O
7 -
8 CD_M_STBY O CD STAND-BY PORT
9 GND -
10 VSW2 I
VOLUME CONTROL PORT
11 VSW1 I
12 RESET I RESET INPUT PORT
13 X_IN I
CRYSTAL CONNECTION PORT
14 X_OUT O
15 GND -
16 BACK_UP I BACK UP MODE CONTROL
17 CD_BUS0 O
18 CD_BUS1 O
CD DATA BUS PORT
19 CD_BUS2 O
20 CD_BUS3 O
21 (DVD)RXDO O CD OPEN CONTROL PORT
22 D_RST O CD CLOSE CONTROL PORT
23 - -
24 TUNER_IN I
TUNED/STEREO DISPLAY CONTROL PORT
25 STEREO_IN I
26 OPLED O LED ON/OFF CONTROL PORT
27 POWER O POWER ON/OFF CONTROL PORT
28 PLL_DATA_IN I PLL DATA INPUT PORT
29 F_STB O
30 F_P_CLK O FUNCTION IC CONTROL PORT
31 F_P_DATA O
32 PLL_CE O PLL ENABLE CONTROL PORT
33 VDD - POWER PORT(+5)
34 OPTION(A) O
35 OPTION(B) O
36 OPTION(C) O
OPTION/FIP SEGMENT CONTROL PORT
37 OPTION(D) O
38 OPTION(E) O
39~65 FIP SEGMENT O
66 VKK(-) - POWER PORT(-30)
67 OPTION I OPTION CONTROL PORT
68 PROTECT I PROTECT INPUT PORT
69 HPIN I HEADPHONE IN/OUT DEFECT PORT
70 CD_PWR O CD POWER PORT
71 CD/RST O CD RESET PORT
72 CD_BUCK O CD BUCK PORT
73 CD/CCE O CD ENABLE CONTROL PORT
74 CD/RW O CD_RW PORT
75 M_OP_M O
MECHA. CONTROL PORT
76 M_CL_M O
77 KEY2 I
KEY CONTROL INPUT
78 KEY1 I
79 SP_ON I SPEAKER ON/OFF PORT
80 T_MUTE O TUNER MUTE PORT
7
NJW1136 (IC24)
I BLOCK DIAGRAM
TONE TONE
AGC1 SS-FIL LF1 LF2 LF3 OUTa SCL SDA AD
-Ha -La
CVA
CVB
IN a VOL1 TONE VOL2 CVW
CTH
NJRC
I2C BUS CTL
Original
Interface CSR
Surround
AGC & LPF VOL2
Simulated Trimmer PORT
Stereo PORT
AUX1
AUX0
IN b VOL1 TONE VOL2
GND
Bias
V+
AGC2 SR-FIL TONETONE OUTb OUTw Vref
-Hb -Lb
TA2125AF (IC13)
I BLOCK DIAGRAM
G OUT
4ch VCC
Driver REG
VR RIN FIN STB IN3 IN4 STB
RL4 RL3
RE
N.C.
36 35 34 33 32 31 30 29 28 FIN 27 26 25 24 23 22 21 20 19
Control STBY STBY 3 3 3 3
Logic
Iref TSD
3 3 3 3
1 2 3 4 5 6 7 8 9 FIN 10 11 12 13 14 15 16 17 18
N.C. N.C. GND N.C. N.C.
RL5
RL2 RL1
VCIN IN1 IN2
8
TA2153FN (IC12)
I BLOCK DIAGRAM
36 pF
10 k 50 k
FEO 16 15 k 15 SBAD
10 pF
15 k
3 pF
30 k
FEN 17 14 TEO
10 k
60 k 20 k
10 k
10 pF
SEB 18 13 TEN
30 k
3 pF
VRO 19 12 2VRO
20 k
20 k 20 k
12 k 3 STATE
21.82 k
RFRP 20 12 k DET. 11 TEB
11 k 48 k
100 20 k 83 k
SW1
BTC 21 2.9 k 10 SEL
100 k
1 k
SW2
RFCT 22 9 LDO
100 k
SW3
1.4 k
238 k
PKC 23 8 MDI
11 k 15 pF 13 k 2.26 k
BOTTOM
RFRPIN 24 I-I 7 TNI
PEAK 238 k
20 k
15 pF
RFGO 25 I-I 6 TPI
150 k
GVSW 26 Frequency 90 k 20 k 40 pF 5 FPI
1 k
60 k 60 k
AGC Amp. 1 k
AGCIN 27 4 FNI
150 k
40 pF
RFO 28 3 GMAD
GND 29 2 RFGC
RFN2 30 1 VCC
9
TC9164AF
I BLOCK DIAGRAM
Vss GND VDD
1 14 28
L-S 1 2 27 R-S 1
L-S 2 3 26 R-S 2
L-S 3 4 25 R-S 3
L-S 4 5 24 R-S 4
LATCH CIRCUIT
LEVEL SHIFTER
LEVEL SHIFTER
LATCH CIRCUIT
L-COM 1 6 23 R-COM 1
L-S 5 7 22 R-S 5
L-S 6 8 21 R-S 6
L-COM 2 9 20 R-COM2
L-S 7 10 19 R-S 7
L-S 8 11 18 R-S 8
L-COM 4 12 17 R-COM 4
ST 13 16 DATA
15 CK
SHIFT REGISTER
TC9163AF (IC21)
I BLOCK DIAGRAM
Vss GND VDD
1 14 28
L-S 1 2 27 R-S 1
L-S 2 3 26 R-S 2
L-S 3 4 25 R-S 3
L-COM 1 5 24 R-COM1
LATCH CIRCUIT
LEVEL SHIFTER
LEVEL SHIFTER
LATCH CIRCUIT
L-S 4 6 23 R-S 4
L-S 5 7 22 R-S 5
L-S 6 8 21 R-S 6
L-COM 2 9 20 R-COM2
L-S 7 10 19 R-S 7
L-S 8 11 18 R-S 8
L-COM 4 12 17 R-COM 4
ST 13 16 DATA
15 CK
SHIFT REGISTER
10
TC9462A (IC10)
I BLOCK DIAGRAM
PVREF
VCOR
VCOF
SBAD
SLCO
RFRP
RFCT
LPFO
AV DD
LPFN
AV SS
VREF
TSIN
RFZI
FOO
TEZI
TRO
RFI
TEI
FEI
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
RFGC 51 30 TMAX
TEBC 52 29 TMAXS
FMO 53 28 PDO
FVO 54 27 ZDET
D/A
slicer
Data
TMAX
DMO 55 26 HSSW
VCO
PLL
A/D
2VREF 56 25 P2VREF
PWM
SEL 57 24 TESIO0
FLGA 58 23 VDD
FLGB 59 adjustment circuit 22 MONIT
Digital equalizer
FLGC 60 21 COFS
status
CLV servo
Automatic
FLGD 61 20 SPDA
VDD 62 19 SPCK
control
Servo
VSS 63 18 SBSY
Synchronous
EFM decode
ROM
RAM
guarantee
IO0 64
Sub code
17 SFSY
decoder
IO1 65 16 DAT A
IO2 66 15 VSS
IO3 67 14 VDD
Address circuit
DMOUT 68 Digital out 13 CLCK
16 KRAM
CKSE 69 12 SBOK
DACT 70 11 IPF
TESIN 71 10 MBOV
generator
Clock
TESIO1 72 9 DOUT
VSS 73 8 AOUT
Correction
circuit
PXI 74 7 BCK
Audio out
circuit
PXO 75 6 VSS
DAC
1 bit
VDD 76 5 LRCK
interface
Micon
XVSS 77 4 EMPH
XI 78 3 UHSO
LPF
XO 79 2 HSO
XVDD 80 1 TEST0
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DVR
BUS0
BUS1
BUS2
BUS3
TSMOD
DV SL
TEST1
TEST2
TEST3
TEST4
LO
DV SR
DV DD
VDD
VSS
BUCK
CCE
RST
RO
11
Pin No. Symbol I/O Functional Description Remarks
1 TEST0 I Tes t mode terminal. Normally, keep at open. With pull-up resistor.
Playback speed mode flag output terminal.
2 HSO O UHSO HSO Playback Speed
H H Normal
H L 2 times
L H 4 times
3 UHSO O
L L
Subcode Q data emphasis flag output terminal.
4 EMPH O Emphasis ON at "H" level and OFF at "L" level.
The output polarity can invert by command.
Channel clock output terminal. (44.1 kHz)
5 LRCK O L-ch at "L" level and R-ch at "H" level. The output polarity can
invert by command.
6 VSS Digital GND terminal.
7 BCK O Bit clock output terminal. (1.4112 MHz)
8 AOUT O Audio data output terminal.
9 DOUT O Digital data output terminal.
Buffer memory over signal output terminal.
10 MBOV O
Over at "H" level.
Correction flag output terminal.
11 IPF O At "H" level, AOUT output isV
, made to correction impossibility
by C2 correction processing.
Subcode Q data CRCC check adjusting result output
12 SBOK O
terminal. The adjusting result is OK at "H" level.
Subcode P~W data readout clock input/output terminal.
13 CLCK I/O Schmitt input
This terminal can select by command bit.
14 VDD Digital power supply voltage terminal.
15 VSS Digital GND terminal.
16 DATA O Subcode P~W data output terminal.
17 SFSY O Play-back frame sync signal output terminal.
18 SBSY O Subcode block sync signal output terminal.
19 SPCK O Processor status signal readout clock output terminal.
20 SPDA O Processor status signal output terminal.
Correction frame clock output terminal.
21 COFS O
(7.35 kHz)
Internal signal (DSP internal flag and PLL clock) output
22 MONIT O terminal. Selected by command.
This terminal output the text data with serial by command.
23 VDD Digital power supply voltage terminal.
Tes t input/output terminal. Normally, keep at "L" level.
24 TESIO0 I The terminal that inputted the clock for read of text data by
command.
25 P2VREF PLL double reference voltage supply terminal.
2-state output.
26 HSSW O This terminal is used to output PVREF or HiZ by command.
(PVREF, HiZ)
27 ZDET O 1 bit DA converter zero detect flag output terminal.
Phase difference signal output terminal of EFM signal and 3-state output.
28 PDO O
PLCK signal. (P2VREF, PVREF SS)
12
Pin No. Symbol I/O Functional Description Remarks
TMAX detection result output terminal. Selected by 3-state output.
29 TMAXS O
command bit (TMPS). (P2VREF, PVREF, VSS)
TMAX detection result output terminal. Selected by
command bit (TMPS).
TMAX Detection TMAX Output
3-state output.
30 TMAX O Longer than fixed freq. "P2VREF" (P2VREF, HiZ, VSS)
Shorter than fixed freq. "VSS"
Within the fixed freq. "HiZ"
31 LPFN I LPF amplifier inverting input terminal for PLL. Analog input.
32 LPFO O LPF amplifier output terminal for PLL. Analog output.
33 PVREF PLL reference voltage supply terminal.
VCO center frequency reference level terminal.
34 VCOREF I
Normally, keep at "PVREF" level.
35 VCOF O VCO filter terminal. Analog output.
36 AVSS Analog GND terminal.
37 SLCO O Data slice level output terminal. Analog output.
Analog input.
38 RFI I RF signal input terminal.
(Zin: selected by command)
39 AVDD Analog power supply voltage terminal.
Analog input.
40 RFCT I RFRP signal center level input terminal.
(Zin: 50 k )
41 RFZI I RFRP zero cross input terminal. Analog input.
42 RFRP I RF ripple signal input terminal. Analog input.
43 FEI I Focus error signal input terminal. Analog input.
44 SBAD I Sub-beam adder signal input terminal. Analog input.
45 TSIN I Tes t input terminal. Normally, keep at "VREF" level. Analog input.
Tracking error signal input terminal.
46 TEI I Analog input.
Tak e in at tracking servo on.
Analog input.
47 TEZI I Tracking error zero cross input terminal.
(Zin: 10 k )
48 FOO O Focus servo equalizer output terminal. Analog output.
49 TRO O Tracking servo equalizer output terminal. (2VREF~AV SS)
50 VREF Analog reference voltage supply terminal.
RF amplitude adjustment control signal output terminal.
51 RFGC O
3-state PWM signal output. (PWM carrier 88.2 kHz)
Tracking balance control signal output terminal.
52 TEBC O
3-state PWM signal output. (PWM carrier 88.2 kHz)
Feed equalizer output terminal. 3-state output.
53 FMO O
3-state PWM signal output. (PWM carrier 88.2 kHz) (2VREF, VREF, VSS)
Speed error signal or feed search equalizer output terminal.
54 FVO O
3-state PWM signal output. (PWM carrier 88.2 kHz)
Disc equalizer output terminal.
55 DMO O
(PWM carrier 88.2 kHz for DSP, Synchronize to PXO)
56 2VREF Analog double reference voltage supply terminal.
APC circuit ON/OFF indication signal output terminal.
57 SEL O At the laser on time, "HiZ" level at UHS L and "H" level at
UHS H.
13
Pin No. Symbol I/O Functional Description Remarks
External flag output terminal for internal signal.
58 FLGA O Can select signal from TEZC, FOON , FOK and RFZC by
command.
External flag output terminal for internal signal.
59 FLGB O Can select signal from DFCT , FOON , FMON and RFZC
by command.
External flag output terminal for internal signal.
60 FLGC O Can select signal from TRON , TRSR , FOK and SRCH
by command.
External flag output terminal for internal signal.
61 FLGD O Can select signal from TRON , DMON , HYS and SHC
by command.
62 VDD Digital power supply voltage terminal.
63 VSS Digital GND terminal.
64 IO0
General I/O terminal be changed over input port or output
65 IO1 port by command. At the input port mode, it can readout a
I/O
66 IO2 state of terminal (H/L) by read command. At the output port
mode, it outputs (H/L/HiZ) by command.
67 IO3
"L" active, when this terminal is set "L", IO 0/1 and 2/3 output
68 DMOUT I feed equalizer signal and disc equalizer signal of 2-state With pull-up resistor.
PWM respectively.
69 CKSE I Normally, keep at open. With pull-up resistor.
70 DACT I DAC test mode terminal. Normally, keep at open. With pull-up resistor.
71 TESIN I Tes t input terminal. Normally, keep at "L" level. Analog input.
72 TESIO1 I Tes t input/output terminal. Normally, keep at "L" level.
73 VSS Digital GND terminal.
Crystal oscillator connecting input terminal for DSP.
74 PXI I
Normally, keep at "L" level.
75 PXO O Crystal oscillator connecting output terminal for DSP.
76 VDD Digital power supply voltage terminal.
77 XVSS Oscillator GND terminal for system clock.
78 XI I Crystal oscillator connecting input terminal for system clock.
79 XO O Crystal oscillator connecting output terminal for system clock.
80 XVDD Oscillator power supply voltage terminal for system clock.
81 DVSR Analog GND terminal for DA converter. (R-ch)
82 RO O R channel data forward output terminal.
83 DVDD Analog supply voltage terminal for DA converter.
84 DVR Reference voltage terminal for DA converter.
85 LO O L channel data forward output terminal.
86 DVSL Analog GND terminal for DA converter. (L-ch)
87 TEST1 I Tes t mode terminal. Normal, keep at open. With pull-up resistor.
88 TEST2 I Tes t mode terminal. Normal, keep at open. With pull-up resistor.
89 TEST3 I Tes t mode terminal. Normal, keep at open. With pull-up resistor.
90 BUS0 I/O
91 BUS1 I/O Schmitt input.
Micon interface data input/output terminal.
92 BUS2 I/O With pull-up resistor.
93 BUS3 I/O
94 VDD Digital power supply voltage terminal.
14
Pin No. Symbol I/O Functional Description Remarks
95 Vss Digital GND terminal.
96 BUCK I Micon in terface clock input terminal Schmitt input
Command and data sending/receiving chip enable signal
97 CCE I input terminal. Schmitt input
The bus line becomes active at "L"level.
98 TEST4 I Test mode selection terminal. With pull-up resistor
99 TSMOD I Local test mode selection terminal With pull-up resistor
100 RST I Reset signal input terminal. Reset at "L"level. With pull-up resistor
15
TC2000 Audio Signal Processor Pin Descriptions
Pin Function Description
1 BIASCAP Bandgap reference times two (typically 2.5VDC). Used to set the common mode
voltage for the input op amps. This pin is not capable of driving external circuitry.
2, 6 FDBKP2, FDBKP1 Positive switching feedback.
3 DCMP Interna