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Contents COVER PAGE Block diagram Power Sequence Silverthorne CPU-1 Silverthorne CPU-2 Poulsbo-1 Host Bus Poulsbo-2 RTC/LPC/PCIE/LVDS Poulsbo-3 USB/AudioIDE/GPIO Poulsbo-4 DDR2 Poulsbo-5 Chipset Power1 Poulsbo-6 Decoupling Cap Poulsbo-7 Chipset Power2 Poulsbo-8 Chipset VSS DDR2 SODIMM CPU Decoupling Clock CK540 FWH_PIC16F505_PCIE
Page 18 19 20 21 22 23 24
Contents
USB Ports CF_Thermal sensor
C
8 9 10 11 12 13 14 15
B
16 17
A
Embedded Menlow XL Processor for Gilmore Summit Baseboard
5
w
w w
la .
4
to p
-s p
h c
m e
25 26 27 28 29 30 31 32 33 34
ic t a
SATA HDD
SDIO_TPM1.2
HDMI CH7315B
LVDS_HDMI Connector LPC super I/O GPIO header COM1~2_LPC Debug Port HD COEDC ALC262 Audio_Amp
C
.c s
m o
D
KB/MS_AMP2_RJ22
Ethernet_RTL8111B LAN SWITCH RTL8366SB RJ-45_LAN LED POWER IN +12V, 5VSB VCC, 5V_Dual, 3VSB & VCC3
+2.5VDD,+1.8V,+1.5V,VTT_DDR Vcore
B
A
Title Size Custom Date: Document Number
Intel
COVER PAGE
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 1 of 35
3
2
5
4
3
2
1
Block Diagram
D
ISL6262-IMVP6
Vcore
P34
Silverthone XL
P04,P05
CK540
P16
SDVO
HD CODEC 2
DDR2 SO-DIMM CHANNEL A P14 SATA HDD P20 JM20330
P20
DDR2 CHA
18/24-bits LVDS
LVDS
P14
C
Poulsbo XL
PCIEx1(1) bus IDE BUS
2.5V, 1.8V, 1.5V, VTT_DDR
P33
CF CONN
P19
VCC, 5V_Dual, 3VSB & VCC3
P32
USB PORT x 4 Rear Panel USB PORT x 1
(DECT module)
USB 0~3
P18
USB 5 USB 6 USB 7
P18 P18
USB PORT x 1
B
POWER IN +12V, 5VSB
(for Touch screen)
P31
USB PORT x 1
(Reserved)
P18
LPC BUS
TPM
P21
4 Bit GPIO
DC Jack +12V@4A
P31 Power LED
A
BIOS
P17
LPC Debug port P25
Debug LED HDD LED
LED Tower
5
w
w w
la .
4
GPIO_SwitchHook
to p
P25
W83627DHG
P24
-s p
P.06~P13 P26
h c
P21
PCIEx1(2) bus
m e
P21
Gbe NIC
RTL8111B
PCI Express X1
P17
ic t a
P23 P28
.c s
SDVO-HDMI CH7315B
SWITCH
DDR2 TERMINATOR
m o
V1.3
D
CPU BUS
HDMI
P23
P22
RJ-45 RTL8366S
P29 P30
C
RJ-45
P30
MUTE_MIC
GP60
Int_Mic,Int_SP Audio Jack 1~2 (Ext_Mic,Ext_SP)
HD CODEC 1
ALC262
B
P27
Audio Jack 3 (Headset-out,Headset-in)
RJ22 Headset
Amp1 SDIO 2
P27
Amp2
P26
SDIO 1
D/A1 HW MONITOR
P19 P21
D/A2
P26
Title Size B Date: Document Number
A
RS232 x 2
KB/MS
Intel
Block diagram
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 2 of 35
3
2
5
4
3
2
1
POWER SEQUENCE
D
Poulsbo +1.8V VCCP +1.5V +2.5VDD VTT_DDR
PG.33
SYSTEM_PG
H_PWRGD
6
Silverthone
PG.4-5
PG.6-13
IMVP6_PGOOD
1
Vmonitor
VRM_ON
2
PG.17
DELAY 99 ms
PG.34
IMVP_ON
3
ISL6262
VCC
C
VCC3
ISL6545
+12V
PG.31
PG.32
PG.32
5VSB
PG.31
W83627DHG
SIO_PWROK
VIN
ISL6545
DC IN
PG.31
3VSB
PG.32
B
VIN 5VSB +12V VCC VCC3 +V1.8
A
+V0.9SB +1.5V VCCP VCC_CORE
5
w
w w
la .
4
to p
-s p
PG.24
h c
5
m e
CK540
4
PG.34
PG.16
VR_PWRGD_CLKEN#
ic t a
7 5
.c s
m o
D
C
4
DELAY
SCH_PWROK
PG.32
B
A
Title Size Custom Date:
3 2
Intel
Power sequence
Document Number
Gilmore Summit
Tuesday, December 30, 2008
1
Rev Z000 3 of 35
Sheet
5
4
3
2
1
SILVERTHORNE_CUST SILVERTHORNE_CUST
U38A 6 H_A#[31:3] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 P21 H20 N20 R20 J19 N19 G20 M19 H21 L20 M20 K19 J20 L21 K20 N21 J21 G19 P20 R19 C19 F19 E21 A16 D19 C14 C18 C20 E20 D20 B18 C15 B16 B17 C16 B19 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 ADSTB0 REQ0 REQ1 REQ2 REQ3 REQ4 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ADSTB1 A20M FERR IGNNE STPCLK LINT0_INTR LINT1_NMI SMI RSVD_D17 RSVD_M18 RSVD_T17 RSVD_V9 RSVD_R4 RSVD_M4 RSVD_D4 RSVD_T6 RSVD_P17 RSVD_A3 RSVD_C1 RSVD_C21 RSVD_N15 RSVD_V15
1 OF 4
V1.05S_VTT_C6 ADS BNR BPRI DEFER DRDY DBSY
CONTROL
U38B 6 H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 Y11 W10 Y12 AA14 AA11 W12 AA16 Y10 Y9 Y13 W15 AA13 Y16 W13 AA9 W9 Y14 Y15 W16 AA5 Y8 W3 U1 W7 W6 Y7 AA6 Y3 W2 V3 U2 T3 AA8 V2 W4 Y4 Y5 Y6 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DSTBN0 DSTBP0 DINV0 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DSTBN1 DSTBP1 DINV1 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 DSTBN2 DSTBP2 DINV2 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DSTBN3 DSTBP3 DINV3
V19 Y19 U21 T21 T19 Y18 T20 F16 V16 W20 D15 W18 Y17 U20 W19 AA17 V20 K17 J18 H15 J15 K18 J16 M17 N16 M16 L17 K16
H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BREQ#0
6 6 6 6 6 6 6
V1.05S_VTT_CPU
R130 1K/4 R529 1K/4
D
BR0 IERR INIT LOCK RESET RS0 RS1 RS2 TRDY HIT HITM BPM0 BPM1 BPM2 BPM3 PRDY PREQ TCK TDI TDO TMS TRST
H_INIT# H_LOCK# H_CPURST_R# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK_0 XDP_TDI XDP_TDO_CPU XDP_TMS XDP_TRST# 6 6 6 6 6 6 6 0/4 R122
6
6 6
H_ADSTB#0 H_REQ#[4:0]
H_CPURST#
6 6 6 6 6 H_DSTBN#0 H_DSTBP#0 H_DINV#0
H_D#[63:0]
6
H_A#[31:3]
V1.05S_VTT_C6
C
V1.05S_VTT_CPU
R536 R531 121/4/1 1K/4/1
R114 68/4
6 24 6 6 6 6 6
H_ADSTB#1 RB751V-40/SC-76 D28 C A H_A20M# H_PBE# H_IGNNE# R208 0/6 H_STPCLK# H_INTR H_NMI H_SMI# R534 1K/4/1
U18 T16 H_IGNNE_R# J4 R16 T15 R15 U17 D17 M18 T17 V9 R4 M4 D4 T6 P17 A3 C1 C21 N15 V15
THERM
PROCHOT THERMDA THERMDC THERMTRIP
24.3/6/1 G17 H_PROCHOT_R# R131 E4 VTIN2 19,24 E5 AAGND 19,24 H17 V11 V12 H_THERMTRIP# 6 CLK_CPU_BCLK 16 CLK_CPU_BCLK# 16
H_PROCHOT# 8,34
MISC
BCLK0 BCLK1
(open)
B
V1.05S_VTT_CPU
RSVD0 RSVD1 RSVD2 RSVD3 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8
A17 B14 B15 A14 D6 G6 H6 K4 K5 M15 L16 A13
0/4 0/4
R169
V1.05S_VTT_C6 XDP_BPM#4 XDP_BPM#3 XDP_BPM#2 XDP_BPM#1 XDP_BPM#0 XDP_BPM#5 H_IGNNE# XDP_TRST# R125 R128 R129 R127 R124 R126 R207 R154 510/4/1 510/4/1 510/4/1 510/4/1 510/4/1 510/4/1 510/4/1 510/4/1
XDP_TMS XDP_TDI
A
XDP_TDO_CPU R132 56/4/1
5
w w
XDP_TCK_0
. w
R113 R123 39/4 150/4/1 R163 27.4/4/1
V1.05S_VTT_CPU
p la
4
to
R583 1K/4 R585 1K/4
-s p
R161 V1.05S_VTT_C6 VCCP CPU_CMREF C482 0.1U/16V/X5R/4
h c
m e
6 6 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1 16 16 16 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 R206 R202 R203 R567 1K/4 R560 2K/4/1 V1.05S_VTT_CPU R526 R535 R530 R527 1K/4/1 1K/4/1 1K/4/1 1K/4/1
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
ic t a
GLTREF CMREF TEST1 TEST2 TEST3 TEST4 BSEL0 BSEL1 BSEL2 U5 V5 M6 N6 0/4 J6 0/4 H5 0/4 G5 H_GTLREF C477 0.1U/16V/X5R/4
DATA GRP 1
ADDR GROUP 1
XDP/ITP SIGNALS
DATA GRP 3
.c s
DATA GRP 2
m o
R3 R2 P1 N1 M2 P2 J3 N3 G3 H2 N2 L2 M3 J2 H1 J1 K2 K3 L1 C2 G2 F1 D3 B4 E1 A5 C3 A6 F2 C6 B6 B3 C4 C7 D2 E2 F3 C5 T1 T2 F20 F21 R18 R17 U4 V17 N18 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_D#[63:0]
6
DATA GRP 0
D
ADDR GROUP 0
H_DSTBN#2 H_DSTBP#2 H_DINV#2
6 6 6 6
H_D#[63:0]
C
H_DSTBN#3 H_DSTBP#3 H_DINV#3
6 6 6
H_GTLREF A7 CPU_CMREF B7
COMP0 COMP1 COMP2 COMP3 DPRSTP DPSLP DPWR PWRGOOD SLP
COMP0 R592 27.4/4/1 COMP1 R593 54.9/4/1 COMP2 R514 27.4/4/1 COMP3 R515 54.9/4/1
HCLK
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP#
6,34 6 6 6 6
B
2 OF 4
R538 49.9/4/1 CLK_CPU_BCLK# CLK_CPU_BCLK R539 49.9/4/1
V1.05S_VTT_C6
Layout note: Comp0,2 connect with trace length shorter Comp1,3 connect with trace length shorter
Zo=27.4 ohm, make than 0.5". Zo=55 ohm, make than 0.5".
H_GTLREF Z=55 ohm "0.5" Max length.
V1.05S_VTT_C6
H_CPUSLP# H_PWRGD H_DPSLP# H_DPRSTP#
6 6 6 6,34
A
Title Size B Date:
3 2
Intel
Silverthorne CPU-1
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 4 of 35
5
4
3
2
1
SILVERTHORNE_CUST
U38D A2 A4 A8 A15 A18 A19 A20 B1 B2 B5 B8 B13 B20 B21 C8 C17 D1 D5 D8 D14 D18 D21 E3 E6 E7 E8 E15 E16 E19 F4 F5 F6 F7 F17 F18 G1 G4 G7 G9 G13 G21 H3 H4 H7 H9 H13 H16 H18 H19 J5 J7 J9 J13 J17 K1 K6 K7 K9 K13 K15 K21 L3 L4 L5 L6 L7 L9 L13 L15 L18 L19 M1 M5 VSS_A2 VSS_A4 VSS_A8 VSS_A15 VSS_A18 VSS_A19 VSS_A20 VSS_B1 VSS_B2 VSS_B5 VSS_B8 VSS_B13 VSS_B20 VSS_B21 VSS_C8 VSS_C17 VSS_D1 VSS_D5 VSS_D8 VSS_D14 VSS_D18 VSS_D21 VSS_E3 VSS_E6 VSS_E7 VSS_E8 VSS_E15 VSS_E16 VSS_E19 VSS_F4 VSS_F5 VSS_F6 VSS_F7 VSS_F17 VSS_F18 VSS_G1 VSS_G4 VSS_G7 VSS_G9 VSS_G13 VSS_G21 VSS_H3 VSS_H4 VSS_H7 VSS_H9 VSS_H13 VSS_H16 VSS_H18 VSS_H19 VSS_J5 VSS_J7 VSS_J9 VSS_J13 VSS_J17 VSS_K1 VSS_K6 VSS_K7 VSS_K9 VSS_K13 VSS_K15 VSS_K21 VSS_L3 VSS_L4 VSS_L5 VSS_L6 VSS_L7 VSS_L9 VSS_L13 VSS_L15 VSS_L18 VSS_L19 VSS_M1 VSS_M5 VSS_M7 VSS_M9 VSS_M13 VSS_M21 VSS_N4 VSS_N5 VSS_N7 VSS_N9 VSS_N13 VSS_N17 VSS_P3 VSS_P4 VSS_P5 VSS_P6 VSS_P7 VSS_P9 VSS_P13 VSS_P15 VSS_P16 VSS_P18 VSS_P19 VSS_R1 VSS_R5 VSS_R7 VSS_R9 VSS_R13 VSS_R21 VSS_T4 VSS_T5 VSS_T7 VSS_T9 VSS_T10 VSS_T11 VSS_T12 VSS_T13 VSS_T18 VSS_U3 VSS_U6 VSS_U7 VSS_U15 VSS_U16 VSS_U19 VSS_V1 VSS_V4 VSS_V6 VSS_V7 VSS_V8 VSS_V13 VSS_V14 VSS_V18 VSS_V21 VSS_W1 VSS_W5 VSS_W8 VSS_W11 VSS_W14 VSS_W17 VSS_W21 VSS_Y1 VSS_Y2 VSS_Y20 VSS_Y21 VSS_AA2 VSS_AA3 VSS_AA4 VSS_AA7 VSS_AA10 VSS_AA12 VSS_AA15 VSS_AA18 VSS_AA19 VSS_AA20 VSS_R6 M7 M9 M13 M21 N4 N5 N7 N9 N13 N17 P3 P4 P5 P6 P7 P9 P13 P15 P16 P18 P19 R1 R5 R7 R9 R13 R21 T4 T5 T7 T9 T10 T11 T12 T13 T18 U3 U6 U7 U15 U16 U19 V1 V4 V6 V7 V8 V13 V14 V18 V21 W1 W5 W8 W11 W14 W17 W21 Y1 Y2 Y20 Y21 AA2 AA3 AA4 AA7 AA10 AA12 AA15 AA18 AA19 AA20 R6
V1.05S_VTT_C6
SILVERTHORNE_CUST
U38C V1.05S_VTT_CPU
D
VCC_CORE A10 A11 A12 B10 B11 B12 C10 C11 C12 D10 D11 D12 E10 E11 E12 F10 F11 F12 G10 G11 G12 H10 H11 H12 J10 J11 J12 K10 K11 K12 L10 L11 L12 M10 M11 M12 N10 N11 N12 P10 P11 P12 R10 R11 R12 D7 F15 D16 E18 G15 G16 E17 G18 C13 D13 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 R142 R147 34 34 34 34 34 34 34 VCC_CORE
0.1U/16V/X5R/4 C143 0.1U/16V/X5R/4 C142 + EC71 270U/2.5V/SP/7343 V1.05S_VTT_C6
A9 B9 E13 E14 F13 F14 V10
VCCP_A9 VCCP_B9 VCCPC6_E13 VCCPC6_E14 VCCPC6_F13 VCCPC6_F14 VCCPC6_V10
C
C9 D9 E9 F8 F9 G8 G14 H8 H14 J8 J14 K8 K14 L8 L14 M8 M14 N8 N14 P8 P14 R8 R14 T8 T14 U8 U9 U10 U11 U12 U13 U14
VCCP_C9 VCCP_D9 VCCP_E9 VCCP_F8 VCCP_F9 VCCP_G8 VCCP_G14 VCCP_H8 VCCP_H14 VCCP_J8 VCCP_J14 VCCP_K8 VCCP_K14 VCCP_L8 VCCP_L14 VCCP_M8 VCCP_M14 VCCP_N8 VCCP_N14 VCCP_P8 VCCP_P14 VCCP_R8 VCCP_R14 VCCP_T8 VCCP_T14 VCCP_U8 VCCP_U9 VCCP_U10 VCCP_U11 VCCP_U12 VCCP_U13 VCCP_U14
VCC_A10 VCC_A11 VCC_A12 VCC_B10 VCC_B11 VCC_B12 VCC_C10 VCC_C11 VCC_C12 VCC_D10 VCC_D11 VCC_D12 VCC_E10 VCC_E11 VCC_E12 VCC_F10 VCC_F11 VCC_F12 VCC_G10 VCC_G11 VCC_G12 VCC_H10 VCC_H11 VCC_H12 VCC_J10 VCC_J11 VCC_J12 VCC_K10 VCC_K11 VCC_K12 VCC_L10 VCC_L11 VCC_L12 VCC_M10 VCC_M11 VCC_M12 VCC_N10 VCC_N11 VCC_N12 VCC_P10 VCC_P11 VCC_P12 VCC_R10 VCC_R11 VCC_R12 VCCA
+1.5V R591 +1_5VCCA C487 0.1U/16V/X5R/4 C486 0/4
0.1U/16V/X5R/4
B
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCC_SENSE VSS_SENSE
3 OF 4
REMOVE WHEN POWERME PLUGGED IN Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4 ohms with 18 mil trace, 7 mil vccsense to vsssense spacing 25 mil spacing from others. Place PU and PD within 1 inch of CPU Tune like differential signal and equal length
A
5
w
w w
la .
4
to p
R143 100/4/1 0/4 0/4 R148 100/4/1
VCCSENSE VSSSENSE
-s p
+ 34 34
EC73 270U/2.5V/SP/7343
h c
m e
ic t a
.c s
m o
D
C
B
4 OF 4
A
Title Size B Date:
3 2
Intel
Silverthorne CPU-2
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 5 of 35
5
4
3
2
1
POULSBO_XL_CUST
U37A 4 H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 AG6 AJ5 AG5 AG3 AH1 AG7 AE2 AH7 AJ7 AG4 AE3 AG1 AG8 AG2 AJ6 AJ8 AL3 AJ3 AL5 AN4 AJ4 AK1 AJ1 AK6 AL4 AL6 AN2 AM6 AP4 AJ2 AN3 AM1 AL11 AL12 AR10 AN12 AT11 AM12 AM14 AT10 AL13 AN14 AP10 AT12 AP12 AK12 AP14 AT13 AT7 AN6 AT5 AM8 AL8 AT6 AT9 AP8 AN10 AL7 AM10 AL10 AT8 AR8 AK10 AN8 H_D0 H_D1 H_D2 H_D3 H_D4 H_D5 H_D6 H_D7 H_D8 H_D9 H_D10 H_D11 H_D12 H_D13 H_D14 H_D15 H_D16 H_D17 H_D18 H_D19 H_D20 H_D21 H_D22 H_D23 H_D24 H_D25 H_D26 H_D27 H_D28 H_D29 H_D30 H_D31 H_D32 H_D33 H_D34 H_D35 H_D36 H_D37 H_D38 H_D39 H_D40 H_D41 H_D42 H_D43 H_D44 H_D45 H_D46 H_D47 H_D48 H_D49 H_D50 H_D51 H_D52 H_D53 H_D54 H_D55 H_D56 H_D57 H_D58 H_D59 H_D60 H_D61 H_D62 H_D63 H_A3 H_A4 H_A5 H_A6 H_A7 H_A8 H_A9 H_A10 H_A11 H_A12 H_A13 H_A14 H_A15 H_A16 H_A17 H_A18 H_A19 H_A20 H_A21 H_A22 H_A23 H_A24 H_A25 H_A26 H_A27 H_A28 H_A29 H_A30 H_A31 H_ADS H_ADSTB0 H_ADSTB1 H_GVREF H_BNR H_BPRI H_BREQ0 H_CPURST H_CGVREF H_CLKINN H_CLKINP H_DBSY H_DEFER H_DINV0 H_DINV1 H_DINV2 H_DINV3 H_DPWR H_DRDY H_DSTBN0 H_DSTBN1 H_DSTBN2 H_DSTBN3 H_DSTBP0 H_DSTBP1 H_DSTBP2 H_DSTBP3 AA4 U1 Y7 AA7 W7 AA5 U2 W3 V7 W4 W2 W5 V1 W1 T1 U8 U6 P1 U4 R8 R3 T7 U7 U5 R1 R7 R5 R4 R6 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_A#[31:3] 4
D
Separate GVREF and CGVREF by 15 mils for stripline and 16 mils for microstrip. Try to place C52 and C53 close to the pin even if the resistors can be
R99 VCCP
C
HGVREF 1K/4/1 R91 2K/4/1
R102 VCCP 1K/4/1 HCGVREF R95 1K/4/1
HOST
AC4 W6 R2 N5 HGVREF AC2 AC7 AA1 N2 N4 HCGVREF K1 L1 AD1 AA2 AF7 H_DINV#0 AK8 H_DINV#1 AR12 H_DINV#2 AL9 H_DINV#3 AR4 AA3 AF1 H_DSTBN#0 AL2 H_DSTBN#1 AR14 H_DSTBN#2 AR6 H_DSTBN#3 AE1 H_DSTBP#0 AL1 H_DSTBP#1 AT14 H_DSTBP#2 AP6 H_DSTBP#3 AD7 AB1 AC5 Y1 W8 U3 AA6 AA8 AC3 AE4 AC6 AC8 AC1
4 4 4 4 4 4 4
VCCP
R89 221/4/1
B
H_SWING R98 100/4/1 C95 0.1U/16V/X5R/4
Note: H_PLLMON1 are for internal validation purposes only can be left as NC.
VCCP
4 4 4 4
VCCP R211
A
4 H_THERMTRIP#
AE8 H_NMI R84 0/4 H_SMI#_R N1 H_SMI# R106 24.9/4/1 H_PBE#_R P7 H_PBE# H_SWING N6 56/4/1 AE7 H_STPCLK# R587 H_TESTIN#_R AR15 R87 H_RCOMPO N3 24.9/4/1 AL15 R198 121/4/1 PM_THRMTRIP# 24.9/4/1 AE5 4 H_INIT# AE6 4 H_INTR
5
w w
. w
H_INIT H_INTR
H_NMI H_SMI H_PBE H_SWING H_STPCLK H_TESTIN H_RCOMPO H_THRMTRIP
p la
1 OF 10
to
H_HIT H_HITM H_LOCK H_REQ0 H_REQ1 H_REQ2 H_REQ3 H_REQ4 H_RS0 H_RS1 H_RS2 H_CPUSLP H_TRDY
-s p
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 N7 AB7 AN15 F14 A19 D14 H_PWRGD H_DPRSTP#_R
CLK_SCH_BCLK# 16 CLK_SCH_BCLK 16 H_DBSY# 4 H_DEFER# 4 H_DINV#0 4 H_DINV#1 4 H_DINV#2 4 H_DINV#3 4 H_DPWR# 4 H_DRDY# 4 H_DSTBN#0 4 H_DSTBN#1 4 H_DSTBN#2 4 H_DSTBN#3 4 H_DSTBP#0 4 H_DSTBP#1 4 H_DSTBP#2 4 H_DSTBP#3 4 H_HIT# H_HITM# H_LOCK# 4 4 4
h c
4 4 4 4 4 4 0/4 12 12 16 R201
m e
4 R101 4.7K/4 H_PWRGD 4 4,34
ic t a
.c s
m o
D
C
B
H_REQ#[4:0]
VCC3
H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# H_TRDY# H_DPSLP#
H_CPUPWRGD H_DPSLP H_DPRSTP CFG0 CFG1 BSEL2
H_DPRSTP#
SCH_BSEL0 SCH_BSEL1 SCH_BSEL2
A
Title Size B Date: Document Number
Intel
Poulsbo-1 Host Bus
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 6 of 35
4
3
2
5
4
3
2
1
POULSBO_XL_CUST
U37B 17,21,24,25 17,21,24,25 17,21,24,25 17,21,24,25 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 R135 R139 R507 R518 R118 R121 22/4 22/4 22/4 22/4 10K/4 8.2K/4 CLK_LPC_0 CLK_LPC_1 CLK_LPC_2 G23 G24 G19 G26 G22 A20 A22 G20 E21 G25 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLKOUT0 LPC_CLKOUT1 LPC_CLKOUT2 LPC_CLKRUN LPC_SERIRQ LPC_FRAME L_BKLTCTL L_BKLTEN L_CTLA_CLK L_CTLB_DATA L_DDCCLK L_DDCDATA L_VDDEN
LVDS RTC LPC BUS
SCH internal VR enable strap for +V1.5 & +V1.05 VRs
RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13 RESERVED14 RESERVED15 RESERVED16 RESERVED17 RESERVED18 RESERVED19 RESERVED20 RESERVED21 RTC_X1 RTC_X2 INTVRMEN RTCRST EXTTS PWROK SLPRDY DPRSLPVR SLPMODE F30 A18 AJ21 AG21 AK14 AL14 W30 V29 H27 J26 U28 R26 T27 R24 T23 T25 U25 B12 F7 D12 B14 A32 A31 G28 G30 B18 D31 All_PWROK C33 PM_SLPRDY#_R B19 E31 F28 E16 B16 W32 V31 AA30 Y29 W34 V33 AA36 Y35 PM_DPRSLPVR_R PM_SLPMODE PM_RSMRST#_R
INTVRMEN
RESERVED1 12
Enable (default) Disable
RTC Reset Clear RTC Keep RTC SLPRDY# 0 0
MISC SIGNALS
D
16,21 PCLK_TPM 17 CLK_LPC_FWH 24 LPC_SIO 25 LPC_PCID 21 LPC_CLKRUN VCC3 21,24 LPC_SERIRQ VCC3
17,21,24,25 LPC_FRAME# 23 23 LCD ADJ L_BKLTEN
All_PWROK
R153
10K/4
12P/50V/NPO/6 12P/50V/NPO/6 C455 C435 C449 CLK_LPC_FWH LPC_SIO LPC_PCID
23
L_VDDEN 23 23 23 23 23 23 23 23 23 23
R120100/6 G18 G17 L_CLKCTLA A15 L_CLKCTLB G13 L_DDC_CLK G15 L_DDC_DATA E14 D16 LA_CLKP LA_CLKN R32 P31 U34 T35 T29 P33 T33 U36 U30 R34 D6 B4 E12 D8 F8 C12 E10 C4 A13 E6 A7 C14 A6 E8 B6 C6 B8 G10 A14 C8 G12 F10 D10 G8 A8 A5 G11 A10 A12 G9 A9 A11 F12 B10 G6
PM_SLPRDY#_R R157 0/4
PM_SLPRDY#
17
LA_CLKP LA_CLKN LA_DATAN0 LA_DATAN1 LA_DATAN2 LA_DATAN3 LA_DATAP0 LA_DATAP1 LA_DATAP2 LA_DATAP3 SD0_CD SD0_CLK SD0_CMD SD0_LED SD0_WP SD0_PWR SD0_DATA0 SD0_DATA1 SD0_DATA2 SD0_DATA3 SD1_CD SD1_CLK SD1_CMD SD1_LED SD1_WP SD1_PWR SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD2_CD SD2_CLK SD2_CMD SD2_LED SD2_WP SD2_PWR SD2_DATA0 SD2_DATA1 SD2_DATA2 SD2_DATA3 SD2_DATA4 SD2_DATA5 SD2_DATA6 SD2_DATA7 XOR_TEST
12P/50V/NPO/6 CAD NOTE: Place all series resistors near the SCH and place all 10 pF caps near farthest component clocked by the LPC bus (For EV testing)
SYSTEM MGMT
LA_DATAN0 LA_DATAN1 LA_DATAN2 LA_DATAN3 LA_DATAP0 LA_DATAP1 LA_DATAP2 LA_DATAP3 SLOT0_CD# SLOT0_CMD
RTC_X1 RTC_X2 SCH_INTVRMEN RTC_RST#
BAT3V 1
JP12 1 2 3
R524
10K/6
V3.3A_RTC C200 1U/6.3V/X5R/4
PM_EXTTS# All_PWROK R512 0/4
14 17
(open)
PH3Px1/2.54mm
C
PM_SLPMODE 17 R155 0/4
RSMRST SDVO_CTRLCLK SDVO_CTRLDATA SDVOB_CLK SDVOB_CLK SDVOB_INT SDVOB_INT SDVOB_STALL SDVOB_STALL SDVOB_TVCLKIN SDVOB_TVCLKIN SDVOB_RED SDVOB_RED SDVOB_GREEN SDVOB_GREEN SDVOB_BLUE SDVOB_BLUE PCIE_PERN1 PCIE_PERP1 PCIE_PETN1 PCIE_PETP1 PCIE_PERN2 PCIE_PERP2 PCIE_PETN2 PCIE_PETP2
SDIO / MMC
21 21 21 21 21 21 SLOT1_DATA[3:0]
B
SLOT1_CD# SLOT1_CLK SLOT1_CMD SLOT1_WP SD1PWR#
SDVO
R108 48.7/6/1 R438 48.7/6/1
SLOT1_CD# SLOT1_R_CLK SLOT1_R_CMD SLOT1_WP SD1PWR# SLOT1_R_DATA0 SLOT1_R_DATA1 SLOT1_R_DATA2 SLOT1_R_DATA3 SLOT2_CD# SLOT2_R_CLK SLOT2_R_CMD SLOT2_WP SD2PWR# SLOT2_R_DATA0 SLOT2_R_DATA1 SLOT2_R_DATA2 SLOT2_R_DATA3 SLOT2_R_DATA4 SLOT2_R_DATA5 SLOT2_R_DATA6 SLOT2_R_DATA7
SLOT1_DATA0 SLOT1_DATA1 SLOT1_DATA2 SLOT1_DATA3 SLOT2_CD# SLOT2_CLK SLOT2_CMD SLOT2_WP SD2PWR#
R80 R81 R495 R88
48.7/6/1 48.7/6/1 48.7/6/1 48.7/6/1
21 21 21 21 21 21 SLOT2_DATA[7:0]
R71 R72
48.7/6/1 48.7/6/1
SLOT2_DATA0 SLOT2_DATA1 SLOT2_DATA2 SLOT2_DATA3 SLOT2_DATA4 SLOT2_DATA5 SLOT2_DATA6 SLOT2_DATA7
R86 R476 R492 R75 R471 R486 R77 R466
48.7/6/1 48.7/6/1 48.7/6/1 48.7/6/1 48.7/6/1 48.7/6/1 48.7/6/1 48.7/6/1
A
5
w w
. w
CG1 CG2
C458 18P/50V/COG/6
p la
RTC_X1
4
2 OF 10
to
PCIE
-s p
AA34 Y33 AA32 Y31 W36 V35 PCIE_CLKINN PCIE_CLKINP PCIE_ICOMPI PCIE_ICOMPO AB35 AC36 AD35 AE36
TP3 Test Point SDVO_TVCLKIN TP15 SDVO_TVCLKIN# TP11
h c
PEG_COMP R622
SDVO_CTRLCLK 22 SDVO_CTRLDATA 22 SDVO_CLK 22 SDVO_CLK# 22 SDVOB_Int+ 22 SDVOB_Int22 Test Point Test Point 22 22 22 22 22 22
m e
PM_DPRSLPVR 34 SCH_RSMRST# TP2 Test Point V1.5S_PCIE_SCH 24.9/4/1
R182 51/6
CMOS Clear
R146 0/4
(open)
MMBT3906/SOT-23 Q40 E 1 3 BAV99/SOT-23 2 D34 1 BAV99/SOT-23 3 2 R725 2.2K/6 VCC3 L_DDC_DATA R105 R115 R490 R104 10K/4 10K/4 4.7K/4 4.7K/4
B
17,24 PM_RSMRST# R726 4.7K/6 3VSB
C D33 B
SDVO_RED SDVO_RED# SDVO_GREEN SDVO_GREEN# SDVO_BLUE SDVO_BLUE#
AC34 AB33 AE34 PCIE_TXN2_SLOT0_C C243 0.047U/16V/X7R/4 AD33 PCIE_TXP2_SLOT0_C C240 0.047U/16V/X7R/4 AB29 AC30 AD31 PCIE_TXN2_SLOT1_C C244 0.047U/16V/X7R/4 AE32 PCIE_TXP2_SLOT1_C C250 0.047U/16V/X7R/4
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 PCIE_RX2PCIE_RX2+ PCIE_TX2PCIE_TX2+
17 17 17 17 28 28 28 28
VCC3 R82 R94 10K/4 SLOT0_CD#
L_DDC_CLK L_CLKCTLA L_CLKCTLB
39.2K/4/1 SLOT0_CMD
VCC3 R85 47K/6 SD1PWR# SLOT1_CD# SLOT1_CMD SLOT1_WP
VCC3 R448 47K/6 R97 R70 10K/4 20K/4 SD2PWR# SLOT2_CD# SLOT2_CMD SLOT2_WP
CLK_PCIE_IN# 16 CLK_PCIE_IN 16
R436 10K/4 R422 20K/4
R532 10M/6/1 RTC_X2
Route PEG_COMP less than 250 milliohm trace impedance.
R76
10K/4
R459 10K/4
X1 32.768KHz/20ppm 1 2 C450 18P/50V/COG/6
Title Size B Date:
3 2
Intel
Poulsbo-2 RTC/LPC/PCIE/LVDS
Document Number
Note: The ground trace of C450, C458 and X1 have to be close asap
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
+ +
ic t a
V3.3A_RTC R188 20K/6/1 3VBT
R197 3 1 BAT_3V C212 1U/6.3V/X5R/4 1K/6 BAT54C/SOT-23
.c s
0 D12 3VSB 2
J1 Shunt Open 1-X (Default)
SLPMODE 1
m o
1 STUFF UNSTUFF
STATE SCH ready to enter S3 SCH ready to enter S4/S5 2
R117
R118
UNSTUFF STUFF
D
BAT1
3
C
SCH_RSMRST# R149 10K/4
A
Rev Z000 7 of 35
5
4
3
2
1
POULSBO_XL_CUST
U37C R170 510/4/1 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB_PN7 USB_PP7 N32 M31 N34 M33 N36 M35 L32 K31 L36 K35 K33 L34 H35 J36 H33 J34 K29 R30 L30 M29 J30 H29 P29 N30 R36 P35 C27 E27 B29 A29 A28 D27 F29 E29 D29 C29 F27 B27 E25 A26 B25 F25 A24 D23 B23 C23 A23 E23 F23 A25 C25 D25 A27 USB_DN0 USB_DP0 USB_DN1 USB_DP1 USB_DN2 USB_DP2 USB_DN3 USB_DP3 USB_DN4 USB_DP4 USB_DN5 USB_DP5 USB_DN6 USB_DP6 USB_DN7 USB_DP7 USB_OC0 USB_OC1 USB_OC2 USB_OC3 USB_OC4 USB_OC5 USB_OC6 USB_OC7 USB_RBIASN USB_RBIASP PATA_DDREQ PATA_IORDY PATA_IDEIRQ PATA_DDACK PATA_DIOW PATA_DIOR PATA_DCS3 PATA_DCS1 PATA_DA2 PATA_DA1 PATA_DA0 PATA_DD15 PATA_DD14 PATA_DD13 PATA_DD12 PATA_DD11 PATA_DD10 PATA_DD9 PATA_DD8 PATA_DD7 PATA_DD6 PATA_DD5 PATA_DD4 PATA_DD3 PATA_DD2 PATA_DD1 PATA_DD0
PATA / IDE
D
Client USB
TRST TMS TDI TDO TCK STPCPU RSTRDY RESET RSTWARN GPIOSUS0 GPIOSUS1 GPIOSUS2 GPIOSUS3 WAKE SMI THRM GPE GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 SPKR HDA_CLK HDA_SYNC HDA_RST HDA_SDI0 HDA_SDI1 HDA_SDO HDA_DOCKEN HDA_DOCKRST
F33 JTAG_TRST# R159 G32 R171 D33 R168 G34 R162 E34 G16 B33 AF35 C34 G36 E32 F31 J28 C31 C16 C18 D35 F16 A17 C19 D19 D21 B21 A21 E18 E19 G14 C21 E1 E2 D5 F5 E4 G4 F3 D3
VCCP 39/4 150/4/1 51/6/1 27.4/4/1
PLACE XDP (TDO AND TCK ONLY)RESISTORS CLOSE TO POULSBO
C120
C114 0.1U/16V/X5R/4
SCH_GPIO_8
PM_RSTRDY#_R R537 100/4 GPIOSUS_0 GPIOSUS_1 GPIOSUS_3 WAKE# R164 1K/4 LPC_PME# SCH_GPIO_0 CRB_DET# FWH_MFG_MODE SCH_GPIO_3 SCH_GPIO_4 SCH_GPIO_6 SLPIOVR# SCH_GPIO_8 LAN_ISOLATE
SYSTEM GPIO
USB2.0 USB2.0
18 VCC3 R116 FWH_MFG_MODE 10K/4 R112 0/4
C
PM_RSTRDY# 17 RST# 17 PM_RSTWARN 17 GPIOSUS_0 26 GPIOSUS_1 26 PM_PWRBTN# 17,24 GPIOSUS_3 18 3VSB LPC_SMI# PM_THRM# LPC_PME# 24 19,24 24
Q10 SMBT3904/SOT-23
BSCH_GPIO8_N
SCH_GPIO8_GATE
PM_STPCPU# 16
C
0.1U/16V/X5R/4
USB_OC#0 USB_OC#2 USB_OC#4 USB_OC#6 R588 USB_RBIAS_PN 22.6/4/1 19,20 19,20 19,20 19,20 19,20 19,20 19,20 19,20 IDE_PDDREQ IDE_PDIORDY INT_IRQ14 IDE_PDDACK# IDE_PDIOW# IDE_PDIOR# IDE_PDCS3# IDE_PDCS1# USB_OC#2
18 18 18
R497 1K/4 FWH_TBL# SLPIOVR# 17
B
Poulsbo strapping table
VCC3
IDE_PDA2 19,20 IDE_PDA2 IDE_PDA1 19,20 IDE_PDA1 IDE_PDA0 19,20 IDE_PDA0 19,20 IDE_PDD[15:0] IDE_PDD15 IDE_PDD14 IDE_PDD13 IDE_PDD12 IDE_PDD11 IDE_PDD10 IDE_PDD9 IDE_PDD8 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0
HD AUDIO
LAYOUT NOTE: Place R(RBIAS) within 500 mils of SCH. Route this trace microstrip, 4 mils wide and 6 mils from other signals
R111 1K/4
R504 1K/4
3
SCH_GPIO_3 SCH_GPIO_0
2
VCC3
A
A
CMC Base Address
SCH_GPIO_3 0 0 1 1 SCH_GPIO_0 0 1 0 1 Address 0xFFFB0000 0xFFFC0000 0xFFFD0000 (Default) 0xFFFE0000
1
R107 1K/4
R509 1K/4
5
w w
. w
p la
4
to
SMB 3 OF 10
HDA_SDATAIN1 HDA_DOCK_EN# HDA_DOCK_RST#
-s p
DA_REFCLKINN DA_REFCLKINP DB_REFCLKINNSSC DB_REFCLKINPSSC CLKREQ CLK14 USB_CLK48 SUSCLK SMB_ALERT SMB_DATA SMB_CLK Test PointTP6 PointTP6 Test PointTP7 PointTP7 Test PointTP5 PointTP5
h c
U32 T31 H31 J32 A16 D18 E36 B31 TP1 Test Point F18 F21 G21
R462 33/4/1 R451 33/4/1 R465 33/4/1
HDA_SDATAIN1 R469 33/4/1 HDA_DOCK_EN# HDA_DOCK_RST#
m e
15 LAN_ISOLATE 28 DREFCLK# DREFCLK DREFSSCLK# DREFSSCLK CLK_SCH_OE# CLK_REF_SCH 16 16 16 16 16 16 SMB_ALERT# SMB_DATA SMB_CLK VCC3 R145 10K/4 R141 10K/4 10K/4 R109
HDA_SPKR 17 HDA_BITCLK 22,27 HDA_SYNC 22,27 HDA_RST# 22,27 HDA_SDATAIN0 27 HDA_SDATAIN1 22 HDA_SDATAOUT 22,27
ic t a
GPE# pin reference Poulsbo_SCH_EDS page 353
.c s
E A 1N4148 C D9
R183 10K/4
USB I/F
Q11
m o
VCC3 R187 10K/4 C R189 B E 1K/4 17,28
JTAG
D
H_PROCHOT# 4,34
SMBT3904/SOT-23
(OPEN)
VCC3
C
R516 R117
10K/4
4.7K/6
WAKE#
PCIE_WAKE#
CLOCK I/F
(OPEN)
SCH_GPIO_6 SCH_GPIO_4 SCH_GPIO_4 R510 22/6 Mute Mute FWH_WP# SPI0_WP# 27
B
R133 22/6 FWH_WP# R138 22/6 SPI0_WP#
17 24
19 14,16,17,19,24,29,31 14,16,17,19,24,29,31 LPC_PME#
(OPEN)
R566 4.7K/6 3VSB
VCC3 R498 300/6 SCH_GPIO_6 C457 0.01U/50V/X7R/6 D27 BAT54S/SOT-23 R513 4.7K/6 ON HOOK 1 2 J22
PH2Px1/2mm
Title Size B Date:
3 2
Intel
Poulsbo-3 USB/AudioIDE/GPIO
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 8 of 35
5
4
3
2
1
POULSBO_XL_CUST
U37D 14 M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AP34 AN33 AT32 AL31 AN35 AK32 AR33 AP32 AR31 AT31 AL29 AN29 AN31 AK30 AM30 AT30 AR29 AT29 AL27 AN27 AK28 AM28 AT28 AR27 AT27 AK26 AN25 AR25 AM26 AP26 AL25 AT25 AM24 AP24 AT23 AK22 AK24 AT24 AL23 AR23 AP22 AT22 AK20 AM20 AM22 AL21 AR21 AT21 AT20 AL19 AM18 AP18 AP20 AN19 AR19 AK18 AL17 AN17 AM16 AP16 AT18 AR17 AK16 AT16 SM_DQ0 SM_DQ1 SM_DQ2 SM_DQ3 SM_DQ4 SM_DQ5 SM_DQ6 SM_DQ7 SM_DQ8 SM_DQ9 SM_DQ10 SM_DQ11 SM_DQ12 SM_DQ13 SM_DQ14 SM_DQ15 SM_DQ16 SM_DQ17 SM_DQ18 SM_DQ19 SM_DQ20 SM_DQ21 SM_DQ22 SM_DQ23 SM_DQ24 SM_DQ25 SM_DQ26 SM_DQ27 SM_DQ28 SM_DQ29 SM_DQ30 SM_DQ31 SM_DQ32 SM_DQ33 SM_DQ34 SM_DQ35 SM_DQ36 SM_DQ37 SM_DQ38 SM_DQ39 SM_DQ40 SM_DQ41 SM_DQ42 SM_DQ43 SM_DQ44 SM_DQ45 SM_DQ46 SM_DQ47 SM_DQ48 SM_DQ49 SM_DQ50 SM_DQ51 SM_DQ52 SM_DQ53 SM_DQ54 SM_DQ55 SM_DQ56 SM_DQ57 SM_DQ58 SM_DQ59 SM_DQ60 SM_DQ61 SM_DQ62 SM_DQ63 SM_BS0 SM_BS1 SM_BS2 SM_CK0 SM_CK1 SM_CK0 SM_CK1 SM_CKE0 SM_CKE1 SM_DQS0 SM_DQS1 SM_DQS2 SM_DQS3 SM_DQS4 SM_DQS5 SM_DQS6 SM_DQS7 SM_MA0 SM_MA1 SM_MA2 SM_MA3 SM_MA4 SM_MA5 SM_MA6 SM_MA7 SM_MA8 SM_MA9 SM_MA10 SM_MA11 SM_MA12 SM_MA13 SM_MA14 SM_VREF SM_RAS SM_CAS SM_WE SM_CS0 SM_CS1 AJ25 AH24 AG32 AM35 AJ19 AM34 AJ18 AL33 AJ33 AM32 AP30 AP28 AT26 AN23 AN21 AT19 AT17 AH26 AG27 AH28 AJ27 AG29 AG28 AG31 AJ31 AJ29 AG30 AG26 AH32 AH30 AG22 AG33 AK35 AG24 AJ23 AG25 AH22 AG23 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_BS0 M_A_BS1 M_A_BS2 14 14 14
D
M_CLK_DDR0 14 M_CLK_DDR1 14 M_CLK_DDR#0 14 M_CLK_DDR#1 14 M_CKE0 M_CKE1 14 14
M_A_DQS[7:0] 14
C
M_A_A[14:0] 14
B
A
5
w w
. w
p la
4 OF 10
SM_RCOMPO
SM_RCVENIN SM_RCVENOUT
to
AG36 AJ36 AH35
-s p
SM_RCOMPOUT MA_RCVENIN MA_RCVENOUT
M_VREF_SCH 14 M_A_RAS# M_A_CAS# M_A_WE# M_CS#0 M_CS#1 14 14
h c
14 14 14 0/4
m e
ic t a
VTT_DDR R626 30.1/6/1
DDR SYSTEM MEMORY
.c s
m o
D
C
LAYOUT NOTE: Min 10mil trace, place R148 as close to pin SM_RCOMPOUT as possible
B
C504 0.1U/16V/X5R/4
R635
Note: Place Resistor within 1" of the SCH pins
A
Title Size B Date: Document Number
Intel
Poulsbo-4 DDR2
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 9 of 35
4
3
2
5
4
3
2
1
POULSBO_XL_CUST
POULSBO_XL_CUST
U37E V1.05S_SCH_VCORE
D
V1.5S_SCH VCC15_J12 VCC15_J13 VCC15_J14 VCC15_J15 VCC15_J16 VCC15_J17 VCC15_J18 VCC15_J19 VCC15_J20 VCC15_J21 VCC15_J22 VCC15_J23 VCC15_J24 VCC15_K13 VCC15_K14 VCC15_K15 VCC15_K16 VCC15_K17 VCC15_K18 VCC15_K19 VCC15_K20 VCC15_K21 VCC15_K22 VCC15_K23 VCC15USB_U23 VCC15USB_U24 VCC15USB_V23 VCC15USB_V24 VCC15USB_W23 VCC15USB_W24 VCC33_H3 VCC33_H5 VCC33_H7 VCC33_J10 VCC33_J4 VCC33_J6 VCC33_J8 VCC33_K11 VCC33_K3 VCC33_K5 VCC33_K7 VCC33_K9 VCC33_L10 VCC33_L4 VCC33_L6 VCC33_L8 VCC33RTC VCC33SUS_L26 VCC33SUS_M25 VCC33SUS_M26 VCC33SUS_M27 VCC33SUS_P27 VCC5REF VCC5REFSUS J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 U23 U24 V23 V24 W23 W24 H3 H5 H7 J10 J4 J6 J8 K11 K3 K5 K7 K9 L10 L4 L6 L8 A30 L26 M25 M26 M27 P27 L25 U27 V3.3_SCH_SUS V1.5S_SCH
VCCHDA M12 N12 +V1.5S_DLVDS_SCH V25 V27 W26 W28 Y27 V3.3_SCH_SUS N26 P25 R25 V1.5S_PCIE_SCH AC28 AD26 AD27 AD28 AD29 AE25 AE26 AE27 AE28 AE29 AE30 +V1.5S_SDVO_SCH AA25 AA26 AB25 AB26 AB27 AC25
U37G VCCHDA_M12 VCCHDA_N12 VCCSM_AD12 VCCSM_AD13 VCCSM_AD14 VCCSM_AD15 VCCSM_AD16 VCCSM_AD17 VCCSM_AD18 VCCSM_AD19 VCCSM_AD20 VCCSM_AD21 VCCSM_AD22 VCCSM_AD23 VCCSM_AD24 VCCSM_AE12 VCCSM_AE13 VCCSM_AE14 VCCSM_AE15 VCCSM_AE16 VCCSM_AE17 VCCSM_AE18 VCCSM_AE19 VCCSM_AE20 VCCSM_AE21 VCCSM_AE22 VCCSM_AE23 VCCSM_AF12 VCCSM_AF15 VCCSM_AF18 VCCSM_AF19 VCCSM_AG12 VCCSM_AG13 VCCSM_AG15 VCCSM_AG18 VCCSM_AG19 VCCSM_AH12 VCCSM_AH13 VCCSM_AH14 VCCSM_AH15 VCCSM_AH16 VCCSM_AH17 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AF12 AF15 AF18 AF19 AG12 AG13 AG15 AG18 AG19 AH12 AH13 AH14 AH15 AH16 AH17 V1.8_SM_SCH
C
B
A
AA12 AA13 AA15 AA17 AA19 AA21 AA23 AA24 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 M13 M14 M15 M17 M18 M19 M21 M22 M23 N13 N15 N17 N19 N21 N23 P13 P15 P17 P19 P21 P23 R12 R13 R15 R17 R19 R21 R23 T13 T15 T17 T19 T21 U12 U13 U15 U17 U19 U21 V13 V15 V17 V19 V21 W12 W13 W15 W17 W19 W21 Y13 Y15 Y17 Y19 Y21 Y23
VCC_AA12 VCC_AA13 VCC_AA15 VCC_AA17 VCC_AA19 VCC_AA21 VCC_AA23 VCC_AA24 VCC_AB13 VCC_AB14 VCC_AB15 VCC_AB16 VCC_AB17 VCC_AB18 VCC_AB19 VCC_AB20 VCC_AB21 VCC_AB22 VCC_AB23 VCC_M13 VCC_M14 VCC_M15 VCC_M17 VCC_M18 VCC_M19 VCC_M21 VCC_M22 VCC_M23 VCC_N13 VCC_N15 VCC_N17 VCC_N19 VCC_N21 VCC_N23 VCC_P13 VCC_P15 VCC_P17 VCC_P19 VCC_P21 VCC_P23 VCC_R12 VCC_R13 VCC_R15 VCC_R17 VCC_R19 VCC_R21 VCC_R23 VCC_T13 VCC_T15 VCC_T17 VCC_T19 VCC_T21 VCC_U12 VCC_U13 VCC_U15 VCC_U17 VCC_U19 VCC_U21 VCC_V13 VCC_V15 VCC_V17 VCC_V19 VCC_V21 VCC_W12 VCC_W13 VCC_W15 VCC_W17 VCC_W19 VCC_W21 VCC_Y13 VCC_Y15 VCC_Y17 VCC_Y19 VCC_Y21 VCC_Y23
VCCLVDS_V25 VCCLVDS_V27 VCCLVDS_W26 VCCLVDS_W28 VCCLVDS_Y27
VCCP33USBSUS_N26 VCCP33USBSUS_P25 VCCP33USBSUS_R25
VCCPCIE_AC28 VCCPCIE_AD26 VCCPCIE_AD27 VCCPCIE_AD28 VCCPCIE_AD29 VCCPCIE_AE25 VCCPCIE_AE26 VCCPCIE_AE27 VCCPCIE_AE28 VCCPCIE_AE29 VCCPCIE_AE30
V3.3S_SCH
V1.5S_DPLLA_SCH V1.5S_DPLLB_SCH
V3.3A_RTC
V1.5S_HPLL_SCH
VCCS_5REF_SCH
VCC_5REFSUS_SCH
5 OF 10
5
w
w w
la .
4
to p
V3.3S_APCIEBG_SCH
V1.5S_PCIEPLL_SCH
V1.5S_AUSBPLL_SCH
-s p
V26 Y26 AC11 AD11 AB31 AA28 V3.3_SCH_SUS U26 W27
h c
VCCADPLLA VCCADPLLB VCCAHPLL VCCDHPLL VCCAPCIEBG VCCAPCIEPLL VCCAUSBBGSUS VCCAUSBPLL
VCCSDVO_AA25 VCCSDVO_AA26 VCCSDVO_AB25 VCCSDVO_AB26 VCCSDVO_AB27 VCCSDVO_AC25
m e
VTT_AA10 VTT_AB10 VTT_AB11 VTT_AB9 VTT_AC10 VTT_AD10 VTT_AD9 VTT_AE10 VTT_AF10 VTT_AF9 VTT_AG10 VTT_AH10 VTT_M9 VTT_N10 VTT_P10 VTT_P11 VTT_P9 VTT_R10 VTT_T10 VTT_T11 VTT_T9 VTT_U10 VTT_V10 VTT_V11 VTT_V9 VTT_W10 VTT_Y10 VTT_Y11 VTT_Y9
ic t a
V1.05S_VTT_SCH
.c s
AA10 AB10 AB11 AB9 AC10 AD10 AD9 AE10 AF10 AF9 AG10 AH10 M9 N10 P10 P11 P9 R10 T10 T11 T9 U10 V10 V11 V9 W10 Y10 Y11 Y9
6 OF 10
C32 C35 C36 C5 C7 C9 D1 D11 D13 D15 D17 D2 D20 D22 D24 D26 D28 D30 D32 D34 D36 D4 D7 D9 E11 E13 E15 E17 E20 E22 E24 E26 E28 E3 E30 E33 E35 E5 E7 E9 F1 F11 F13 F15 F17 F19 F2 F20 F22 F24 F26 F32 F34 F35 F36 F4 F6 F9 G1 G2 G27 G29 G3 G31 G33 G35 G5 G7 H1 H10 H11 H12 H13 N24
VSS_C32 VSS_C35 VSS_C36 VSS_C5 VSS_C7 VSS_C9 VSS_D1 VSS_D11 VSS_D13 VSS_D15 VSS_D17 VSS_D2 VSS_D20 VSS_D22 VSS_D24 VSS_D26 VSS_D28 VSS_D30 VSS_D32 VSS_D34 VSS_D36 VSS_D4 VSS_D7 VSS_D9 VSS_E11 VSS_E13 VSS_E15 VSS_E17 VSS_E20 VSS_E22 VSS_E24 VSS_E26 VSS_E28 VSS_E3 VSS_E30 VSS_E33 VSS_E35 VSS_E5 VSS_E7 VSS_E9 VSS_F1 VSS_F11 VSS_F13 VSS_F15 VSS_F17 VSS_F19 VSS_F2 VSS_F20 VSS_F22 VSS_F24 VSS_F26 VSS_F32 VSS_F34 VSS_F35 VSS_F36 VSS_F4 VSS_F6 VSS_F9 VSS_G1 VSS_G2 VSS_G27 VSS_G29 VSS_G3 VSS_G31 VSS_G33 VSS_G35 VSS_G5 VSS_G7 VSS_H1 VSS_H10 VSS_H11 VSS_H12 VSS_H13 VSS_N24
m o
POULSBO_XL_CUST
U37F
VSS_H14 VSS_H15 VSS_H16 VSS_H17 VSS_H18 VSS_H19 VSS_H2 VSS_H20 VSS_H21 VSS_H22 VSS_H23 VSS_H24 VSS_H25 VSS_H26 VSS_H28 VSS_H30 VSS_H32 VSS_H34 VSS_H36 VSS_H4 VSS_H6 VSS_H8 VSS_H9 VSS_J1 VSS_J11 VSS_J2 VSS_J25 VSS_J27 VSS_J29 VSS_J3 VSS_J31 VSS_J33 VSS_J35 VSS_J5 VSS_J7 VSS_J9 VSS_K10 VSS_K12 VSS_K2 VSS_K24 VSS_K25 VSS_K26 VSS_K27 VSS_K28 VSS_K30 VSS_K32 VSS_K34 VSS_K36 VSS_K4 VSS_K6 VSS_K8 VSS_L11 VSS_L12 VSS_L13 VSS_L14 VSS_L15 VSS_L16 VSS_L17 VSS_L18 VSS_L19 VSS_L2 VSS_L20 VSS_L21 VSS_L22 VSS_L23 VSS_L24 VSS_L27 VSS_L28 VSS_L29 VSS_L3 VSS_L31 VSS_L33 VSS_L35 VSS_P24
H14 H15 H16 H17 H18 H19 H2 H20 H21 H22 H23 H24 H25 H26 H28 H30 H32 H34 H36 H4 H6 H8 H9 J1 J11 J2 J25 J27 J29 J3 J31 J33 J35 J5 J7 J9 K10 K12 K2 K24 K25 K26 K27 K28 K30 K32 K34 K36 K4 K6 K8 L11 L12 L13 L14 L15 L16 L17 L18 L19 L2 L20 L21 L22 L23 L24 L27 L28 L29 L3 L31 L33 L35 P24
D
C
B
9 OF 10
A
Title Size B Date:
3 2
Intel
Poulsbo-5 Chipset Power 1
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 10 of 35
5
4
3
2
1
All decoupling should be placed on the backside
VCCP R200 0.1U/16V/X5R/4 0.1U/16V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 2.2U/10V/X5R/6 10U/6.3V/X5R/8 10U/6.3V/X5R/8
10U/6.3V/X5R/8
EC72 220U/4V/KO/7343
D
+
0/1206 C446 4.7U/6.3V/X5R/6 0.1U/16V/X5R/4 VCCP R511 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4 10U/6.3V/X5R/8 2.2U/10V/X5R/6 10U/6.3V/X5R/8 C132 C168 C159 C116 C196 C127 C113 C144 C125 C158 C123 C122 C169 C211 C176 C160 C138 C147
V1.05S_VTT_SCH
EC70 220U/4V/KO/7343
+
0/1206 C447 4.7U/6.3V/X5R/6
C126
C112
C153 1U/6.3V/X5R/4
C121
C161 1U/6.3V/X5R/4
C118
C139 1U/6.3V/X5R/4
C110
C130 1U/6.3V/X5R/4
C108
C173
C439
C437
C448 10U/6.3V/X5R/8
1U/6.3V/X5R/4
10U/6.3V/X5R/8
+1.5V
R232
V1.5S_SCH 1U/6.3V/X5R/4 1U/6.3V/X5R/4 1U/6.3V/X5R/4
VCCP
R517
V1.05S_VTT_CPU
0.1U/16V/X5R/4 C456 C443 C171
C
C252 4.7U/6.3V/X5R/6
0/8
0/1206 C111 1U/6.3V/X5R/4 C137 C129 C109 C124 C115 C195 1U/6.3V/X5R/4 0.1U/16V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
0.1U/16V/X5R/4
V1.5S_SCH
R230
V1.5S_PCIE_SCH LAYOUT NOTE: PLACE CAPS NEXT TO CPU PINS AG35 AND AG36 3VSB
R214
0/8 C230 1U/6.3V/X5R/4
C229 1U/6.3V/X5R/4
0/8
V1.5S_SCH
R186
+V1.5S_DLVDS_SCH
B
0/8 C194 1U/6.3V/X5R/4
+1.8V C218 1U/6.3V/X5R/4 C232 4.7U/6.3V/X5R/6
R215
V1.5S_SCH
R228
+V1.5S_SDVO_SCH
0/8 C227 1U/6.3V/X5R/4
C249 1U/6.3V/X5R/4
A
5
w
w w
la .
4
C89 4.7U/6.3V/X5R/6
to p
0/8 VCC3 R90 0/8
1U/6.3V/X5R/4
-s p
1U/6.3V/X5R/4 C216 C210 1U/6.3V/X5R/4 C97 C103
0.1U/16V/X5R/4
h c
C190 1U/6.3V/X5R/4 C199 C187 V3.3S_SCH
0.1U/16V/X5R/4
m e
V3.3_SCH_SUS C180 C215 0.1U/16V/X5R/4 1U/6.3V/X5R/4 C167 C172 VCCHDA C424 1U/6.3V/X5R/4
0.1U/16V/X5R/4 0.1U/16V/X5R/4
ic t a
0.1U/16V/X5R/4 C459 C445 C208 GND_VSSAUSBBGSUS 1U/6.3V/X5R/4 C192 C209 1U/6.3V/X5R/4 R483 0/8
.c s
C188 C162 10U/6.3V/X5R/8 V1.8_SM_SCH C225 1U/6.3V/X5R/4
m o
V1.05S_SCH_VCORE C128 C179 10U/6.3V/X5R/8
D
C442
Place these inside socket cavity on L8 ( North side Secondary)
C
0.1U/16V/X5R/4 C170 0.1U/16V/X5R/4
GND_VSSAUSBBGSUS
B
C217
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
VCC3
(open)
R477 C431 1U/6.3V/X5R/4 0/8 +1.5V
C107 1U/6.3V/X5R/4
C106 1U/6.3V/X5R/4
1U/6.3V/X5R/4
A
Title Size B Date:
3 2
Intel
Poulsbo-6 Decoupling Cap
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 11 of 35
5
4
3
2
1
V1.5S_DPLLA_SCH L6 10uH/0.015A/8 EC60 220U/4V/KO/7343 + C246 0.1U/16V/X5R/4 C235 0.1U/16V/X5R/4 GND_VSSAPCIEBG V1.5S_DPLLB_SCH
D
V3.3S_SCH R217 0/6
V3.3S_APCIEBG_SCH
L4 10uH/0.015A/8 V1.5S_PLLS_SCH EC59 220U/4V/KO/7343
VCC
+ C241 0.1U/16V/X5R/4
VCC3
VCCS_5REF_SCH
R180
10/6
BAT54C/SOT-23 D10 PLACE BOTTOM SIDE OF PCB UNDER SCH
R233
L5 1uH/0.05A/8 C251 10U/6.3V/X5R/8 R227 1/6/1 C248 0.1U/16V/X5R/4 AHPLL AND DHPLL CONNECTED TOGETHER C186 0.1U/16V/X5R/4
0/8
3
V1.5S_SCH
V1.5S_PCIEPLL_SCH
C
V1.5S_HPLL_SCH FB21
5VSB
3VSB VCC_5REFSUS_SCH D13 R83 BAT54C/SOT-23 3 R79 0/6 0/6 VCCP
120Z/3A/1206 C228 22U/6.3V/X5R/8 C226 0.1U/16V/X5R/4 R219 10/6
V1.5S_AUSBPLL_SCH R231 0/6 C253 0.1U/16V/X5R/4 LAYOUT NOTE: Please place C256 near pin VCCA_USBPLL OF Poulsbo
B
C231 0.1U/16V/X5R/4
VCCP
PLACE BOTTOM SIDE OF PCB UNDER SCH
Note: RESERVED0 is for internal use only and may be left unconnected. VCC3
R480 10K/6
RESERVED1
7
R485 10K/6
LPC Clock 0 Buffer Strength
RESERVED1 Value 1 Load (Default) 0 2 Loads 1
(open)
A
5
w w
. w
p la
4
to
FSB 100 133
Note: Clock Frequencies are in Mhz Default Frequency determined by FSB speed Position 1-2 = 1 Position 2-3 = 0
-s p
CFG1 (BSEL1) 0 0
(open)
R491 R494
h c
(open)
0/6 0/6 Gfx_Freq 200 200
SCH_BSEL0_R
R496
m e
R74 10K/6
ic t a
SCH_BSEL0 6 SCH_BSEL1 6
.c s
m o
D
2
1
C
2
1
10K/6
B
Graphics Core Frequency Select
CFG0 (BSEL0) 0 1
A
Title Size B Date:
3 2
Intel
Poulsbo-7 Chipset Power 2
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 12 of 35
5
4
3
2
1
POULSBO_XL_CUST
U37J
POULSBO_XL_CUST POULSBO_XL_CUST
U37H A2 A3 A33 A34 A35 A36 A4 AA11 AA14 AA16 AA18 AA20 AA22 AA27 AA29 AA31 AA33 AA35 AA9 AB12 AB2 AB24 AB28 AB3 AB30 AB32 AB34 AB36 AB4 AB5 AB6 AB8 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC26 AC27 AC29 AC31 AC33 AC35 AC9 AD2 AD25 AD3 AD30 AD32 AD34 AD36 AD4 AD5 AD6 AD8 AE11 AE24 AE31 AE33 AE35 AE9 AF11 AF13 AF14 AF16 VSS_A2 VSS_A3 VSS_A33 VSS_A34 VSS_A35 VSS_A36 VSS_A4 VSS_AA11 VSS_AA14 VSS_AA16 VSS_AA18 VSS_AA20 VSS_AA22 VSS_AA27 VSS_AA29 VSS_AA31 VSS_AA33 VSS_AA35 VSS_AA9 VSS_AB12 VSS_AB2 VSS_AB24 VSS_AB28 VSS_AB3 VSS_AB30 VSS_AB32 VSS_AB34 VSS_AB36 VSS_AB4 VSS_AB5 VSS_AB6 VSS_AB8 VSS_AC12 VSS_AC13 VSS_AC14 VSS_AC15 VSS_AC16 VSS_AC17 VSS_AC18 VSS_AC19 VSS_AC20 VSS_AC21 VSS_AC22 VSS_AC23 VSS_AC24 VSS_AC26 VSS_AC27 VSS_AC29 VSS_AC31 VSS_AC33 VSS_AC35 VSS_AC9 VSS_AD2 VSS_AD25 VSS_AD3 VSS_AD30 VSS_AD32 VSS_AD34 VSS_AD36 VSS_AD4 VSS_AD5 VSS_AD6 VSS_AD8 VSS_AE11 VSS_AE24 VSS_AE31 VSS_AE33 VSS_AE35 VSS_AE9 VSS_AF11 VSS_AF13 VSS_AF14 VSS_AF16 VSS_AF17 VSS_AF2 VSS_AF20 VSS_AF21 VSS_AF22 VSS_AF23 VSS_AF24 VSS_AF25 VSS_AF26 VSS_AF27 VSS_AF28 VSS_AF29 VSS_AF3 VSS_AF30 VSS_AF31 VSS_AF32 VSS_AF33 VSS_AF34 VSS_AF36 VSS_AF4 VSS_AF5 VSS_AF6 VSS_AF8 VSS_AG11 VSS_AG14 VSS_AG16 VSS_AG17 VSS_AG20 VSS_AG34 VSS_AG35 VSS_AG9 VSS_AH11 VSS_AH18 VSS_AH19 VSS_AH2 VSS_AH20 VSS_AH21 VSS_AH23 VSS_AH25 VSS_AH27 VSS_AH29 VSS_AH3 VSS_AH31 VSS_AH33 VSS_AH34 VSS_AH36 VSS_AH4 VSS_AH5 VSS_AH6 VSS_AH8 VSS_AH9 VSS_AJ10 VSS_AJ11 VSS_AJ12 VSS_AJ13 VSS_AJ14 VSS_AJ15 VSS_AJ16 VSS_AJ17 VSS_AJ20 VSS_AJ22 VSS_AJ24 VSS_AJ26 VSS_AJ28 VSS_AJ30 VSS_AJ32 VSS_AJ34 VSS_AJ35 VSS_AJ9 VSS_AK11 VSS_AK13 VSS_AK15 VSS_AK17 AF17 AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF31 AF32 AF33 AF34 AF36 AF4 AF5 AF6 AF8 AG11 AG14 AG16 AG17 AG20 AG34 AG35 AG9 AH11 AH18 AH19 AH2 AH20 AH21 AH23 AH25 AH27 AH29 AH3 AH31 AH33 AH34 AH36 AH4 AH5 AH6 AH8 AH9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ20 AJ22 AJ24 AJ26 AJ28 AJ30 AJ32 AJ34 AJ35 AJ9 AK11 AK13 AK15 AK17 AK19 AK2 AK21 AK23 AK25 AK27 AK29 AK3 AK31 AK33 AK34 AK36 AK4 AK5 AK7 AK9 AL16 AL18 AL20 AL22 AL24 AL26 AL28 AL30 AL32 AL34 AL35 AL36 AM11 AM13 AM15 AM17 AM19 AM2 AM21 AM23 AM25 AM27 AM29 AM3 AM31 AM33 AM36 AM4 AM5 AM7 AM9 AN1 AN11 AN13 AN16 AN18 AN20 AN22 AN24 AN26 AN28 AN30 AN32 AN34 AN36 AN5 AN7 AN9 AP1 AP11 AP13 AP15 AP17 AP19 AP2 AP21 AP23
U37I VSS_AK19 VSS_AK2 VSS_AK21 VSS_AK23 VSS_AK25 VSS_AK27 VSS_AK29 VSS_AK3 VSS_AK31 VSS_AK33 VSS_AK34 VSS_AK36 VSS_AK4 VSS_AK5 VSS_AK7 VSS_AK9 VSS_AL16 VSS_AL18 VSS_AL20 VSS_AL22 VSS_AL24 VSS_AL26 VSS_AL28 VSS_AL30 VSS_AL32 VSS_AL34 VSS_AL35 VSS_AL36 VSS_AM11 VSS_AM13 VSS_AM15 VSS_AM17 VSS_AM19 VSS_AM2 VSS_AM21 VSS_AM23 VSS_AM25 VSS_AM27 VSS_AM29 VSS_AM3 VSS_AM31 VSS_AM33 VSS_AM36 VSS_AM4 VSS_AM5 VSS_AM7 VSS_AM9 VSS_AN1 VSS_AN11 VSS_AN13 VSS_AN16 VSS_AN18 VSS_AN20 VSS_AN22 VSS_AN24 VSS_AN26 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN34 VSS_AN36 VSS_AN5 VSS_AN7 VSS_AN9 VSS_AP1 VSS_AP11 VSS_AP13 VSS_AP15 VSS_AP17 VSS_AP19 VSS_AP2 VSS_AP21 VSS_AP23 VSS_AP25 VSS_AP27 VSS_AP29 VSS_AP3 VSS_AP31 VSS_AP33 VSS_AP35 VSS_AP36 VSS_AP5 VSS_AP7 VSS_AP9 VSS_AR1 VSS_AR11 VSS_AR13 VSS_AR16 VSS_AR18 VSS_AR2 VSS_AR20 VSS_AR22 VSS_AR24 VSS_AR26 VSS_AR28 VSS_AR3 VSS_AR30 VSS_AR32 VSS_AR34 VSS_AR35 VSS_AR36 VSS_AR5 VSS_AR7 VSS_AR9 VSS_AT1 VSS_AT15 VSS_AT2 VSS_AT3 VSS_AT33 VSS_AT34 VSS_AT35 VSS_AT4 VSS_B1 VSS_B11 VSS_B13 VSS_B15 VSS_B17 VSS_B2 VSS_B20 VSS_B22 VSS_B24 VSS_B26 VSS_B28 VSS_B3 VSS_B30 VSS_B32 VSS_B34 VSS_B35 VSS_B36 VSS_B5 VSS_B7 VSS_B9 VSS_C1 VSS_C10 VSS_C11 VSS_C13 VSS_C15 VSS_C17 VSS_C2 VSS_C20 VSS_C22 VSS_C24 VSS_C26 VSS_C28 VSS_C3 VSS_C30 AP25 AP27 AP29 AP3 AP31 AP33 AP35 AP36 AP5 AP7 AP9 AR1 AR11 AR13 AR16 AR18 AR2 AR20 AR22 AR24 AR26 AR28 AR3 AR30 AR32 AR34 AR35 AR36 AR5 AR7 AR9 AT1 AT15 AT2 AT3 AT33 AT34 AT35 AT4 B1 B11 B13 B15 B17 B2 B20 B22 B24 B26 B28 B3 B30 B32 B34 B35 B36 B5 B7 B9 C1 C10 C11 C13 C15 C17 C2 C20 C22 C24 C26 C28 C3 C30
D
C
B
A
7 OF 10
5
w w
. w
p la
4
to
-s p
h c
L5 L7 L9 M1 M10 M11 M16 M2 M20 M24 M28 M3 M30 M32 M34 M36 M4 M5 M6 M7 M8 N11 N14 N16 N18 N20 N22 N25 N27 N28 N29 N31 N33 N35 N8 N9 P12 P14 P16 P18 P2 P20 P22 P26 P28 P3 P30 P32 P34 P36 P4 P5 P6 P8 R11 R14 R16 R18 R20 R22 R27 R28 R29 R31 R33 R35 R9 T12 T14 T16 T18 T2 T20 Y8
VSS_L5 VSS_L7 VSS_L9 VSS_M1 VSS_M10 VSS_M11 VSS_M16 VSS_M2 VSS_M20 VSS_M24 VSS_M28 VSS_M3 VSS_M30 VSS_M32 VSS_M34 VSS_M36 VSS_M4 VSS_M5 VSS_M6 VSS_M7 VSS_M8 VSS_N11 VSS_N14 VSS_N16 VSS_N18 VSS_N20 VSS_N22 VSS_N25 VSS_N27 VSS_N28 VSS_N29 VSS_N31 VSS_N33 VSS_N35 VSS_N8 VSS_N9 VSS_P12 VSS_P14 VSS_P16 VSS_P18 VSS_P2 VSS_P20 VSS_P22 VSS_P26 VSS_P28 VSS_P3 VSS_P30 VSS_P32 VSS_P34 VSS_P36 VSS_P4 VSS_P5 VSS_P6 VSS_P8 VSS_R11 VSS_R14 VSS_R16 VSS_R18 VSS_R20 VSS_R22 VSS_R27 VSS_R28 VSS_R29 VSS_R31 VSS_R33 VSS_R35 VSS_R9 VSS_T12 VSS_T14 VSS_T16 VSS_T18 VSS_T2 VSS_T20 VSS_Y8
m e
10 OF 10
VSS_T22 VSS_T24 VSS_T28 VSS_T3 VSS_T30 VSS_T32 VSS_T34 VSS_T36 VSS_T4 VSS_T5 VSS_T6 VSS_T8 VSS_U11 VSS_U14 VSS_U16 VSS_U18 VSS_U20 VSS_U22 VSS_U29 VSS_U31 VSS_U33 VSS_U35 VSS_U9 VSS_V12 VSS_V14 VSS_V16 VSS_V18 VSS_V2 VSS_V20 VSS_V22 VSS_V28 VSS_V3 VSS_V30 VSS_V32 VSS_V34 VSS_V36 VSS_V4 VSS_V5 VSS_V6 VSS_V8 VSS_W11 VSS_W14 VSS_W16 VSS_W18 VSS_W20 VSS_W22 VSS_W25 VSS_W29 VSS_W31 VSS_W33 VSS_W35 VSS_W9 VSS_Y12 VSS_Y14 VSS_Y16 VSS_Y18 VSS_Y2 VSS_Y20 VSS_Y22 VSS_Y24 VSS_Y25 VSS_Y28 VSS_Y3 VSS_Y30 VSS_Y32 VSS_Y34 VSS_Y36 VSS_Y4 VSS_Y5 VSS_Y6 VSS_AT36
ic t a
T22 T24 T28 T3 T30 T32 T34 T36 T4 T5 T6 T8 U11 U14 U16 U18 U20 U22 U29 U31 U33 U35 U9 V12 V14 V16 V18 V2 V20 V22 V28 V3 V30 V32 V34 V36 V4 V5 V6 V8 W11 W14 W16 W18 W20 W22 W25 W29 W31 W33 W35 W9 Y12 Y14 Y16 Y18 Y2 Y20 Y22 Y24 Y25 Y28 Y3 Y30 Y32 Y34 Y36 Y4 Y5 Y6 AT36
.c s
m o
D
C
R225 0/8 GND_VSSAPCIEBG R210
B
0/8 GND_VSSAUSBBGSUS Layout Note: Use dedicated via for each pin and then connect them straight to pcb gnd plane
VSSAPCIEBG VSSAUSBBGSUS
AC32 T26 GND_VSSAPCIEBG GND_VSSAUSBBGSUS
A
8 OF 10
Title Size B Date:
3 2
Intel
Poulsbo-8 Chipset VSS
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 13 of 35
5
4
3
2
1
R256 VCC3 7 9 PM_EXTTS# M_A_A[14:0] R255 10K/4 J33 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 Test Point M_A_BS2 9 9 9 9 9 9 9 9 9 9 9 9 9 M_A_BS0 M_A_BS1 M_CS#0 M_CS#1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 M_CKE0 M_CKE1 M_A_CAS# M_A_RAS# M_A_WE#
0/4
83 120 50 69 163
122 196 193 8 18 24 41 53 42 54 59 65 60 66 127 139 128 145
NC1 NC2 NC3 NC4 NCTEST
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18
D
TP16 9
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 114 119 198 200 197 195 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 199 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 CS0# CS1# CLK0_P CLK0_N CLK1_P CLK1_N CKE0 CKE1 CAS# RAS# WE# ODT0 ODT1 SA0 SA1 SCL SDA DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
C
ODT0 ODT1
R252 10K/4 SA0_DIM0 R253 10K/4 SA1_DIM0 R251 10K/4 R276 10K/4 R277 150/4 8,16,17,19,24,29,31 SMB_CLK 8,16,17,19,24,29,31 SMB_DATA DM_7_0_R
9 M_A_DQS[7:0]
B
R254
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 DQS_7_0_R
150/4
V1.8_DIMM VCC3 R261 10K/4 C273 2.2U/10V/X5R/6
9 M_VREF_SCH R260 10K/4
C265 2.2U/10V/X5R/6
A
5
w
w w
165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40
CG1 CG2
la .
C272 C266 0.1U/25V/X7R/6 V1.8_DIMM
4
0.1U/25V/X7R/6
t p
VDDSPD VREF 112 111 117 96 95 118 81 82 87 103 88 104 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12
p o
-s
h c
m e
VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 138 150 162 47 133 183 77 12 48 184 78 71 72 121
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_A_DQ[63:0] 9 VTT_DDR
R263 56/4/1 R239 56/4/1
ic t a
.c s
R246 R270 R245 R269 R244 R268 R243 R242 R267 R266 R271 R241 R265 R250 R240 VTT_DDR C261 C256 0.1U/16V/X5R/4 VTT_DDR C279 C276 0.1U/16V/X5R/4
R272 56/4/1 R247 56/4/1 R264 56/4/1 R273 56/4/1 R274 56/4/1 R248 56/4/1 R249 56/4/1 R275 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1 56/4/1
m o
M_CKE0 M_CKE1 9 9 9 9 9 M_A_BS0 M_A_BS1 M_A_BS2 M_A_WE# 9 M_A_CAS# 9 M_A_RAS# 9 M_CS#0 M_CS#1 9 9 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 C260 C274 C262 0.1U/16V/X5R/4
D
M_A_A[14:0] 9
C
Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9 and place it within 100 mils
0.1U/16V/X5R/4 0.1U/16V/X5R/4 C275
0.1U/16V/X5R/4 0.1U/16V/X5R/4 C258
0.1U/16V/X5R/4
0.1U/16V/X5R/4 0.1U/16V/X5R/4 C280
0.1U/16V/X5R/4 C278 C277
0.1U/16V/X5R/4 C257 C259
B
0.1U/16V/X5R/4 0.1U/16V/X5R/4
V1.8_DIMM 2.2U/10V/X5R/6 C534 2.2U/10V/X5R/6 C535 C536 C537 0.1U/25V/X7R/6 C550 C548 0.1U/25V/X7R/6 C547 C549 R708 0/1206
+1.8V
0.1U/25V/X7R/6
DDR2_SODIMM_Socket
2.2U/10V/X5R/6
2.2U/10V/X5R/6
0.1U/25V/X7R/6
A
VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43
CG1 CG2
Title Size Custom Date: Document Number
Intel
DDR2 SODIMM
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 14 of 35
3
2
5
4
3
2
1
16 x 1uF, 0402 Place CPU Die Shadow - Secondary side
VCC_CORE Isolation resistor on the VR page
Vcc Core Decoupling
4 3 4 3 1U/6.3V/X5R/4 C152 C154 1U/6.3V/X5R/4 C149 C145 1U/6.3V/X5R/4 C148 C184 C164 C178 1U/6.3V/X5R/4 H4 5 6 7 8 H5 1 2 5 6 1 2
4
3
4 5 6 7
C150
D
C181
C151
C146
C155
C183
C185
C182
5 6
1 2
3 1 2 8
D
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4 MountingHole 220U/4V/KO/7343
14 x 10uF,0603 Need to identify specific parts to meet ESR/ESL Place between VR and CPU plane
10U/6.3V/X5R/8 C495 10U/6.3V/X5R/8 C224 C197 10U/6.3V/X5R/8 10U/6.3V/X5R/8 C237 C177 10U/6.3V/X5R/8 10U/6.3V/X5R/8 C494 C493 10U/6.3V/X5R/8 10U/6.3V/X5R/8 C233 C492 10U/6.3V/X5R/8 10U/6.3V/X5R/8 C214 C496 10U/6.3V/X5R/8 10U/6.3V/X5R/8 C236 10U/6.3V/X5R/8 Low ESL Capacitors C234 10U/6.3V/X5R/8 C491 + EC74 + EC55 220U/4V/KO/7343
7
8
7
8
7
8
7
Secondary Side
V1.05S_VTT_C6 1U/6.3V/X5R/4
C
12 x 1uF, 0402 Place CPU Die Shadow - Secondary side
1U/6.3V/X5R/4 C191 C193 1U/6.3V/X5R/4 C201 C135 1U/6.3V/X5R/4 C204 C165 1U/6.3V/X5R/4 C205 C99 C136 C207 1U/6.3V/X5R/4
MountingHole
MountingHole
MountingHole
MountingHole
C134 1U/6.3V/X5R/4
C202
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
1U/6.3V/X5R/4
8 x 0.1uF, 0402 Place CPU Die Shadow - Secondary side
0.1U/16V/X5R/4 C102 0.1U/16V/X5R/4 C157 C100 C101 C98 C133 C203 C206 0.1U/16V/X5R/4
0.1U/16V/X5R/4 0.1U/16V/X5R/4 0.1U/16V/X5R/4 0.1U/16V/X5R/4
0.1U/16V/X5R/4
VCC
B
+12V
V1.05S_VTT_CPU D
VCC3 R434 100K/6/1 R433 8 SLPIOVR# 0/6 R432 1K/6
R431 4.7K/6
R458 4.7K/6
G
D
V105S_EN Q27 C419 2N7002/SOT-23 0.1U/25V/X7R/6
Q28
G
D S G
D S
2N7002/SOT-23
SLPIOVR# = 0(C6) SLPIOVR# = 1(Normal)
A
5
w
w w
=> =>
Switch OFF +VCCP1.05_CPU_C6_OFF = 0 Switch ON +VCCP1.05_CPU_C6_OFF = +V1.05S_VTT_CPU
A
la .
4
to p
S
Q33
AP2306AGN/SOT23-3
V1.05S_VTT_C6
C432 0.1U/25V/X7R/6
-s p
h c
m e
8
Place around the CPU socket
ic t a
4 3 H2 5 6 1 2 4 3 H3 5 6 1 2 7 8 MountingHole
.c s
7 8 MountingHole 4 3 H1 5 6 1 2 4 5 6 7 8 3 H10 1 2 MountingHole
m o
H7 7 MountingHole 8 4 3 H8 5 6 1 2
H6
MountingHole
4 5 6
3 1 2
H9
C
B
D
D
G
G
G
S
S
S
Title Size B Date:
3 2
Intel
CPU Decoupling
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 15 of 35
5
4
3
2
1
R699 VCC3 0/6 C542 10U/6.3V/X5R/8 V3.3S_CK505
FB52 120Z/3A/1206
0.1U/16V/X5R/4 C531
0.1U/16V/X5R/4 VDD_CLK_SNG C530 0.1U/16V/X5R/4 C524 U41
CK540 MLF56
3 10 18 17 27 53 40 1 2 11 12 13 VDDREFIO_3.3 VDDIO_PCI3.3 VDD48PLL_3.3 VDD48IO_3.3 VDDCDPLL_3.3 VDDCPUPLL_3.3 VDDCORE_3.3 X2 X1 PCI0 PCI1 PCI_F2 VDDIO_SRC VDDIO_CPU VDDI0_LCD VDDIO_96MHz 35 49 26 19
Res terminator
Place the 0.1 uF caps as close as possible to each VDD_IO pin. Place the 10 uF cap on the VDD_IO plane. 0.1U/16V/X5R/4 C497 0.1U/16V/X5R/4 C507 C513 +1.5V C516 C541 10U/6.3V/X5R/8
FB53
D
0.1U/16V/X5R/4 0.1U/16V/X5R/4 VDD_CLK_DIF C498 C519 C520 0.1U/16V/X5R/4
C499 120Z/3A/1206 0.1U/16V/X5R/4
0.1U/16V/X5R/4 CPU0 CPU#0 CPU1 CPU#1 R662 0/4 R656 0/4 R647 0/4 R640 0/4
0.1U/16V/X5R/4
C538 12P/50V/NPO/6 12P/50V/NPO/6 C529 PCLK_TPM 14.318MHz/30ppm
22P/50V/NPO/6 XTAL_OUT 1 R693 10M/6
CPU0T_LPRS CPU0C_LPRS CPU1T_LPRS CPU1C_LPRS CPUITPT_LPRS CPUITPC_LPRS SRC0T_LPRS SRC0C_LPRS CLKREQ0# SRC1T_LPRS SRC1C_LPRS CLKREQ1# SRC2T_LPRS SRC2C_LPRS CLKREQ2# SRC3T_LPRS SRC3C_LPRS CLKREQ3#
52 51 48 47 46 45 31 30 29 33 32 28 37 36 42 39 38 41
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_SCH_BCLK 6 CLK_SCH_BCLK# 6
C533 CLK_REF_SCH C525 SIO_48M
X4 2 C539
22P/50V/NPO/6
XTAL_IN 33/4 33/4 33/4 PCI_STOP# PCICLK REF0_R USB48_R
12P/50V/NPO/6
(open)
7,21 PCLK_TPM 8 CLK_REF_SCH 24
C
R687 R691 R677
4 16 9 44 6 5
REF0 USB_48MHz PCI_STOP# CPU_STOP# SCLK SDATA
SRC0 SRC0# CLKREQ0# SRC1 SRC1# CLKREQ1# SRC2 SRC2#
R617 R618 R612 R615 R616 R625
0/4 0/4 475/4/1 33/4 33/4 475/4/1
CLK_PCIE+ CLK_PCIE-
17 17
SIO_48M
CLK_LAN2_PCIE+ 28 CLK_LAN2_PCIE- 28
VCCP 8 PM_STPCPU# R630 56/4/1 R205 56/4/1 R680 56/4/1 3VSB
R694 10K/4 R695 10K/4
8,14,17,19,24,29,31 SMB_CLK 8,14,17,19,24,29,31 SMB_DATA
R613 0/4 R614 0/4
(open)
4 CPU_BSEL0 CPU_BSEL0 R204 1K/4 4 CPU_BSEL1 CPU_BSEL1 R679 33/4 4 CPU_BSEL2 SCH_BSEL2 6 R631 1K/4
CPU_BSEL1
R632 0/4
CPU_BSEL1_R CPU_BSEL2
43 55
FSLB FSLC
R689 10K/4 R690 10K/4
8 7
TEST_MODE TEST_SEL
R681 1K/4
B
3VSB X3 4 C468 0.1U/16V/X5R/4 1 VCC OE OUT 3 2
OUT_25M
25MHz/50ppm
OUT_25M R522 10/4
A
28 20
25MHZ_2 25MHZ_1
5
w
w w
25MHZ 1 REF 25MHZ_2 2 25MHZ_1 3 4 CLK2 CLK1 GND
U34
ICS9112-16/SO-8
la .
GND CLKOUT 8 CLK4 7 VDD 6 CLK3 5
4
25M_REF 25MHZ_4
to p
C469 0.1U/16V/X5R/4 R543 0/6 25MHZ_3 29
15 56 14 34 50 23 22
GND48 GNDREF GNDPCI GNDSRC GNDCPU GND GND1
ICS9UMS9001/MLF56
-s p
LCD100T_LPRS LCD100C_LPRS CK_PWRGD#/PD THERMGND 25M_REF 25MHZ_1 25MHZ_2 25MHZ_3 25MHZ_4
DOT96C_LPRS DOT96T_LPRS
20 21
25 24
54
57
h c
DOT96# DOT96 0/4 C473 C451 C117 C470 C119
R657 0/4 R651 0/4
SS_CLK R641 0/4 SS_CLK# R648 0/4
m e
R633 10K/4 DREFCLK# DREFCLK 8 8 DREFSSCLK 8 DREFSSCLK# 8 22P/50V/NPO/6 22P/50V/NPO/6 22P/50V/NPO/6 22P/50V/NPO/6 22P/50V/NPO/6
CLK_PCIE_IN 7 CLK_PCIE_IN# 7 CLK_SCH_OE# 8
a
34
ic t
.c s
CLK_SCH_BCLK# CLK_SCH_BCLK
CLK_PCIE-
CLK_PCIE+
m o
R639 49.9/4/1 R646 49.9/4/1 R601 49.9/4/1 R600 49.9/4/1 R602 49.9/4/1 R603 49.9/4/1 R599 49.9/4/1 R598 49.9/4/1 R658 49.9/4/1 R652 49.9/4/1
(open)
D
(open)
(open) (open)
(open) (open)
CLK_LAN2_PCIECLK_LAN2_PCIE+
(open) (open)
C
CLK_PCIE_IN# CLK_PCIE_IN
(open)
DREFCLK# DREFCLK
(open)
R649 49.9/4/1 DREFSSCLK# DREFSSCLK R642 49.9/4/1
(open) (open)
B
CLKPWRGOOD R674
VR_PWRGD_CLKEN#
R542 10/4 R519 10/4 R165 10/4 R540 10/4 R166 10/4
A
3VSB
Vbuffer 25MHZ_3
Title Size B Date: Document Number
Intel
Clock CK540
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 16 of 35
3
2
5
4
3
2
1
VCC3
FWH
C532 0.1U/16V/X5R/4 C528 0.1U/16V/X5R/4 R697 100/4/1 19,20,21,22,24,25,27,28,29 PLT_RST# VCC3 8 8 FWH_WP# FWH_TBL# R698 1K/4 R654 R655 R664 R676 PLT_RST_R# 10K/4 FGPI3 10K/4 FGPI2 10K/4 FGPI1 10K/4 FPGI0 FWH_WP# R696 TBL22/6 R688 1K/4 4 3 2 1 32 31 30
D
VCC3
VCC
C517 0.1U/16V/X5R/4 C518 0.1U/16V/X5R/4 R234 4.7K/6 C255 FGPI4 FWHIC CLK_LPC_FWH 7 R653 10K/4 VCC3
J4
5 6 7 8 9 10 11 12 13 FGPI1 FGPI0 WP# TBL# ID3 ID2 ID1 ID0 FWH0
24
BEEP
BEEP
Z2004
SOCKET PLCC32
VCC3
FWH1 FWH2 GND_1 FWH3 RES_1 RES_2 RES_3
IC GNDA VCCA GND_2 VDD1 INIT# LFRAME# NC_1 RES_4
29 28 27 26 25 24 23 22 21
0.1U/25V/X7R/6
8 HDA_SPKR
PLT_RST_R# LPC_FRAME# 7,21,24,25
R238
7,21,24,25 LPC_AD0 7,21,24,25 LPC_AD1 7,21,24,25 LPC_AD2
C
14 15 16 17 18 19 20
PLCC32_Socket
LPC_AD3
7,21,24,25
R692 FWH_WP# 22/6 R675 1K/4 FWHIC JP11 JP10 PH2Px1/2mm 3VSB 1 2 U13 PH2Px1/2mm 1 2 JP7 PH2Px1/2mm 1 2 TBL-
C94 0.1U/25V/Y5V/4
34 7 7 8
IMVP6_PGOOD PM_SLPRDY# PM_SLPMODE PM_RSTRDY#
8,24 PM_PWRBTN#
31 SYS_RESET# J25
B
1 2 3 4 5 6 7 3VSB
VDD RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR#/Vpp RC5/T0CKI RC4 RC3
Vss RB0/CSPDAT RB1/CSPCLK RB2 RC0 RC1 RC2
14 13 12 11 10 9 8
ICSPDAT
SLP_S5# 33 PM_RSMRST#7,24 PM_RSTWARN8 RST# 8 All_PWROK 7 SLP_S3# 24,32,33
PIC16F505/SOIC-14
1 2 3 4 5 6 PH6Px1/2.54mm
U14 RST# 1 2 3
A
VCC3 VCC 5
B A GND
Y
4
SN74AHCT1G08/SOT23-5
R134 10K/6
5
w
w w
PLT_RST# 19,20,21,22,24,25,27,28,29
la .
4
to p
-s p
h c
m e
C485 10U/6.3V/X5R/8 8,14,16,19,24,29,31 8,14,16,19,24,29,31 7 7 VCC3
PCIe Interface
ic t a
3VSB C488 0.1U/25V/X7R/6 SMB_CLK SMB_DATA PCIE_WAKE# PCIE_TXP1 PCIE_TXN1 2.2K/6 EXP_EN_HDRX1
1K/6 C264 0.01U/50V/X7R/6
B
.c s
R237 BZ_07 BZ_06 C 47/6 Q15 SMBT3904/SOT-23 E J41 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26
m o
BZ1
VCC
D
1
FGPI2 FGPI3 RST# VPP VDD2 CLK FGPI4
2
Buzzer
R236 470K/6
C521 0.1U/25V/X7R/6
PC_BEEP
27
R235 47K/6
C
VCC3 +12V
+12V VCC3
SMB_CLK SMB_DATA
PLT_RST# CLK_PCIE+ CLK_PCIE-
PLT_RST# CLK_PCIE+ CLK_PCIE-
19,20,21,22,24,25,27,28,29 16 16 PCIE_RXP1 PCIE_RXN1 7 7
B
8,28 PCIE_WAKE# PCIE_TXP1 PCIE_TXN1 R279
C554 0.047U/16V/X7R/4 PCIE_RXP1 C553 0.047U/16V/X7R/4 PCIE_RXN1
A
Title Size B Date:
3 2
Intel
FWH_PIC16F505_PCIE
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 17 of 35
5
4
3
2
1
USB Port
USBV3
FS1 FB40 2 30Z/3A/6
USBV2
FS2 FB39 2 30Z/3A/6 C321 0.1U/25V/X7R/6 3VSB FS3 FB35 2 30Z/3A/6
USBV6 5V_Dual
1
5V_Dual
1
60 mil
C322 0.1U/25V/X7R/6
3VSB
5V_Dual
1
60 mil
60 mil
C306 0.1U/25V/X7R/6
5V_Dual
PS1.6/6V/SMD
D
PS1.6/6V/SMD
PS1.6/6V/SMD
(OPEN)
3VSB R24 10K/4
R23 15K/6/1
(OPEN)
3VSB FB34 R33 10K/4
R29 15K/6/1
(OPEN)
R678 10K/4
R31 15K/6/1
8 USB_OC#0
C9 1000P/50V/X7R/6 R25 27K/6 +
USBV1
8 USB_OC#2
FB38 C29 1000P/50V/X7R/6 R28 27K/6 30Z/3A/6 +
USBV5
8 USB_OC#6
FB36 C30 1000P/50V/X7R/6 R30 27K/6 +
USBV7
60 mil
30Z/3A/6 EC7 470U/16V/EL/8x11.5 C300 0.1U/25V/X7R/6
60 mil
C320 0.1U/25V/X7R/6
60 mil
EC8 220U/10V/EL/6.3x11
30Z/3A/6 EC10 470U/16V/EL/8x11.5
60 mil (pin1~pin2)
8 USB_PP4 8 USB_PN4
C
R382 R383
0/6 0/6
USBD4P USBD4N
USBD6P
1 2
D19 LINE-1 LINE-4 GND VDD 6 5 4
USBV2
JP6 1 2 3
USBD7P 5V_Dual USBD7N
8 USB_PP0 8 USB_PN0
R346 R347
0/6 0/6
LINE-2 LINE-3
USBD0P USBD0N USBD1P
1 2
USBG6 USBG7
AZC002-04S/SOT23-6 D17 LINE-1 LINE-4 GND VDD 6 5 4
VCC3
8 USB_PN6 8 USB_PP6
R365 R364
0/6 0/6
USBD6N USBD6P
USBD0P 5V_Dual USBD0N
USBD1N
3
LINE-2 LINE-3
AZC002-04S/SOT23-6 D18
USBD5P 8 USB_PP3 8 USB_PN3
B
1 2
LINE-1 LINE-4 GND VDD
6 5 4
R384 R385
0/6 0/6
USBD3N
USBD5N
G
LINE-2 LINE-3
4.7U/6.3V/X5R/6
USBG2 USBG5
CG1 CG2 CG3 CG4
AZC002-04S/SOT23-6 D20
C283
B
8 USB_PP1 8 USB_PN1
R344 R345
0/6 0/6
USBD1P USBD1N
USBD4P USBD4N
1 2 3
LINE-1 LINE-4 GND
VDD
LINE-2 LINE-3
8 USB_PP2 8 USB_PN2
R369 R370
0/6 0/6
USBD2P USBD2N
Client USB
8 USB_PN5 8 USB_PP5
A
R372 R371
0/6 0/6
USBD5N USBD5P
8 USB_PP7 8 USB_PN7
R366 R367
5
w w
0/6 0/6
USBD7P
USBD7N
. w
p la
L11 USB_PP5 USB_PN5 USB_PP2 USB_PN2 1 2 3 4 L12 USB_PP4 USB_PN4 USB_PP3 USB_PN3 1 2 3 4
4
AZC002-04S/SOT23-6
8 USBD5P 7 USBD5N 6 USBD2P 5 USBD2N
to
6 5 4
USBD3P 5V_Dual
USBD3N
S
3
USBD2N
(open)
FB7
USBV1
VUSB4
USBD1N USBD1P EC15 1 2 3 USBG1 4 CG1 CG2 470U/16V/EL/8x11.5
J9 USB/TypeA USBV USB_N USB_P USB_G CG1 CG2
5V_Dual
USBD4N USBD4P
30Z/3A/6 VUSB4 USBD4N USBD4P USBG4 1 2 3 4
J16 +
L9 USB_PP1 USB_PN1 USB_PP0 USB_PN0 1 2 3 4 8 USBD1P 7 USBD1N 6 USBD0P 5 USBD0N
BH4Px1/2mm
J15
USBG1
A
USBV3
L10 USB_PP6 USB_PN6 USB_PP7 USB_PN7 1 2 3 4 8 USBD6P 7 USBD6N 6 USBD7P 5 USBD7N
USBD3N USBD3P USBG3
8 USBD4P 7 USBD4N 6 USBD3P 5 USBD3N
1 2 3 4 BH4Px1/2mm
Title Size B Date: Document Number
Intel
USB PORTS
CG1 CG2 CG3 CG4
G
S
USBD3P
USBD2P 5V_Dual
-s p
h c
USBV2_CLIENT
R283 100K/6
R284 4.7K/6 GPIOSUS_3 Q16 D 8 USBD5N USBD5P
DualUSB/TypeA
D
Q17 2N7002/SOT-23
USB CLIENT
USBV5
USBG5
B1 B2 B3 B4 A1 A2 A3 A4
V1 D1D1+ G1 V0 D0D0+ G0
D
D G S
USBV2_PWR
2N7002/SOT-23 USBD2N USBD2P USBG2
R282 100K/6
G
S
CG1 CG2 CG3 CG4
USBD6N
3
USBV2_CLIENT
m e
+
PH3Px1/2mm
EC14 220U/10V/EL/6.3x11
CG1 CG2 CG3 CG4
USBV2_PWR
a
USBV2_PWR
ic t
C307 0.1U/25V/X7R/6
.c s
USBD7N USBD7P
C23 1000P/50V/X7R/6
m o
(OPEN)
R32 R665 10K/4 15K/6/1
USB_OC#4 8
D
R26 27K/6
J12
USBV6
USBD6N USBD6P USBG6
DualUSB/TypeA B1 B2 B3 B4 A1 A2 A3 A4 V1 D1D1+ G1 V0 D0D0+ G0
USBV7
USBG7
C
J11
1 2 3 4
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 18 of 35
3
2
5
4
3
2
1
8,20 IDE_PDD[15:0]
IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
CF Connector
J29 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_PDA0 IDE_PDA1 IDE_PDA2 21 22 23 2 3 4 5 6 47 48 49 27 28 29 30 31 20 19 18 17 16 15 14 12 11 10 8 7 32 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 #IOR #IOW #IOCS16 BVD1 BVD2 #RESET #IOCHRDY #DACK #DREQ VS1 VS2 34 35 24 46 45 41 42 43 44 IDE_PDIOR# IDE_PDIOW# R152
D
8,20 IDE_PDD[15:0]
(open)
IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0 IDE_PDIOW# IDE_PDIOR# IDE_PDIORDY IDE_PDDACK# INT_IRQ14 IDE_PDA1 IDE_PDA0 IDE_PDCS1# IDE_PDCS3# IDE_PDA2 IDE_PDACTIVE#
IDE_PDACTIVE#
8,20 IDE_PDIOW# 8,20 IDE_PDIOR# 8,20 IDE_PDIORDY 8,20 IDE_PDDACK# 8,20 INT_IRQ14 8,20 IDE_PDA1 8,20 IDE_PDA0 8,20 IDE_PDCS1# 8,20 IDE_PDCS3# 8,20 IDE_PDA2 20,31 IDE_PDACTIVE#
C
VCC3
R179 8.2K/4 R176 4.7K/4
INT_IRQ14 IDE_PDIORDY
VCC3
B
C484 0.1U/50V/Y5V/6 1 C483 4,24 4,24 VTIN2 AAGND 2200P/50V/X7R/6 SHB_OVT# 2 3 4
U39 VDD D+ DSMCLK SMDATA ALERT# GND 8 7 6 5 SMB_CLK SMB_DATA SMB_ALERT# 8,14,16,17,24,29,31
8,14,16,17,24,29,31 8
THERM#
EMC1402/MSOP-8
R584 SHB_OVT# D30
A
8.2K/6
VCC3
C
A RB751V-40/SC-76
5
w w
. w
PM_THRM# 8,24
p la
4
to
-s p
J43 2 1 24 SYS_VTIN 24 VREF 4,24 VTIN2 24 VREF 24 AUXTIN
Ext. Temp Sensor
PH2Px1/2mm
h c
3300P/50V/X7R/6 R590 10K/6/1 R586 15K/6/1 R582 10K/6/1
C* close to W83627 pin
m e
IDE_PDCS1# IDE_PDCS3# C490 C481 AAGND 3300P/50V/X7R/6 R548 C479 AAGND
#CS0 #CS1
ic t a
33 40 #CSEL #REQ 39 37 #WE #OE #CD1 #CD2 36 9 26 25 13 38 VCC1 VCC2 GND1 GND2 1 50 CG1 CG2 CG1 CG2 4,24
Z1703 IDE_PDIORDY Z1705 SSECT
.c s
150/4 CF_PDIAGn R119 R156 0/4 R178 R160 INT_IRQ14 Z1706 R151 4.7K/4 + C426 0.1U/25V/X7R/6 VCC_CORE R547 10K/6/1 VCC R574
IDE_PDDREQ 0/4 0/4
m o
20 33/4 PLT_RST# IDE_PDDREQ IDE_PDDACK# IDE_PDDREQ 1 2
D
17,20,21,22,24,25,27,28,29 8,20
JP13
CF_SLAVE/MASTER#
VCC
R195 470/4
PH2Px1/2mm
VCC
EC45 100U/25V/EL/6.3x11
C
Voltage Monitor
VCOREIN VCC5IN R549 30K/6/1 VCC3 R575 10K/6/1 +12V R573 R546 150K/6/1 10K/6/1 10K/6/1 VCC3IN R550 10K/6/1 +12VIN AAGND 24 4,24 AAGND 24 4,24 AAGND 24
B
Use Thermistor 10k ohms at 25 deg.C
24 4,24
RT1
System Temperature
10K/8/1
CPU Temperature
C* close to W83627 pin
10K/6/1
4,24
A
3300P/50V/X7R/6
Title Size B Date:
3 2
Intel
CF_Thermal sensor
Document Number
Gilmore Summit
Tuesday, December 30, 2008 Sheet
1
Rev Z000 19 of 35
5
4
3
2
1
IDE_PDCS1# IDE_PDCS3# IDE_PDIAGn UAO VCC3 UAI GND 1V8 PHYRDY GND GND GND VCC3 GND IDE_DASPn MSSEL
Bypass CAP, close to power pins
PIN#4
VCC3 C221 0.1U/25V/X7R/6
D
VCC3 UAI UAO PHYRDY TP9 TP8 Test Point Test Point
PIN#9
1V8
PIN#41
1V8
PIN#44
VCC3
PIN#56
1V8
TP10 Test Point
Reserve for measure SATA Eye Pattern.
1.Mode[2]=1 Host Bridge (IDE to SATA HDD/ODD) Mode[2:0]=110 =>150MB/s Mode[2:0]=101 =>133MB/s 2.CLKSEL[1:0]=01 25MHz 3.SSCEN=0 Disable 4.FXDMA=0 Adjustable Speed rate according set Feature Command FXDMA=1--->Mode[1:0] 5.PMEN=0 Disable 6.ATAIOEN=1 Enable ATA output 7.MSSEL=0 : Device 0 MSSEL=1 : Device 1
JP14
C
C131 0.1U/25V/X7R/6
C105 0.1U/25V/X7R/6
C220 0.1U/25V/X7R/6
C222 0.1U/25V/X7R/6
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
U15
CS0n/DD7 CS1n/RESETn PDIAGn/PATAOR UAO VCCO2 UAI DGND2 VCCK2 PHYRDY PMEN FXDMA CLKSEL1 CLKSEL0 SSCEN DASPn/GPIO0 MSSEL/GPIO1
Cap Place near SATA connector
C198 0.01U/50V/X7R/6 C189 0.01U/50V/X7R/6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TXP TXN GND AVDDL3 RXN RXP REXT GND AVDDH3 XIN_25M VCC3 MOD2 MOD1 MOD0 PORn STXP1 STXN1 1 2 3 4 5 6 7
J28
FB50 VCC3 220Z/2A/8 C465 10U/6.3V/X5R/8 AVDDH3 C466 0.1U/25V/X7R/6 1V8
FB51 AVDDL3 220Z/2A/8 C472 10U/6.3V/X5R/8 C471 0.1U/25V/X7R/6
PIN#24
PIN#29
(SATA HDD POWER)
BH4Px1/2mm
C
VCC3 +1.8V R181 1V8
DD13/DD0 DD2/DD15 DD12/DMARQ VCCO1 DD3/DIOWn DD11/DIORn DD4/DMACKn DGND1 VCCK1 DD10/INTRQ DD5/GPIO2 DD9/DA1 DD6/DA0 DD8/DA2 DD7/CS0n RESETn/CS1n
IDE_PDA2 IDE_PDA0 IDE_PDA1 SP INT_IRQ14 IDE_PDDACK# IDE_PDIORDY 1V8 GND IDE_PDIOR# IDE_PDIOW# IDE_PDDREQ IDE_PDD15 IDE_PDD0 IDE_PDD14 IDE_PDD1
J26 1 2 3 4
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
R136 47K/6
JM20300/TQFP64 PORn C104 1U/25V/X5R/8
DA2/DD8 DA0/DD6 DA1/DD9 SP/GPIO2/DD5 INTRQ/DD10 DMACKn/DD4 IORDY VCCK3 DGND3 DIORn/DD11 DIOWn/DD3 DMARQ/DD12 DD15/DD2 DD0/DD13 DD14/DD1 DD1/DD14
JM20330
(LQFP64)
TXP TXN AGND2 AVDDL RXN RXP REXT AGND1 AVDDH XTALO XTALI/OSCI ATAIOEN MODE2 MODE1 MODE0 PORn
SRXN1 SRXP1 C174 0.01U/50V/X7R/6 C163 0.01U/50V/X7R/6
R177 12K/6/1
0/8 SATA_VDD EC46 100U/25V/EL/6.3x11 +
VCC
+ EC49 100U/25V/EL/6.3x11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
C175 10U/6.3V/X5R/8
VCC3 SATA_VDD +12V
B
JP9 1 2 3
(SATA HDD/SSD HDD POWER Select)
JP21
PH3Px1/2mm 1 2 19 CF_PDIAGn
R190 10K/6 IDE_PDIAGn PH2Px1/2mm
16
25MHZ_1
25MHZ_1 R520 10/4
XIN_25M
close to CF Connector
R565 3VSB VCC3 R564
A
0/8 +3.3VCCSEL
(Open)
3 0/8 + EC52 100U/25V/EL/6.3x11
U36 AMS1117-ADJ/SOT-223 V_IN V_OUT 2 GND/ADJ
OUT
5
w w
1 R528
100/6
. w
1V8 R533 220/6 4
C467 10U/6.3V/X5R/8
p la
4
to
IDE_DASPn
-s p
VCC3
(Open)
R191 100/6
IDE_PATADET
Rb
h c
R192
m e
SP
MOD[2:0]=110 =>150MB/s
MOD0 R140 1K/6 MOD1 R158 1K/6 MOD2 R172 1K/6 MOD0 R144 22/6 MOD1 R150 22/6 MOD2 R167 22/6 VCC3
IDE_PDD13 IDE_PDD2 IDE_PDD12 VCC3 IDE_PDD3 IDE_PDD11 IDE_PDD4 GND 1V8 IDE_PDD10 IDE_PDD5 IDE_PDD9 IDE_PDD6 IDE_PDD8 IDE_PDD7 IDE_RESETn
a
To SATA Hard Disk
ic t
CG1 CG2
GND1 TX+ TXGND2 RXRX+ GND3 CG1 CG2
SATA/180Deg.
.c s
VCC3 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_P