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GUADALUPE
D
DOTHAN/YONAH-ALVISO CUSTOMER REFERENCE BOARD
Fan Header
PG 5
Fab 2
Dothan/Yonah Processor
478 uFCPGA
PG 3,4
Clocking
PG 30
IMVP-IV VR
PG 48,49
CRT PG 16 LVDS/ALS/BLI PG 17 VGA LVDS TVO PG 16 TVOUT PEG/SDVO PCIE x 16 CPU Thermal Sensor PG 5
XDP
SODIMM0
PG 26 PSB Single Channel DDR1
PG 18,19,20,21
Alviso
1257 PCBGA
PG 6,7,8,9,10,11
ALVISO VCCP VR
PG 45
5V PCI SLOT 3
PG 38, 39 SATA
DMI 33MHz PCI PG 23,24
PG 12
ICH6-M
DOCKING USB7 PG 35 FRONT PANEL USB5 PG 34 PATA
PG 13,14,15
PG 35 USB6 USB4 USB3
USB 2.0
B
AC97/Azalia USB1 USB0 USB2 PG 35
BACK PANEL
MDC Header
PG 22
A
5
. w w w
to p la
FWH PORT80/83
PG 36 8 Mbit PG 37
4
-s p
PCIEx1 PCIEx1 PCIEx1 10/100 LCI
PCIEx1
Lane3 Lane1 Lane2 Lane0
PCIE Slot2 PCIE Slot0 PCIE Slot1
RJ45
PCIE Dock
609 BGA
h c
PS/2
5V PCI SLOT 4
C
PCI GOLDFINGERS
PCI EXPRESS GFX
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SYSTEM CHARGER VR DDR VR Platform Power VR Notes & Annotation
PG 2
REV 1.201
PG 43,44
D
PG 42 PG 46, 51, 52
SODIMM1
Mobile Power On Sequence
PG 56 PG 57
Desktop Power On Sequence
C
PG 55
AZALIA USB VGA LAN
PG 25
B
82570EI/82562EZ LAN PG 32,33
PG 29 LPC, 33MHz
SMC/KSC
PG 27
REDUCED SIO
PG 40
TPM Header
PG 29
PG 28
PS/2
LPC Sideband Headers
PG 29
LPC SLOT
GUADALUPE
Serial PG 41 CIR PG 41
AON
PG 31
Scan KB
PG 28
INTEL CONFIDENTIALA
Title Size A Date:
PG 28
Title Page Document Number C58015 Thursday, December 11, 2003
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Rev 1.201 Sheet 1
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GUADALUPE CUSTOMER REFERENCE PLATFORM
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
D
Voltage Rails
POWER PLANE +VBATA +VBAT +VBATS +V12A +V12S -V12A -V12S +V5A +V5 +V5S +V3.3A +V3.3 +V3.3S +V1.5A +V1.5 +V1.5S +VCCA_PROC_IN +V2.5 +V1.25S +V2.5A +V2.5S +V1 +VCC_GMCH +VCCP +VCC_CORE VOLTAGE 9V-12.5V 9V-12.5V 9V-12.5V 12V 12V -12V -12V 5V 5V 5V 3.3V 3.3V 3.3V 1.5V 1.5V 1.5V 1.5V or 1.8V 2.5V 1.25V 2.5V 2.5V 1.0V 1.05V 1.05V 0.700V-1.77V S3COLD ACTIVE S0, S3,S4,S5 S0, S3, S4, S5 S0 S0, S3,S4,S5 S0 S0, S3,S4,S5 S0 S0, S3,S4,S5 S0, S3 S0 S0, S3,S4,S5 S0, S3 S0 S0, S3,S4,S5 S0, S3 S0 S0 S0, S3 S0 S0, S3,S4,S5 S0 S0, S3 S0 S0 S0 S3HOT ACTIVE S0, S3,S4,S5 S0, S3, S4, S5 S0 S0, S3,S4,S5 S0, S3 S0, S3,S4,S5 S0, S3 S0, S3,S4,S5 S0, S3 S0, S3 S0, S3,S4,S5 S0, S3 S0, S3 S0, S3,S4,S5 S0, S3 S0, S3 S0 S0, S3 S0, S3 S0, S3,S4,S5 S0, S3 S0, S3 S0, S3 S0 S0 DESCRIPTION Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Only on in DT Power Mode Only on in DT Power Mode Only on in DT Power Mode Only on in DT Power Mode
I 2 C / SMB Addresses
Device Clock Generator Spread Spectrum Clock PCI Express Clock SO-DIMM0 SO-DIMM1 DDR Thermal Sensor LVDS Backlight Inverter Ambient Light Sensor Always ON Display Thermal Diode Smart Battery Trusted Platform Module LAN PCI Express Docking Hex Address 1101 001x D2/D3* D4/D5* 1101 010x 1101 110x DC/DD* 1010 010x A4 1010 000x A0 0100 1100 4C 0101 1000 58 0111 0010 72 3C 011 110x 1001 110x 9C SEE PAGE 44 TBD TBD 1100 1000 C8 TBD TBD Bus SMB_ICH_S3 SMB_ICH_S3 SMB_ICH_S3 SMB_ICH_S2 SMB_ICH_S2 SMB_ICH_S2 SMB_ICH_S2 AON_ALS SMB_ICH SMB_THRM SMB_BS SMB_ICH_S4 SMB_ICH SMB_ICH_A1
Default Jumper Settings
Jumper Default J3B3 1-2 & 3-4 1-X J6H1 1-X J5G1 J8F1 1-X 1-2 J7E1 1-2 J7C3 2-3 J6E1 5-6 J6E1 2-3 J8E1 2-3 J8E2 2-3 J1E2 2-3 J1E3 1-X J9J3 1-X J9J1 SW9J1 1-2 1-X J9J7 1-2 J8G1 SW9J2 1-2 1-X J9J6 1-2 J9J5 1-X J9H1 1-X J7E3 2-3 J8H1 1-X J8H2 1-2 J9J2 1-2 J9J8 1-2 J7E4 1-2 J7A2 1-2 J7A3 1-2 J7J1 1-X J2H1 SW4A1 1-2 Option 1-X & 3-X 1-2 1-2 1-2 2-3 2-3 1-2 4-5 1-2 1-2 1-X or 1-2 1-X or 1-2 1-2 1-2 2-3 1-2 2-3 2-3 1-2 1-X 1-2 1-2 1-2 1-2 1-X 1-X 1-X or 2-3 2-3 2-3 2-3 1-2 2-3
* First address is for a write command and second is for a read command. Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The rest come out of EC.
CPU PLLs DDR core DDR command & control pull up.
C
Northway Rail, Only on when NW is stuffed GMCH core rail FSB pull up rail. CPU core rail
LEDs and Switches
LED ATA Activity LED SMC/KBC Num Lock SMC/KBC Scroll Lock SMC/KBC Caps Lock VID0 VID1 VID2 VID3 VID4 VID5 S0 State S3 Hot State S3 Cold State S4 State S5 State
PCI Devices
Device Slot 3 Slot 4 LAN IDSEL # AD18 AD19 (AD24 internal) REQ/GNT # 2 2 3 3 Interrupts C, D, B, A D, C, F, G
Net Naming Conventions
Suffix # = Active Low Signal Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else)
B
Power States
STATE Full ON S3 Hot (Suspend to RAM) S3 (Suspend to RAM) S4 (Suspend To Disk) S5 / Soft OFF SIGNAL SLP_S3 HOT# HIGH LOW LOW SLP_S3# HIGH LOW LOW SLP_S4# HIGH HIGH HIGH LOW LOW SLP_S5# HIGH HIGH HIGH +V*A ON ON ON
+V*
ON ON ON
A
5
. w w w
LOW LOW LOW HIGH LOW ON LOW ON
OFF
OFF
to p la
+V*S ON Clocks ON ON LOW OFF OFF OFF OFF OFF OFF
-s p
Switch Power On/Off Reset S3HOT Enable
h c
Page 13 27 27 27 41 41 41 41 41 41 51 51 51 51 51 Page 50 50 53
Reference CR7J1 CR9G1 CR9G2 CR9G3 CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR3G4 CR3G2 CR3G1 CR3G3 CR2G1
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Description Thermal diode disable CMOS clear Host Deepersleep Enable PM_S3HOT# PWM Data Select PWM Clock Select L_VDD_VDL2 Select L_VDD_VDL1 Select Azalea Docking Datain 1 Select Azalea Docking Datain 2 Select FSB Clock Frequency Select 0 FSB Clock Frequency Select 1 Ext. H8 Program Enable KBC Disable Virtual Battery Switch Virtual Battery Enable KBC/SMC Disable LID switch LID Open On-Chip Emulator Disable SMC 1Hz Clock Disable (NMI Jumper) Port 80-81/82-83 Select CRB / SV Detect BIOS Recovery SATA Status 1 SATA Status 2 SIO_RST# Enable In Ckt Prpgramming In Ckt Prpgramming In Ckt Prpgramming Force Shutdown S3HOT Enable Page 5 13 13 14 17 17 17 17 22 22 26 26 27 27 27 27 27 27 27 27 28 36 37 37 38 39 40 41 41 41 50 53
D
C
Reference SW1C2 SW1C1 SW4A1
B
Wake Events
Wake Events RI# from serial port PME# from PCI, LPC slot/device PCI Express, Newcard wake event Wake on LAN LID switch attached to SMC USB AC97/Azalia wake on ring SmLink for AOLII Hot Key from Scan matrix keyboard PS/2 Keyboard/mouse PWRBTN# State Supported S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3 S3-Hot, S3, S4, S5
PCB Footprints
1 3 2
SOT-23
As seen from top
1 2 3
5
SOT23-5
4
GUADALUPE Title Notes and Annotations Size A Date: Document Number C58015 Thursday, December 11, 2003
2
INTEL CONFIDENTIAL
A
Rev 1.201 Sheet 2
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4,6,9,13,15,26,41,45,49,52 +VCCP
6 H_A#[31:3] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 6 H_ADSTB#0 6 H_REQ#[4:0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 U3 R2 P3 T2 P1 T1 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5 C2 D3 A3 H_STPCLK_R C6 D1 D4 B4
U2E1A A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0 REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB#1 A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# ADS# BNR# BPRI# DEFER# DRDY# DBSY# N2 L1 J3 L4 H2 M2 N4 A4 B5 J2 B11 H1 H_RS#0 K1 H_RS#1 L2 H_RS#2 M3 K3 K4 C8 B8 A9 C9 A10 B10 A13 C12 A12 C11 B13 A7 B17 B18 A18 C17 A15 A16 B14 B15 H_ADS# 6 H_BNR# 6 H_BPRI# 6 H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6 H_IERR# H_INIT# 13
R2U3 56
D
CONTROL
BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM# BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
Place testpoint on H_IERR# with a GND 0.1" away
H_LOCK# 6 H_CPURST# 6,26,29 H_RS#[2:0] 6
4,6,9,13,15,26,41,45,49,52 +VCCP H_TRDY# 6 H_HIT# 6 H_HITM# 6 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 26 26 26 26 26 R2U10 56 XDP_BPM#5 26 6 H_D#[63:0]
6 H_A#[31:3]
C
6 H_ADSTB#1 13 H_A20M# 13 H_FERR# 13 H_IGNNE# 13 H_INTR 13,29 H_NMI 13,29 H_SMI# R2F1 0
XDP_TCK 26 XDP_TDI 26 XDP_TDO 26 XDP_TMS 26 XDP_TRST# 26 XDP_DBRESET# 26,50 H_THERMDA 5 H_THERMDC 5 PM_THRMTRIP# 7,13 PM_THRMTRIP# 7,13 CLK_XDP_CPU# 30 CLK_XDP_CPU 30 CLK_CPU_BCLK# 30 CLK_CPU_BCLK 30
R1F7 56
THERM
PROCHOT# THERMDA THERMDC
H_PROCHOT#
13 H_STPCLK#
Dothan_Yonah_Processor-Skt
H CLK
ITP_CLK1 ITP_CLK0 BCLK1 BCLK0
B
XDP_TMS XDP_TDI
XDP_TCK
A
5
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4,6,9,13,15,26,41,45,49,52 +VCCP R2U11 R2U4 54.9 54.9 1% 1% R2U5 54.9 1%
t p la
4
p o
-s
H_GTLREF
6 6 6 6
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[63:0]
DATA GRP 0
TP2F1 NO_STUFF
THERMTRIP#
PM_THRMTRIP# should connect to ICH6 and Alviso without T-ing (No stub)
DATA GRP 1
h c
6 H_DSTBN#1 6 H_DSTBP#1 6 H_DINV#1 48 PM_PSI# 26 CPU_BSEL0 26 CPU_BSEL1 R3R2 2K 1%
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H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 C23 C22 D25 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 K24 L24 J26 E1 C16 C14 TP_CPU_NC1 TP_NC_2 TP_NC_3 TP_NC_4 TP_NC_5 B2 C3 AF7 AC1 E26 AD26
a
U2E1B D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# PSI# BSEL0 BSEL1 NC1 RSVD2 RSVD3 RSVD4 RSVD5 GTLREF0
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H_D#[63:0] 6 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 W25 W24 T24 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
XTP/ITP SIGNALS
ADDR GROUP 0 ADDR GROUP 1
D
C
DATA GRP 2 DATA GRP 3
H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 AE24 AE25 AD20 P25 P26 AB2 AB1 G1 B7 C19 E4 A6 C5 F23
Layout note: Comp0,2 connect with trace length shorter Comp1,3 connect with trace length shorter H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6
Zo=27.4ohm, make than 0.5". Zo=55ohm, make than 0.5".
B
4,6,9,13,15,26,41,45,49,52 +VCCP
COMP0 COMP1 COMP2 COMP3
R3T2 R3T3 R1T1 R1R8
MISC
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# TEST1 TEST2
R3R1 1K 1%
4,6,9,13,15,26,41,45,49,52 +VCCP 27.4 54.9 1% 27.4 54.9 1% R1T6 200 1% H_DPRSTP# 13,29 H_DPSLP# 13,29 H_DPWR# 6 H_CPUSLP# 6,13,29
H_PWRGD 13,29
Layout note: 0.5" max length.
TEST1 TEST2 R2U1 1K NO_STUFF
R1T5 1K
Dothan_Yonah_Processor-Skt
Layout note: Connect R1T5 to H_PWRGD with no stub.
H_PWRGD_XDP 26
R3T6 1K NO_STUFF
GUADALUPE Title Yonah (1 of 2) Size A Date:
3
INTEL CONFIDENTIAL
A
Document Number C58015 Thursday, December 11, 2003
2
Rev 1.201 Sheet 3
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1
48,49,52 +VCC_CORE
D
U2E1C AA11 AA13 AA15 AA17 AA19 AA21 AA5 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC9 AD10 AD12 AD14 AD16 AD18 AD8 AE11 AE13 AE15 AE17 AE19 AE9 AF10 AF12 AF14 AF16 AF18 AF8 D18 D20 D22 D6 D8 E17 E19 E21 E5 E7 E9 F18 F20 F22 F6 F8 G21 VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58
48,49,52 +VCC_CORE VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCCA0 VCCA1 VCCA2 VCCA3 VCCP0 VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24 VCCQ0 VCCQ1 VID0 VID1 VID2 VID3 VID4 VID5 VCCSENSE VSSSENSE G5 H22 H6 J21 J5 K22 U5 V22 V6 W21 W5 Y22 Y6 F26 B1 N1 AC26 D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L21 L5 M22 M6 N21 N5 P22 P6 R21 R5 T22 T6 U21 P23 W4 E2 F2 F3 G3 G4 H4 AE7 AF6 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 TP_VCCSENSE 47 47 47 47 47 47 NO_STUFF TPVCC1D1 R1D1 NO_STUFF 54.9 1%
53 +VCCA_PROC_IN C3T1 0.01uF TP_VCCA1 TP_VCCA2 TP_VCCA3 CPU_D10 R2U8 0 C3T2 10uF
3,6,9,13,15,26,41,45,49,52 +VCCP
C
9,14,15,51..53 +V1.5S R3C4
53 +VCCA_PROC
0.01 +V1.8 33,52
NO_STUFF
Dothan_Yonah_Processor-Skt
B
Layout Note: VCCSENSE and VSSSENSE lines should be of equal length
TP_VSSSENSE
Layout note: Connect R1E4 to TP_VSSSENSE with no stub.
R1E4 1K 1% NO_STUFF
A
5
. w w w
to p la
TPVCCG1D1 NO_STUFF NO_STUFF TPVSS1D1 R1D2 NO_STUFF 54.9 1% TPVSSG1D1 NO_STUFF CPU_VSS8
Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55ohm transmission line
-s p
h c
R3C5 0.01
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U2E1D A2 A5 A8 A11 A14 A17 A20 A23 A26 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24
D
C
B
Dothan_Yonah_Processor-Skt
GUADALUPE Title Yonah (2 of 2) Size A Date: Document Number C58015 Thursday, December 11, 2003
2
INTEL CONFIDENTIAL
A
Rev 1.201 Sheet 4
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TP_ADM_1 RP3B2D 4 10K
1
TP_ADM_2
5
CPU Thermal Sensor
9,12..19,21..23,25..30,34,37..41,45,47,50..53,55 Layout Note: Route H_THERMDA and H_THERMDC on same layer. 10 mil trace 10 mil spacing +V3.3S 9,12..19,21..23,25..30,34,37..41,45,47,50..53,55 1 +V3.3S
2
D
J3B3 Default Stuffing: 1-2 3-4 Option Stuffing: 1-X 3-X
J3B3
0.1uF
R3N4 1K
R3N3 1K U3B2 STBY#
RP3B2A 10K 2 3 4 10 6 15 12 14 11 1 5 9 13 16 8
3
C3N2
RP3B2B 10K 7 6
RP3B2C 10K
THERM_DXP 1 3 2X2HDR 2 4 C3N3 2200PF ADD0 ADD1 THERM_DXN Note: If using Thermal Diode Conn, NO STUFF C3N3 and U3B2
3 H_THERMDA 3 H_THERMDC
VCC DXP DXN ADD0 ADD1
STBY# SMBDATA SMBCLK ALERT# NC1 NC2 NC3 NC4 NC5
THRM_ALERT# TP_ADM_NC1 TP_ADM_NC2 TP_ADM_NC3 TP_ADM_NC4 TP_ADM_NC5
SMB_THRM_DATA 27,29 SMB_THRM_CLK 27,29
R3B2 0 NO_STUFF
7 8
GND1 GND2 ADM1023
PM_THRM# 14,15,27,29
3Pin_Recepticle J4A1 NO_STUFF 2 THERMDP 1 THERMDN
Note: No-Stuff R3B2 for normal operation
GND2 GND0 GND1 3 4 5 6 GND3
Thermal Diode Conn
C
Thermal Monitoring Enabled (Default) Disabled
R2B7 Non-stuffed Stuffed
R2B8 Stuffed Non-stuffed
B
A
5
. w w w
12..15,22..25,27,29,35,40,41,44,46,50..52,55 +V3.3A 100K NO_STUFF R2B7 27,29 FAN_ON R2B8 100K
15..17,23,25,29,34,36,38,39,41,45,47,48,50..53
to p la
Q2B3 +V5S 3 2 1 SI7458DP 5 R2B6 1M C2B5 1000pF 4 3 FAN_ON_Q R2B5 100K FAN_ON_D 1 2 Q2B2 BSS138
Fan Power Control
-s p
V5S_FAN C3B1 22uF 1 3
h c
J3B1 1 2
m e
a
m o .c s ic t
Spare Resistor of R-Pack
D
C
B
C4B1 0.1uF
CR4B2 1N4148
CONN2_HDR
GUADALUPE Title CPU Thermal Sensor & Fan Size A Date: Document Number C58015 Thursday, December 11, 2003
2
INTEL CONFIDENTIAL
A
Rev 1.201 Sheet 5
1
of
60
4
3
5
4
3
2
1
H_XRCOMP 3 H_D#[63:0] R4E9 24.9 1% H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 E4 E1 F4 H7 E2 F1 E3 D3 K7 F2 J7 J8 H6 F3 K8 H5 H1 H2 K5 K6 J4 G3 H3 J1 L5 K4 J5 P7 L7 J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6 W6 U3 V5 W8 W7 U2 U1 Y5 Y2 V4 Y7 W1 W3 Y3 Y6 W2 C1 C2 D1 T1 L1 P1
U4E1A HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HADS# HADSTB#0 HADSTB#1 HVREF HBNR# HBPRI# HBREQ0# HCPURST# G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13 F8 B9 E13 J11 A5 D5 E7 H10 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
D
3,4,9,13,15,26,41,45,49,52 +VCCP
R4E10 54.9 1% H_XSCOMP
3,4,9,13,15,26,41,45,49,52 +VCCP
R4E6 221 1% H_XSWING H_XSWING
C
0.1uF
3,4,9,13,15,26,41,45,49,52 +VCCP
R4E5 54.9 1% H_YSCOMP
3,4,9,13,15,26,41,45,49,52 +VCCP
B
H_YSWING
R4E4 221 1% H_YSWING
R4E3 100 1%
C4T5 0.1uF
A
5
. w w w
H_YRCOMP R4E1 24.9 1%
t p la
4
p o
-s
h c
HOST
R4E8 100 1%
C4E1
m e
HCLKINN HCLKINP AB1 AB2 C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5 HDBSY# HDEFER# HDINV#0 HDINV#1 HDINV#2 HDINV#3 HDPWR# HDRDY# HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HEDRDY# HHIT# HHITM# HLOCK# HPCREQ# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HRS0# HRS1# HRS2# HCPUSLP# HTRDY#
a
m o .c s ic t
H_A#[31:3] 3 3,4,9,13,15,26,41,45,49,52 +VCCP H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 R4T4 100 1% H_BNR# 3 H_BPRI# 3 H_BREQ#0 3 H_CPURST# 3,26,29 H_VREF R4T3 200 1% CLK_MCH_BCLK# 30 CLK_MCH_BCLK 30 H_DBSY# 3 H_DEFER# 3 H_DINV#[3:0] 3 H_DPWR# 3 H_DRDY# 3 H_DSTBN#[3:0] 3 H_DSTBP#[3:0] 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_REQ#[4:0] 3 H_RS#[2:0] 3 R2U7 0 NO_STUFF H_CPUSLP# 3,13,29 H_TRDY# 3
D
C
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 TP_H_EDRDY#
H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING
HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING
TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP#_GMCH
B
ALVISO_90
GUADALUPE Title Alviso (1 of 5) Size A Date:
3
INTEL CONFIDENTIAL
A
Document Number C58015 Thursday, December 11, 2003
2
Rev 1.201 Sheet 6
1
of
60
5
4
3
2
1
XDP_OBS0 26 MCH_BSEL1 26 MCH_BSEL0 26 CFG[20:3] 11 14 DMI_TXN[3:0] U4E1B DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 AA31 AB35 AC31 AD35 Y31 AA35 AB31 AC35 AA33 AB37 AC33 AD37 Y33 AA37 AB33 AC37 AM33 AL1 AJ34 AF6 AN33 AK1 AJ33 AF5 AP21 AM21 AH21 AK21 AN16 AM14 AH15 AG16 AF22 AF16 AP14 AL15 AM11 AN10 M_RCOMPN AK10 M_RCOMPP AK11 AF37 AD1 SMXSLEW AE27 AE28 SMYSLEW AF9 AF10 DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMITXP0 DMITXP1 DMITXP2 DMITXP3 SM_CK0 SM_CK1 SM_CK3 SM_CK4 SM_CK0# SM_CK1# SM_CK3# SM_CK4# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CS0# SM_CS1# SM_CS2# SM_CS3# CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25 AE11 AE10 AC10 AD10
Alviso will provide SDVO_CTRLCLK and CTRLDATA pulldowns on-die
U4E1G 12 SDVO_CTRLDATA 12 SDVO_CTRLCLK 30 CLK_MCH_3GPLL# 30 CLK_MCH_3GPLL H24 H25 AB29 AC29 A15 C16 A17 TVIREF J18 B15 B16 B17
D
14 DMI_TXP[3:0]
MISC
14 DMI_RXN[3:0]
14 DMI_RXP[3:0]
18 M_CLK_DDR3 18 M_CLK_DDR4 18 M_CLK_DDR#0 18 M_CLK_DDR#1 18 M_CLK_DDR#3 18 M_CLK_DDR#4
R5U5
255 1%
C
18,20 18,20 18,20 18,20 18,20 18,20 18,20 18,20 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS#0 M_CS#1 M_CS#2 M_CS#3
MCH_P LT _RS T _R
R5R4
100
SM_OCDCOMP0 SM_OCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT
CLK
M_OCDCOMP0 M_OCDCOMP1
Layout note: Route as short as possible
R5R2 40.2 1%
DREF_CLKN DREF_CLKP DREF_SSCLKN DREF_SSCLKP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11
A24 A23 C37 D37 AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37 TP_NC1 TP_NC2 TP_NC3 TP_NC4 TP_NC5 TP_NC6 TP_NC7 TP_NC8 TP_NC9 TP_NC10
DREFCLK# 30 DREFCLK 30 DREFSSCLK# 30 DREFSSCLK 30
TP6F1 TP6E1 TP6E2
NO_STUFF NO_STUFF NO_STUFF
R5R1 40.2 1%
42 M_VREF_MCH
ALVISO_90 9,11,15,16,21,51..53 +V2.5S
B
R5P2 R5P1
10K 10K
PM_EXTTS#0 PM_EXTTS#1
A
5
. w w w
9,21,33,42,52 +V2.5_SM 1 R4R1 80.6 2 1 R4R2 80.6 2
M_RCOMPN M_RCOMPP
t p la
4
p o
J7B1 1 3 2 EPOT_DEFAULT
TP_NC11
-s
L_IBG R7B21 1.5K
17 17 17 17
LA_CLKN LA_CLKP LB_CLKN LB_CLKP
B30 B29 C25 C24 B34 B33 B32 A34 A33 B31 C29 D28 C27 C28 D27 C26
LACLKN LACLKP LBCLKN LBCLKP LADATAN0 LADATAN1 LADATAN2 LADATAP0 LADATAP1 LADATAP2 LBDATAN0 LBDATAN1 LBDATAN2 LBDATAP0 LBDATAP1 LBDATAP2
NC
17 LA_DATAN0 17 LA_DATAN1 17 LA_DATAN2 17 LA_DATAP0 17 LA_DATAP1 17 LA_DATAP2 17 LB_DATAN0 17 LB_DATAN1 17 LB_DATAN2 17 LB_DATAP0 17 LB_DATAP1 17 LB_DATAP2
LVDS
BM_BUSY# EXT_TS0# EXT_TS1# THRMTRIP# PWROK RSTIN#
J23 J21 H22 F5 AD30 AE29
PM_BMBUSY# 14 PM_EXTTS#0 19 PM_EXTTS#1 19 PM_THRMTRIP# 3,13 DELAY_VR_PWRGOOD 14 PLT_RST# 12,14,27,36,37,40,55
h c
21 L_BKLTCTL 21 L_BKLTEN 21,26 LCTLA_CLK 21,26 LCTLB_DATA 21 L_DDC_CLK 21 L_DDC_DATA 17 L_VDDEN
m e
PCI-EXPRESS GRAPHICS
DDR MUXING
Note: CRT_Red, CRT_Green, CRT_Blue are ground referenced.
R5F5
150 1%
16 CRT_RED R5F2 R5F1 39 39 VSYNC HSYNC CRTIREF
16 CRT_VSYNC 16 CRT_HSYNC
VGA
18 M_CLK_DDR0 18 M_CLK_DDR1
CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 TP_ALV_RSVD28 TP_ALV_RSVD29 TP_ALV_RSVD30 TP_ALV_RSVD31
SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC
DMI
R4U6 150 1% R4U5 150 1% R4U4 150 1%
R4T5 4.99k
CFG/RSVD
Layout Note: Place 150 Ohm termination resistors close to GMCH 16 CRT_DDC_CLK 16 CRT_DDC_DATA 16 CRT_BLUE 16 CRT_GREEN E24 E23 E21 D21 C20 B20 A19 B19 H21 G21 J20 DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET
TV
16 TV_DACA_OUT 16 TV_DACB_OUT 16 TV_DACC_OUT
RSVD[27:21]
R5F3 R5F4
150 1% 150 1%
E25 F25 C23 C22 F23 F22 F26 L_IBG C33 L_LVBG C31 L_VREFH F28 L_VREFL F27
a
LBKLT_CRTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL
m o .c s ic t
9 +V1.5S_PCIE EXP_COMPI EXP_ICOMPO D36 D34 PEG_COMP R5T1 24.9 1% EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34 D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34 E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36 D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXN[15:0] 12 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 PEG_RXP[15:0] 12 EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15 ALVISO_90 PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 PEG_TXN[15:0] 12 PEG_TXP[15:0] 12
D
C
PM
B
J7B1 Default: pins 2-3. For EV work jumper pins 1-2
EPOT_WIPER
GUADALUPE Title Alviso (2 of 5) Size A Date:
3
INTEL CONFIDENTIAL
A
Document Number C58015 Thursday, December 11, 2003
2
Rev 1.201 Sheet 7
1
of
60
5
4
3
2
1
D
19 M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AG35 AH35 AL35 AL37 AH36 AJ35 AK37 AL34 AM36 AN35 AP32 AM31 AM34 AM35 AL32 AM32 AN31 AP31 AN28 AP28 AL30 AM30 AM28 AL28 AP27 AM27 AM23 AM22 AL23 AM24 AN22 AP22 AM9 AL9 AL6 AP7 AP11 AP10 AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6 AL4 AM3 AK2 AK3 AG2 AG1 AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5
U4E1C SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63 SA_BS0# SA_BS1# SA_BS2# SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# AK15 AK16 AL21 AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3 AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5 AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4 AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A[13:0] 18,20 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_BS#0 18,20 M_A_BS#1 18,20 M_A_DM[7:0] 19 AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31 AJ31 AK30 AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23 AJ22 AK22 AH24 AH23 AG22 AJ21 AG10 AG9 AG8 AH8 AH11 AH10 AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5
U4E1D SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63
M_A_DQS[7:0] 19
DDR SYSTEM MEMORY A
C
B
ALVISO_90
A
5
. w w w
to p la
4
AN15 AP16 AF29 TP_MA_RCVENIN# AF28 TP_MA_RCVENOUT# AP15
-s p
M_A_CAS# 18,20 M_A_RAS# 18,20 M_A_WE# 18,20
h c
DDR SYSTEM MEMORY B
m e
a
m o .c s ic t
SB_BS0# SB_BS1# SB_BS2# AJ15 AG17 AG21 AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7 M_B_BS#0 18,20 M_B_BS#1 18,20 SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4 AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7# SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A[13:0] 18,20 AH14 AK14 AF15 TP_MB_RCVENIN# AF14 TP_MB_RCVENOUT# AH16 M_B_CAS# 18,20 M_B_RAS# 18,20 M_B_WE# 18,20
D
C
SB_CAS# SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#
B
ALVISO_90
GUADALUPE Title Alviso (3 of 5) Size A Date:
3
INTEL CONFIDENTIAL
A
Document Number C58015 Thursday, December 11, 2003
2
Rev 1.201 Sheet 8
1
of
60
5
4
3
+V3.3S_TVDACA
2
FB4U1 1 3 C4T10 22nF 2 TVDACA_FB C4U1 0.1uF
1
5,12..19,21..23,25..30,34,37..41,45,47,50..53,55 +V3.3S_TVDAC 16,52 4,14,15,51..53 +V1.5S CR5E1 V1_5SFOLLOW 3 +V3.3S
+VCC_GMCH_CORE 45,52 R4T2 0.002 1% C5T3 10uF C5T4 10uF C5T5 10uF C5T2 0.1uF 10 +VCC_GMCH T29 R29 N29 M29 K29 J29 V28 U28 T28 R28 P28 N28 M28 L28 K28 J28 H28 G28 V27 U27 T27 R27 P27 N27 M27 L27 K27 J27 H27 K26 H26 K25 J25 K24 K23 K22 K21 W20 U20 T20 K20 V19 U19 K19 W18 V18 T18 K18 K17 AC2 AC1 B23 C35 AA1 AA2 F19 E19 G19 H20 K13 J13 K12 W11 V11 U11 T11 R11 P11 N11 M11 L11 K11 W10 V10 U10 T10 R10 P10 N10 M10 K10 J10 Y9 W9 U9 R9 P9 N9 M9 L9 J9 N8 M8 N7 M7 N6 M6 A6 N5 M5 N4 M4 N3 M3 N2 M2 B2 V1 N1 M1 G1 U4E1E VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCCH_MPLL1 VCCH_MPLL0 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCC_SYNC VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCA_TVBG VSSA_TVBG VCCD_TVDAC VCCDQ_TVDAC VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCA_LVDS VCCHV0 VCCHV1 VCCHV2 VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCSM52 VCCSM53 VCCSM54 VCCSM55 VCCSM56 VCCSM57 VCCSM58 VCCSM59 VCCSM60 VCCSM61 VCCSM62 VCCSM63 VCCSM64 F17 E17 D18 C18 F18 E18 H18 G18 D19 H17 B26 B25 A25 A35 B22 B21 A21 AM37 AH37 AP29 AD28 AD27 AC27 AP26 AN26 AM26 AL26 AK26 AJ26 AH26 AG26 AF26 AE26 AP25 AN25 AM25 AL25 AK25 AJ25 AH25 AG25 AF25 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 AE15 AE14 AP13 AN13 AM13 AL13 AK13 AJ13 AH13 AG13 AF13 AE13 AP12 AN12 AM12 AL12 AK12 AJ12 AH12 AG12 AF12 AE12 AD11 AC11 AB11 AB10 AB9 AP8 AM1 AE1 B28 A28 A27 AF20 AP19 AF19 AF18 AE37 W37 U37 R37 N37 L37 J37 Y29 Y28 Y27 F37 G37 7,11,15,16,21,51..53 +V2.5S +V2.5S_3GBG R6E2 V2.5_DDR_CAP1 V2.5_DDR_CAP2 C5R3 V2.5_DDR_CAP5 C5R5 C5R2 0.1uF 0.1uF 0.1uF +V1.5S_QTVDAC +V3.3S_TVDACB +V3.3S_TVDACC +V3.3S_ATVBG +V1.5S_TVDAC +V1.5S_DLVDS
C5T6 0.1uF
C4T6 0.1uF
1 2
TVDACB_FB 3 C5U5 0.1uF C5T18 22nF
D
1 2
TVDACC_FB C5U3 0.1uF C5T17 22nF 3
4,14,15,51..53 +V1.5S
+V2.5S_ALVDS
1 2
3 C5T14 22nF
R4D2 0.002 1% +V1.5S_HMPLL
L5U1
+V1.5S_DPLLA
1 2
3 C5E3 22nF
10uH
+ C5F6 470uF
C5T12 0.1uF
L6E1
+V1.5S_DPLLB
Note: All VCCSM pins shorted internally.
1
C
10uH
+ C6E15 470uF
C5T9 0.1uF
L4D2 1 1uH 30% 2
+V1.5S_HPLL
+ C3D6 470uF
C4R5 0.1uF
42 +V2.5_SM_DDR
L4D3 1 1uH 30% 2
+V1.5S_MPLL
+ C3D7 470uF
C4T1 0.1uF
..53 +V2.5S
B
1%
R5F7 0.002 R4E11 1 2 VCCGFOLLOW 10 5% FB5U4
45,52 +VCC_GMCH_CORE CR4F2 3 1 BAT54 1 C5U6 0.1uF 2 +V2.5S_CRTDAC 3 C5U2 22nF
CRTDAC_FB 180ohm@100MHz
+V2.5S_SYNC
Layout note: VSSA_CRTDAC Route caps within 250mil of Alviso. Route FB within 3" of Alviso.
A
,49,52 +VCCP R4T1 0.002 1%
10 +VCCP_GMCH
C4T4 4.7uF
5
. w w w
C5T10 0.1uF Route VSSA_CRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane C4T9 0.47uF C4T8 0.47uF C4T3 C4T2 C4T7 0.22uF 0.22uF 2.2uF
VCCP_GMCH_CAP1
to p la
ALVISO_90
-s p
V2.5_DDR_CAP6 V2.5_DDR_CAP4 V2.5_DDR_CAP3 C5T8 0.1uF
h c
C4R6 10uF
m e
+V2.5S_HV C5T11 0.1uF C5R8 10uF C5C14 330uF R5B33 0.002 1% 0.1uF 7 +V1.5S_PCIE C5T7 10uF
C5F5 10uF
a
3 C5E2 22nF 2 1 100uF
TVDAC_FB C5F2 0.1uF
QTVDAC_FB
POWER
7,11,15,16,21,51..53 +V2.5S R5U17 0.002 1%
m o .c s ic t
180ohm@100MHz FB5U3 1 1 BAT54 180ohm@100MHz R4F1 10 5% 2 FB5U1 R4F2 0.002 1% NO_STUFF 180ohm@100MHz FB5U2 ATVBG_FB C5U4 0.1uF 180ohm@100MHz 4,14,15,51..53 +V1.5S R5U15 0.002 1% Route VSSATVBG gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane C5T13 0.1uF 4,14,15,51..53 +V1.5S 7,11,15,16,21,51..53 +V2.5S R5F8 0.002 1% R5U1 0.002 1% C5T19 0.1uF FB5F1 180ohm@100MHz C5F1 0.1uF 7,11,15,16,21,51..53 +V2.5S R5F6 0.002 1% C5E1 4,14,15,51..53 +V1.5S R4D1 2 DDRDLL_D_L 0.002 1% 1uH 20% L4D1 4,14,15,51..53 +V1.5S L5D1 PCIE_L R6D12 0.002 1%
D
+V1.5S_DLVDS
C5T15 10uF
+V2.5S_ALVDS
C5T20 0.01uF
+V2.5S_TXLVDS
0.1uF
C5T16 4.7uF
C
7,21,33,42,52 +V2.5_SM
+V1.5S_DDRDLL
C5R1 + C4C18
B
Note: All VCCSM pins shorted internally.
C4R1 C4R2 C4R3 0.1uF 0.1uF 0.1uF
C5R4 10uF
C6E3 220uF
91nH 20%
VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2 VCCA_SM0 VCCA_SM1 VCCA_SM2 VCCA_SM3 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6
+V2.5S_TXLVDS
+V1.5S_3GPLL R6R1 C5R7 0.1uF C5T1 10uF 3GPLL_R_L 0.5 1% 1
4,14,15,51..53 +V1.5S L6D1 1uH R6D10 0.002 1% 3GPLL_FB_L 2 20%
GUADALUPE Title Alviso (4 of 5) Size A Date:
3
INTEL CONFIDENTIAL
A
VCCA_3GPLL0 VCCA_3GPLL1 VCCA_3GPLL2 VCCA_3GBG VSSA_3GBG
VCCP_GMCH_CAP2 VCCP_GMCH_CAP3 VCCP_GMCH_CAP4
0.002 1%
Document Number C58015 Thursday, December 11, 2003
2
Rev 1.201 Sheet 9
1
of
60
4
A
B36 VSSALVDS
B
C
D
5
18,21,42 +V2.5_DDR 9 +VCCP_GMCH L12 M12 N12 P12 R12 T12 U12 V12 W12 L13 M13 N13 P13 R13 T13 U13 V13 W13 VTT_NCTF17 VTT_NCTF16 VTT_NCTF15 VTT_NCTF14 VTT_NCTF13 VTT_NCTF12 VTT_NCTF11 VTT_NCTF10 VTT_NCTF9 VTT_NCTF8 VTT_NCTF7 VTT_NCTF6 VTT_NCTF5 VTT_NCTF4 VTT_NCTF3 VTT_NCTF2 VTT_NCTF1 VTT_NCTF0 VCCSM_NCTF31 VCCSM_NCTF30 VCCSM_NCTF29 VCCSM_NCTF28 VCCSM_NCTF27 VCCSM_NCTF26 VCCSM_NCTF25 VCCSM_NCTF24 VCCSM_NCTF23 VCCSM_NCTF22 VCCSM_NCTF21 VCCSM_NCTF20 VCCSM_NCTF19 VCCSM_NCTF18 VCCSM_NCTF17 VCCSM_NCTF16 VCCSM_NCTF15 VCCSM_NCTF14 VCCSM_NCTF13 VCCSM_NCTF12 VCCSM_NCTF11 VCCSM_NCTF10 VCCSM_NCTF9 VCCSM_NCTF8 VCCSM_NCTF7 VCCSM_NCTF6 VCCSM_NCTF5 VCCSM_NCTF4 VCCSM_NCTF3 VCCSM_NCTF2 VCCSM_NCTF1 VCCSM_NCTF0 AB12 AC12 AD12 AB13 AC13 AD13 AC14 AD14 AC15 AD15 AC16 AD16 AC17 AD17 AC18 AD18 AC19 AD19 AC20 AD20 AC21 AD21 AC22 AD22 AC23 AD23 AC24 AD24 AC25 AD25 AC26 AD26
5
. w w w to p la -s p h c
NCTF
Title Size A GUADALUPE Alviso (5 of 5) Document Number C58015 Thursday, December 11, 2003
2 4 3
4 3
VSS
Y12 VSS_NCTF68 AA12 VSS_NCTF67 Y13 VSS_NCTF66 AA13 VSS_NCTF65 L14 VSS_NCTF64 M14 VSS_NCTF63 N14 VSS_NCTF62 P14 VSS_NCTF61 R14 VSS_NCTF60 T14 VSS_NCTF59 U14 VSS_NCTF58 V14 VSS_NCTF57 W14 VSS_NCTF56 Y14 VSS_NCTF55 AA14 VSS_NCTF54 AB14 VSS_NCTF53 L15 VSS_NCTF52 M15 VSS_NCTF51 N15 VSS_NCTF50 P15 VSS_NCTF49 R15 VSS_NCTF48 T15 VSS_NCTF47 U15 VSS_NCTF46 V15 VSS_NCTF45 W15 VSS_NCTF44 Y15 VSS_NCTF43 AA15 VSS_NCTF42 AB15 VSS_NCTF41 L16 VSS_NCTF40 M16 VSS_NCTF39 N16 VSS_NCTF38 P16 VSS_NCTF37 R16 VSS_NCTF36 T16 VSS_NCTF35 U16 VSS_NCTF34 V16 VSS_NCTF33 W16 VSS_NCTF32 Y16 VSS_NCTF31 AA16 VSS_NCTF30 AB16 VSS_NCTF29 R17 VSS_NCTF28 Y17 VSS_NCTF27 AA17 VSS_NCTF26 AB17 VSS_NCTF25 AA18 VSS_NCTF24 AB18 VSS_NCTF23 AA19 VSS_NCTF22 AB19 VSS_NCTF21 AA20 VSS_NCTF20 AB20 VSS_NCTF19 R21 VSS_NCTF18 Y21 VSS_NCTF17 AA21 VSS_NCTF16 AB21 VSS_NCTF15 Y22 VSS_NCTF14 AA22 VSS_NCTF13 AB22 VSS_NCTF12 Y23 VSS_NCTF11 AA23 VSS_NCTF10 AB23 VSS_NCTF9 Y24 VSS_NCTF8 AA24 VSS_NCTF7 AB24 VSS_NCTF6 Y25 VSS_NCTF5 AA25 VSS_NCTF4 AB25 VSS_NCTF3 Y26 VSS_NCTF2 AA26 VSS_NCTF1 AB26 VSS_NCTF0
VCC_NCTF78 VCC_NCTF77 VCC_NCTF76 VCC_NCTF75 VCC_NCTF74 VCC_NCTF73 VCC_NCTF72 VCC_NCTF71 VCC_NCTF70 VCC_NTTF69 VCC_NCTF68 VCC_NCTF67 VCC_NCTF66 VCC_NCTF65 VCC_NCTF64 VCC_NCTF63 VCC_NCTF62 VCC_NCTF61 VCC_NCTF60 VCC_NCTF59 VCC_NCTF58 VCC_NCTF57 VCC_NCTF56 VCC_NCTF55 VCC_NCTF54 VCC_NCTF53 VCC_NCTF52 VCC_NCTF51 VCC_NCTF50 VCC_NCTF49 VCC_NCTF48 VCC_NCTF47 VCC_NCTF46 VCC_NCTF45 VCC_NCTF44 VCC_NCTF43 VCC_NCTF42 VCC_NCTF41 VCC_NCTF40 VCC_NCTF39 VCC_NCTF38 VCC_NCTF37 VCC_NCTF36 VCC_NCTF35 VCC_NCTF34 VCC_NCTF33 VCC_NCTF32 VCC_NCTF31 VCC_NCTF30 VCC_NCTF29 VCC_NCTF28 VCC_NCTF27 VCC_NCTF26 VCC_NCTF25 VCC_NCTF24 VCC_NCTF23 VCC_NCTF22 VCC_NCTF21 VCC_NCTF20 VCC_NCTF19 VCC_NCTF18 VCC_NCTF17 VCC_NCTF16 VCC_NCTF15 VCC_NCTF14 VCC_NCTF13 VCC_NCTF12 VCC_NCTF11 VCC_NCTF10 VCC_NCTF9 VCC_NCTF8 VCC_NCTF7 VCC_NCTF6 VCC_NCTF5 VCC_NCTF4 VCC_NCTF3 VCC_NCTF2 VCC_NCTF1 VCC_NCTF0
L17 M17 N17 P17 T17 U17 V17 W17 L18 M18 N18 P18 R18 Y18 L19 M19 N19 P19 R19 Y19 L20 M20 N20 P20 R20 Y20 L21 M21 N21 P21 T21 U21 V21 W21 L22 M22 N22 P22 R22 T22 U22 V22 W22 L23 M23 N23 P23 R23 T23 U23 V23 W23 L24 M24 N24 P24 R24 T24 U24 V24 W24 L25 M25 N25 P25 R25 T25 U25 V25 W25 L26 M26 N26 P26 R26 T26 U26 V26 W26
m e
Date: Sheet 10
1
a
9 +VCC_GMCH U4E1H ALVISO_90
2
Y1 VSS271 D2 VSS270 G2 VSS269 J2 VSS268 L2 VSS260 P2 VSS259 T2 VSS258 V2 VSS257 AD2 VSS256 AE2 VSS255 AH2 VSS254 AL2 VSS253 AN2 VSS252 A3 VSS251 C3 VSS250 AA3 VSS249 AB3 VSS248 AC3 VSS247 AJ3 VSS246 C4 VSS245 H4 VSS244 L4 VSS243 P4 VSS242 U4 VSS241 Y4 VSS240 AF4 VSS239 AN4 VSS238 E5 VSS237 W5 VSS236 AL5 VSS235 AP5 VSS234 B6 VSS233 J6 VSS232 L6 VSS231 P6 VSS230 T6 VSS229 AA6 VSS228 AC6 VSS227 AE6 VSS226 AJ6 VSS225 G7 VSS224 V7 VSS223 AA7 VSS222 AG7 VSS221 AK7 VSS220 AN7 VSS219 C8 VSS218 E8 VSS217 L8 VSS216 P8 VSS215 Y8 VSS214 AL8 VSS213 A9 VSS212 H9 VSS211 K9 VSS210 T9 VSS209 V9 VSS208 AA9 VSS207 AC9 VSS206 AE9 VSS205 AH9 VSS204 AN9 VSS203 D10 VSS202 L10 VSS201 Y10 VSS200 AA10 VSS199 F11 VSS198 H11 VSS197 Y11 VSS196 AA11 VSS195 AF11 VSS194 AG11 VSS193 AJ11 VSS192 AL11 VSS191 AN11 VSS190 B12 VSS189 D12 VSS188 J12 VSS187 A14 VSS186 B14 VSS185 F14 VSS184 J14 VSS183 K14 VSS182 AG14 VSS181 AJ14 VSS180 AL14 VSS179 AN14 VSS178 C15 VSS177 K15 VSS176 A16 VSS175 D16 VSS174 H16 VSS173 K16 VSS172 AL16 VSS171 C17 VSS170 G17 VSS169 AF17 VSS168 AJ17 VSS167 AN17 VSS166 A18 VSS165 B18 VSS164 U18 VSS163 AL18 VSS162 C19 VSS161 H19 VSS160 J19 VSS159 T19 VSS158 W19 VSS157 AG19 VSS156 AN19 VSS155 A20 VSS154 D20 VSS153 E20 VSS152 F20 VSS151 G20 VSS150 V20 VSS149 AK20 VSS148 C21 VSS147 F21 VSS146 AF21 VSS145 AN21 VSS144 A22 VSS143 D22 VSS142 E22 VSS141 J22 VSS140 AH22 VSS139 AL22 VSS138 H23 VSS137 AF23 VSS136 B24 VSS135 D24 VSS134 F24 VSS133 J24 VSS132 AG24 VSS131 AJ24 VSS130 U4E1F ALVISO_90
VSS267 VSS266 VSS265 VSS264 VSS263 VSS262 VSS261 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
AL24 AN24 A26 E26 G26 J26 B27 E27 G27 W27 AA27 AB27 AF27 AG27 AJ27 AL27 AN27 E28 W28 AA28 AB28 AC28 A29 D29 E29 F29 G29 H29 L29 P29 U29 V29 W29 AA29 AD29 AG29 AJ29 AM29 C30 Y30 AA30 AB30 AC30 AE30 AP30 D31 E31 F31 G31 H31 J31 K31 L31 M31 N31 P31 R31 T31 U31 V31 W31 AD31 AG31 AL31 A32 C32 Y32 AA32 AB32 AC32 AD32 AJ32 AN32 D33 E33 F33 G33 H33 J33 K33 L33 M33 N33 P33 R33 T33 U33 V33 W33 AD33 AF33 AL33 C34 AA34 AB34 AC34 AD34 AH34 AN34 B35 D35 E35 F35 G35 H35 J35 K35 L35 M35 N35 P35 R35 T35 U35 V35 W35 Y35 AE35 C36 AA36 AB36 AC36 AD36 AE36 AF36 AJ36 AL36 AN36 E37 H37 K37 M37 P37 T37 V37 Y37 AG37
1
m o .c s ic t
INTEL CONFIDENTIAL
of 60 Rev 1.201
A
B
C
D
5
4
3
2
LAYOUT NOTE: TEST CAPS Place on BOTTOM of the board
TP_A22 C1P4 1 2 10pFTP_B22
1
Ohlone CRB is strapped for PCI-E lane reversal for ease of routing. If in integrated gfx mode, need to use lane-reversal ADD2 add-in card since SDVO i/f does not support lane reversal.
7 CFG5 7 CFG9
LAYOUT NOTE: TEST CAPS Place on TOP of the board
TP_A1 TP_A2 TP_A3 TP_A4 TP_A5 C5J3 1 C5J2 C4H1 C5J4 C2F1 C2F2 C4H2 C5J5 C5J6 2 10pFTP_B1 22pF 0.01uF 0.1uF 1.0uF 0.1uF 10pF 18PF 33pF TP_B2 TP_B3 TP_B4 TP_B5 TP_B6 TP_B7 TP_B8 TP_B9
D
CFG5
Low = DMIx2 High = DMIx4
R1F5 2.2K 5% NO_STUFF
CFG9 PCIe Graphics Lane
Low = Reverse Lane High = Normal operation
R1E16 2.2K 5%
TP_A6 TP_A7 TP_A8 TP_A9
7,9,15,16,21,51..53 +V2.5S
TP_A10 CP1B2A 1 TP_A11 C5J7 TP_A12 C5J8 TP_A13 C5J9 TP_A14 C2F3
TP_B10 8 47PF 47pF .01uF TP_B11 TP_B12
J5G2
0.047uF TP_B13 0.47uF 1uF 2.2uF 3.3uF 10uF 100uF 5.6pF + TP_B14 TP_B15
7 CFG7 CFG18_R CFG18 (VCC Select) Low = 1.05V High = 1.5V
TP_A15 C1B2 TP_A16 C4B2
CFG7 (CPU Strap)
Low = DT/Transportable CPU High = Mobile CPU
R1T3 2.2K 5% NO_STUFF
R5U22 1K
TP_A17 C3B3 TP_A18 C3B2 TP_A19 C1C5 TP_A20 C4B3
7 CFG18
C
7,9,15,16,21,51..53 +V2.5S
7 CFG16 R5U21 1K NO_STUFF
CFG19 (VTT Select) CFG16 (FSB Dynamic ODT) Low = Dynamic ODT Disabled High = Dynamic ODT Enabled R1E15 2.2K 5% NO_STUFF
Low = 1.05V High = 1.2V
7 CFG19
CFG[17:3] have internal pullup resistors. CFG[19:18] have internal pulldown resistors
B
7 CFG6
A
5
. w w w
CFG6 Low = DDR-II High = DDR-I
to p la
R1T2 2.2K 5% NO_STUFF
-s p
h c
m e
TP_A21 C1D1 6.8uF +
a
TP_B17 TP_B18 TP_B19 TP_B20 TP_B21
TP_B16
m o .c s ic t
TP_A23 C1P5 22pF TP_B23 TP_A24 C1P3 0.01uF 0.1uF TP_B24 TP_A25 C1P6 TP_B25 TP_A26 C1R3 1.0uF TP_B26 TP_A27 C1R6 TP_B27 0.1uF NO_STUFF TP_A28 C1P7 0.33uF TP_B28 TP_B29 TP_B30 TP_B31 TP_B32 TP_A29 C1R1 TP_A30 C1R2 TP_A31 C1R5 TP_A32 C1R4 2.2uF 4.7uF 4.7uF 10uF TP_A33 C5Y1 TP_B33 22uF NO_STUFF +
D
C
B
GUADALUPE Title Alviso Strapping Size A Date: Document Number C58015 Thursday, December 11, 2003
2
INTEL CONFIDENTIAL
A
Rev 1.201 Sheet 11
1
of
60
4
3
5
4
3
2
1
+V12S_PEG
+V12S_PEG J6C1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 +12V1 +12V2 +12V3 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG1 3.3VAUX WAKE# Key RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5 HSOP_1 HSON_1 GND10 GND11 HSOP_2 HSON_2 GND12 GND13 HSOP_3 HSON_3 GND14 RSVD3 PRSNT2#1 GND15 HSOP_4 HSON_4 GND22 GND23 HSOP_5 HSON_5 GND24 GND25 HSOP_6 HSON_6 GND26 GND27 HSOP_7 HSON_7 GND28 PRSNT2#2 GND29 HSOP_8 HSON_8 GND38 GND39 HSOP_9 HSON_9 GND40 GND41 HSOP_10 HSON_10 GND42 GND43 HSOP_11 HSON_11 GND44 GND45 HSOP_12 HSON_12 GND46 GND47 HSOP_13 HSON_13 GND48 GND49 HSOP_14 HSON_14 GND50 GND51 HSOP_15 HSON_15 GND52 PRSNT2#3 RSVD4 PRSNT1# +12V4 +12V5 GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3 PWRGD GND7 REFCLK+ REFCLKGND8 HSIP_0 HSIN_0 GND9 RSVD5 GND16 HSIP_1 HSIN_1 GND17 GND18 HSIP_2 HSIN_2 GND19 GND20 HSIP_3 HSIN_3 GND21 RSVD6 RSVD7 GND30 HSIP_4 HSIN_4 GND31 GND32 HSIP_5 HSIN_5 GND33 GND34 HSIP_6 HSIN_6 GND35 GND36 HSIP_7 HSIN_7 GND37 RSVD8 GND54 HSIP_8 HSIN_8 GND55 GND56 HSIP_9 HSIN_9 GND57 GND58 HSIP_10 HSIN_10 GND59 GND60 HSIP_11 HSIN_11 GND61 GND62 HSIP_12 HSIN_12 GND63 GND64 HSIP_13 HSIN_13 GND65 GND66 HSIP_14 HSIN_14 GND67 GND68 HSIP_15 HSIN_15 GND69 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 +V3.3S_PEG
D
+V3.3S_PEG
13,29 SMB_CLK_S4 13,29 SMB_DATA_S4 5,13..15,22..25,27,29,35,40,41,44,46,50..52,55 +V3.3A
0 PLT_RST#_R
R6C3 NO_STUFF R6C4 0
PLT_GATED_RST# 27,31,32 PLT_RST# 7,14,27,36,37,40,55
14,15,25,32,55 PCIE_WAKE#
7 PEG_TXP[15:0] 7 PEG_TXN[15:0] 7 SDVO_CTRLCLK
PEG_TXP15 PEG_TXN15
C6C7 0.1uF C6C8 0.1uF C6C9 0.1uF C6C10 0.1uF C6C11 0.1uF C6C12 0.1uF C6C13 0.1uF C6C14 0.1uF
PEG_C_TXP15 PEG_C_TXN15
PEG_RXP15 PEG_RXN15
CLK_PCIE_PEG 30 CLK_PCIE_PEG# 30 PEG_RXP[15:0] 7 PEG_RXN[15:0] 7
PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12
PEG_C_TXP14 PEG_C_TXN14 PEG_C_TXP13 PEG_C_TXN13 PEG_C_TXP12 PEG_C_TXN12
PEG_RXP14 PEG_RXN14 PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12
C
7 SDVO_CTRLDATA PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8
C6D2 0.1uF C6D3 0.1uF C6D5 0.1uF C6D6 0.1uF C6D7 0.1uF C6D8 0.1uF C6D9 0.1uF C6D10 0.1uF C6D12 0.1uF C6D13 0.1uF C6D15 0.1uF C6D16 0.1uF C6E1 0.1uF C6E2 0.1uF C6E4 0.1uF C6E5 0.1uF C6E6 0.1uF C6E7 0.1uF C6E8 0.1uF C6E9 0.1uF
PEG_C_TXP11 PEG_C_TXN11 PEG_C_TXP10 PEG_C_TXN10 PEG_C_TXP9 PEG_C_TXN9 PEG_C_TXP8 PEG_C_TXN8
PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9
PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5 PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0
PEG_C_TXP7 PEG_C_TXN7 PEG_C_TXP6 PEG_C_TXN6 PEG_C_TXP5 PEG_C_TXN5 PEG_C_TXP4 PEG_C_TXN4 PEG_C_TXP3 PEG_C_TXN3
B
C6E11 0.1uF C6E12 0.1uF C6E13 0.1uF C6E14 0.1uF
A
5
. w w w
Layout Note: place AC coupling caps close to Alviso. All AC coupling caps are 0603 size.
t p la
PEG_C_TXP2 PEG_C_TXN2 PEG_C_TXP1 PEG_C_TXN1 PEG_C_TXP0 PEG_C_TXN0
p o
PCIE_X16
-s
PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0
h c
m e
a
m o .c s ic t
51,52 +VBAT_S4 16,17,51,52 +VBATS +V12S_PEG R6B7 0.002 1% R6N6 0.002 1% NO_STUFF + C6B11 100uF C6B7 22uF C6B5 22uF C6B10 0.1uF C6B9 0.1uF C6B8 0.1uF 13,22,23,27,29,31,33,41,42,45,51..53,55 5,9,13..19,21..23,25..30,34,37..41,45,47,50..53,55 +V3.3S R6C1 0.002 1% +V3.3 R6C2 0.002 1% NO_STUFF + C6C6 100uF C6C4 22uF C6B13 22uF C6B12 0.1uF C6C5 0.1uF C6C3 0.1uF
D
C
B
For D3 HOT/ D3 ON: Stuff R6N6, R6C2 and R6C3, unstuff R6B7, R6C1 and R6C4.
+V3.3S_PEG
5,13..15,22..25,27,29,35,40,41,44,46,50..52,55
+V3.3A
C6C2 22uF
C6C1 0.1uF
GUADALUPE Title PCI Express Graphics Size A Date: Document Number C58015 Thursday, December 11, 2003
2
INTEL CONFIDENTIAL
A
Rev 1.201 Sheet 12
1
of
60
4
3
5
+V3.3A CR6H1 1 BAT54 CR6H2 BAT_D R6H13 1K BAT 1 2 1 BAT54 R6H17 1M 3 R6H16 180K C6H5 0.1uF J6H1 3 15 +V3.3A_RTC C6H7 1uF
4
3
2
1
5,22..25,27,29,35,40,41,44,46,50..52,55
RTC Circuitry
D
1
2 1 1 R8V9 10M 4 2 RTC_X1 RTC_X2 RTC_RST# SM_INTRUDER# Y1 Y2 AA2 AA3 AA5 D12 B12 D11 F13 F12 B11 E12 E11 C13 C12 C11 E13 C10 B9 A10 F11 F10 B10 C9 AC19 AE3 AD3 AG2 AF2 AD7 AC7 AF6 AG6 AC2 AC1
C8V1 10pF Y8G1 32.768KHZ Cap values depend on Xtal
RTC
LPC
BT5H1 Battery_Holder
CMOS Settings Clear CMOS Keep CMOS
J6H1 Shunt Open
+V3.3 C8U1 0.1uF TP_EEP_DC TP_EEP_ORG 8 7 6 5
1
2
U7F3A RTCX1 RTCX2 RTCRST# LAD[0] LAD[1]/FB[1] LAD[2]/FB[2] LAD[3]/FB[3] P2 N3 N5 N4 N6 P4 P3 AF22 AF23 AE27 H_CPUSLP#_R AE24 AD27 AF24 H_DPSLP#_R H_FERR_R LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 27,29,36,37,40 27,29,36,37,40 27,29,36,37,40 27,29,36,37,40
C8V2 10pF
12,22,23,27,29,31,33,41,42,45,51..53,55
INTRUDER# INTVRMEN EE_CS EE_SHCLK EE_DOUT EE_DIN LAN_CLK
LDRQ[0]# LDRQ[1]#/GPI[41] LFRAME# A20GATE A20M# CPUSLP#
ICH_DRQ#0 40 ICH_DRQ#1 40 LPC_FRAME# 27,29,36,37,40 H_A20GATE 28 H_A20M# 3 R2U9 0 H_DPRSTP#_R R6V8 0
U8F3 VCC CS DC SK ORG DI GND DO AT88SC153 1 2 3 4 EEP_CS EEP_SK EEP_DOUT EEP_DIN 32 LAN_JCLK 32 LAN_RSTSYNC
CPU
LAN_RSTSYNC LANRXD[0] LANRXD[1] LANRXD[2] LANTXD[0] LANTXD[1] LANTXD[2] ACZ_BIT_CLK ACZ_SYNC ACZ_RST# ACZ_SDIN[0] ACZ_SDIN[1] ACZ_SDIN[2] ACZ_SDO SATALED#
X1, X2 Docking
ACZ_SYNC PORT X LINE R7U4
5,9,12,14..19,21..23,25..30,34,37..41,45,47,50..53,55
+V3.3S
32 LAN_RXD0 32 LAN_RXD1 32 LAN_RXD2 32 LAN_TXD0 32 LAN_TXD1 32 LAN_TXD2
DPRSTP#/TP[4] DPSLP#/TP[2] FERR#
C
1 0
1X2, 2X1 4X1
STUFF UNSTUFF
R7U4 1K NO_STUFF
CPUPWRGD/GPO[49] IGNNE# INIT3_3V# INIT# INTR RCIN# NMI SMI#
AG25 AG26 AE22 AF27 AG24 AD23
AC-97/AZALIA
22 ACZ_BITCLK 22 ACZ_SYNC 22 ACZ_RST# 22 ACZ_SDATAIN0 22 ACZ_SDATAIN1 22 ACZ_SDATAIN2 22 ACZ_SDATAOUT
21..23,25..30,34,37..41,45,47,50..53,55
+V3.3S
R7J7 330 5,9,12,14..19,21..23,25..30,34,37..41,45,47,50..53,55 LED_R 2 C7J12 CR7J1 GREEN 50 ATA_LED# 4 1 5 U7J1 1 2 3 0.1uF
+V3.3S
R7J2 10K
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
74AHC1G08
SATA_LED# IDE_PDACTIVE# 34
B
Place within 500mils of ICH6 ball
38 SATA_RXN0 38 SATA_RXP0 38 SATA_TXN0 38 SATA_TXP0 39 SATA_RXN2 39 SATA_RXP2 39 SATA_TXN2
C8V5 C8V3 C8V7 C8V6
C7H5 C7H6 C7H4 C7H3
A
39 SATA_TXP2
Placement note
Distance between the ICH-6 M and cap on the "P" signal should be identical distance between the ICH-6 M and cap on the "N" signal for same pair.
5
. w w w
3900pF 3900pF 3900pF SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C 3900pF 5,9,12,14..19,21..23,25..30,34,37..41,45,47,50..53,55 SATA_RXN2_C SATA_RXP2_C SATA_TXN2_C SATA_TXP2_C 3900pF 3900pF 3900pF 3900pF
to p la
SATA_RBIAS_PN R7H1 24.9 1% +V3.3S R7D10 R7D1 R7R3 10K 10K 10K EN2 EN3 EN4 R7C24 R7D2 R6D4 R6D11 R9A2 R9A5 10K 10K 10K 10K 10K 10K SMB_CLK_S2 SMB_DATA_S2 SMB_CLK_S3 SMB_DATA_S3 SMB_CLK_S4 SMB_DATA_S4
30 CLK_PCIE_SATA# 30 CLK_PCIE_SATA
SATA_CLKN SATA_CLKP
AG11 AF11
SATARBIAS# SATARBIAS
SATA IDE
SATA_RXN2_C SATA_RXP2_C SATA_TXN2_C SATA_TXP2_C
34 IDE_PDIORDY 34 INT_IRQ14 34 IDE_PDDACK# 34 IDE_PDIOW# 34 IDE_PDIOR#
-s p
SATA[0]RXN SATA[0]RXP SATA[0]TXN SATA[0]TXP SATA[2]RXN SATA[2]RXP SATA[2]TXN SATA[2]TXP AF16 AB16 AB15 AC14 AE16 IORDY IDEIRQ DDACK# DIOW# DIOR# ICH-6_M EN1 R7R2 10K SMB_CLK_A1 R9D1 10K SMB_DATA_A1 R9D2 10K
h c
STPCLK# THRMTRIP# DA[0] DA[1] DA[2] DCS1# DCS3# DD[0] DD[1] DD[2] DD[3] DD[4] DD[5] DD[6] DD[7] DD[8] DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15] DDREQ
AF25 AG27H_SMI#_R AE26 AE23
AC16 AB17 AC17 AD16 AE17
m e
H_NMI 3,29 H_THERMTRIP_R
H_PWRGD 3,29
H_IGNNE# 3 FWH_INIT# 37 H_INIT# 3 H_INTR 3
H_RCIN# 15,27,29
a
R6V11 0
H_CPUSLP# 3,6,29
m o .c s ic t
3,4,6,9,15,26,41,45,49,52 +VCCP NO_STUFF R6V6 Open J5G1 for Dothan A step Shunt for Dothan B step & all Yonah 56 H_DPSLP#
D
3
Layout note: place testpoint next to jumper J5G1
3,4,6,9,15,26,41,45,49,52 +VCCP
LAN
R5G3 0 NO_STUFF
R6V12 56
H_DPSLP# 3,29
J5G1
H_DPRSTP# 3,29 56
R6V10
H_FERR# 3
TP6H2
C
1Pin_HDR NO_STUFF
3,4,6,9,15,26,41,45,49,52 +VCCP H_SMI# 3,29 R6V9 75 PM_THRMTRIP# 3,7
H_STPCLK# 3 R6V7 56
IDE_PDA0 34 IDE_PDA1 34 IDE_PDA2 34 IDE_PDCS1# 34 IDE_PDCS3# 34
Layout note: R6V7 needs to placed within 2" of ICH6, R6V9 must be placed within 2" of R6V7 w/o stub.
AD14 AF15 AF14 AD12 AE14 AC11 AD11 AB11 AE13 AF13 AB12 AB13 AC13 AE15 AG15 AD13 AB14
IDE_PDD0 34 IDE_PDD1 34 IDE_PDD2 34 IDE_PDD3 34 IDE_PDD4 34 IDE_PDD5 34 IDE_PDD6 34 IDE_PDD7 34 IDE_PDD8 34 IDE_PDD9 34 IDE_PDD10 34 IDE_PDD11 34 IDE_PDD12 34 IDE_PDD13 34 IDE_PDD14 34 IDE_PDD15 34 5,12,14,15,22..25,27,29,35,40,41,44,46,50..52,55 IDE_PDDREQ 34
B
5,12,14,15,22..25,27,29,35,40,41,44,46,50..52,55 +V3.3A
+V3.3A
C7C6 0.1uF U7C3 R7P3 R7P5 R7R1 R7P4 10K 10K 10K 10K CL1 CL2 DA1 DA2 1 2 18 19 3 4 EN1 EN2 EN3 EN4 7 11 14 17 10 EXPSCL1 EXPSCL2 EXPSDA1 EXPSDA2 SCL0 SDA0 EN1 EN2 EN3 EN4 VSS VCC SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 SCL4 SDA4 20 5 6 8 9 12 13 15 16 SMB_CLK_A1 23..25,55 SMB_DATA_A1 23..25,55 SMB_CLK_S2 17..19 SMB_DATA_S2 17..19 SMB_CLK_S3 30 SMB_DATA_S3 30 SMB_CLK_S4 12,29 SMB_DATA_S4 12,29
14,15,29,31,32 SMB_CLK 14,15,29,31,32 SMB_DATA
EXP. 5-CH-I2C HUB +V3.3A
5,12,14,15,22..25,27,29,35,40,41,44,46,50..52,55
GUADALUPE Title ICH-6M (1 of 3) Size A Date:
3
INTEL CONFIDENTIAL
A
Document Number C58015 Thursday, December 11, 2003
2
Rev 1.201 Sheet 13
1
of
60
4
5
23,24 PCI_AD[31:0] U7F3B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 E2 E5 C2 F5 F3 E9 F2 D6 E6 D3 A2 D2 D5 H3 B4 J5 K2 K5 D4 L6 G3 H4 H2 H5 B3 M6 B2 K6 K3 A5 L1 K4 J3 N2 L2 M1 L3 AC5 AD5 AF4 AG4 AC9 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]
4
3
+V3.3S 5,9,12,13,15..19,21..23,25..30,34,37..41,45,47,50..53,55 PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#3 PCI_GNT#3 15,24 24 15,24 24 15,23 23 15,23 23
2
1
PCI
PCI-EXPRESS
D
REQ[0]# GNT[0]# REQ[1]# GNT[1]# REQ[2]# GNT[2]# REQ[3]# GNT[3]# REQ[4]#/GPI[40] GNT[4]#/GPO[48] REQ[5]#/GPI[1] GNT[5]#/GPO[17] REQ[6]#/GPI[0] GNT[6]#/GPO[16] C/BE[0]# C/BE[1]# C/BE[2]# C/BE[3]# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# PLTRST# PCICLK PME# PIRQ[E]#/GPI[2] PIRQ[F]#/GPI[3] PIRQ[G]#/GPI[4] PIRQ[H]#/GPI[5] RSVD[6] RSVD[7] RSVD[8] RSVD[9]
L5 C1 B5 B6 M5 F1 B8 C8 F7 E7 E8 F6 B7 D8 J6 H6 G4 G2 A3 E1 R2 C3 E3 C5 G5 J1 J2 R5 G6 P6 D9 C7 C6 M3 AD9 AF8 AG8 U3
Layout Note: Place stuffing option to minimize stubs.
ICH_GPI40_R PCI_GNT#5_R ICH_GPI0_R FWH_WP#_R
R7U18
100
U7F3C 15,29,40 PM_RI# R6W5 R6W1 R6W3 R6W6 13,15,29,31,32 SMB_CLK 13,15,29,31,32 SMB_DATA 15,29 SMB_LINK_ALERT# 15 SMLINK0 15 SMLINK1 MCH_SYNC# 22 ACZ_SPKR 27,29,40,55 PM_SUS_STAT# 50 PM_SYSRST# 7 PM_BMBUSY# 100 100 100 100 SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3 T2 AF17 AE18 AF18 AG18 Y4 W5 Y5 W4 U6 AG21 F8 W3 U2 AD19 SMC_RUNTIME_SCI#_R AE19 SMC_EXTSMI#_R R1 R6W8 10K 5% NO_STUFF R6W9 10K 5% NO_STUFF R7W8 15,17,32 SMB_ALERT# OP2_R SMC_WAKE_SCI#_R 0 PM_STPPCI_ICH# TP_GPO19 R7W7 29,34 PATA_PWR_EN# 0 PM_STPCPU_ICH# W6 M2 R6 AC21 AB21 AD22 RI# SATA[0]GP/GPIO[26] SATA[1]GP/GPIO[29] SATA[2]GP/GPIO[30] SATA[3]GP/GPIO[31] SMBCLK SMBDATA LINKALERT# SMLINK[0] SMLINK[1] MCH_SYNC# SPKR
FWH_TBL# 29,37 PCI_REQ#5 15,24 R7U17 100
HSIN[0] HSIP[0] HSON[0] HSOP[0] HSIN[1] HSIP[1] HSON[1] HSOP[1] HSIN[2] HSIP[2] HSON[2] HSOP[2] HSIN[3] HSIP[3] HSON[3] HSOP[3]
GPIO
PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
23,24 23,24 23,24 23,24
15,23,24 PCI_FRAME# 15,23 15,23,24 15,23 15,23 INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# RSVD_1 RSVD_2
FRAME# PIRQ[A]# PIRQ[B]# PIRQ[C]# PIRQ[D]# RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5] ICH-6_M
PLT_RST# 7,12,27,36,37,40,55 CLK_ICHPCI 30 PCI_PME# 23,24,29 INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# RSVD_6 RSVD9
GPI[7] GPI[8] SMBALERT#/GPI[11] GPI[12] GPI[13] STP_PCI#/GPO[18] GPO[19] STP_CPU#/GPO[20] GPO[21] GPO[23]
Direct Media Interface
PCI_IRDY# 15,23,24 PCI_PAR 23,24 PCI_RST# 23,24,27 PCI_DEVSEL# 15,23,24 PCI_PERR# 15,23,24 PCI_LOCK# 15,23,24 PCI_SERR# 15,23,24 PCI_STOP# 15,23,24 PCI_TRDY# 15,23,24
SUS_STAT#/LPCPD# SYS_RESET# BM_BUSY#/GPI[6]
DMI[0]RXN DMI[0]RXP DMI[0]TXN DMI[0]TXP DMI[1]RXN DMI[1]RXP DMI[1]TXN DMI[1]TXP DMI[2]RXN DMI[2]RXP DMI[2]TXN DMI[2]TXP DMI[3]RXN DMI[3]RXP DMI[3]TXN DMI[3]TXP
Interrupt I/F
15,24 15,23,24 29,30 PM_STPPCI# 15,23,24 15,24 29,30,48 PM_STPCPU#
RESERVED
C
TP_RSVD3 TP_RSVD4
TP_RSVD7 TP_RSVD8
AD20 NEWCARD_RST#1_R AD21 OP3_R V3
RSVD_5
+V3.3S 5,9,12,13,15..19,21..23,25..30,34,37..41,45,47,50..53,55 C7T5 5 0.1uF 4 Buffer to reduce loading on PLT_RST# U8E1 1 25,27,29,32,55 BUF_PLT_RST# 74AHC1G08 2 PLT_RST# 7 DELAY_VR_PWRGOOD
NEWCARD_RST#0_R P5 PM_S3HOT#_R R3 SATA_PWR_EN#0_R T3 AF19 15,23,24,27,29,40 PM_CLKRUN# NEWCARD_RST#2_R AF20 +V3.3S 5,9,12,13,15..19,21..23,25..30,34,37..41,45,47,50..53,55 SATA_PWR_EN#2_R AC18 12,15,25,32,55 PCIE_WAKE# R3P3 10K 5%
15,23,27,29,40 INT_SERIRQ 5,15,27,29 PM_THRM#
29,48 PM_DPRSLPVR
B
5,12,13,15,22..25,27,29,35,40,41,44,46,50..52,55
C6F3 PCIE_TXN3_C C6U3 NO_STUFF 0.1uF C6F2 PCIE_TXP3_C C6U1 NO_STUFF 0.1uF C6V2
0.1uF
DOCK_PCIE_TXN3 55 PCIE_LAN_TXN3 32
0.1uF
DOCK_PCIE_TXP3 55 PCIE_LAN_TXP3 32
PCIE_TXN1_C
C6G1 NO_STUFF
0.1uF
PCIE_TXP1_C
C6F4 NO_STUFF
0.1uF
PCIE_TXN0_C
C6V4 NO_STUFF
0.1uF
A
PCIE_TXP0_C C6V3 NO_STUFF
0.1uF
Layout note: PCIE AC coupling caps need to be within 250 mils of the driver.
5
. w w w
0.1uF PCIE_TXN1 25 DOCK_PCIE_TXN1 55 PCIE_TXP1 25 C6U5 0.1uF DOCK_PCIE_TXP1 55 PCIE_TXN0 25 C6G8 0.1uF PCIE_LAN_TXN0 32 PCIE_TXP0 25 C6G7 0.1uF PCIE_LAN_TXP0 32
NEWCARD_RST#1_R PM_S3HOT#_R SMC_RUNTIME_SCI#_R FWH_WP#_R PCI_GNT#5_R NEWCARD_RST#2_R SATA_PWR_EN#2_R SMC_EXTSMI#_R OP3_R SMC_WAKE_SCI#_R NEWCARD_RST#0_R SATA_PWR_EN#0_R OP2_R
t p la
+V3.3A R6W4 10K MCH_SYNC# R7W5 R8V4 R7W4 R7U5 R7U6 R7W3 R7W6 R8V2 R8V8 R8V6 R8V3 R8V5 0 0 0 0 0 0 0 0 0 0 0 0 R8V1
NO_STUFF
+V3.3S 5,9,12,13,15..19,21..23,25..30,34,37..41,45,47,50..53,55 R7H6 R8F12 8.2K
PM_BATLOW#_R
p o
8.2K PM_S3HOT#_R2
R8G7 29,41,51,53 PM_SLP_S3# R8G1 27,29,33,42,45,51..53 PM_SLP_S4# 29,51 PM_SLP_S5# 15,27,29,45 VCC_MCH_VRPWRGD
27,29 PM_BATLOW#
27,29,32,33 PM_LAN_ENABLE 15,27,29 PM_RSMRST#
-s
30 CLK_ICH14
E10 A27 V6 T4 T5 T6
CLK14 CLK48
POWER MGT CLOCKS USB
3
30 CLK_USB48
29,36 SUS_CLK
h c
R7H7 100 R8F11 0 R8E8 10K J8F1
m e
GPIO[24] GPIO[25] GPIO[27] GPIO[28] CLKRUN#/GPIO[32] GPIO[33] GPIO[34] WAKE# U5 AB20 SERIRQ THRM# AC20 AF21 VRMPWRGD SUSCLK SLP_S3# SLP_S4# SLP_S5# PWROK DPRSLPVR/TP[1] BATLOW#/TP[0] PWRBTN# LAN_RST# RSMRST# ICH-6_M AA1 AE20 V2 U1 V5 +V3.3S R7F7 1K NO_STUFF
a
DMI_CLKN DMI_CLKP
m o .c s ic t
H25 H24 G27 G26 K25 K24 J27 J26 PCIE_TXN0_C PCIE_TXP0_C PCIE_RXN0_R 25 PCIE_RXP0_R 25 PCIE_RXN1 25 PCIE_RXP1 25 PCIE_TXN1_C PCIE_TXP1_C M25 M24 L27 L26 P24 P23 N27 N26 T25 T24 R27 R26 V25 V24 U27 U26 PCIE_RXN2 25 PCIE_RXP2 25 PCIE_TXN2_C PCIE_TXP2_C C6G4 C6G5 0.1uF R6F7 R6F6 0.1uF PCIE_RXN3 PCIE_RXP3 PCIE_TXN3_C PCIE_TXP3_C DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7 DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7 DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7 DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7 0 0 NO_STUFF R6U2 0 R6U3 0 NO_STUFF Y25 Y24 W27 W26 AB24 AB23 AA27 AA26 +V1.5S 4,9,15,51..53 AD25 AC25 F24 F23 C23 D23 C25 C24 C27 B27 B26 C26 C21 D21 A20 B20 D19 C19 A18 B18 E17 D17 B16 A16 C15 D15 A14 B14 A22 B22 USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB_PN7 USB_PP7 USB_RBIAS_PN 35 35 35 35 35 35 35 35 35 35 35 35 35 35 55 55 22.6 DMI_IRCOMP_R R7F13 R7F12 R7F15 R7F14 R7F19 R7F18 R7F17 R7F16 0 0 0 0 0 0 0 0 CLK_PCIE_ICH# 30 CLK_PCIE_ICH 30 R7U16 24.9 1% USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R R7U19
D
PCIE_TXN2 25 PCIE_TXP2 25 DOCK_PCIE_RXN3 55 DOCK_PCIE_RXP3 55 PCIE_LAN_RXN3 32 PCIE_LAN_RXP3 32
C
Place within 500 mils of ICH
DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9] OC[5]#/GPI[10] OC[6]#/GPI[14] OC[7]#/GPI[15] OC[0]# OC[1]# OC[2]# OC[3]# USBP[0]N USBP[0]P USBP[1]N USBP[1]P USBP[2]N USBP[2]P USBP[3]N USBP[3]P USBP[4]N USBP[4]P USBP[5]N USBP[5]P USBP[6]N USBP[6]P USBP[7]N USBP[7]P USBRBIAS# USBRBIAS
USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3
35 35 35 35 35 35 35 35
100 SLP_S3#_R 100 SLP_S4#_R
PM_DPRSLPVR_R
PM_BATLOW#_R
B
27,29 PM_PWRBTN#
R8G17 PM_RSMRST#_R Y3 100
Place within 500 mils of ICH
ICH6-M Strapping Options
5,9,12,13,15..19,21..23,25..30,34,37..41,45,47,50..53,55
REF R7F9 R7F8 R7F7
FUNCTION No Reboot A16 Swap Override Boot BIOS
DEFAULT NO_STUFF NO_STUFF NO_STUFF
OPTIONAL OVERRIDE STUFF STUFF STUFF
R7F9 ACZ_SPKR 22 1K NO_STUFF +V3.3A 5,12,13,15,22..25,27,29,35,40,41,44,46,50..52,55 FWH_WP#_R R7F8 1K NO_STUFF PCI_GNT#5_R
Default: Open
NEWCARD_RST#1 25 SMC_RUNTIME_SCI# 27,29 FWH_WP# 29,37 PCI_GNT#5 24 NEWCARD_RST#2 25 SATA_PWR_EN#2 39 SMC_EXTSMI# 27,29,40,55 TP_OP3 SMC_WAKE_SCI# 27,29 NEWCARD_RST#0 25 SATA_PWR_EN#0 38
GUADALUPE Title ICH-6M (2 of 3) Size A Date: Document Number C58015 Thursday, December 11, 2003
2
INTEL CONFIDENTIAL
A
Rev 1.201 Sheet 14
1
100
of
60
4
3
5
FB6G1
4
U7F3E
3
+V1.5S_ICH_EV F9 U17 U16 U14 U12 U11 T17 T11 P17 P11 M17 M11 L17 L16 L14 L12 L11 AA21 AA20 AA19 AA10 AG19 AG16 AG13 AD17 AC15 AA17 AA15 AA14 AA12 P1 M7 L7 L4 J7 H7 H1 E4 B1 A6 U7 R7 G19 G20 F20 E24 E23 E22 E21 E20 D27 D26 D25 D24 G8 C6U4 0.1uF
2
+V1.5S_ICH R6G10 RESD,2010,PwrMsrmt-PadsShorted C7H10 220uF
1
4,9,14,51..53 +V1.5S
R6G7
+V1.5S_PCIE_L 0.002 1%
+V1.5S_PCIE_ICH C6G9 220uF C6G10 0.1uF C6V1 0.1uF C6G11 0.1uF AA22 AA23 AA24 AA25 AB25 AB26 AB27 F25 F26 F27 G22 G23 G24 G25 H21 H22 J21 J22 K21 K22 L21 L22 M21 M22 N21 N22 N23 N24 N25 P21 P25 P26 P27 R21 R22 T21 T22 U21 U22 V21 V22 W21 W22 Y21 Y22 AA6 AB4 AB5 AB6 AC4 AD4 AE4 AE5 AF5 AG5 AA7 AA8 AA9 AB8 AC8 AD8 AE8 AE9 AF9 AG9 AC27 E26 VCC1_5[1] VCC1_5[2] VCC1_5[3] VCC1_5[4] VCC1_5[5] VCC1_5[6] VCC1_5[7] VCC1_5[8] VCC1_5[9] VCC1_5[10] VCC1_5[11] VCC1_5[12] VCC1_5[13] VCC1_5[14] VCC1_5[15] VCC1_5[16] VCC1_5[17] VCC1_5[18] VCC1_5[19] VCC1_5[20] VCC1_5[21] VCC1_5[22] VCC1_5[23] VCC1_5[24] VCC1_5[25] VCC1_5[26] VCC1_5[27] VCC1_5[28] VCC1_5[29] VCC1_5[30] VCC1_5[31] VCC1_5[32] VCC1_5[33] VCC1_5[34] VCC1_5[35] VCC1_5[36] VCC1_5[37] VCC1_5[38] VCC1_5[39] VCC1_5[40] VCC1_5[41] VCC1_5[42] VCC1_5[43] VCC1_5[44] VCC1_5[45] VCC1_5[46] VCC1_5[47] VCC1_5[48] VCC1_5[49] VCC1_5[50] VCC1_5[51] VCC1_5[52] VCC1_5[53] VCC1_5[54] VCC1_5[55] VCC1_5[56] VCC1_5[57] VCC1_5[58] VCC1_5[59] VCC1_5[60] VCC1_5[61] VCC1_5[62] VCC1_5[63] VCC1_5[64] VCC1_5[65] VCCDMIPLL VCC3_3[1] VCC1_5[98] VCC1_5[97] VCC1_5[96] VCC1_5[95] VCC1_5[94] VCC1_5[93] VCC1_5[92] VCC1_5[91] VCC1_5[90] VCC1_5[89] VCC1_5[88] VCC1_5[87] VCC1_5[86] VCC1_5[85] VCC1_5[84] VCC1_5[83] VCC1_5[82] VCC1_5[81] VCC1_5[80] VCC1_5[79] VCC3_3[21] VCC3_3[20] VCC3_3[19] VCC3_3[18] VCC3_3[17] VCC3_3[16] VCC3_3[15] VCC3_3[14] VCC3_3[13] VCC3_3[12] VCC3_3[11] VCC3_3[10] VCC3_3[9] VCC3_3[8] VCC3_3[7] VCC3_3[6] VCC3_3[5] VCC3_3[4] VCC3_3[3] VCC3_3[2] VCCSUS1_5[3] VCCSUS1_5[2] USB VCCSUS1_5[1] VCC1_5[78] VCC1_5[77] VCC1_5[76] VCC1_5[75] VCC1_5[74] VCC1_5[73] VCC1_5[72] VCC1_5[71] VCC1_5[70] VCC1_5[69] VCC1_5[68] VCC1_5[67] VCC2_5[4] VCC2_5[2] V5REF[2] V5REF[1] C7V25 0.1uF C7V17 0.1uF C7V10 0.1uF C7V16 0.1uF
100ohm@100MHz
C7V27 NO_STUFF 0.01uF Layout note: Place near pin AA19
Layout note: Place above Caps within 100 mils of ICH near F27, P27, AB27
CORE
Layout note: Distribute near pin ICH6 Package edge
D
+V5S 5,16,17,23,25,29,34,36,38,39,41,45,47,48,50..53 +V3.3S 5,9,12..14,16..19,21..23,25..30,34,37..41,45,47,50..53,55 1 R7F6 100 3 C7U5 1uF C7U10 0.1uF CR7F1 BAT54 VCC5REF Layout note: C7U10needs be placed within 100mils of pin A8 of ICH6
C7V15 C7V11 C7V14 C7V24 C7V21 C6G12 NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF 0.1uF 0.1uF 0.1uF 22uF 0.1uF 0.1uF
+V5A 35,42,46,50,51,55 +V3.3A 5,12..14,22..25,27,29,35,40,41,44,46,50..52,55 1 R7U3 10 5% 3 CR6U1 BAT54 V5REF_SUS Layout note: C7V3 needs be placed within 100mils of pin F21 of ICH6
+V3.3S_ICH
PCIE
C7V40 0.1uF
5,9,12..14,16..19,21..23,25..30,34,37..41,45,47,50..53,55 C7V39 0.1uF Place within 100 mils of ICH6 pin AG13, AG16
C7V7 1uF
C7V3 0.1uF
+V3.3S_ICH R8U3 C7U7 0.1uF C7V9 0.1uF C7U12 0.1uF 0.002 1%
7,29,35,40,41,44,46,50..52,55
+V3.3A +V3.3_VCCPAUX
R7U2 0.002 1%
Layout Note: Distribute in PCI section +V1.5A_ICH near pin A2-A6 near D1-H1
C
4,9,14,51..53 +V1.5S
+V1.5S_ICH R7H13 RESD,2010,PwrMsrmt-PadsShorted NO_STUFF Place within 100 mils of ICH near pin AG5 C7H1 C7V31 C7V36 0.1uF NO_STUFF NO_STUFF 0.1uF 0.1uF
SATA
+V1.5S_GPLL_ICH +V1.5S_ICH R6V13 0 C6W1 10uF R6W2
+V1.5S_ICH 2 C6V5 0.01uF Place within 100 mils of ICH near AG9
L6V1 1uH 1 GPLL_R_L 1
PCI/IDE REF
Place within 100 mils of ICH
C7V30 C7V29 C7H2