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Capell Valley
D
YONAH-CALISTOGA CUSTOMER REFERENCE BOARD
Fan Header
PG 5
Clocking
Yonah 478 uFCPGA
PG 3,4
FSB
PG 30,31
IMVP-6 VR
PG 51, 52
LVDS/ALS/BLI
SODIMM0
PG 19
CRT (DVI-I)
PG 18
VGA LVDS
CPU Thermal Sensor
XDP
PG 37
PG 5
TVOUT
PG 20
Calistoga 1466 FCBGA
PG 6,7,8,9,10,11,12
PG 21,22,23
C
PEG/ SDVO
SDVO
PG 13
X4 DMI interface SATA CC PG 43 SATA DC PG 44 SATA PORT 0
33 Mhz PCI
ICH7M
SATA PORT 2
PATA
B
PG 39
BACK PANEL FPIO/DB BACK PANEL FPIO/DB
2.0 USB7
2.0 USB6
2.0 USB5
2.0 USB4
8 USB ports total
DOCKING
BACK PANEL
2.0 USB0
2.0 USB1
BACK PANEL USB
PG 40
A
5
. w w w
2.0 USB2 2.0 USB3
FPIO/DB USB
FPIO/DB BACK PANEL
HD AUDIO / MDC 1.5 HEADER
PG 27
PG 29
t p la
USB 2.0
4
HD AUDIO/ AC97
p o
PG 14-17
652 BGA
-s
SPI LPC, 33MHz
PCIEx1 PCIEx1
PCIEx1
h c
TPM
PG 35
m e
PG 28
a
SODIMM1
Dual Channel DDR2
m o .c s ic t
PG 25
Fab 5 REV 1.502 IPN: C75289-501
Calistoga VCCP VR
PG 48
D
DDR VR
PG 46
SYSTEM VR
PG 49
SLEEP CONTROL
PG 55
C
PCI SLOT3
PG 25
PCI SLOT4
PG 26
BATTERY CHARGER VR
PG 50
PCI EDGE-CONN
PG 28
PCIe SLOT0
PG 28
PCIe SLOT2 PCIe SLOT1
MOBILE POWER ON SEQUENCE
PCIEx1 PCIEx1 PCIEx1
B
PCIE DOCKING
Tekoa/EkronR LAN PORT 80-83
PG 41 PG 33, 34
RJ45
SIO
PG 42
IR/ SERIAL
PG 45
SPI Flash
PG 33
SMC/KSC FWH
8 Mbit PG 24 PG 32
LPC SLOT
PG 35
Capell Valley LPC DOCK Title
PG 57
Intel Confidential
A
TITLE PAGE Size A Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 1
1
EMA
PG 36
SCN KB/ PS2
PG 38
3
Date:
of
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CALISTOGA CUSTOMER REFERENCE PLATFORM
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
D
Default Jumper Settings For Stuffed Jumpers I C / SMB Addresses Voltage Rails
POWER PLANE +VBATA +VBAT +VBATS +V12S -V12A -V12S +V5A +V5 +V5S +V3.3A +V3.3 +V3.3S +V1.5S +V1.8 +V0.9 +V2.5S +V2.5_LAN +V1.2 +1.05S +VCC_CORE VOLTAGE 9V-12.5V 9V-12.5V 9V-12.5V 12V -12V -12V 5V 5V 5V 3.3V 3.3V 3.3V 1.5V 1.8V 0.9V 2.5V 2.5V 1.2V 1.05V 0.700V-1.77V S3COLD ACTIVE S0, S3, S4, S5 S0, S3, S4, S5 S0 S0 S0, S3,S4,S5 S0 S0, S3,S4,S5 S0, S3 S0 S0, S3,S4,S5 S0, S3 S0 S0 S0, S3 S0, S3 S0 S0, S3 S0, S3 S0 S0 DESCRIPTION Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Only on in DT Power Mode Only on in DT Power Mode Only on in DT Power Mode Address Device 1101 001x Clock Generator Spread Spectrum Clock 1101 010x PCI Express Clock 1101 110x 1010 010x SO-DIMM0 SO-DIMM1 1010 000x DDR Thermal Sensor 0100 1100 IC2 Buss Expander 0011 xxxx Ambient Light Sensor 0111 0010 Always ON Display 011 110x Thermal Diode 1001 100B Battery A 0001 0110 Battery B 11110 1100 1000 LAN TBD PCI Express Docking Trusted Platform Module TBD Hex D2/D3* D4/D5* DC/DD* A4 A0 4C 3x 72 3C 4C 16 1E 1E TBD TBD AON_ALS SMB_ICH SMB_THRM SMB_BS SMB_BS SMB_BS SMB_ICH_A1 Bus SMB_ICH_S3 SMB_ICH_S3 SMB_ICH_S3 SMB_ICH_S2 SMB_ICH_S2 SMB_ICH_S2 2 Jumper Default Description
DDR core DDR command & control pull up. LAN Rail LAN Rail GMCH, ICH core, and FSB rail CPU core rail
* First address is for a write command and second is for a read command. Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The rest come out of EC.
C
LEDs and Switches
LED ATA Activity LED SMC/KBC Num Lock SMC/KBC Scroll Lock SMC/KBC Caps Lock VID0 VID1 VID2 VID3 VID4 VID5 S0 State S3 State S4 State S5 State
PCI Devices
B
Device Slot 3 Slot 4 LAN IDSEL # AD18 AD19 (AD24 internal) REQ/GNT # 2 2 3 3 Interrupts C, D, B, A D, C, F, G
Net Naming Conventions
Suffix # = Active Low Signal
Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else)
Power States
A
STATE
Full ON
S3 (Suspend to RAM)
S4 (Suspend To Disk) S5 / Soft OFF
5
. w w w
SIGNAL
SLP S4#
HIGH
SLP S5#
HIGH
+V*A
to p la
+V* +V*S Clocks
ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF
-s p
VID6
Switch Power On/Off Reset LID Virtual battery
h c
Page
Reference
14 32 32 32 45 45 45 45 45 45 45 55 55 55 55
CR7J1 CR9G1 CR9G2 CR9G3 CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B5 CR1C1 CR3G1 CR3G2 CR3G3 CR2G1
m e
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J3B1 J3B1 J6H1 J8H1 J2J10 J9J8 J1F4 J1G1 J1G2 J9J2 J9J6 J9J4 J9J1 J9J7 J9J5 J8G1 J8A1 J9G3 J9H1 J7J3 J7E1 J7E3 J9J3 J5H2 J7A3 J7A4 J3H1
m o .c s ic t
Page
D
1-2 3-4 1-X 1-X 2-3
1-2 1-2 1-2 1-2 1-2 1-X 1-X 1-X 1-X 1-2 1-X 1-2 1-X 1-2 1-X 1-2 1-2 1-2 1-2 1-2 1-X
H_THERMDA H_THERMDC CMOS CLEAR BIOS RECOVERY CRB/SV DETECT MFG/TEST BSEL2 BSEL1 BSEL0 MDO MD1 MD2 KSC DISABLE VB JMPR LID JMPR SMC RST# LAN PROTECT BOOT BLOCK PROG NMI JMPR PATA HotSwap PORT80 SEL SIO RST# SATA DET SATA HotSwap H8 PROG# H8 PROG# SHUTDOWN
5 5 14 16 16 16 30 30 30 32 32 32 32 32 32 32 33 38 38 39 41 42 44 44 45 45 54
C
Page
Reference
54 54 32 32
SW1C1 SW1C2 SW9J2 SW9J1
B
Wake Events
Wake Events RI# from serial port PME# from PCI, mini PCI slot/device, LPC slot/device PCI Express, mini PCI Express, Newcard wake event Wake on LAN LID switch attached to SMC USB AC97/Azalia wake on ring SmLink for AOLII Hot Key from Scan matrix keyboard PS/2 Keyboard/mouse PWRBTN# State Supported S3 S3 S3 S3 S3 S3 S3 S3 S3 S3 S3 S3, S4, S5
PCB Footprints
1 3 2
SOT-23
As seen from top
1 2 3
5
SOT23-5
4
ON
Capell Valley
Title NOTES Size A Date: Document Number D15378 Wednesday, July 20, 2005
2
Intel Confidential
A
HIGH LOW
HIGH
ON
HIGH LOW
ON
Rev 1.501 Sheet 2
1
LOW
ON
of
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4,6,9,10,14,17,30,37,45,48,53,56,58
+V1.05S
6 H_A#[31:3] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 6 H_ADSTB#0 6 H_REQ#[4:0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 K3 H2 K2 J3 L5 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 A6 A5 C4 D5 C6 B4 A3 TP_A32# TP_A33# TP_A34# TP_A35# TP_A36# TP_A37# TP_A38# TP_A39# TP_APM0# TP_APM1# TP_HFPLL AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 B25
U2E1A A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] RSVD[11] ADS# BNR# BPRI# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 D21 A24 A25 C7 H_RS#0 H_RS#1 H_RS#2 H_ADS# 6 H_BNR# 6 H_BPRI# 6 H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6 H_IERR# H_INIT# 14 H_LOCK# 6 H_CPURST# 6,37 H_RS#[2:0] 6 R3T5 56
D
DEFER# DRDY# DBSY# BR0#
CONTROL
Place testpoint on H_IERR# with a GND 0.1" away
IERR# INIT# LOCK#
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
H_TRDY# 6 H_HIT# 6 H_HITM# 6 XDP_BPM#0 37 XDP_BPM#1 30 XDP_BPM#2 30 XDP_BPM#3 30,58 XDP_BPM#4 37 XDP_BPM#5 37 XDP_TCK 37 XDP_TDI 37 XDP_TDO 37 XDP_TMS 37 XDP_TRST# 37 XDP_DBRESET# 37,54,58 H_THERMDA 5 H_THERMDC 5 PM_THRMTRIP# 7,14 PM_THRMTRIP# 7,14
6 H_A#[31:3]
+V1.05S 4,6,9,10,14,17,30,37,45,48,53,56,58
R3R1 75
6 H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26
U2E1B
Layout note: no stub on H_STPCLK TP
H_STPCLK#_R NO_STUFF TP2F1 14 H_STPCLK#
14 H_A20M# 14 H_FERR# 14 H_IGNNE# 14 H_INTR 14,35 H_NMI 14,35,58 H_SMI# R2F2 0
THERMTRIP#
PM_THRMTRIP# should connect to ICH7 and GMCH without T-ing (No stub)
H CLK
BCLK[0] BCLK[1] RSVD[12]
A22 A21 T22 D2 F6 D3 C1 AF1 D22 C23 C24 TP_EXTBREF TP_SPARE0 TP_SPARE1 TP_SPARE2 TP_SPARE3 TP_SPARE4 TP_SPARE5 TP_SPARE6 TP_SPARE7
CLK_CPU_BCLK 30 CLK_CPU_BCLK# 30
RESERVED
A#[32-39], APM#[0-1]: Leave escape routing on for future functionality
RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20]
Yonah Ball-out Rev 1.0
B
4,6,9,10,14,17,30,37,45,48,53,56,58 XDP_TMS XDP_TDI XDP_BPM#5 R1R4 R2R3 R1R3 54.9 54.9 54.9
XDP_TCK
R2R4
54.9
A
NO_STUFF NO_STUFF NO_STUFF NO_STUFF
TP3D1 TP3D3 TP3D5 TP3D7
TP_CPN_L1 TP_CPN_L3 TP_CPN_L6 TP_CPN_L8
5
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NO_STUFF NO_STUFF NO_STUFF NO_STUFF TP3D2 TP3D4 TP3D6 TP3D8
t p la
+V1.05S 1% 1% 1% 1%
p o
4,6,9,10,14,17,30,37,45,48,53,56,58
58 H_GTLREF
-s
R3T1 1K 1%
+V1.05S
h c
6 6 6 6 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[63:0] 6 H_DSTBN#1 6 H_DSTBP#1 6 H_DINV#1 NO_STUFF
DATA GRP 2
C
THERM
6 H_ADSTB#1
PROCHOT# THERMDA THERMDC
H_PROCHOT# 51
m e
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26 AD26 R3U2 1K ACLKPH 51DCLKPH J2G1 C26 D25 B22 B23 C21
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF
a
DATA GRP 0 DATA GRP 1
m o .c s ic t
H_D#[63:0] 6 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE6 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
XDP/ITP SIGNALS
DATA GRP 3
ADDR GROUP 0 ADDR GROUP 1
D
C
Layout note: Comp0,2 connect with trace length shorter Comp1,3 connect with trace length shorter H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6
Zo=27.4ohm, make than 0.5". Zo=55ohm, make than 0.5".
B
MISC
Layout note: Zo=55 ohm, 0.5" max for GTLREF.
R3R3 2K 1%
TEST1 TEST2 BSEL[0] BSEL[1] BSEL[2]
COMP0 COMP1 COMP2 COMP3
R3T3 R3T2 R2T2 R2T1
27.4 1% 54.9 1% 27.4 1% 54.9 1%
R3U1
H_DPRSTP# 14,35 H_DPSLP# 14,35 H_DPWR# 6 H_PWRGD H_CPUSLP# 6,35 PSI# Layout: Connect test point TP3F1 with no stub R2U4 1K 14,35 H_PWRGD_XDP 37
30 CPU_BSEL0 30 CPU_BSEL1 30 CPU_BSEL2
Yonah Ball-out Rev 1.0 TP3F1 NO_STUFF
Place Series Resistor on H_PWRGD_XDP Without Stub
Capell Valley
Title CPU (1 of 2) Size A Date:
4 3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 3
1
of
60
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2
1
53,56,58 +VCC_CORE U2E1C
53,56,58 +VCC_CORE A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 53,56,58 +VCC_CORE AD6 AF5 AE5 AF4 AE3 AF2 AE2 AF7 AE7 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 51 51 51 51 51 51 51
D
C
+V1.05S 3,6,9,10,14,17,30,37,45,48,53,56,58
C3T1 270uF 20%
10,17,27,48,56,58 +V1.5S +V1.5S 10,17,27,48,56,58 C3T4 0.01uF C3T3 10uF
B
Yonah Ball-out Rev 1.0
A
5
. w w w
to p la
R2R2 100 1%
R2R1 100 1%
VCCSENSE VSSSENSE
-s p
LAYOUT NOTE: NEAR PIN B26
PLACE C3T4
Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.
h c
m e
a
A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
m o .c s ic t
U2E1D VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24
D
C
B
Yonah Ball-out Rev 1.0
Capell Valley
Title CPU (2 of 2) Size A Date:
4 3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 4
1
of
60
5
4
3
2
1
7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
CPU Thermal Sensor
7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S C3N2 0.1uF J3B1 Default Stuffing: 1-2 3-4 Option Stuffing: 1-X 3-X J3B1 3 H_THERMDA 3 H_THERMDC 1 3 2X2HDR 2 4 THERM_DXP R3N3 499 1% R3N7 10K U3B2 8 7 6 5 THRM_ALERT#
D
Layout Note: Route H_THERMDA and H_THERMDC on same layer w/ 10 mil trace & 10 mil spacing. Route away from noise sources with ground guard tracks on each side.
1 VDD SCLK ADT_THERM_DXP 2 D+ SDATA C3N3 ADT_THERM_DXN 3 DALRT#/THM2# THERM_DXN R3N8 499 1% 1000pF ADT_THM# 4 THM# GND ADT7461A-TEMP MON
R3N5
3Pin_Recepticle J4A1 2 THERMDP 1 THERMDN
Note: No-Stuff R3N5 for normal operation. No Stuff R9G18 if R3N5 is stuffed
GND2 GND0 GND1 3 4 5 6 GND3 NO_STUFF
C
Thermal Diode Conn
B
Fan Power Control
Q2B3 10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S 3 2 1 R2B4 1M C2B4 SI7458DP 5
32,35 FAN_ON
A
5
. w w w
1000pF 4 3 FAN_ON_Q FAN_ON_D# R2B3 100K 1 Q2B2 BSS138 2
to p la
V5S_FAN C3D1 C3B2 22uF 3 0.1uF CR3D1 1N4148 1
Place fan connector near CPU
-s p
J3C1 1 2 CONN2_HDR
h c
m e
a
m o .c s ic t
+V3.3S R3N4 10K R3N6 10K SMB_THRM_CLK 32,35 SMB_THRM_DATA 32,35 PM_THRM# 16,32,35 0 NO_STUFF
D
C
B
Capell Valley
Title CPU THERMAL SENSOR AND FAN Size A Date:
4 3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 5
1
of
60
5
H_XRCOMP
4
3
2
1
R4T3 24.9 1%
3,4,9,10,14,17,30,37,45,48,53,56,58
+V1.05S
3 H_D#[63:0]
U5E1A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 E1 E2 E4 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
D
R4E3 54.9 1% H_XSCOMP
3,4,9,10,14,17,30,37,45,48,53,56,58
+V1.05S
R4E8 221 1% H_XSWING 58
R4T4 100 1%
C4T8 0.1uF
C
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S
R4T2 54.9 1% H_YSCOMP
3,4,9,10,14,17,30,37,45,48,53,56,58
+V1.05S
R4E2 221 1% H_YSWING 58
R4E1 100 1%
C4T5 0.1uF
B
H_YRCOMP R4T1 24.9 1%
A
5
. w w w
to p la
30 CLK_MCH_BCLK 30 CLK_MCH_BCLK#
H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING
-s p
H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING H_CLKIN H_CLKIN# Y1 U1 W1 AG2 AG1 CALISTOGA_1p0
h c
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_HIT# H_HITM# H_LOCK#
m e
J7 W8 U3 AB10 K4 T7 Y5 AC4 K3 T6 AA5 AC5 D3 D4 B3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 D8 G8 B8 F8 A8 B4 E6 D6 E3 E7 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
a
HOST
m o .c s ic t
H_A#[31:3] 3
D
Note: H_CPURST# has T topology
3,4,9,10,14,17,30,37,45,48,53,56,58
+V1.05S
H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3
R4E5 100 1%
H_VREF
H_BNR# 3 H_BPRI# 3 H_BREQ#0 3 H_CPURST# 3,37 H_DBSY# 3 H_DEFER# 3 H_DPWR# 3 H_DRDY# 3 H_DINV#[3:0] 3
C5T10 0.1uF
C
R4E4 200 1%
H_DSTBN#[3:0] 3
H_DSTBP#[3:0] 3
H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_REQ#[4:0] 3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_SLPCPU# H_TRDY#
B
H_RS#[2:0] 3
H_CPUSLP# 3,35 H_TRDY# 3
Capell Valley
Title CALISTOGA (1 OF 6) Size A Date:
4 3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 6
1
of
60
5
4
3
2
1
U5E1C MCH_RSVD_[2:1] MCH_RSVD_0 MCH_RSVD_1 MCH_RSVD_2 TP_MCH_RSVD_3 TP_MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8 MCH_RSVD_9 MCH_RSVD_10 MCH_RSVD_11 MCH_RSVD_12 MCH_RSVD_13 U5E1B H32 RSVD_0 T32 RSVD_1 R32 RSVD_2 F3 RSVD_3 F7 RSVD_4 AG11 RSVD_5 AF11 RSVD_6 H7 RSVD_7 J19 RSVD_8 A41 RSVD_9 A35 RSVD_10 A34 RSVD_11 D28 RSVD_12 D27 RSVD_13 19 L_BKLTCTL 19 L_BKLTEN 19,37 L_CLKCTLA 19,37 L_CLKCTLB 19 L_DDC_CLK 19 L_DDC_DATA TP5E1 NO_STUFF 19 L_VDDEN D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 A33 A32 E27 E26 C37 B35 A37
SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3 SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3
AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21 AL20 AF10 BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41 AF33 AG33 A27 A26 C40 D41 AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS#0 M_CS#1 M_CS#2 M_CS#3 TP_M_OCDCOMP_0 TP_M_OCDCOMP_1 M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_RCOMP# M_RCOMP 21,23 21,23 22,23 22,23 21,23 21,23 22,23 22,23 21,23 21,23 22,23 22,23
21 21 22 22 21 21 22 22
L_IBG L_LVBG
D
L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LA_CLK# LA_CLK LB_CLK# LB_CLK
19 19 19 19
LA_CLKN LA_CLKP LB_CLKN LB_CLKP
MUXING
CLK
C
16 PM_BMBUSY# 21,23 PM_EXTTS#0
R6E4 22,23 PM_EXTTS#1 3,14 PM_THRMTRIP# 16 DELAY_VR_PWRGOOD 13,15,24,28,32,41,42,57 RST_IN#_MCH R5R1 100 PLT_RST# 13 SDVO_CTRLCLK 13 SDVO_CTRLDATA 15 MCH_ICH_SYNC# 31 CLK_MCH_OE#
G28 F25 PM_EXTTS#1_R H26 0 G6 AH33 AH34 H28 H27 K28 D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3
PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN# SDVO_CTRLCLK SDVO_CTRLDATA LT_RESET# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
CLK_PCIE_3GPLL# 31 CLK_PCIE_3GPLL 31 DREFCLK# 30 DREFCLK 30 DREFSSCLK# 30 DREFSSCLK 30 DMI_TXN[3:0] 15
Layout Note: Place 150 Ohm termination resistors close to GMCH 18,20 TV_DACA_OUT 18,20 TV_DACB_OUT 18,20 TV_DACC_OUT
DMI_TXP[3:0] 15
B
TP_MCH_NC0 TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16 TP_MCH_NC17 TP_MCH_NC18
DMI
AE37 DMI_RXN0 AF41 DMI_RXN1 AG37DMI_RXN2 AH41DMI_RXN3 DMI_RXP0 AC37 AE41 DMI_RXP1 AF37 DMI_RXP2 AG41DMI_RXP3
DMI_RXN[3:0] 15
CALISTOGA_1p0
PM_EXTTS#1_R
R6E5 0 NO_STUFF
PM_DPRSLPVR 16,35,51 58 EPOT_WIPER
A
5
. w w w
R5P2 R5P3 10K PM_EXTTS#0 10K PM_EXTTS#1 +V1.8 9,21,22,34,46,47,56,58 R4R1 80.6 1% M_RCOMP# M_RCOMP R4R2 80.6 1%
+V3.3S 5,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
t p la
R7N3 0 NO_STUFF
p o
L_IBG R7N4 1.5K 1%
DMI_RXP[3:0] 15
-s
Layout Note: Place 150 Ohm termination resistors close to GMCH R5T4 R5T5 R5T6
18 CRT_HSYNC
h c
R5T3 150 1% R4T7 150 1% R4T6 150 1%
20 TV_DCONSEL0 20 TV_DCONSEL1
18 CRT_BLUE
18 CRT_GREEN
18 CRT_RED 150 1% 150 1% 150 1%
m e
R4T5 4.99k 1% R5E7 39 HSYNC VSYNC 255 1% CRTIREF R5E6 39
PCI-EXPRESS
MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17 MCH_CFG_18 MCH_CFG_19 MCH_CFG_20
SM_OCDCOMP_0 SM_OCDCOMP_1 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP# SM_RCOMP SM_VREF_0 SM_VREF_1
19 LA_DATAP0 19 LA_DATAP1 19 LA_DATAP2 19 LB_DATAN0 19 LB_DATAN1 19 LB_DATAN2
B37 B34 A36 G30 D30 F29
LA_DATA_0 LA_DATA_1 LA_DATA_2
M_VREF_MCH 47,58
19 LB_DATAP0 19 LB_DATAP1 19 LB_DATAP2
F30 D29 F28
A16 C18 A19
TVIREF J20 B16 B18 B19 K30 J29
a
DDR
LB_DATA#_0 LB_DATA#_1 LB_DATA#_2
LB_DATA_0 LB_DATA_1 LB_DATA_2
GRAPHICS
30 MCH_BSEL0 30 MCH_BSEL1 30 MCH_BSEL2 12,13 MCH_CFG_[20:3]
K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
19 LA_DATAN0 19 LA_DATAN1 19 LA_DATAN2
LA_DATA#_0 LA_DATA#_1 LA_DATA#_2
TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC TV_DCONSEL0 TV_DCONSEL1 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
m o .c s ic t
10,58 +V1.5S_PCIE R5E1 24.9 1% EXP_A_COMPI EXP_A_COMPO D40 PEG_COMP D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15 EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15
PEG_RXN[15:0] 13
RSVD CFG PM
MISC
D
LVDS
PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15
PEG_RXP[15:0] 13
EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15 EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15
F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15
PEG_TXN[15:0] 13
C
TV
E23 D23 C22 B22 A21 B21
18 CRT_DDC_CLK 18 CRT_DDC_DATA
C26 C25 G23 J22 H23
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC
R5E5
PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
PEG_TXP[15:0] 13
VGA
NC
CALISTOGA_1p0
18 CRT_VSYNC
B
Capell Valley
Title CALISTOGA (2 OF 6) Size A Date:
4 3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 7
1
of
60
5
4
3
2
1
21 M_A_DQ[63:0]
U5E1D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 CALISTOGA_1p0 SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AU12 AV14 BA20 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_BS0 21,23 M_A_BS1 21,23 M_A_BS2 21,23 M_A_CAS# 21,23 M_A_DM[7:0] 21
22 M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
U5E1E SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
D
SB_BS_0 SB_BS_1 SB_BS_2
A
M_A_DQS[7:0] 21
SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#
M_A_DQS#[7:0] 21
SYSTEM
M_A_A[13:0] 21,23
SYSTEM
C
AW14 AK23 TP_MA_RCVENIN# AK24 TP_MA_RCVENOUT# AY14
M_A_RAS# 21,23 M_A_WE# 21,23
B
A
5
. w w w
to p la
4
-s p
h c
m e
CALISTOGA_1p0
a
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
m o .c s ic t
AT24 AV23 AY28 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_BS0 22,23 M_B_BS1 22,23 M_B_BS2 22,23 M_B_CAS# 22,23 M_B_DM[7:0] 22 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS[7:0] 22 M_B_DQS#[7:0] 22 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A[13:0] 22,23 AU23 AK16 TP_MB_RCVENIN# AK18 TP_MB_RCVENOUT# AR27 M_B_RAS# 22,23 M_B_WE# 22,23
D
MEMORY
MEMORY
B
C
DDR
DDR
SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#
B
Capell Valley
Title CALISTOGA (3 OF 6) Size A Date:
3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 8
1
of
60
5
+V1.05S 3,4,6,10,14,17,30,37,45,48,53,56,58 U5E1G AA33 VCC_0 W33 VCC_1 P33 VCC_2 N33 VCC_3 L33 VCC_4 J33 VCC_5 AA32 VCC_6 Y32 VCC_7 W32 VCC_8 V32 VCC_9 P32 VCC_10 N32 VCC_11 M32 VCC_12 L32 VCC_13 J32 VCC_14 AA31 VCC_15 W31 VCC_16 V31 VCC_17 T31 VCC_18 R31 VCC_19 P31 VCC_20 N31 VCC_21 M31 VCC_22 AA30 VCC_23 Y30 VCC_24 W30 VCC_25 V30 VCC_26 U30 VCC_27 T30 VCC_28 R30 VCC_29 P30 VCC_30 N30 VCC_31 M30 VCC_32 L30 VCC_33 AA29 VCC_34 Y29 VCC_35 W29 VCC_36 V29 VCC_37 U29 VCC_38 R29 VCC_39 P29 VCC_40 M29 VCC_41 L29 VCC_42 AB28 VCC_43 AA28 VCC_44 Y28 VCC_45 V28 VCC_46 U28 VCC_47 T28 VCC_48 R28 VCC_49 P28 VCC_50 N28 VCC_51 M28 VCC_52 L28 VCC_53 P27 VCC_54 N27 VCC_55 M27 VCC_56 L27 VCC_57 P26 VCC_58 N26 VCC_59 L26 VCC_60 N25 VCC_61 M25 VCC_62 L25 VCC_63 P24 VCC_64 N24 VCC_65 M24 VCC_66 AB23 VCC_67 AA23 VCC_68 Y23 VCC_69 P23 VCC_70 N23 VCC_71 M23 VCC_72 L23 VCC_73 AC22 VCC_74 AB22 VCC_75 Y22 VCC_76 W22 VCC_77 P22 VCC_78 N22 VCC_79 M22 VCC_80 L22 VCC_81 AC21 VCC_82 AA21 VCC_83 W21 VCC_84 N21 VCC_85 M21 VCC_86 L21 VCC_87 AC20 VCC_88 AB20 VCC_89 Y20 VCC_90 W20 VCC_91 P20 VCC_92 N20 VCC_93 M20 VCC_94 L20 VCC_95 AB19 VCC_96 AA19 VCC_97 Y19 VCC_98 N19 VCC_99 M19 VCC_100 L19 VCC_101 N18 VCC_102 M18 VCC_103 L18 VCC_104 P17 VCC_105 N17 VCC_106 M17 VCC_107 N16 VCC_108 M16 VCC_109 L16 VCC_110
4
3
2
1
D
C
VCC
B
A
5
. w w w
CALISTOGA_1p0
VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107
to p la
0.47uF 0.47uF
AU41 AT41 VCCSM_LF4 C5D2 +V1.05S 3,4,6,10,14,17,30,37,45,48,53,56,58 AM41 VCCSM_LF5 C5D4 AU40 0.47uF BA34 0.47uF AY34 AW34 AV34 C4T7 C4T6 C5T6 C5T2 C5T7 AU34 270uF 270uF 10uF 1uF 10uF AT34 20% 2.0V, 3.3Arms 20% AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 C5D3 AJ23 BA22 0.47uF AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 +V1.8 7,21,22,34,46,47,56,58 AP8 BA6 AY6 AW6 AV6 AT6 C5R4 C5R3 C5D1 AR6 AP6 10uF 10uF 0.47uF AN6 AL6 Place C5D1 near AK6 PLACE IN CAVITY AJ6 pin BA15 on AV1 VCCSM_LF2 Layer1 AJ1 VCCSM_LF1 C4D1 C4D2
U5E1F C5T4 0.22uF C5T5 0.22uF C5T3 0.22uF AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72
-s p
h c
m e
a
m o .c s ic t
VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17 10,58 +V1.5S_AUX VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57 AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15
D
C
NCTF
B
CALISTOGA_1p0
Capell Valley
Title CALISTOGA (4 OF 6) Size A Date: Document Number D15378 Wednesday, July 20, 2005
2
Intel Confidential
A
Rev 1.501 Sheet 9
1
of
60
4
3
5
+V1.5S 4,17,27,48,56,58
4
3
18,20,49,56,58 +V2.5S
2
1
4,17,27,48,56,58 +V1.5S
NOTE: 0.1uF caps in 1.5SxPLL need to be located as edge caps within 200mils
+V1.5S_DPLLA L5F1 1 2 10uH 10%
NOTE: CAPS USED IN +V3.3_TVDAC should be within 250mils of edge of MCH
47,56 +V3.3S_TVDAC FB4F1 180ohm@100MHz C4F6 10uF +80-20% 3 C4F3 2 0.1uF C4E4 3 +V1.5S_DPLLB C4F2 0.1uF 0.1uF +V3.3S_TVDACC 1 10uF C4E3 3 0.1uF C4F1 2 0.1uF +V1.5S_HPLL 18,20,49,56,58 +V2.5S C5F2 0.1uF C5F1 22nF 22nF 2 22nF 1 +V3.3S_TVDACB +VCCA_TVDAC C4E5 22nF 1 +V3.3S_TVDACA 18,20,49,56,58 +V2.5S
C5T8
0.1uF U5E1H H22 C30 B30 A30 AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41 F21 E21 G21 B26 C39 AF1 A38 B39 AF2 VCCSYNC VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS VCCA_MPLL VCCA_TVBG VSSA_TVBG
3,4,6,9,14,17,30,37,45,48,53,56,58
7,58 +V1.5S_PCIE
D
C5U2 470uF 20%
C5U1 0.1uF
+V1.5S_3GPLL 18,20,49,56,58 +V2.5S C5R6 C5T1
L6F1 1 2 10uH 10% C6F1 470uF 20%
C5T13
58 +V2.5S_CRTDAC 1 3 2
VCCA_CRTDAC +V1.5S_DPLLA +V1.5S_DPLLB +V1.5S_HPLL
FB4D2 1
2 C4R5 0.1uF +V1.5S_MPLL C5E6 3 C5F5 22nF 1 C5T11 C5T12 0.01uF 0.1uF +V3.3S_ATVBG +V1.5S_MPLL
120ohm@100MHz C4T1 22uF 20%
H20 G20
FB4D1 1
2 C4R4 0.1uF
0.1uF
+V3.3S_TVDACA +V3.3S_TVDACB +V3.3S_TVDACC 4,17,27,48,56,58 +V1.5S
C
120ohm@100MHz C4R3 22uF 20%
3,4,6,9,14,17,30,37,45,48,53,56,58 +V1.05S +V2.5S 18,20,49,56,58 R5U5 1 10 FB5E1 180ohm@100MHz CR5F1 2 VCCGFOLLOW 3 BAT54 1
4,17,27,48,56,58 +V1.5S
NOTE: CAPS USED IN +V2.5_CRTDAC should be5,7,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 within 250mils of edge of MCH
58 +V2.5S_CRTDAC
4,17,27,48,56,58 +V1.5S 7,58 +V1.5S_PCIE L5E1 PCIE_LR5E2 0.002 1% C5E2 10uF C5D5 10uF 4,17,27,48,56,58 +V1.5S +V1.5S_3GPLL L5D1 R5D1 0.5 1% 3GPLL_R_L 1 1uH 3GPLL_FB_L 2 20% R6D8 0.002 1% C5E1 220uF 91nH 20%
NOTE: CAPS USED IN +V1.5_PCIE should be on top layer
B
NOTE: 10uF CAPS USED IN +V1.5_3GPLL should be placed in cavity
+V1.5S_AUX
4,17,27,48,56,58 +V1.5S 9,58 R6D6 0.002 1%
C5R5 0.1uF
+V3.3S
C5F7
10uF
A
47,56 +V3.3S_TVDAC
4,17,27,48,56,58 +V1.5S CR4F1 V1_5SFOLLOW 3 1 BAT54 R4F3 10 32,35,47,48,49,55,56 PM_SLP_S3#
R4F2 0.002 1%
5
. w w w
C5T16 0.1uF +V3.3S_TVDAC_LDO 3 1 2
5,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56
PM_SLP_S3_SHDN2
5,7,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 R4U3 10K 5,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S U4F1 IN SC1563 OUT
to p la
C4T2 C4T4 4.7uF 2.2uF +V5S
3,4,6,9,14,17,30,37,45,48,53,56,58 C4E2
-s p
+V1.05S C4E1 270uF 20% +V3.3S_TVDAC_LDO C4F4 0.1uF 22uF
h c
+V3.3S
58 +V1.5S_TVDAC
+V1.5S_QTVDAC
+V1.5S_AUX 9,58
m e
E19 F19 C20 D20 E20 F20 AH1 AH2 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 A28 B28 C28 D21 A23 B23 B25 VCCD_TVDAC VCC_HV0 VCC_HV1 VCC_HV2 H19 VCCD_QTVDAC VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40 AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
a
POWER
m o .c s ic t
C5T14 +V1.05S 0.1uF VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76 AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1 18,20,49,56,58 VTTLF_CAP3 C4T10 0.47uF VTTLF_CAP2 VTTLF_CAP1 C4T3 0.47uF C4T9 0.22uF
C5T17 10uF
D
+V2.5S
C5T15 0.1uF
C5F6 4.7uF
18,20,49,56,58 +V2.5S
2
C5E3 0.1uF
C
NOTE: .1uF CAPS USED IN +V1.5S_DLVDS, +V2.5S_ALVDS, +V2.5S_TXLVDS, +V2.5S_3GBG should be placed within 200mils of edge
B
NOTE: CAPS USED IN +V1.5_TVDAC and +V1.5_QTVDAC should be within 250mils of edge
4,17,27,48,56,58 +V1.5S
58 +V1.5S_TVDAC 1 2 TVDAC_FB C5F3 0.1uF C5E4 22nF 3
R5F3 0.002 1%
0.22uF
PLACE IN CAVITY
PLACE ON THE EDGE
+V1.5S_QTVDAC FB5F1 1 2 3 C5E5 22nF QTVDAC_FB 180ohm@100MHz C5F4 0.1uF
5 1
C4F5 1.0uF
4
CALISTOGA_1p0
SHDN GND 2
ADJ 3
R4U1 17.8K 1%
C4F7
Capell Valley
Title CALISTOGA (5 OF 6) Size A Date: Document Number D15378 Wednesday, July 20, 2005
2
Intel Confidential
A
TVDAC_ADJ2 Q4U1 BSS138 R4U4 100 NO_STUFF R4U2 10K 1%
1
Rev 1.501 Sheet 10
1
2
of
60
4
3
5
4
3
2
1
U5E1I AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11
U5E1J VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272
D
VSS
C
B
A
5
. w w w
to p la
4
-s p
h c
m e
a
VSS
m o .c s ic t
VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
D
C
B
CALISTOGA_1p0
CALISTOGA_1p0
Capell Valley
Title CALISTOGA (6 OF 6) Size A Date:
3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 11
1
of
60
5
4
3
2
1
7 MCH_CFG_5
Layout Note: Location of all MCH_CFG strap resistors needs to be close to trace to minimize stub
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
D
MCH_CFG_5
Low = DMIx2 High = DMIx4
R1D3 2.2K NO_STUFF
7 MCH_CFG_12 7 MCH_CFG_13 R1E12 2.2K
MCH_CFG_18 (VCC Select)
7 MCH_CFG_6
NO_STUFF
NO_STUFF R1E11 2.2K
LOW = MCH_CFG_6 (DDR)
Moby Dick
R1D4 2.2K NO_STUFF
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
HIGH = Calistoga
MCH_CFG_19 (DMI LANE REVERSAL)
7 MCH_CFG_7
7 MCH_CFG_16
C
Low = Dynamic ODT Disabled High = Dynamic ODT Enabled
MCH_CFG_7 (CPU Strap)
Low = RSVD High = Mobile CPU
R1E3 2.2K NO_STUFF
MCH_CFG_16 (FSB Dynamic ODT)
R1E1 2.2K NO_STUFF
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 MCH_CFG_20 (PCIe Backward Interpoerability mode) Low = Only SDVO or PCIE x1 is operational (defaults) High = SDVO and PCIE x1 are operating simultaneously via the PEG port
7 MCH_CFG_9
MCH_CFG_9 PCIE Graphics Lane
Low = Reverse Lane High = Normal operation
R1E8 2.2K
B
7 MCH_CFG_10
MCH_CFG_10 HOST PLL VCO SELECT
Low = RESERVED High = MOBILITY
7 MCH_CFG_11
A
MHC_CFG_11 PSB 4x CLK ENABLE
5
. w w w
Low = Reserved High = Calistoga R1D5 2.2K NO_STUFF
R1E2 2.2K NO_STUFF
to p la
4
-s p
h c
m e
a
m o .c s ic t
+V3.3S Low = 1.05V High = 1.5V R6F1 1K NO_STUFF 7 MCH_CFG_18 Low = Normal High = LANES REVERSED R5U3 1K NO_STUFF 7 MCH_CFG_19 +V3.3S R5F1 1K NO_STUFF 7,13 MCH_CFG_20
D
C
B
Capell Valley
Title CALISTOGA STRAPPING Size A Date:
3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 12
1
of
60
5
4
3
2
1
+V12S_PEG +V12S_PEG +V3.3S_PEG J6C1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 +12V1 +12V2 +12V3 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG1 3.3VAUX WAKE# Key 7 PEG_TXP[15:0] 7 PEG_TXN[15:0] 7 SDVO_CTRLCLK PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 C6C8 0.1uF C6C9 C6C10 0.1uF C6C11 C6C12 0.1uF C6C13 0.1uF 0.1uF PEG_C_TXP12 PEG_C_TXN12 0.1uF PEG_C_TXP13 PEG_C_TXN13 PEG_C_TXP14 PEG_C_TXN14 PEG_TXP15 PEG_TXN15 PEG_C_TXP15 PEG_C_TXN15 RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5 HSOP_1 HSON_1 GND10 GND11 HSOP_2 HSON_2 GND12 GND13 HSOP_3 HSON_3 GND14 RSVD3 PRSNT2#1 GND15 HSOP_4 HSON_4 GND22 GND23 HSOP_5 HSON_5 GND24 GND25 HSOP_6 HSON_6 GND26 GND27 HSOP_7 HSON_7 GND28 PRSNT2#2 GND29 HSOP_8 HSON_8 GND38 GND39 HSOP_9 HSON_9 GND40 GND41 HSOP_10 HSON_10 GND42 GND43 HSOP_11 HSON_11 GND44 GND45 HSOP_12 HSON_12 GND46 GND47 HSOP_13 HSON_13 GND48 GND49 HSOP_14 HSON_14 GND50 GND51 HSOP_15 HSON_15 GND52 PRSNT2#3 RSVD4 GND7 REFCLK+ REFCLKGND8 HSIP_0 HSIN_0 GND9 RSVD5 GND16 HSIP_1 HSIN_1 GND17 GND18 HSIP_2 HSIN_2 GND19 GND20 HSIP_3 HSIN_3 GND21 RSVD6 RSVD7 GND30 HSIP_4 HSIN_4 GND31 GND32 HSIP_5 HSIN_5 GND33 GND34 HSIP_6 HSIN_6 GND35 GND36 HSIP_7 HSIN_7 GND37 RSVD8 GND54 HSIP_8 HSIN_8 GND55 GND56 HSIP_9 HSIN_9 GND57 GND58 HSIP_10 HSIN_10 GND59 GND60 HSIP_11 HSIN_11 GND61 GND62 HSIP_12 HSIN_12 GND63 GND64 HSIP_13 HSIN_13 GND65 GND66 HSIP_14 HSIN_14 GND67 GND68 HSIP_15 HSIN_15 GND69 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 CLK_PCIE_PEG 30 CLK_PCIE_PEG# 30 PEG_RXP[15:0] 7 PEG_RXN[15:0] 7 PRSNT1# +12V4 +12V5 GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3 PWRGD A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 +V3.3S_PEG
D
14,35 SMB_CLK_S4 14,35 SMB_DATA_S4 14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
R6C4 0 NO_STUFF
16,28,33 PCIE_WAKE#
PEG_SLT_RST#
R6C5
0
C6C6
0.1uF C6C7 0.1uF
PEG_RXP15 PEG_RXN15
PEG_RXP14 PEG_RXN14 PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12
C
7 SDVO_CTRLDATA PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 7,12 MCH_CFG_20 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5 PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0 C6D13 0.1uF C6D14 C6D16 0.1uF C6D17 C6E1 0.1uF C6E2 0.1uF PEG_C_TXP4 PEG_C_TXN4 PEG_C_TXP3 PEG_C_TXN3 0.1uF PEG_C_TXP5 PEG_C_TXN5 0.1uF PEG_C_TXP6 PEG_C_TXN6 PEG_C_TXP7 PEG_C_TXN7 C6D3 0.1uF C6D4 C6D6 0.1uF C6D7 C6D8 0.1uF C6D9 C6D10 0.1uF C6D11 0.1uF 0.1uF PEG_C_TXP8 PEG_C_TXN8 0.1uF PEG_C_TXP9 PEG_C_TXN9 0.1uF PEG_C_TXP10 PEG_C_TXN10 PEG_C_TXP11 PEG_C_TXN11
PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9
B
C6E3
0.1uF C6E4
0.1uF
C6E5
0.1uF C6E6
0.1uF
C6E7
0.1uF C6E8
0.1uF
C6E10
0.1uF C6E11
0.1uF
A
5
. w w w
C6E12 0.1uF C6E13
0.1uF
Layout Note: place AC coupling caps close to GMCH. All AC coupling caps are 0603 size.
t p la
PEG_C_TXP2 PEG_C_TXN2 PEG_C_TXP1 PEG_C_TXN1 PEG_C_TXP0 PEG_C_TXN0
p o
PCIE_X16
-s
PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0
h c
m e
a
m o .c s ic t
PLT_GATED_RST# 32,33,36 PLT_RST# 7,15,24,28,32,41,42,57 55,56 +VBAT_S4 18,19,27,55,56 +VBATS +V12S_PEG R6N6 0.002 1% R6N7 0.002 1% NO_STUFF C6B11 22UF C6B7 22UF C6B4 22UF C6B6 22UF C6B8 0.1uF 10% C6N8 0.1uF 10% +V3.3 +V3.3S_PEG R6C2 0.002 1% R6C3 0.002 1% NO_STUFF + C6C5 100uF C6C4 0.1uF C6C3 0.1uF
D
C
14,15,17,25,27,32,33,34,35,36,38,45,46,55,56 5,7,10,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
For D3 HOT/ D3 ON: Stuff R6N7, R6C3, and R6C4, unstuff R6N6, R6C2 and R6C5.
B
14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
+V3.3A
C6C2 22uF
C6C1 0.1uF
Capell Valley
Title PCIE GRAPHICS Size A Date:
4 3
Intel Confidential
A
Document Number D15378 Wednesday, July 20, 2005
2
Rev 1.501 Sheet 13
1
of
60
5
+V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 CR6H1 1 BAT54 CR6H2 BAT_D 1 BAT54 R6H10 1M 3 C6H5 1uF J6H1 3 17 +V3.3A_RTC C6H7 1uF
4
3
2
1
RTC Circuitry
R6H11 20K
D
R6H9 1K BAT 1 2
Y8G1 32.768KHZ Cap values depend on Xtal 4
1
C8V1 10pF
R8V5 10M
U7G1A BT5H1 Battery_Holder
RTC_RST# SM_INTRUDER# ICH_INTVRMEN 1 2 3 4 EEP_CS EEP_SK EEP_DOUT EEP_DIN 33 LAN_JCLK 33 LAN_RSTSYNC 33 LAN_RXD0 33 LAN_RXD1 33 LAN_RXD2 33 LAN_TXD0 33 LAN_TXD1 33 LAN_TXD2
AA3 Y5 W4 W1 Y1 Y2 W3 V3 U3 U5 V4 T5 U7 V6 V7 U1 R6 R5 T2 T3 T1 T4 AF18
RTCRST# INTRUDER# INTVRMEN EE_CS EE_SHCLK EE_DOUT EE_DIN LAN_CLK
RTC LPC
CMOS Settings Clear CMOS Keep CMOS
J6H1 Shunt Open
+V3.3 C8U1 0.1uF TP_EEP_DC TP_EEP_ORG 8 7 6 5
C8V2 10pF
RTC_X1 RTC_X2
AB1 AB2
RTXC1 RTCX2
LAD0 LAD1 LAD2 LAD3 LDRQ0# LDRQ1#/GPIO23 LFRAME# A20GATE A20M# CPUSLP#
AA6 AB5 AC4 Y6 AC3 AA5 AB3 AE22 AH28 AG27 AF24 AH25 AG26 AG24 AG22 AG21 AF22 AF25 AG23 AH24 AF23 AH22 AF26
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_AD[3:0] 24,32,35,41,42
13,15,17,25,27,32,33,34,35,36,38,45,46,55,56
U8F3 VCC CS DC SK ORG DI GND DO AT88SC153 NO_STUFF
ICH_DRQ#0 42 ICH_DRQ#1 42
LPC_FRAME# 24,32,35,41,42
LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
TP1/DPRSTP# TP2/DPSLP# FERR#
H_DPRSTP#_R H_DPSLP#_R
GPIO49/CPUPWRGD IGNNE# INIT3_3V# INIT# INTR RCIN# NMI SMI#
C
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 R7H11 10K 27 ACZ_SDATAOUT
AC-97/AZALIA
27 ACZ_BITCLK 27 ACZ_SYNC 27 ACZ_RST# 27 ACZ_SDATAIN0 27 ACZ_SDATAIN1 27 ACZ_SDATAIN2 ACZ_SDATAOUT
ACZ_BIT_CLK ACZ_SYNC ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
ACZ_SDOUT SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP
ICH_SATA_LED# R7J5 330 LED_R 2 C7J12 0.1uF CR7J1 GREEN 1 54 ATA_LED# 4 5 U7J1 1 2 3 IDE_PDACTIVE# 39 R7J3 10K 43 43 43 43 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_RXN2 SATA_RXP2 SATA_TXN2 SATA_TXP2 C7W2 C7W1 C7W3 C7W4 C7H5 C7H6 C7H4 C7H3 3900pF 3900pF 3900pF 3900pF 3900pF 3900pF 3900pF 3900pF SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C SATA_RXN2_C SATA_RXP2_C SATA_TXN2_C SATA_TXP2_C
44 44 44 44
74AHC1G08
B
Distance between the ICH-7 M and cap on the "P" signal should be identical distance between the ICH-7 M and cap on the "N" signal for same pair.
31 CLK_PCIE_SATA# 31 CLK_PCIE_SATA
17 +V3.3A_RTC
R7V1 332K 1% ICH_INTVRMEN
Short pins AH10 and AG10 at the package. Place R7H1 within 500 mils of ICH7 ball
ICH7 internal VR enable strap
R7V2 0 NO_STUFF
Enable (default) Disable
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
A
R8G8 1K NO_STUFF ACZ_SDATAOUT
RSVD9 15 R7U13 1K NO_STUFF
5
. w w w
1 STUFF UNSTUFF STUFF 0 UNSTUFF
INTVRMEN
R7V1
R7V2
t p la
R7H1 24.9 1% +V3.3S R7R6 R7D11 R7D1 R7R5
p o
SATA_RBIAS_PN 39 IDE_PDIOR# 39 IDE_PDIOW# 39 IDE_PDDACK# 39 INT_IRQ14 39 IDE_PDIORDY 39 IDE_PDDREQ 3 4 I2C_EN1 7 I2C_EN2 11 I2C_EN3 14 I2C_EN4 17 10
-s
AF7 AE7 AG6 AH6 AF1 AE1 AH10 AG10 AF15 AH15 AF16 AH16 AG16 AE15 DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
AF3 AE3 AG2 AH2
SATA_CLKN SATA_CLKP
SATARBIASN SATARBIASP
h c
SATA IDE
THERMTRIP# DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DA0 DA1 DA2 DCS1# DCS3#
m e
H_SMI#_R STPCLK# AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15 AH17 AE17 AF17 AE16 AD16 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_PDA0 IDE_PDA1 IDE_PDA2
a
H_A20GATE 32,35 H_A20M# 3
TP_H_CPUSLP#
H_PWRGD 3,35 H_IGNNE# 3 FWH_INIT# 24 H_INIT# 3 H_INTR 3
m o .c s ic t
+V1.05S 3,4,6,9,10,17,30,37,45,48,53,56,58 R6V11 56 R5V9 56 NO_STUFF NO_STUFF R5G5 0 H_DPRSTP# 3,35 H_DPSLP# 3,35 R6V13 0 +V1.05S 3,4,6,9,10,17,30,37,45,48,53,56,58 R6V14 56 R6V16 0 R6V12 H_SMI# 3,35,58 24.9 1%
D
3
3,4,6,9,10,17,30,37,45,48,53,56,58 +V1.05S
LAN CPU
R6V17 56
H_FERR# 3
C
H_RCIN# 16,32,35 H_NMI 3,35 H_STPCLK# 3
H_THERMTRIP_R IDE_PDD[15:0] 39
PM_THRMTRIP# 3,7
Layout note: R6V12 needs to placed within 2" of ICH7, R6V14 must be placed within 2" of R6V12 w/o stub.
IDE_PDA[2:0] 39
B
IDE_PDCS1# 39 IDE_PDCS3# 39
ICH7M REV 1.02 EDS
5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 SMB_CLK_S2 SMB_CLK_A1 10K R9D1 10K SMB_DATA_S2 10K SMB_CLK_S3 SMB_DATA_A1 10K R9D2 10K SMB_DATA_S3 10K SMB_CLK_S4 10K SMB_DATA_S4 10K 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
R7C23 R7D2 R6D5 R6D7 R9A5 R9A6
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 U7C4 CL1 R7P23 10K 1 EXPSCL1 VCC 20 CL2 R7P28 10K 2 EXPSCL2 DA1 R7R2 10K 18 EXPSDA1 SCL1 5 DA2 R7P24 10K 19 EXPSDA2 SDA1 6 SCL0 SDA0 EN1 EN2 EN3 EN4 VSS SCL2 SDA2 SCL3 SDA3 SCL4 SDA4 8 9 12 13 15 16 C7C6 0.1uF SMB_CLK_A1 25,26,28 SMB_DATA_A1 25,26,28 SMB_CLK_S2 21,22,23 SMB_DATA_S2 21,22,23 SMB_CLK_S3 30,31 SMB_DATA_S3 30,31 SMB_CLK_S4 13,35 SMB_DATA_S4 13,35
Capell Valley
Title ICH7-M (1 of 4) Size A Date: Document Number D15378 Wednesday, July 20, 2005
2
Intel Confidential
A
16,33,58 SMB_CLK 16,33,58 SMB_DATA 10K 10K 10K 10K
Rev 1.501 Sheet 14
1
EXP. 5-CH-I2C HUB
of
60
4
3
5
4
3
2
1
+V3.3S 5,7,10,12,13,14,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 C7T4 5 0.1uF U8E2 1 32,33,35 BUF_PLT_RST# R8B3 100K 4 74AHC1G08 2 Buffer to reduce loading on PLT_RST# 28 28 28 28 28 28 28 28 33 PCIE_RXN1_LAN 33 PCIE_RXP1_LAN 33 PCIE_TXN1_LAN 33 PCIE_TXP1_LAN PCIE_RXN2_SLOT1 PCIE_RXP2_SLOT1 PCIE_TXN2_SLOT1 PCIE_TXP2_SLOT1 PCIE_RXN3_SLOT2 PCIE_RXP3_SLOT2 PCIE_TXN3_SLOT2 PCIE_TXP3_SLOT2 C6V1 C6U2 0.1uF 0.1uF PCIE_TXN1_C PCIE_TXP1_C F26 F25 E28 E27 H26 H25 G28 G27 K26 K25 J28 J27 M26 M25 L28 L27 P26 P25 N28 N27 T25 T24 R28 R27 R2 P6 P1 P5 P2 PLT_RST#
Layout note: PCIE AC coupling caps need to be within 250 mils of the driver.
U7G1D PERn1 PERp1 PETn1 PETp1 PERn2 PERp2 PETn2 PETp2 PERn3 PERp3 PETn3 PETp3 PERn4 PERp4 PETn4 PETp4 PERn5 PERp5 PETn5 PETp5 PERn6 PERp6 PETn6 PETp6
D
C6F7 C6F6
0.1uF 0.1uF
PCIE_TXN2_C PCIE_TXP2_C PCIE_RXN3_R PCIE_RXP3_R PCIE_TXN3_C PCIE_TXP3_C PCIE_RXN4_R PCIE_RXP4_R PCIE_TXN4_C PCIE_TXP4_C PCIE_RXN5_R PCIE_RXP5_R PCIE_TXN5_C PCIE_TXP5_C PCIE_RXN6_R PCIE_RXP6_R PCIE_TXN6_C PCIE_TXP6_C
R6V5 0 R6V4 0 C6V3 0.1uF C6V2 0.1uF R6V8 R6V6 C6G5 C6G3 0 0 0.1uF 0.1uF 0 0 0.1uF 0.1uF 0 0 0.1uF 0.1uF
+V3.3 13,14,17,25,27,32,33,34,35,36,38,45,46,55,56
NOTE: R7F3-5 are not needed when sharing SPI flash with ICH7M and Tekoa
R7F5 R7F4 R7F3 10K 10K 10K NO_STUFF NO_STUFF NO_STUFF
28 PCIE_RXN4_SLOT0 28 PCIE_RXP4_SLOT0 28 PCIE_TXN4_SLOT0 28 PCIE_TXP4_SLOT0 PCIE_RXN4_SLOT0 R6G5 PCIE_RXP4_SLOT0 R6G4 PCIE_TXN4_SLOT0 C6G1 PCIE_TXP4_SLOT0 C6F5 PCIE_RXN3_SLOT2 PCIE_RXP3_SLOT2 PCIE_TXN3_SLOT2 PCIE_TXP3_SLOT2 R6G3 R6G2 C6G7 C6G6
NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
40 40 29 40 29 40 29 40
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R
25,26 PCI_AD[31:0]
U7G1B
B
A
5
. w w w
16,25 16,25,26 16,25 16,25 INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
t p la
PCI
A3 B4 C5 B5 AE5 AD5 AG4 AH4 AD9 PIRQA# PIRQB# PIRQC# PIRQD# RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4#/GPIO22 GNT4#/GPIO48 GPIO1/REQ5# GPIO17/GNT5# C/BE0# C/BE1# C/BE2# C/BE3#
p o
D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8 B15 C12 D12 C15 A7 E10 B18 A12 C9 E11 B10 F15 F14 F16 C26 A9 B19 G8 F7 F8 G7 AE9 AG8 AH8 F21 AH20 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# RSVD[6] RSVD[7] RSVD[8] RSVD[9] MCH_SYNC#
-s
h c
16,26 26 16,26 26 16,25 25 16,25 25,26 25,26 25,26 25,26 16,26 16,25,26 16,25,26 16,26
R7F15 R7F14 R7F13 R7F12 R7F8 R7F9 R7F11 R7F10
0 0 0 0 0 0 0 0
D3 C4 D5 D4 E5 C3 A2 B3
OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31
USB
C
SPI
33 SPI_SCLK 33 SPI_CE# 33 SPI_ARB 33 SPI_SI 33 SPI_SO
m e
R8U4 1K NO_STUFF R8U3 R8U2 1K
SPI_CLK SPI_CS# SPI_ARB
SPI_MOSI SPI_MISO
a
0
m o .c s ic t
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP V26 V25 U28 U27 DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7 DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7 DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7 DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7 Y26 Y25 W28 W27 AB26 AB25 AA28 AA27 AD25 AD24 AC28 AC27 AE28 AE27 C25 D25 F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3 D2 D1 +V1.5S_PCIE_ICH 17 DMI_CLKN DMI_CLKP CLK_PCIE_ICH# 30 CLK_PCIE_ICH 30 DMI_ZCOMP DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P R7U9 24.9 1% DMI_IRCOMP_R USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB_PN7 USB_PP7 40 40 40 40 29 29 40 40 29 29 40 40 29 29 40 40 USBRBIAS# USBRBIAS USB_RBIAS_PN R8U5 22.6 1% Place within 500 mils of ICH FWH_WP# 24,35 FWH_TBL# 24,35 PCI_GNT#5 26 PCI_GNT#5_R GNT5_SPI 29
Direct Media Interface
D
3
PCI-Express
Place within 500 mils of ICH
C
ICH7M REV 1.02 EDS
PCI_GNT#3 25
PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#3
R7U18 - A16 swap override NO_STUFF by default STUFF for A16 swap override
B
PCI_GNT#5_R
PCI_REQ#5 16,26 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
R7F7 1K NO_STUFF
ICH7 Boot BIOS select
STRAP LPC (default) PCI