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MEROM/CRESTLINE FORM FACTOR REFERENCE DESIGN
D
Fan Header
PG 5
CRT LVDS/ALS/BLI CPU Thermal Sensor
PWM
Merom/Penryn 478 uFCPGA
PG 3,4
FSB
IMVP VR
Pages 52-54
Clocking
PG 37
ITP
PG 20
DB200
PG 38
PG 16
VGA
PG 5
HDMI
PG 18
C
LVDS SDVO HDMI Controller
Crestline 1299 FCBGA
Pages 6-11
Pages 13-15
Azalia
Port Header
USB0 PG 29
Port Header
PG 19
X4 DMI interface SATA HDD PG 30 SATA Dock PG 45 Dock PG 45 ODD PG 32 PATA SATA PORT 0 C-LINK
USB1 PG 29
Sky Forest
USB2 PG 26
Port Header
ICH8-M
SATA PORT 2
USB3 PG 29
Port Header
B
USB 2.0
PCIEx1
(LANE5) (LANE6)
GLCI
MINICARD
USB5 PG 25
MINICARD RJ11
Dock PG 45
Azalia
Azalia
SPI
HDR
USB4 PG 29
ODD PG 62 Interposer
LPC, 33MHz
USB6 PG 25
BLUETOOTH
USB7 PG 41
DOCKING
USB8 PG 45
A
Sky Forest
USB9 PG 26
5
. w w w
Audio
MDC
Page 27
Audio
Page 28
t p la
Nut Tree
PG 61
4
p o
Nut Tree HDR
PG 58
676 BGA
Pages 21-24
-s
33 Mhz PCI
C-LINK
PCIEx1
PCIEx1
PCIEx1 PCIEx1
h c
(LANE1) (LANE2) (LANE3) (LANE4)
m e
CardBus
PG 33,34
a
SODIMM1
PG 17
Dual Channel DDR2
m o .c s ic t
REV 1.1
Crestline GFX VR
PG 49
Crestline VCCP VR
PG 48
D
SODIMM0
SYSTEM Discharge
DDR VR
PG 56
PG 47
SYSTEM VR
PG 46
SLEEP CONTROL
PG 57
C
BATTERY CHARGER VR
PG 51
Minicard 1
PG 25
MOBILE POWER ON SEQUENCE
PG 55
Minicard 2
PG 25 PG 26
Sky Forrest AIC PGS 68-69 Expresscard & IR
B
DOCKING
PG 45
Nineveh LAN
PG 35
LAN Switch
PG 36
RJ45
I/O Xpander
PG 39
TPM
PG 44
SPI Flash
PG 36
SPI Flash
PG 36
Dock PG 45
SIO
PG 40
SMC/KSC
PG 42
Serial Header
Touch Pad HDR
PG 31
Oakmont Form Factor Reference Design
Title Title Page Size A Date: Document Number Sheet
2
Intel Confidential
A
Keyboard
SCN KBD HDR PG 31
3
Rev 1
1
Touch Pad
of
64
5
4
3
2
1
OAKMONT FORM FACTOR REFERENCE PLATFORM
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
2
I Voltage Rails
POWER PLANE +VBATA +VBAT +V5A +V5 +V5S +V3.3A +V3.3M +V3.3 +V3.3S +V1.5S +V1.8 +V0.9 +V1.25M +V1.25S +V1.05S +V1.05M +VCC_CORE +VCC_GFXCORE VOLTAGE 9V-12.5V 9V-12.5V 5V 5V 5V 3.3V 3.3V 3.3V 3.3V 1.5V 1.8V 0.9V 1.25V 1.25V 1.05V 1.05V 0.700V-1.77V 0.7V-1.25V ACTIVE IN S0 to S5, M0 to M-off S0 to S5, M0 to M-off S0 to S5, M0 to M-off S0/M0, S3/M1, S3/M-off S0/M0 S0 to S5, M0 to M-off S0 to S5, M0, M1 S0/M0, S3/M1, S3/M-off S0/M0 S0/M0 S0/M0, (S3 to S5)/M1, S3/M-off S0/M0, (S3 to S5)/M1, S3/M-off S0/M0, S3/M1, S3/M-off S0/M0 S0/M0 S0/M0, S3/M1, S3/M-off S0/M0 S0/M1 DESCRIPTION Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode
C / SMB Addresses System Support
Device Clock Generator DB200 Clock Buffer SO-DIMM0 SO-DIMM1 SO-DIMM0 Thermal Sensor SO-DIMM1 Thermal Sensor DDR Thermal Sensor Board ID Port Expander Ambient Light Sensor CPU Thermal Sensor IMVP6 Amb. Temp. Sensor Battery H8 TPM 5-CH-I2C HUB Minicard 1 Minicard 2 Express Card Refdes U32 U7 J8 J9 J8 J9 U6 U35 J7 U19 U5 J4 U60 U59 U63 J39 J32 J2000 Binary 1101 001x 1101 110x 1010 000x 1010 010x 0011 000x 0011 010x 0100 110x 0011 000x 0111 001x 0100 110x 1001 101x 0001 011x TBD 0100 1110 0011 xxxx N/A N/A N/A Hex D2 DC A0 A4 30 34 4C 30 72 4C 9A 16 TBD 4E 3x N/A N/A N/A Bus * SMB_ICH_M3 SMB_ICH_M3 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_BS ALS SMB_THRM SMB_THRM SMB_BS SMB_ME LPC SMB_ICH SMB_ICH_A1 SMB_ICH_A1 SMB_ICH_A1 Part Reference J6 J19 J20 J21 J23
Feature/Function
DDR core DDR command & control pull up. GMCH, ICH core, and FSB rail CPU core rail GMCH Graphics core rail
C
Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The rest come out of EC.
1 3 2
SOT-23
As seen from top
1 2 3
5
SOT23-5
Net Naming Conventions
Suffix # = Active Low Signal
4
Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else)
B
Power States
SIGNAL
SLP S3#
HIGH
SLP S4#
HIGH
SLP S5#
HIGH
S4 STATE#
HIGH
SLP M#
HIGH
STATE S0 (Full ON) /M0
S3 (Suspend to RAM) / M1
LOW
HIGH
HIGH
HIGH
HIGH
S4 (Suspend To Disk) /M1
S5 (Soft OFF) /M1
S3 (Suspend to RAM) / M-Off
S4 (Suspend To Disk) /M-Off
S5 (Soft OFF) /M-Off
A
. w w w
LOW HIGH HIGH LOW HIGH LOW HIGH LOW LOW HIGH LOW HIGH HIGH HIGH LOW LOW LOW HIGH LOW LOW LOW LOW LOW LOW LOW
to p la
+V*A +V*M +V* +V*S Clocks
ON ON ON ON ON ON ON ON OFF ON ON ON OFF (DDR ON) ON OFF ON ON ON OFF ON ON OFF ON OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF OFF
-s p
h c
m e
Interposer Add-In-Cards REF DEZ
Sky Forest Page 63 & 64
CR2000 CR2001 CR2002 J2000
a
ITP Connector Boot BIOS Strap H8 Program Shunt header H8 External Reflash Connector SIO Program Header
m o .c s ic t
Strapping Default (1 2) Default (1 2)
D
Feature Support
Bus Supported
Power Requirements
+V5S +V3.3S +V3.3A +V1.5S
C
LED_NETDETECT LED_PWR-GD/TURBO LED_S3 EXPRESSCARD 54MM CONNECTOR
Nut Tree Page 61
J2001 J2002 SW2000 SW2001 U2007 CR3000 CR3001 CR3002 CR3003 CR3004 CR3005 CR3006 CR3007 CR3008 MIC3000 SW3000 SW3001
SPEAKER HEADER 60-Pin Plug NETDETECT SWITCH LID SWITCH IRDA LED_WWAN LED_WLAN LED_BLUE TOOTH LED_Caps-lock LED_Num-lock LED_HDD Activity LED_S3 LED_Battery (Full/Low) LED_PWR-GD/TURBO Microphone POWER_SWITCH RF_KILL_SWITCH 50-PIN DVD RECEPTACLE (Short) Connects to Oakmont PB 50-PIN DVD RECEPTACLE (Long) Connects to ODD
N/A N/A N/A PCIEx1 (LANE3) USB (PORT 2) AUDIO FROM CODEC (Azalia) N/A N/A N/A IR (LPC) N/A N/A N/A N/A N/A N/A N/A N/A N/A AUDIO FROM CODEC (Azalia) SYSTEM_GROUND SYSTEM_GROUND
Power supplied by LED driving signals
ODD Interposer Page 62
J4000
IDE
+V5S
J4001
IDE
B
Wake Events
Wake Events RI# from serial port PME# from Cardbus Mini-card, Express-card wake event Wake on LAN LID switch attached to SMC USB HDA wake on ring SmLink for AOLII Hot Key from Scan matrix keyboard PWRBTN# Netdetect State Supported S3 S3 S3 S3/M1 S3 S3 S3 S3 S3 S3 S3, S4, S5 / M1
Oakmont Form Factor Reference Design
Title NOTES Size A Date:
4 3 2
Intel Confidential
A
Document Number Sheet 2
1
Rev of 64
5
5
4
3
2
1
4,6,9,10,20,21,24,45,48,54,56
+V1.05S
6
H_A#[35:3] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
U22A
D
6 6
H_ADSTB#0 H_REQ#[4:0]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE#
ADS# BNR# BPRI# DEFER# DRDY# DBSY#
H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_RS#0 H_RS#1 H_RS#2
H_ADS# 6 H_BNR# 6 H_BPRI# 6 H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ# 6 IERR# H_INIT# 21 H_LOCK# 6 H_CPURST# 6,20 H_RS#[2:0]
R613 56
CONTROL
BR0# IERR# INIT# LOCK#
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
6
H_TRDY# 6 H_HIT# 6 H_HITM# 6 ITP_BPM#0 20 ITP_BPM#1 20 ITP_BPM#2 20 ITP_BPM#3 20 ITP_BPM#4 20 ITP_BPM#5 20 ITP_TCK 20 ITP_TDI 20 ITP_TDO 20 ITP_TMS 20 ITP_TRST# 20 ITP_DBRESET# 20,55
6
H_A#[35:3]
+V1.05S
4,6,9,10,20,21,24,45,48,54,56
R612 75
6
THERMAL
PROCHOT# THERMDA THERMDC THERMTRIP# D21 A24 B25 C7
H_PROCHOT# 52 H_THERMDA 5 H_THERMDC 5 PM_THRMTRIP# 7,21
C
6 21 21 21 21 21 21 21 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#
PM_THRMTRIP# should connect to ICH8 and GMCH without T-ing (No stub)
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
H CLK
BCLK[0] BCLK[1] A22 A21
CLK_CPU_BCLK 37 CLK_CPU_BCLK# 37
TP_CPU_RSVD01 M4 TP_CPU_RSVD02 N5 TP_CPU_RSVD03 T2 TP_CPU_RSVD04 V3 TP_CPU_RSVD05 B2 TP_CPU_RSVD06 C3 TP_CPU_RSVD07 D2 TP_CPU_RSVD08 D22 TP_CPU_RSVD09 D3 TP_CPU_RSVD10 F6
Merom Ball-out Rev 1a_Oakmont
4,6,9,10,20,21,24,45,48,54,56
+V1.05S
B
DATA GRP 3
Layout Note: 1. Leave Escape routing for TP_CPU_RSVD[01:06] Signals for future functionality. 2. Route TP_CPU_RSVD[07:10] signals to TP via and place gnd via w/in 100mils.
A
5
. w w w
to p la
Layout note: Zo=55 ohm, 0.5" max for GTLREF.
-s p
R610 1K 1% R609 2K 1%
h c
6 6 6 6 6 6 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1
RESERVED
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[63:0]
m e
H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 CPU_TEST4 7,37 MCH_BSEL0 7,37 MCH_BSEL1 7,37 MCH_BSEL2
DATA GRP 2
a
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
U22B
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL[0] BSEL[1] BSEL[2]
m o .c s ic t
H_D#[63:0] 6
XDP/ITP SIGNALS
1K 1% 1K 1%
C550 0.1uF 10% NO_STUFF
R623 NO_STUFF R611 NO_STUFF
ADDR GROUP 0 ADDR GROUP 0
D
ADDR GROUP 1
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3]
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
C
DATA GRP 0
ICH
H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
DATA GRP 1
Layout note: Comp0,2 connect with Zo=27.4ohm (14 mils width on SL, 18 mils width on MS), make trace length shorter than 0.5". Comp1,3 connect with Zo=55ohm, make trace length shorter than 0.5".
H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R604 R605 R521 R519 27.4 54.9 27.4 54.9 1% 1% 1% 1%
B
H_GTLREF AD26 CPU_TEST01 C23 CPU_TEST02 D25 TP_CPU_TEST03 C24 AF26 TP_CPU_TEST05 AF1 TP_CPU_TEST06 A26
MISC
B22 B23 C21
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
H_DPRSTP# 7,21,52 H_DPSLP# 21 H_DPWR# 6 H_PWRGD 21 H_CPUSLP# 6 PSI# 52
Merom Ball-out Rev 1a_Oakmont
Place C552 close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signals.
A
Oakmont Form Factor Reference Design
Title Merom (1 of 2) Size Custom Date:
4 3 2
Intel Confidential
Document Number Sheet 3
1
Rev of 64
5
4
3
2
1
53,54,56
+VCC_CORE U22C
53,54,56
+VCC_CORE
D
2
C
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
R525 100 1%
+V1.05S
3,6,9,10,20,21,24,45,48,54,56
Customer Recommended bulk Cap
+ C382 220uF 10%
C542 270uF
10,18,24..26,48,56
+V1.5S
53,54,56 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 52 52 52 52 52 52 52
+VCC_CORE
C549 0.01uF 10%
R524 100 1% VCCSENSE 52 VSSSENSE 52
Merom Ball-out Rev 1a_Oakmont
B
A
5
. w w w
to p la
4
-s p
C151 10uF
LAYOUT NOTE: NEAR PIN B26
Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.
h c
PLACE C551
m e
a
m o .c s ic t
U22D
D
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
1
C
B
Merom Ball-out Rev 1a_Oakmont
A
Oakmont Form Factor Reference Design
Title Merom (2 of 2) Size Custom Date:
3 2
Intel Confidential
Document Number Sheet 4
1
Rev of 64
5
4
3
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
2
1
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 Layout Note: Route H_THERMDA and H_THERMDC on same layer w/ 10 mil trace & 10 mil spacing. Route away from noise sources with ground guard tracks on each side.
+V3.3S
CPU Thermal Sensor
C520 0.1uF U19: Place at SouthEast corner of CPU, near H_THERMDA/C pins 8 7 6 5 THRM_ALERT# R10525 NO_STUFF 0 R116 10K R109 10K
R596 10K U29 1 3 3 H_THERMDA H_THERMDC R103 R122 499 1% 499 1% ADT_THERM_DXP C521 1000pF 5% ADT_THERM_DXN ADT_THM# 2 3 4 VDD D+ DTHM#
SCLK SDATA ALRT#/THM2# GND
SMB_THRM_CLK 42 SMB_THRM_DATA 42 PM_THRM# 23,42
D
ADT7461A-TEMP MON
System thermal monitoring
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
+V3.3S
Q95: Place below fan at west edge of board
R484 10K 7481_D1P R41 0 7481_D1P_R 7481_D1N_R 0 7481_THRM# 1 2 3 4 5
C354 0.1uF
PLACE PULLUPS BY DEVICE U5: Place north of IMVP on primary side Q1: Place near RHE at extreme North edge of board 3 C48 1000pF 10%
C
3 1 Q68 2 2N3904 U7 VDD SCLK D1+ SDATA D1ALRT#/THM2# THM# D2+ GND D210 9 8 7 6 7481_THRM2# 7481_D2P 7481_D2N C357 1000pF 10% 7481_D1N R42
SMB_THRM_CLK 42 SMB_THRM_DATA 42
ADT7481ARMZ-1 TEMP MON 7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
R496 10K
R482 NO_STUFF R483 NO_STUFF
B
CPU Fan Power Control
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
16..18,24,26,28,30..32,34,49,50,52,53,56,57
42 CPU_PWM_FAN
A
. w w w
8 9 _ R593 15K OPA567_POSIN 1% C533 1uF 10% OPA567_NEGIN
C136 0.1uF 10%
C131 4.7uF 10% EU2
TF EN OUT OPA567 + ISIF HS V4 5 13 6 7
to p la
+V5S 1 12 10 11 V+ 2 3 VOUT_OPAMP R603 1.74K 1% 3 Q70 BAT54 OPA567_ISIN_R 1 R607 20K R599 3.32K 1%
-s p
0 0 +V3.3S R591 1.07k 1% 3 2 1 3 2 1 2 1 2 1 J12 CONN3_HDR
PM_THRM# 23,42
h c
2 CPU_TACHO_FAN
1
Q1 2N3904
m e
a
m o .c s ic t
Note: No-Stuff R141 for normal operation.
D
C
B
42
J11 CONN2_HDR
Oakmont Form Factor Reference Design
Title CPU Thermal Sensor & Fan Size A Date: Document Number Sheet
2
Intel Confidential
A
Rev 5
1
of
64
5
4
3
5
4
3
2
1
U17A 3 H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B3 C2 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_A#[35:3]
D
+V1.05S
3,4,9,10,20,21,24,45,48,54,56
R173 221 1%
H_SWING
R10526 100 1%
C167 0.1uF
H_RCOMP R177 24.9 1%
C
+V1.05S
3,4,9,10,20,21,24,45,48,54,56 54.9 1% 54.9 1% H_SCOMP
R175
R176
H_SCOMP#
B
Note: H_CPURST# has T topology
3,4,9,10,20,21,24,45,48,54,56
+V1.05S
A
. w w w
R146 2K 1%
R154 1K 1%
C149 0.1uF 10%
t p la
3,20 H_CPURST# 3 H_CPUSLP#
p o
H_SWING H_RCOMP H_SCOMP H_SCOMP#
W1 W2
B6 E5
-s
H_SWING H_RCOMP H_SCOMP H_SCOMP# H_CPURST# H_CPUSLP# H_AVREF H_DVREF
h c
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
m e
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 K5 L2 AD13 AE13 M7 K3 AD2 AH11 L7 K2 AC2 AJ10 M14 E13 A11 H13 B12 E12 D7 D8 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
a
HOST
m o .c s ic t
3 H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3 H_BPRI# 3 H_BREQ# 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 37 CLK_MCH_BCLK# 37 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 3 3 3 3 3 3 3 3 3 3 3 3 H_REQ#[4:0] 3 H_RS#[2:0] 3
D
C
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
B
B9 A9
CRESTLINE_1p0_OAKMONT
H_VREF
Oakmont Form Factor Reference Design
Title CRESTLINE (1 OF 6) Size A Date:
4 3 2
Intel Confidential
A
Document Number Sheet 6
1
Rev of 64
5
5
U17B TP_MCH_RSVD1 TP_MCH_RSVD2 TP_MCH_RSVD3 TP_MCH_RSVD4 TP_MCH_RSVD5 TP_MCH_RSVD6 TP_MCH_RSVD7 TP_MCH_RSVD8 TP_MCH_RSVD9 TP_MCH_RSVD10 TP_MCH_RSVD11 TP_MCH_RSVD12 TP_MCH_RSVD13 TP_MCH_RSVD14 P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
4
5,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
3
+V3.3S R84 R71 10K 1% 10K 1% 10K 1% CLK_MCH_OE# PM_EXTTS#0 PM_EXTTS#1
2
1
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1
AV29 BB23 BA25 AV23 AW30 BA23 AW25 AW23 BE29 AY32 BD39 BG37 BG20 BK16 BG16 BE13 BH18 BJ15 BJ14 BE16 BL15 BK14 SM_RCOMP SM_RCOMP#
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4 M_CKE0 M_CKE1 M_CKE3 M_CKE4 M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_ODT0 M_ODT1 M_ODT2 M_ODT3 13,15 13,15 14,15 14,15 13,15 13,15 14,15 14,15 13,15 13,15 14,15 14,15
13 13 14 14 13 13 14 14
R83
D
17 L_BKLT_CTRL 17 L_BKLT_EN 17 L_CTRL_CLK 17 L_CTRL_DATA 17 LVDS_DDC_CLK 17 LVDS_DDC_DATA 17 LVDS_VDD_EN LVDS_IBG TP_LVDS_VBG
J40 H39 E39 E40 C37 D35 K40 L41 L43 N41 N40 D46 C45 D44 E42 G51 E51 F49 C48 G50 E50 F48 D47
GRAPHICS
DDR
TP_MCH_RSVD20 TP_MCH_RSVD21 TP_MCH_RSVD22 TP_MCH_RSVD23 TP_MCH_RSVD24 TP_MCH_RSVD25 TP_MCH_RSVD26 TP_MCH_RSVD27 TP_MCH_RSVD28 TP_MCH_RSVD29 TP_MCH_RSVD30 TP_MCH_RSVD31 TP_MCH_RSVD34 TP_MCH_RSVD35 TP_MCH_RSVD36
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BH39 AW20 BK20
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD34 RSVD35 RSVD36 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
MUXING
17 17 17 17 17 17 17 17 17 17 17 17 M_VREF_MCH 13,14,47
LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3
BK31 SM_RCOMP_VOH BL31 SM_RCOMP_VOL AR49 AW4
17 LVDSB_DATA#0 17 LVDSB_DATA#1 17 LVDSB_DATA#2 DREFCLK 37 DREFCLK# 37 DREFSSCLK 37 DREFSSCLK# 37 CLK_PCIE_3GPLL 37 CLK_PCIE_3GPLL# 37 R124 R119 R111 17 LVDSB_DATA0 17 LVDSB_DATA1 17 LVDSB_DATA2
CLK
PEG_CLK PEG_CLK#
K44 K45
C
Don't need to strap CFG[4:3]. BIOS will read SPD and determine DDR frequency.
3,37 MCH_BSEL0 3,37 MCH_BSEL1 3,37 MCH_BSEL2 TP_MCH_CFG_3 TP_MCH_CFG_4 TP_MCH_CFG_5 TP_MCH_CFG_6 TP_MCH_CFG_7 TP_MCH_CFG_8 MCH_CFG_9 TP_MCH_CFG_10 TP_MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 TP_MCH_CFG_14 TP_MCH_CFG_15 TP_MCH_CFG_16 TP_MCH_CFG_17 TP_MCH_CFG_18 MCH_CFG_19 TP_MCH_CFG_20 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
AN47 AJ38 AN42 AN46 AM47 AJ39 AN41 AN45
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN[3:0] 22
DMI_TXP[3:0] 22
R129 4.02K NO STUFF 1%
AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40 DMI_RXN2 AM44 DMI_RXN3 AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39 DMI_RXP2 AM43 DMI_RXP3
DMI_RXN[3:0]
22
GRAPHICS VID
R95 4.02K 1% NO_STUFF
B
23 PM_BMBUSY# 3,21,52 H_DPRSTP# 13,15 PM_EXTTS#0 14,15 PM_EXTTS#1 23,52 DELAY_VR_PWRGOOD R10527 19,22,25,26,40,58 PLT_RST# 3,21 PM_THRMTRIP# 23,52 PM_DPRSLPVR
G41 L39 L36 J36 AW49 100 RST_IN#_MCH AV20 N20 G36
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
A
MCH CONFIG STRAPS
PCI Express Graphics Lane Low = Reverse Lane High = Normal operation (default) MCH_CFG_9 DMI Lane Reversal Low = Normal (default) High = Lanes Reversed MCH_CFG_19
. w w w
CRESTLINE_1p0_OAKMONT
TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
to p la
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN E35 A39 C38 B39 E36 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AM49 AK50 AT43 AN49 AM50 SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2 H35 K36 G39 G40 A37 R32 MCH_TEST_R MCH_CFG_12 MCH_CFG_13
DFGT_VID_0 DFGT_VID_1 DFGT_VID_2 DFGT_VID_3 DFGT_VR_EN
ME
CL_CLK0 23 CL_DATA0 23 MPWROK 23,47 CL_RST#0 23
-s p
DMI_RXP[3:0] 22 49 49 49 49 49 10,37,48,56,57 MCH_CLVREF R81 10K R113 4.02K 1% NO_STUFF
h c
R89 R94 R91 16 16 CRT_HSYNC CRT_VSYNC R72 1K 1% R66 392 1% +V1.8_GMCH R152 20 1%
16
16
m e
150 1% 150 1% 150 1% TVA_DAC TVB_DAC TVC_DAC CRT_BLUE CRT_GREEN R88 R87 30.1 30.1 1% 1% 2 9,10,45 C128 0.01uF 10% 402 C514 2.2uF 10% 1 C117 0.01uF 10% 402 C499 2.2uF 10%
PCI-EXPRESS
TP_MCH_RSVD39 B44 TP_MCH_RSVD40 C44 TP_MCH_RSVD41 A35 TP_MCH_RSVD42 B37 TP_MCH_RSVD43 B36 TP_MCH_RSVD44 B34 TP_MCH_RSVD45 C34 +V3.3S 5,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
B42 C42 H48 H47
a
G44 B47 B45 E44 A47 A45
E27 G27 K27
m o .c s ic t
U17C L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK PEG_COMPI PEG_COMPO N43 M43 PEG_COMP R70 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 TP_PEG_RX#0 TP_PEG_RX#2 TP_PEG_RX#3 TP_PEG_RX#4 TP_PEG_RX#5 TP_PEG_RX#6 TP_PEG_RX#7 TP_PEG_RX#8 TP_PEG_RX#9 TP_PEG_RX#10 TP_PEG_RX#11 TP_PEG_RX#12 TP_PEG_RX#13 TP_PEG_RX#14 TP_PEG_RX#15 TP_PEG_RX0
10
+VCC_PEG
24.9 1%
DMI
MISC
XOR / ALLZ / Clock Un-gating MCH_CFG_12 MCH_CFG_13 Configuration 0 0 Reserved 0 1 XOR Mode Enabled 1 0 All-Z Mode Enabled 1 1 Clock Gating Enabled (default)
RSVD CFG PM NC
SDVOB_INTN 18
D
LVDS LVDS
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
TP_PEG_RX2 TP_PEG_RX3 TP_PEG_RX4 TP_PEG_RX5 TP_PEG_RX6 TP_PEG_RX7 TP_PEG_RX8 TP_PEG_RX9 TP_PEG_RX10 TP_PEG_RX11 TP_PEG_RX12 TP_PEG_RX13 TP_PEG_RX14 TP_PEG_RX15
SDVOB_INTP 18
TVA_DAC TVB_DAC TVC_DAC TVA_RTN TVB_RTN TVC_RTN
F27 J27 L27
TP_TV_DCONSEL_0 TP_TV_DCONSEL_1
M35 P33
TV_DCONSEL_0 TV_DCONSEL_1
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
TP_PEG_TX#4 TP_PEG_TX#5 TP_PEG_TX#6 TP_PEG_TX#7 TP_PEG_TX#8 TP_PEG_TX#9 TP_PEG_TX#10 TP_PEG_TX#11 TP_PEG_TX#12 TP_PEG_TX#13 TP_PEG_TX#14 TP_PEG_TX#15
SDVOB_RN 18 SDVOB_GN 18 SDVOB_BN 18 SDVOB_CLKN 18
C
TV TV
16 CRT_RED 150 1% 150 1% 150 1%
H32 G32 K29 J29 F29 E29 K33 G35 HSYNC F33 CRTIREF C32 VSYNC E33
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
16 CRT_DDC_CLK 16 CRT_DDC_DATA
+V1.8_GMCH R99 1K 0.10%
R588 1.30K 0.5%
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
TP_PEG_TX4 TP_PEG_TX5 TP_PEG_TX6 TP_PEG_TX7 TP_PEG_TX8 TP_PEG_TX9 TP_PEG_TX10 TP_PEG_TX11 TP_PEG_TX12 TP_PEG_TX13 TP_PEG_TX14 TP_PEG_TX15
SDVOB_RP 18 SDVOB_GP 18 SDVOB_BP 18 SDVOB_CLKP 18
VGA VGA
B
CRESTLINE_1p0_OAKMONT
+V1.25M
SM_RCOMP_VOH R93 3.01k
C71 0.1uF 10%
LVDS_IBG SM_RCOMP_VOL R90 1K 0.10% R77 2.37K 1%
SDVO_CTRLCLK 18 SDVO_CTRLDATA 18 CLK_MCH_OE# 37 MCH_ICH_SYNC# 23
9,10,45
Oakmont Form Factor Reference Design
Title
SM_RCOMP SM_RCOMP# R153 20 1%
Intel Confidential
A
CRESTLINE (2 OF 6) Size A Date: Document Number Sheet
2
R121 4.02K 1% NO_STUFF
Rev 7
1
of
64
5
4
3
5
4
3
2
1
13 M_A_DQ[63:0]
U17D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 BB19 BK19 BF29 BL17 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29 BE18 AY20 BA19 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 TP_SA_RCVEN# M_A_BS0 13,15 M_A_BS1 13,15 M_A_BS2 13,15 M_A_CAS# 13,15 M_A_DM[7:0] 13
14 M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
U17E SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
D
A
B
M_A_DQS[7:0] 13
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_RAS# SA_RCVEN# SA_WE#
M_A_DQS#[7:0]
13
SYSTEM
M_A_RAS# 13,15 M_A_WE# 13,15
B
CRESTLINE_1p0_OAKMONT
A
. w w w
5
to p la
4
-s p
h c
DDR
DDR
SYSTEM
C
M_A_A[14:0] 13,15
m e
a
MEMORY
m o .c s ic t
SB_BS_0 SB_BS_1 SB_BS_2 AY17 BG18 BG36 BE17 M_B_BS0 14,15 M_B_BS1 14,15 M_B_BS2 14,15 M_B_CAS# 14,15 M_B_DM[7:0] 14 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_DQS[7:0] 14 M_B_DQS#[7:0] 14 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24 AV16 AY18 BC17 M_B_A[14:0] 14,15 SB_RAS# SB_RCVEN# SB_WE# TP_SB_RCVEN# M_B_RAS# 14,15 M_B_WE# 14,15
D
MEMORY
C
B
CRESTLINE_1p0_OAKMONT
Oakmont Form Factor Reference Design
Title CRESTLINE (3 OF 6) Size A Date:
3 2
Intel Confidential
A
Document Number Sheet 8
1
Rev of 64
5
4
3
2
1
+V1.05S 3,4,6,10,20,21,24,45,48,54,56 +V1.05S
3,4,6,10,20,21,24,45,48,54,56
Customer Recommended bulk Cap
U17G 1 + C60 220uF 10% AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
49,56 +VCC_GFXCORE
D
R30
+VCC_GFXCORE
49,56
+V1.8_GMCH
7,10,45 AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
POWER
These caps are cavity capacitors
3 + C204 330uF + C195 330uF 3 2 C524 0.47uF C517 1uF C556 10uF C592 22uF C535 0.1uF 10% 1 1
C
+VCC_GFXCORE
49,56 R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
B
A
. w w w
CRESTLINE_1p0_OAKMONT
to p la
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 AW45 BC39 BE39 BD17 BD4 AW8 AT6 VCC_SM_LF1_C VCC_SM_LF2_C VCC_SM_LF3_C VCC_SM_LF4_C VCC_SM_LF5_C VCC_SM_LF6_C VCC_SM_LF7_C C541 0.1uF 10%
VCC GFX
-s p
C554 0.22uF C536 0.22uF
VCC AXM NCTF
h c
C2032 1uF C454 1uF
m e
+V1.05M48,56 C472 22uF C495 0.22uF Edge +V1.8 10,13,14,18,45,47,56 R85 0.002 1%
VCC NCTF
C523 0.1uF 10%
VCC SM
VCC GFX NCTF
VSS SCB
a
C500 0.1uF 10%
2
VSS NCTF
VCC_13
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
VCC CORE
C402 270uF
C482 0.1uF 10%
C2030 22uF
C2031 0.22uF
EDGE
CAVITY
m o .c s ic t
3,4,6,10,20,21,24,45,48,54,56 Q16 R64 1 2 10 VCCGFOLLOW2 3 1 BAT54 U17F C474 0.22uF AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
+V3.3S
5,7,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V1.05S
2
D
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
C
POWER
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 A3 B2 C1 BL1 BL51 A51
48,56 +V1.05M VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
C496 0.22uF
C480 0.1uF 10%
C509 0.1uF 10%
Cavity
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 7,10,45
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
VCC AXM
B
+V1.8_GMCH
CRESTLINE_1p0_OAKMONT + C437 330uF C106 22uF C101 22uF C483 0.1uF 10%
VCC SM LF
C538 0.1uF 10%
C470 0.47uF
Oakmont Form Factor Reference Design
Title CRESTLINE (4 OF 6) Size A Date:
4 3 2
Intel Confidential
A
Document Number Sheet 9
1
Rev of 64
5
5
+V1.25S 24,56,57 +V1.25S_DPLLA 10uH L3 1 1 10% 2 C424 470uF C91 0.1uF 10%
4
3
5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 C497 0.1uF 10% Keep C112 near A33 and B33 R82 FB9 V3.3S_CRTDAC_FB 180ohm@100MHz 1 2 3 22nF V3.3S_CRTDAC C110 0.1uF 10% +V3.3S_BGDAC_VCCA_TV J32 A33 B33 A30 +V3.3S
2
NOTE Place caps on this page close to GMCH
1
U17H VCCSYNC VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 VCCA_DAC_BG VSSA_DAC_BG VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL VCCA_LVDS VSSA_LVDS
+ C208 220uF 10%
Customer Recommended bulk Cap
10uH L2 1
D
1 10%
2 C65 470uF C86 0.1uF 10% 5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S FB11 V3.3S_CRTDAC__BG_FB 180ohm@100MHz C516 10uF C126 0.1uF 10% 1 2 Keep C516 and FB11 close to source R102 3 22nF +V1.25S_DPLLA +V1.25S_DPLLB +V1.25M_HPLL
CRT
+V1.25S_DPLLB
B32 B49 H49 +V1.25M_MPLL AL2 AM2 A41 B41
+V1.25M_HPLL FB12 1 2 C184 22uF FB13 1 2 R183 0.5 1% +V1.25M_MPLL_R C186 22uF 120ohm@100MHz C174 0.1uF 10% +V1.25M_MPLL 120ohm@100MHz
+V1.8_TXLVDS
PLL
+V1.25M
7,37,48,56,57
Place near A41
C96 1000pF 10%
C175 0.1uF 10% C85 0.1uF 10% +V1.8_GMCH 7,37,48,56,57 C133 22uF +V1.25M Placeholder R589 for inductor 0
+V1.25S_PEGPLL
VSSA_PEG_BG
A PEG
5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
+V3.3S
C87 0.1uF 10%
VCCA_PEG_BG
K49 U51
VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5
+V1.25M_A_SM
+V1.8_SM_CK
1uH L5 R128 1 2
1.00 +V1.8_SMCK_RC 1% C137 10uF
4,18,24..26,48,56 +V1.25M 7,37,48,56,57
+V1.5S R86
R601 C526 1.0uF 402 C142 4.7uF 10% C537 22uF 1 + C548 100uF
0 C527 22uF NO_STUFF C112 0.1uF 10%
1 2
3 22nF
VCCD_CRTDAC
M32 L29 N28 AN2 U48 J41 H42
B
+V1.5S
4,18,24..26,48,56 FB10
+V1.25S_PEGPLL FB29 220ohm_at_100MHz
2
24,56,57
+V1.25S
R69
1.00 1%
+V1.25S_PEGPLL_RC C67 10uF
A
. w w w
5
5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
t p la
+V1.5S_VCCDQ_CRT_FB 180ohm@100MHz +V3.3S
R92
C88 0.1uF 10%
C468 1.0uF 402
VCCD_LVDS_1 VCCD_LVDS_2
LVDS
PLACE ON THE EDGE
C119 0.1uF 10%
3,4,6,9,20,21,24,45,48,54,56
p o
1 3 22nF +V1.05S 1 Q19 BAT54 V1_05S_SD 3 1 R78 10 2 R80 0
DMI
VCCD_CRT VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL
D TV/CRT
PEG
+V1.25M_A_SM
R602 to be used if 3.9nH needs to be stuffed
-s
+V1.25M C170 0.1uF 10% C100 0.1uF 10%
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
HV
TVO Supplies must be powered even if TV is not used. Seperate LDO must be used if TV is enabled.(This design has TV disabled)
VCCA_SM_CK[1_2] C512 180pF 5% NO_STUFF C498 180pF 5% NO_STUFF
C507 0.1uF 10%
2
VCCDQ_CRT 7,37,48,56,57
VTTLF
+V1.25S_PEGPLL
h c
C508 22uF +V1.8
AT22 AT21 AT19 AT18 AT17 AR17 AR16 BC29 BB29
VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_CK_1 VCCA_SM_CK_2
A SM
C
7,9,45
+V3.3S_BGDAC_VCCA_TV
m e
C25 B25 C27 B27 B28 A28 +VCC_PEG 7 C401 10uF
AW18 AV19 AU19 AU18 AU17
SM CK
a
L18 + C64 220uF 10%
AXD
K50
AXF
POWER
m o .c s ic t
A LVDS
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 C578 4.7uF 10% C568 4.7uF 10% C176 0.47uF
+V1.05S
3,4,6,9,20,21,24,45,48,54,56
1
2
C177 2.2uF 10%
2
C187 270uF
D
VTT
2
+V1.25M
7,37,48,56,57
R594 0
Placeholder for 5.6nH inductor
24,56,57
+V1.25S 1 0 2
VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6
AT23 VCC_AXD[1_6] AU28 AU24 AT29 AT25 AT30 AR29
C519 1.0uF 402
C525 22uF NO_STUFF
R134 Placeholder for 0.1uH inductor
VCC_AXD_NCTF VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI
VCC_AXF[1_3] 24,56,57
+V1.25S
B23 B21 A21
C130 1.0uF 402
C134 10uF NO_STUFF
AJ50
+V1.8_SM_CK
C83 0.1uF 10%
C
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
BK24 BK23 BJ24 BJ23
C132 0.1uF 10% +V1.8_TXLVDS
A CK
VCC_TX_LVDS VCC_HV_1 VCC_HV_2
A43 +V3.3S_HV C40 B40 AD51 W50 W51 V49 V50 7 +VCC_PEG AH50 AH51 A7 F2 AH1 MCH_VTTLF1 MCH_VTTLF2 MCH_VTTLF3 C178 0.47uF C555 0.47uF C152 0.47uF 7 +VCC_PEG Place near A43 C99 1000pF 10%
TV
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
VCC_RXR_DMI_1 VCC_RXR_DMI_2 VTTLF1 VTTLF2 VTTLF3
9,13,14,18,45,47,56
B
CRESTLINE_1p0_OAKMONT
91nH 1
+V1.05S 3,4,6,9,20,21,24,45,48,54,56
2
9,13,14,18,45,47,56 +V1.8_TXLVDS 1uH L19 1 1 + C94 220uF 10% 2
+V1.8
+V3.3S_HV
Oakmont Form Factor Reference Design
Title CRESTLINE (5 OF 6) Size A Date: Document Number Sheet
2
2
Intel Confidential
A
Rev 10
1
of
64
4
3
5
4
3
2
1
U17I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
D
VSS
C
B
A
. w w w
5
to p la
4
-s p
h c
m e
a
C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39
m o .c s ic t
U17J VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 CRESTLINE_1p0_OAKMONT VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
D
C
VSS
K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
B
Oakmont Form Factor Reference Design
Title CRESTLINE (6 OF 6) Size A Date:
3 2
Intel Confidential
A
CRESTLINE_1p0_OAKMONT
Document Number Sheet 11
1
Rev of 64
5
4
3
2
1
D
C
THIS PAGE INTENTIONALLY LEFT BLANK
B
A
. w w w
5
to p la
4
-s p
h c
m e
a
m o .c s ic t
D
C
B
Oakmont Form Factor Reference Design
Title BLANK Size A Date:
3 2
Intel Confidential
A
Document Number Sheet 12
1
Rev of 64
5
4
3
2
1
EXTTS#0 & EXTTS#1 connection options table
9,10,14,18,45,47,56
+V1.8
R459 10K 1%
D
7,14,47 M_VREF_MCH R460 10K 1% M_A_DQ[63:0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 8
8,15 M_A_A[14:0]
J8A M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
8,15 M_A_BS2 8,15 8,15 7,15 7,15 7 7 7 7 7,15 7,15 8,15 8,15 8,15 M_A_BS0 M_A_BS1 M_CS#0 M_CS#1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 M_CKE0 M_CKE1 M_A_CAS# M_A_RAS# M_A_WE#
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
C
Note: SO-DIMM0 SPD Address is A0 Hex SO-DIMM0 TS Address is 30 Hex
10K 10K
SA0_DIM0 SA1_DIM0
14,15,23 SMB_CLK_M2 14,15,23 SMB_DATA_M2 7,15 M_ODT0 7,15 M_ODT1 8 M_A_DM[7:0]
8 M_A_DQS[7:0]
B
A
. w w w
5
t p la
8 M_A_DQS#[7:0]
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
p o
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
CON200_DDR2-SODIMM-REV DQ0 5 DQ1 7 DQ2 17 DQ3 19 DQ4 4 DQ5 6 DQ6 14 DQ7 16 DQ8 23 DQ9 25 DQ10 35 DQ11 37 DQ12 20 DQ13 22 DQ14 36 DQ15 38 DQ16 43 DQ17 45 DQ18 55 DQ19 57 DQ20 44 DQ21 46 DQ22 56 DQ23 58 DQ24 61 DQ25 63 DQ26 73 DQ27 75 DQ28 62 DQ29 64 DQ30 74 DQ31 76 DQ32 123 DQ33 125 DQ34 135 DQ35 137 DQ36 124 DQ37 126 DQ38 134 DQ39 136 DQ40 141 DQ41 143 DQ42 151 DQ43 153 DQ44 140 DQ45 142 DQ46 152 DQ47 154 DQ48 157 DQ49 159 DQ50 173 DQ51 175 DQ52 158 DQ53 160 DQ54 174 DQ55 176 DQ56 179 DQ57 181 DQ58 189 DQ59 191 DQ60 180 DQ61 182 DQ62 192 DQ63 194
14,15,23,24,35,36,42,45,50,56,57
14 PM_EXTTS#0-1
7,15 PM_EXTTS#0
-s
h c
m e
+V1.8 C441 0.1uF 10% +V1.8
a
R61 C107 0.1uF 10%
m o .c s ic t
Dimms EXTTS# options Stuffing Options To EXTTS#0 (Default) To EXTTS#1 Stuff: R64 No-stuff: R59
Dimm-0
Stuff: R59, R63 No-stuff: R64
To EXTTS#0 & EXTTS#1 Stuff: To EXTTS#0 (Default) To EXTTS#1
R64, R59, R63
Stuff: R64, R59 No-stuff: R63 Stuff: R63 No-stuff: R59
D
Dimm-1
To EXTTS#0 & EXTTS#1 Stuff:
R64, R59, R63
+V3.3M
+V1.8
9,10,14,18,45,47,56 J8B
CON200_DDR2-SODIMM-REV VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
C147 0.1uF 10%
C144 2.2uF 10%
112 111 117 96 95 118 81 82 87 103 88 104 199 83 120 50 69 163 1
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12
VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF GND0 GND1 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
C
0
7,14,47 M_VREF_MCH C339 0.1uF 10% C340 2.2uF 10%
201 202 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8
R151
R160
9,10,14,18,45,47,56
C429 0.1uF 10%
C93 0.1uF 10%
Layout Note: Place these Caps near So-Dimm0.
B
Layout Note: Place these Caps near So-Dimm0.
9,10,14,18,45,47,56
C515 330uF
C97 2.2uF 10%
C89 2.2uF 10%
C103 2.2uF 10%
C458 2.2uF 10%
C459 2.2uF 10%
Oakmont Form Factor Reference Design
Title DDR SODIMM 0 Size A Date:
4 3 2
Intel Confidential
A
Document Number Sheet 13
1
Rev of 64
5
4
3
2
1
D
8,15 M_B_A[14:0]
J9A M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186
8,15 M_B_BS2 8,15 8,15 7,15 7,15 7 7 7 7 7,15 7,15 8,15 8,15 8,15 M_B_BS0 M_B_BS1 M_CS#2 M_CS#3 M_CLK_DDR3 M_CLK_DDR#3 M_CLK_DDR4 M_CLK_DDR#4 M_CKE3 M_CKE4 M_B_CAS# M_B_RAS# M_B_WE#
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
13,15,23,24,35,36,42,45,50,56,57
+V3.3M
C
R158 10K
SA0_DIM1 SA1_DIM1
Note: SO-DIMM1 SPD Address is A4 Hex SO-DIMM1 TS Address is 34 Hex
13,15,23 SMB_CLK_M2 13,15,23 SMB_DATA_M2 7,15 M_ODT2 7,15 M_ODT3 8 M_B_DM[7:0] R157 10K
8 M_B_DQS[7:0]
8 M_B_DQS#[7:0]
B
A
. w w w
5
t p la
4
CON200_DDR2-SODIMM-STAN DQ0 5 DQ1 7 DQ2 17 DQ3 19 DQ4 4 DQ5 6 DQ6 14 DQ7 16 DQ8 23 DQ9 25 DQ10 35 DQ11 37 DQ12 20 DQ13 22 DQ14 36 DQ15 38 DQ16 43 DQ17 45 DQ18 55 DQ19 57 DQ20 44 DQ21 46 DQ22 56 DQ23 58 DQ24 61 DQ25 63 DQ26 73 DQ27 75 DQ28 62 DQ29 64 DQ30 74 DQ31 76 DQ32 123 DQ33 125 DQ34 135 DQ35 137 DQ36 124 DQ37 126 DQ38 134 DQ39 136 DQ40 141 DQ41 143 DQ42 151 DQ43 153 DQ44 140 DQ45 142 DQ46 152 DQ47 154 DQ48 157 DQ49 159 DQ50 173 DQ51 175 DQ52 158 DQ53 160 DQ54 174 DQ55 176 DQ56 179 DQ57 181 DQ58 189 DQ59 191 DQ60 180 DQ61 182 DQ62 192 DQ63 194
M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
8
13,15,23,24,35,36,42,45,50,56,57
13 PM_EXTTS#0-1 7,15 PM_EXTTS#1
p o
-s
h c
C433 0.1uF 10% C109 2.2uF 10%
+V1.8 9,10,13,18,45,47,56
m e
R58 0 0 R60 NO_STUFF C447 0.1uF 10% C104 0.1uF 10% C95 0.1uF 10% C461 2.2uF 10% C462 2.2uF 10% C92 2.2uF 10%
a
PM_EXTTS#0-1_R
m o .c s ic t
+V3.3M 9,10,13,18,45,47,56 +V1.8 J9B 112 111 117 96 95 118 81 82 87 103 88 104 199 83 120 50 69 163 1 C338 0.1uF 10% C2033 2.2uF 10% 201 202 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF GND0 GND1 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 C171 0.1uF 10% C758 2.2uF 10% VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57
D
CON200_DDR2-SODIMM-STAN 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
C
7,13,47 M_VREF_MCH
Layout Note: Place these Caps near So-Dimm1.
+V1.8 9,10,13,18,45,47,56
B
C98 2.2uF 10% C471 330uF
Layout Note: Place these Caps near So-Dimm1.
SO-DIMM 1 is placed farther from the GMCH than SO-DIMM 0
Oakmont Form Factor Reference Design
Title DDR2 SODIMM 1 Size A Date:
3 2
Intel Confidential
A
Document Number Sheet 14
1
Rev of 64
5
4
3
2
1
DDR2 Thermal Sensor So-Dimm 0 & 1
Layout Note: Place Q17 under SO-DIMM0 3 1 2 7,14 PM_EXTTS#1 R51 DDR_THERM2 DDR_THERM1 0
+V3.3M
13,14,23,24,35,36,42,45,50,56,57
U8
D
Q15 2N3904
1 2 3
VDD D+ DTHERM#
SCLK SDATA ALERT# GND
8 7 6 5 PM_EXTTS#0_D R52 0
SMB_CLK_M2 13,14,23 SMB_DATA_M2 13,14,23 PM_EXTTS#0 7,13 +V0.9 47,56
PM_EXTTS#1_D 4
ADM1032AR Layout Note: Place U6 under SO-DIMM1
R545 R535 R540 R539 R580 R587 R579 R586 R573 R568 R549 R577 R581 R572 R570 R567 R541 R574 R578 R571 R576 R585 R575 R582
+V0.9
47,56
Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9
C
C452 0.1uF 10%
C434 0.1uF 10%
C2034 0.1uF 10%
C440 0.1uF 10%
C432 0.1uF 10%
C455 0.1uF 10%
C473 0.1uF 10%
C469 0.1uF 10%
C444 0.1uF 10%
C467 0.1uF 10%
C475 0.1uF 10%
C477 0.1uF 10%
C450 0.1uF 10%
C435 0.1uF 10%
C490 0.1uF 10%
C489 0.1uF 10%
C2035 0.1uF 10%
C445 0.1uF 10%
C431 0.1uF 10%
C2036 0.1uF 10%
C485 0.1uF 10%
C484 0.1uF 10%
C465 0.1uF 10%
C466 0.1uF 10%
C443 0.1uF 10%
B
A
. w w w
5
to p la
4
-s p
h c
C476 0.1uF 10%
m e
a
R563 R564 R559 R560 R534 R556 R555 R533 R547 R548 R569 R551 R546 R584 R10528 R562 R561 R558 R557 R554 R553 R538 R537 R544 R543 R566 R536 R542 R583 R104
m o .c s ic t
56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 M_CKE0 M_CKE1 M_CKE3 M_CKE4 7,13 7,13 7,14 7,14 7,13 7,13 7,14 7,14 M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_A_BS0 8,13 M_A_BS1 8,13 M_A_BS2 8,13 M_A_WE# 8,13 M_A_CAS# 8,13 M_A_RAS# 8,13 M_B_BS0 8,14 M_B_BS1 8,14 M_B_BS2 8,14 M_B_WE# 8,14 M_B_CAS# 8,14 M_B_RAS# 8,14 M_CS#0 M_CS#1 M_CS#2 M_CS#3 7,13 7,13 7,14 7,14 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_A_A[14:0] 8,13 M_B_A[14:0] 8,14
D
C
B
Oakmont Form Factor Reference Design
Title DDR2 TERMINATION AND THERMAL SENSOR Size A Date:
3 2
Intel Confidential
A
Document Number Sheet 15
1
Rev of 64
5
4
3
2
1
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
+V3.3S C333 0.1uF 7
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
+V3.3S CR3009
ESD DIODE ARRAY
D
R457 10K 5%
CRT_L2_RED CRT_L2_BLUE CRT_L2_GREEN
1 2 4
I/O1 I/O2 I/O3
I/O6 I/O5 I/O4
8 6 5
CRT_Q_VSYNC CRT_Q_HSYNC
3
VN
42 DOCK_CRT_EN#
+V3.3S 5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
C
U10 42 DOCK_CRT_EN# 7 7 7 7 7 CRT_RED CRT_GREEN CRT_BLUE CRT_VSYNC CRT_HSYNC 12 2 5 6 8 11 3 7 10 20 SEL Y_A Y_B Y_C Y_D Y_E GND1 GND2 GND3 GND4 VDD1 VDD2 VDD3 VDD4 I_A0 I_B0 I_C0 I_D0 I_E0 I_A1 I_B1 I_C1 I_D1 I_E1 1 4 9 19 24 22 18 17 14 23 21 16 15 13 CRT_Q_RED CRT_Q_GREEN CRT_Q_BLUE CRT_Q_VSYNC CRT_Q_HSYNC
C371 0.1uF
C388 0.1uF
C389 0.1uF
C387 0.1uF
R429 2.2K
R427 2.2K
PI3V512QE
B
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
+V3.3S
1
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
A
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
. w w w
R446 2.2K Q144 BSS138 7 CRT_DDC_DATA 2 +V3.3S R19 2.2K Q145 BSS138 7 CRT_DDC_CLK 2 +V3.3S 1
3 CRT_DDC_DATA_Q 45 CRT_DDC_DATA_DOCK
t p la
DOCK_CRT_EN# CRT_DDC_CLK_Q 45 CRT_DDC_CLK_DOCK
p o
+V3.3S 5 Q53 2 4 INVERTER 3 U71 1 2 3 4 OE1# 1A 1B GND VCC OE2# 2B 2A 8 7 6 5 74CBT3306 U4 1 2 3 4 OE1# 1A 1B GND VCC OE2# 2B 2A 8 7 6 5 74CBT3306
+V5S_L_DAC
-s
C336 0.1uF
CRT_DDC_DATA_ISO
CRT_DDC_CLK_ISO CRT_Q_RED R426 150 1% C316 10pF 5% FB23 CRT_L_RED 47ohm@100MHz C2 22pF 5% FB1 47ohm@100MHz C3 10pF 5% GND1 CRT_L2_RED RED GND2 CRT_L2_GREEN GRN GND3 FB2 47ohm@100MHz CRT_L2_BLUE BLU VCC C317 NC1 10pF GND4 5% GND5 6 1 7 2 8 3 9 4 10 5 GND_SHLD . G1 G2
+V5S_L_DAC
CRT_RED_DOCK 45 CRT_GRN_DOCK 45 CRT_BLUE_DOCK 45 CRT_VSYNC_DOCK 45 CRT_HSYNC_DOCK 45
h c
1 2 C335 0.1uF 10% 1 2 C23 0.1uF 10%
m e
CRT_Q_GREEN R428 150 1% CRT_Q_BLUE R430 150 1% CRT_Q_VSYNC CRT_Q_HSYNC
a
5,17,18,24,26,28,30..32,34,49,50,52,53,56,57
m o .c s ic t
+V5S RT1 +1 2 +V5S_L_DAC_FB 1 1.1A Q52 BAT54 3 +V5S_CRT_DDC FB26 50OHM J2 11 NC2 12 DATA 13 HSYNC 14 VSYNC 15 CLK C9 10pF 5% FB24 CRT_L_GREEN 47ohm@100MHz C5 22pF 5%
VP
D
C
B
CRT_EN# +V5S 5,17,18,24,26,28,30..32,34,49,50,52,53,56,57 C14 10pF 5%
FB25 CRT_L_BLUE 47ohm@100MHz C16 22pF 5%
FB3 47ohm@100MHz C320 10pF 5%
CRT_DDC_DATA_ISO
C318 33pF 5% +V5S 5,17,18,24,26,28,30..32,34,49,50,52,53,56,57
C321 33pF 5%
Oakmont Form Factor Reference Design
Title CRT Size A Date: Document Number Sheet
2
Intel Confidential
A
3
CRT_DDC_CLK_ISO
Rev 16
1
of
64
5
4
3
5
4
3
2
1
D
5,16,18,24,26,28,30..32,34,49,50,52,53,56,57 5,7,9,10,16,18,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
5,16,18,24,26,28,30..32,34,49,50,52,53,56,57
+V5S C346 0.1uF
LVDS Panel Backlight
C
BIOS Note: Disable both BKLTSEL lines before enabling one.
40 L_BKLTSEL0# 7 L_BKLT_CTRL
GMCH_PWM Support
U6 1 2 3 4 OE1# 1A 1B GND VCC OE2# 2B 2A 8 7 6 5 L_BKLTSEL1# 40
R468 10K
L_CTRL_DATA 7
GM_Data_D Support
74CBT3306
L_BRIGHTNESS
5,7,9,10,16,18,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
B
5,7,9,10,16,18,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
+V3.3S
7 LVDS_VDD_EN
A
. w w w
R492 100K L_VDDEN# 3 Q64 BSS138 1 R494 100K 2
1
R493 1M
C366 1000pF 10%
t p la
SI2307DS
2
3
Q65
C364 22UF
p o
L_VDD_VDL C376 0.1uF
-s
7 LVDS_DDC_CLK 7 LVDS_DDC_DATA
h c
7 LVDSA_CLK# 7 LVDSA_CLK 7 LVDSB_CLK# 7 LVDSB_CLK
R499 2.2K
m e
7 L_CTRL_CLK R500 2.2K C379 0.1uF C381 0.1uF 10% NO_STUFF
a
R467 10K
m o .c s ic t
+V5S C355 0.1uF U73 1 2 3 OE# A GND Y 4 DBL_CLK 7 L_BKLT_EN R497 100K VCC 5 C375 0.1uF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 J7 74CBTLV1G125 42 ALS_CLK 42 ALS_DATA 42 KBC_PROG_TX# L_VDD_VDL 7 LVDSA_DATA#0 7 LVDSA_DATA0 7 LVDSA_DATA#1 7 LVDSA_DATA1 7 LVDSA_DATA#2 7 LVDSA_DATA2 7 LVDSA_DATA#3 7 LVDSA_DATA3
D
49,52,53,55,56
+VBAT
1
40 L_BKLTSEL1#
GM_CLK_D Support
+V3.3S
Adaptive Clocking
C380 0.1uF 10% NO_STUFF
7 LVDSB_DATA#0 7 LVDSB_DATA0 7 LVDSB_DATA#1 7 LVDSB_DATA1 7 LVDSB_DATA#2 7 LVDSB_DATA2 TP_LVDS_RSVD_B3M TP_LVDS_RSVD_B3P
L_VDDEN_D#
VDD_BLI VSS_BLI VSS_DBC VDD_DBC DBL_CLK DBL_DATA ENA_BL NC1 VDD_ALS VSS_ALS ALS_CLK ALS_DATA ALS_INTR NC2 VSS_VDL VDD_VDL1 VDD_VDL2 VDD_VCL RSVD VCL_CLK VCL_DATA A0M A0P VSS_SHIELD1 A1M A1P VSS_SHIELD2 A2M A2P VSS_SHIELD3 A3M A3P VSS_SHIELD4 VDL_CLKAM VDL_CLKAP VSS B0M B0P VSS_SHIELD5 B1M B1P VSS_SHIELD6 B2M B2P VSS_SHIELD7 B3M B3P VSS_SHIELD8 VDL_CLKBM VDL_CLKBP LVDS,CONN50
2
C374 0.1uF 10%
C
B
Adaptive Clocking
C378 0.1uF 10% NO_STUFF
C377 0.1uF 10% NO_STUFF
Oakmont Form Factor Refe