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5
4
3
2
1
BLOCK DIAGRAM
D
C
B
A
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D
C
B
A
295 Lane, Zuchongzhi Road, Zhangjiang, Shanghai, China, 201203
Amoi IT Division.
www.amoi.com.cn
3 2
5
Single End Impedance
Host Clock SRC Clock Host Bus DDR2 CLK DDR2 Strobe DDR2 Bus DMI Bus PCIE Bus SATA SDVO LVDS USB IEEE1394 Lan 50 ohm +/- 15% 55 ohm +/- 15% 55 ohm +/- 15% 55 ohm +/- 15% 55 ohm +/- 15% 42 ohm +/- 15% 55 ohm +/- 15% 55 ohm +/- 15% 55 ohm +/- 15% 55 ohm +/- 15% 95 ohm +/- 15% 95 ohm +/- 15% 95 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15% 90 ohm +/- 15% 110 ohm +/- 15% 70 ohm +/- 20% 95 ohm +/- 15% 95 ohm +/- 15%
4
Differential Impedance for Microstrip Differential Impedance for Stripline
100 ohm +/- 15% 100 ohm +/- 15% 70 ohm +/- 20% 85 ohm +/- 20% 100 ohm +/- 15% 100 ohm +/- 15% 100 ohm +/- 15% 100 ohm +/- 15% 100 ohm +/- 15% 90 ohm +/- 15% 110 ohm +/- 15%
3
Power Rail
VCC_CORE
2
Destination Voltage
1.3319V~1.4375V~1.4591V 0.9221V~0.9625V~0.9739V 0.997V~1.05V~1.102V 1.0V~1.05V~1.1V 0.9475V~1.05V~1.1025V 1.425V~1.5V~1.575V 1.425V~1.5V~1.575V 1.425V~1.5V~1.575V 1.425V~1.5V~1.575V 1.425V~1.5V~1.575V 1.425V~1.5V~1.575V
1
S0 Current
36A 2.5A 4.6A 1.4A
D
C
B
A
w
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2.5VDDM 3VDDM 3VDDS 3VDDA 5VDDM 5VDDS PMU3V
Yonah HFM: LFM: Yonah: AGTL+ termination 1.05VDDM 945GM: Core 945GM: AGTL+ termination ICH7m: 1.5VDDM Yonah PLL 945GM: PCIE 945GM: LVDS 945GM: TVDAC 945GM: Various PLLS analog supply 945GM: DDR DLLS,DDRII,FSB HSIO ICH7m: ICH7m: ICH7m: ICH7m: Mini Card: Express Card: 1.8VDDS: 945GM: DDRII System Memory SO-DIMM: 0.9VDDT_DDRII: DDRII Terminator: 945GM: PCIE analog 945GM: LVDS analog 945GM: LVDS I/O 945GM: CRT DAC CH7307: 945GM: HV CMOS 945GM: TVDAC analog ICH7m: ICH7m: ICH7m: ICH7m: ICH7m: Mini Card: Express Card: CLK Generator: ICS954226 Mini PCI: WirelessLan KBC: KB3886 Flash ROM: BIOS Azalia Codec: ALC260 Azalia MDC: HDD: SATA CardBus: TI PCI7411 CardBus: Slot voltage Lan: Broadcom BCM4401 Card Reader: SD/MMC/MS Azalia MDC: For wake up Mini PCI: For wake up ICH7m: ICH7m: ICH7m: LCD: Mini PCI: Azalia Codec: ALC260 Azalia MDC: HDD: SATA ODD: PATA Audio AMP: G1420 Woofer AMP: LM4991 Inverter: CardBus: Slot voltage USB: x 4 ports EC: PMU08 ICH7m: RTC
a
ic t
1.7V~1.8V~1.9V
.c s
120mA 1.5A 60mA 24mA 320mA 1.885A
m o
D
3.1A 1.0A 2mA 10mA 60mA 70mA 40mA 120mA
0.855V~0.9V~0.945V 2.32V~2.5V~2.625V 2.375V~2.5V~2.625V 2.375V~2.5V~2.625V 2.32V~2.5V~2.625V
C
3.135V~3.3V~3.465V 3.135V~3.3V~3.465V
3.135V~3.3V~3.465V
400mA
3.0V~3.3V~3.6V
3.0V~3.3V~3.6V
B
3.0V~3.3V~3.6V 3.0V~3.3V~3.6V 4.75V~5.0V~5.25V 4.75V~5.0V~5.25V
1.0A
Max: 1.0A ; R/W: 460mA ; STDBY: 70mA Max: 1.8A ; R/W: 900mA ; STDBY: 45mA
5V
2.0A
A
5
4
3
2
1
+V3.3S FB40 1 7 21 28 34 42 48 2 6 29 45 51 11 13 X1 14.318MHZ osc-b276x197mil-4 1 2 37 38 50 49 U16 VDD_REF VDD_PCI VDD_SRC1 VDD_SRC2 VDD_SRC_ITP VDD_CPU VDDA2 VSS_REF VSS_PCI VSS_SRC VSS_CPU VSSA2 VDD_48 VSS_48 VDDA VSSA XIN XOUT CPU0 CPU0# CPU1 CPU1# CPU2_ITP/SRC7 CPU2#_ITP/SRC7# 44 43 41 40 36 35 CPU_CLK0 CPU_CLK0# CPU_CLK1 CPU_CLK1# R325 R337 1 R350 1 R358 1 1 33 2 33 2 33 2 33 2 R0402 CLK_CPU_BCLK 9 R0402 CLK_CPU_BCLK# 9 R0402 CLK_MCH_BCLK 11 R0402 CLK_MCH_BCLK# 11
C549 1uF,0805,X7R C0805
BLM21PG331SN1 C555 FB0805 10u C1206
C300 0.1u C0402
C264 0.1u C0402
C270 0.1u C0402
C249 0.1u C0402
C543 0.1u C0402
C541 0.1u C0402
C287 0.1u C0402
CLK_MCH_BCLK CLK_MCH_BCLK# CLK_CPU_BCLK
D
+V3.3S C533 1uF,0805,X7R C0805 +V3.3S
R707 1
4.7 2
R0805 C539 10u C1206 C538 0.1u C0402
CLKREQA#/SRC6 CLKREQB#/SRC6# SRC5 SRC5# SRC4_SATA SRC4#_SATA SRC3 SRC3# SRC2 SRC2# SRC1 SRC1#
33 32 31 30 26 27 24 25 22 23 19 20
CLKREQA# CLKREQB# PCIE_CLK5 PCIE_CLK5# PCIE_CLK4 PCIE_CLK4# PCIE_CLK3 PCIE_CLK3#
FB39
C545 BLM21PG331SN1 FB0805 1uF,0805,X7R 10u C0805 C1206
C548
C547 C242 0.1u C0402 33p C0603 C244
R379 R411 1 1 R420 R430 1 R403 1 R410 1 R387 1 R391 1 RE1 1 RE2 1 R361 1 R375 1 1 R348 R347 1 1 R334 R345 1 1
POP = NA 0 R0603 R0603 2 0 POP = NA 2 33 R0402 R0402 2 33 2 33 R0402 R0402 2 33 R0402 2 33 2 33 R0402 R0402 2 33 R0402 2 33 2 33 R0402 R0402 2 33 2 33 2 33 2 33 2 33 2
CLK_MCH_OE# 12 CLK_PCIE_SATA_OE# CLK_PCIE_3GPLL 12 CLK_PCIE_3GPLL# 12 CLK_PCIE_SATA 21 CLK_PCIE_SATA# 21 CLK_PCIE_ICH 22 CLK_PCIE_ICH# 22 CLK_PCIE_VGA CLK_PCIE_VGA# CLK_PCIE 27 CLK_PCIE# 27
23
35 KBC_CLOCKIN_14.318 9,12 CPU_BSEL2 9,12 CPU_BSEL1 9,12 CPU_BSEL0
R297 R714 1 R709 1 1 27,51 CLK_FWHPCI
R296 1K 1 2 1K 2 2.2K 2 CLK_FWHPCI
33 2 R0603 R0603 R0603 23 22
R0603 FS_B R321 R303 1 R311 1 1 R267 R280 1 R287 1 R295 1 1 33 2 33 2 33 2 33 2 33 2 33 2 33 2
33p C0603
CLK_USB48 CLK_ICHPCI
FS_A R0402 ITP_EN R0402 R0402 96_100M_SEL SEL_CLKREQ R0402 PCI3 R0402 PCI4 R0402 PCI5 R0402
53 16 12 8 9 56 3 4 5 55 54
FS_C(TEST_SEL)/REF0 FS_B/TESTMODE FS_A/48M_0 ITP_EN/PCIF0 96_100_SEL/PCIF1 PCI2/SEL_CLKREQ PCI3 PCI4 PCI5 PCI_STP# CPU_STP# REF1
96_100_SSC 96_100_SSC# DOT96 DOT96# SDATA SCLK VTTPWRGD#/PD IREF
17 18 14 15 47 46 10 39
DREFSSCLK_D DREFSSCLK#_D DOT96 DOT96#
R0402 DREFSSCLK R0402 DREFSSCLK# R0402 DREFCLK R0402 DREFCLK#
12 12 12 12
CHANGE 0808 CHANGE 0808 PVT 1110
30 CLK_CARDBUS 29 CLK_LAN 28 CLK_MINIPCI 35,54 CLK_KBCPCI
SMB_DATA_S2 17,18,19,23 SMB_CLK_S2 17,18,19,23 R711 1 1K 2 R0603
CLK_EN#
23 PM_STPPCI# 23 PM_STPCPU# 23 CLK_ICH14 R308 1 33 2 REF_CLK1 R0402
52
R372 1
2
C
CY28442ZXC-2 tssop50p740-56n +V1.05S +V1.05S +V1.05S POP = NA FSB R57 1 1K 2 R56 R0402 1 1K 2 CPU_BSEL1 0 POP = NAR43 R0402 2 1 R53 R0402 1 1K 2 CPU_BSEL2 0 2 R0402 533 667 R51 1 1K 2 POP = NA R50 R0402 1 1 1 0 1 0 0 R0402 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
BSEL Setup
CPU_BSEL0
B
A
w
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+V3.3S +V3.3S R278 1 10K R0603 2 R292 1 10K 2 ITP_EN R288 1 10K POP R0402 = NA 2 R306 1 2 1:Set pin36/35 to CPU_ITP 0:Set Pin36/35 to SRC7
96_100M_SEL
POP = NA 10K R0603 R270 1
m e h c
C542 0.1u C0603 475_1% R0402
CHANGE 0728
a
42 +V3.3S R402 1 R390 1
ic t
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CLK_CPU_BCLK# CLK_PCIE_VGA CLK_PCIE_VGA# R357 1 R356 1 R417 1 R421 1 R404 1 R413 1 R386 1 R395 1 R365 1 R376 1 R322 1 R331 1 R333 1 R344 1 CLK_PCIE_3GPLL CLK_PCIE_3GPLL# CLK_PCIE_SATA CLK_PCIE_SATA# CLK_PCIE_ICH CLK_PCIE_ICH# CLK_PCIE CLK_PCIE# DREFSSCLK DREFSSCLK# DREFCLK DREFCLK#
R349 1 R367 1 R312 1 R329 1
m o
49.9_1% R0402 49.9_1% R0402 49.9_1% R0402 49.9_1% R0402 2 2 2 2 49.9_1% R0402 49.9_1% R0402 49.9_1% R0402 49.9_1% R0402 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 49.9_1% R0402 2 2 2 2 2
D
3
4
C
For EMI
CLK_USB48 C272 10p C0402 C263 10p C0402 C268 10p C0402 C245 10p C0402 C253 10p C0402 C258 10p C0402 C262 10p C0402
B
CLK_FWHPCI
CLK_ICHPCI
+V3.3S
CHENGE 0815
R392 10K 10K R0603 R0603 1 2 2 POP = NA
CLK_CARDBUS
R0402 R262 1
10K
R0603
POP = NA
2
CLK_LAN
CLKREQB# CLKREQA# CLK_MINIPCI
SEL_CLKREQ
10K POP R0402 = NA
2
CLK_KBCPCI R407 10K 10K R0402 R0402 1 2 2
1:Set pin17/18 to 100MHZ 0:Set Pin17/18 to 96MHZ
1:Set pin32/33 as clock request pin 0:Set Pin32/33 as SRC
3
2
5
4
3
2
1
11
D
H_A#[31:3]
11
H_D#[63..0]
U35A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 11 H_ADSTB#0 11 H_REQ#[4:0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 K3 H2 K2 J3 L5 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 21 H_A20M# 21 H_FERR# 21 H_IGNNE# 21 H_STPCLK# R97 0 1 2 21 H_INTR 21 H_NMI 21 H_SMI# TP98 TP101 TP100 TP99 TP28 TP29 TP96 TP97 TP83 TP81 TP85 A6 A5 C4 H_STPCLK#_C D5 R0402 C6 B4 A3 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 B25 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 D21 A24 A25 C7 H_BPM0_ITP# H_BPM1_ITP# H_BPM2_ITP# H_BPM3_ITP# H_BPM4_PRDY# H_BPM5_PREQ# H_TCK TDI_FLEX H_TDO H_TMS H_TRST# ITP_DBRESET H_PROCHOT# H_THERMDA H_THERMDC PM_THRMTRIP# 12,21 PM_THRMTRIP# 12,21 A22 A21 T22 D2 F6 D3 C1 AF1 D22 C23 C24 R100 1 68 2 H_RS#0 H_RS#1 H_RS#2 H_IERR# R101 1 H_ADS# 11 H_BNR# 11 H_BPRI# 11 H_DEFER# 11 H_DRDY# 11 H_DBSY# 11 H_BREQ#0 11 R0402 +V1.05S 56 2 H_INIT# 21 H_LOCK# 11 H_CPURST# 11,35 H_RS#[2:0] H_TRDY# H_HIT# H_HITM# 11 11 11 11 H_DSTBN#[3:0] +V1.05S 11 H_DSTBP#[3:0] 150 2 R0402 +V1.05S 11 H_DINV#[3:0] 11 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26
U35B D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 BSEL[0] BSEL[1] BSEL[2] CPU bga-127p-26x26-478
IERR# INIT# LOCK#
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
XDP/ITP SIGNALS
C
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 11 H_ADSTB#1
R136 1
75 OHM WILL BETTER R0402
A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] RSVD[11] A1
THERM
PROCHOT# THERMDA THERMDC
H_PROCHOT#
THERMTRIP#
BCLK[0] BCLK[1] RSVD[12]
CLK_CPU_BCLK CLK_CPU_BCLK#
8 8
DVT 0926
RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20]
CPU bga-127p-26x26-478
B
COST 060326
R107 POP = NA 1 2
100K
35 CPU_TEMP_DBUS
A
w
5
w w
p la .
+V3.3A_KBC C474 0.1u R0603 C0402 U34 1 3 2 VDD BBUS GND DN 5 sot95p240-5
4
EMC1212AGZQTR# H_THERMDA DP 4 C470
s p to
TP30 TP23 TP27 TP82 TP80 TP105 TP25 TP79 TP87
m e h c
+V1.05S
CHANGE 0716
R659 1K
42
H_GTLREF
a
ACLKPH DCLKPH R94 POP = NA 1
N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26
ic t
DATA GRP 3 DATA GRP 1 MISC
+V1.05S +V3.3S
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
.c s
AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE6 COMP0 COMP1 COMP2 COMP3
CONTROL
DATA GRP 2
m o
5 mil wild
R655 R656 1 R654 1 R657 1 1 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# PSI# 27.4_1% R0402 2 54.9_1% R0402 2 27.4_1% R0402 2 54.9_1% R0402 2 21,42 21 11 21 11 42
D
H CLK
RESERVED
KEY1
A2
KEY2
ADDR GROUP 0 ADDR GROUP 1
DATA GRP 0
18 mil wild
C
AD26 C26 D25
R660
2K,1%,1/16W,0402
POP = NA R0402 R646 1K 1 2 R647 49.9_1% R0402 1 2 R643 R642 1 R644 1 1
COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
8,12 CPU_BSEL0 8,12 CPU_BSEL1 8,12 CPU_BSEL2
0 2 0 2 0 2
R0603 B22 R0603 B23 R0603 C21
51 OHM WILL BETTER
INSTALL 0808
Layout note: Comp0,2 connect with trace length shorter Comp1,3 connect with trace length shorter
Zo=27.4ohm, make than 0.5". Zo=55ohm, make than 0.5".
Intel ITP DEBUG PORT
DVT 0921
B
DVT
0921
R138 54.9_1% R0402 R103R0402 R13754.9_1% 54.9_1% R0402 150 2 1 1 2 2 1 2 POP = NA R143 R95 1 1
R0402
ITP_DBRESET H_TMS H_TDO H_CPURST#
DVT 1009
22.6_1% R0402 2 22.6_1% R0402 H_BPM0_ITP# 2 H_BPM1_ITP# H_BPM2_ITP# H_BPM3_ITP# H_BPM4_PRDY# H_BPM5_PREQ# TDI_FLEX 54.9_1% R0402 2 680 R0402 2
33p H_THERMDC C0603 R150 R149 1 1
TP24 TP33 TP34 TP26 TP106 TP107 TP104 TP32 TP102 TP103 TP31 H_TCK H_TRST# TP36 TP35
3
2
5
4
3
2
1
VCC(CORE) Decoupling
PLACE NEAR CPU
+VCC_CORE +VCC_CORE U35C A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 AD6 AF5 AE5 AF4 AE3 AF2 AE2
Mid Frequency
D
(0805,MLCC,>=X5R)
+VCC_CORE
Place these inside socket cavity on L8 ( North side Secondary)
C130 22u C0805
C122 22u C0805
C124 22u C0805
C125 22u C0805
C129 22u C0805
C123 22u C0805
C127 22u C0805
C126 22u C0805
C128 22u C0805
C121 22u C0805
+VCC_CORE
Place these inside socket cavity on L8 ( South side Secondary)
C157 22u C0805
C164 22u C0805
C165 22u C0805
C163 22u C0805
C162 22u C0805
C161 22u C0805
C160 22u C0805
C159 22u C0805
C158 22u C0805
C156 22u C0805
Place these inside socket cavity on L1 ( North side Primary)
C498 22u C0805 POP = NA
C495 22u C0805 POP = NA
C499 22u C0805 POP = NA
C497 22u C0805 POP = NA
C496 22u C0805 POP = NA
C494 22u C0805 POP = NA
2
C
+VCC_CORE
+VCC_CORE Place these inside socket cavity on L1 ( South side Primary)
C492 22u C0805 POP = NA
C490 22u C0805 POP = NA
C489 22u C0805 POP = NA
C488 22u C0805 POP = NA
C491 22u C0805 POP = NA
C493 22u C0805 POP = NA
B
If use Low Inductance Low-Frequency Decoupling Cap (Total LF Cap ESR=1.5mohm,ESL=0.8nH/6), these cap can NA, If use Commom Low-Frequency Decoupling Cap (Total LF Cap ESR=1.5mohm,ESL=1.8nH/6), these must be mounted
VCCP Decoupling
PLACE NEAR CPU
High Frequency
(0603,MLCC,>=X7R)
A
+V1.05S
C140 0.1u C0402
C138 0.1u C0402
C146 0.1u C0402
w
C147 C152 0.1u C0402 0.1u C0402
5
w w
C151 Place these inside socket cavity on L8 ( North side Secondary) 0.1u C0402
p la .
4
s p to
VCCSENSE VSSSENSE CPU
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
AF7 TP_VCCSENSE AE7 TP_VSSSENSE
bga-127p-26x26-478
m e h c
1 CP22 + 330u C7343 +V1.5S LAYOUT NOTE: PLACE C82 NEAR PIN B26 C482 H_VID[6..0] C477 42 0.01u C0402 10u C0805 R675 1
+V1.05S
a
2 VCCSENSE VSSSENSE 2
ic t
42 42
.c s
A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
U35D
m o
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24
D
C
+VCC_CORE
100_1% R0603
Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.
R676 1
100_1% R0603
B
CPU
bga-127p-26x26-478
18 mil wild
3
2
5
4
3
2
1
D
H_XRCOMP R35 1 24.9_1% R0402 2
9
H_D#[63..0] H_A#[31:3] U33A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 E1 E2 E4 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 9
Trace should be 10-mil wide with 20-mil spacing.
+V1.05S
R33 1
54.9_1% R0402 2 H_XSCOMP
+V1.05S
C
R29 1
221_1% R0402 2
Signal voltage level = 0.3125*Vcc1_05 Trace should be 10-mil wide with 20-mil spacing.
H_XSWING
R22 1
100_1% R0603 C20 2 0.1u C0402
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF_0 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF_1
H_YRCOMP R637 1 24.9_1% R0402 2
Trace should be 10-mil wide with 20-mil spacing.
B
H_XRCOMP H_XSCOMP H_XSWING +V1.05S
R631 1
54.9_1% R0402 2 H_YSCOMP
+V1.05S
R632 1
221_1% R0402 2
Signal voltage level = 0.3125*Vcc1_05 Trace should be 10-mil wide with 20-mil spacing.
H_YSWING
R635 1
100_1% R0603 C463 2 0.1u C0402
A
w
5
w w
p la .
8 CLK_MCH_BCLK 8 CLK_MCH_BCLK#
4
H_YRCOMP H_YSCOMP H_YSWING
s p to
H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING H_CLKIN H_CLKIN# Y1 U1 W1 AG2 AG1 INTEL945 FBGA_1466_42_34
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_HIT# H_HITM# H_LOCK#
m e h c
E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13 J7 W8 U3 AB10 K4 T7 Y5 AC4 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 K3 T6 AA5 AC5 D3 D4 B3 D8 G8 B8 F8 A8 B4 E6 D6 E3 E7 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_RS#[2:0]
H_ADS# 9 H_ADSTB#0 9 H_ADSTB#1 9
HOST
H_BNR# 9 H_BPRI# 9 H_BREQ#0 9 H_CPURST# 9,35 H_DBSY# 9 H_DEFER# 9 H_DPWR# 9 H_DRDY# 9 H_DINV#[3:0] 9
a
9 9 9 9 9 9 9
ic t
+V1.05S R52 1 2 H_VREF C50 0.1u C0402 R48 1 2
.c s
m o
D
100_1% R0603
Signal voltage level = 2/3 of Vcc1_05
C
200_1% R0603
H_DSTBN#[3:0]
H_DSTBP#[3:0]
H_HIT# 9 H_HITM# 9 H_LOCK# H_REQ#[4:0]
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
B
H_SLPCPU# H_TRDY#
H_CPUSLP# H_TRDY#
3
2
5
4
3
2
1
+V3.3S
U33B
D
R30 R28 1 1 SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3 SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_OCDCOMP_0 SM_OCDCOMP_1 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP# SM_RCOMP SM_VREF_0 SM_VREF_1 G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21 AL20 AF10 BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41 C599 C600 AF33 AG33 A27 A26 C40 D41 AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 AE37 AF41 AG37 AH41 AC37 AE41 AF37 AG41 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP[3:0] DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN[3:0] 22 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 22 M_RCOMP# M_RCOMP M_ODT0 M_ODT1 M_ODT2 M_ODT3 R80 R79 1 1 M_VREF 0.1u C0402 0.1u C0402 CLK_PCIE_3GPLL# 8 CLK_PCIE_3GPLL 8 8 DREFCLK# DREFCLK 8 DREFSSCLK# 8 DREFSSCLK 8 DMI_TXN[3:0] 17,19 17,19 18,19 18,19 80.6_1% R0402 2 80.6_1% R0402 2 17,18,40 +V1.8 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS#0 M_CS#1 M_CS#2 M_CS#3 17 17 18 18 17 17 18 18
10K R25 10K 2 2 1
R0402 R0402 R629 10K 2 1
R0402 10K 2
R0402 U33C TP14
TP18 TP17 TP10 TP7 TP270 TP271 TP13 TP8 TP65 TP70 TP71 TP9 TP3
MCH_RSVD_2 MCH_RSVD_3 MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8 MCH_RSVD_9 MCH_RSVD_12 MCH_RSVD_13 MCH_RSVD_14 MCH_RSVD_15 MCH_RSVD_16 R114 R115 1 R120 1 1
T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A35 A34 D28 D27
RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN# SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC# CLK_REQ# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
47
L_BKLTEN
47 L_DDC_CLK 47 L_DDC_DATA
R628 1 47
L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG 1.5K_1% R0603 L_LVBG 2 TP6 L_VDDEN
DVT 1009
8,9 CPU_BSEL0 8,9 CPU_BSEL1 8,9 CPU_BSEL2
17,19 17,19 18,19 18,19 17,19 17,19 18,19 18,19
D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 A33 A32 E27 E26 C37 B35 A37
L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LA_CLK# LA_CLK LB_CLK# LB_CLK LA_DATA#_0 LA_DATA#_1 LA_DATA#_2
EXP_A_COMPI EXP_A_COMPO EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15 EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15 EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15 EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15
D40 D38
TP4 TP74
PVT 1122 NA
R503 R791 1 1
TP1
2.2K 2 2.2K 2 TP67 TP11 TP2
17,19 PM_EXTTS#0 18,19 PM_EXTTS#1
C
0 R0402 K16 2 0 R0402 K18 R0402 J18 2 0 MCH_CFG_3 2 F18 MCH_CFG_4 E15 MCH_CFG_5 F15 MCH_CFG_6 E18 MCH_CFG_7 D19 MCH_CFG_8 D16 MCH_CFG_9 G16 MCH_CFG_10 E16 MCH_CFG_11 D15 MCH_CFG_12 R0402 POP = NA G15 MCH_CFG_13 R0402 POP = NA K15 MCH_CFG_14 C15 MCH_CFG_15 H16 MCH_CFG_16 G18 MCH_CFG_17 H15 MCH_CFG_18 J25 MCH_CFG_19 K27 MCH_CFG_20 J26 G28 PM_EXTTS#0F25 PM_EXTTS#1H26 G6 AH33 RST_IN#_MCH R0402 AH34 H28 H27 K28 H32
MUXING
CHANGE 0808
47 47 47 47
GM_LA_CLKN GM_LA_CLKP GM_LB_CLKN GM_LB_CLKP
47 GM_LA_DATAN0 47 GM_LA_DATAN1 47 GM_LA_DATAN2
47 GM_LA_DATAP0 47 GM_LA_DATAP1 47 GM_LA_DATAP2 47 GM_LB_DATAN0 47 GM_LB_DATAN1 47 GM_LB_DATAN2
B37 B34 A36 G30 D30 F29
LA_DATA_0 LA_DATA_1 LA_DATA_2 LB_DATA#_0 LB_DATA#_1 LB_DATA#_2
DVT 0922
PCI-EXPRESS
23 PM_BMBUSY# R31 10K R26 1 2 10K 1 2 9,21 PM_THRMTRIP# 35,42,44 DELAY_VR_PWRGOOD R67 22,23,27,51,54 PLT_RST# 1 TP15 TP12 22 MCH_ICH_SYNC# 8 CLK_MCH_OE# TP78 TP72 TP77 TP88 TP94 TP92 TP89 TP90 TP91 TP66 TP76 TP95 TP86 TP93 TP84 TP73 TP68 TP69 TP75
R0402 R0402 100 2
CLK
+V3.3S
22
GM_TV_DACA GM_TV_DACB GM_TV_DACC R622POP = NA150_1% R0603 R623POP = NA150_1% R0603 1 2 R624POP = NA150_1% R0603 1 2 TVIREF 1 R54 2 4.99K_1%R0402 1 2 +V3.3S
TP_MCH_NC0 TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16 TP_MCH_NC17 TP_MCH_NC18
D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
INTEL945
B
CFG2 CFG1 CFG0 Frequency 0
Layout Note: Location of all MCH_CFG strap resistors needs to be close to trace to minimize stub
1 0
0
MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_16
R13 R16 1 R15 1 R14 1 R18 1 R12 1 R17 1 1
2 2 2 2 2 2 2
2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K
R0402 R0402 R0402 R0402 R0402 R0402 R0402
POP = NA POP = NA POP = NA POP = NA POP = NA POP = NA POP = NA
CFG[17:3] have internal pullup resistors CFG[20:18] have internal pulldown resistors
CFG5 :Low=DMIx2 CFG6 :Low=Moby Dick CFG7 :Low=Reserve :High=DMIx4 :High=Calistoga :High=Mobile CPU CPU Strap
MCH_CFG_18 MCH_CFG_19 MCH_CFG_20
R27 R23 1 R24 1 1
1K 2 1K 2 1K 2
A
w
5
w w
+V3.3S R0402 POP = NA R0402 POP = NA R0402 POP = NA
CFG9 :Low=Reserve Lane :High=Normal CFG10:Low = Reserved :High = Mobility CFG11:Low = Reserved :High = Calistoga CFG16:Low=Disabled :High=Enabled
CFG18:Low=1.05V :High=1.5V (VCC Select) CFG19:Low=Normal :High=Lane Reversal (DMI Lane Reversal) CFG20:Low=Only SDVO or PCIE x1 is operational :High=SDVO and PCIE x1 are operating simutaneously via the (PCIE Backward Interoperability mode)
p la .
1 1 FSB667 FSB533
4
PCIE Graphics Lane Host PLL VCC Select SB 4x CLK Enable (FSB Dynamic ODT)
s p to
20 20 DMI_RXP[3:0] 22 20 GM_CRT_HSYNC 20 GM_CRT_VSYNC R36 1 R37 1 2 2 39 R0402
DVT 0920
GM_CRT_B
GM_CRT_G
20 GM_CRT_R R627 150_1% R0603 R626 1 2 150_1% R0603 R625 1 2 150_1% R0603 1 2 20 GM_CRT_DDC_CLK 20 GM_CRT_DDC_DATA 39 R0402
m e h c
47 GM_LB_DATAP0 47 GM_LB_DATAP1 47 GM_LB_DATAP2 F30 D29 F28 LB_DATA_0 LB_DATA_1 LB_DATA_2 A16 C18 A19 J20 B16 B18 B19 TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC R73 R126 1 1 2.2K 2 2.2K 2 E23 D23 C22 B22 A21 B21 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# HSYNC CRTIREF VSYNC C26 C25 G23 J22 H23 R55 1 255_1% R0402 2 INTEL945
TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT
a
TV TV
ic t
GRAPHICS
F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38
.c s
PEG_COMP R41 1 2 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
24.9_1% R0402
m o
+V1.5S_PCIE PEG_RXN[15:0] PEG_RXP[15:0]
D
DDR
DMI
RSVD CFG PM
MISC
LVDS LVDS
R0402 K30 TV_DCONSEL0 R0402 J29 TV_DCONSEL1
F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40
C
NC
VGA VGA
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC
B
PEG port
3
2
5
4
3
2
1
D
17 M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
U33D SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 INTEL945 SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# AU12 AV14 BA20 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 AW14 AK23 AK24 AY14 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 TP_MA_RCVENIN# TP_MA_RCVENOUT# M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# M_A_DM[7..0] 17,19 17,19 17,19 17,19 17
18 M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
U33E SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_BS_0 SB_BS_1 SB_BS_2 AT24 AV23 AY28
M_A_DQS[7..0]
17
M_A_DQS#[7..0]
17
C
M_A_A[13..0] 17,19
B
A
w
5
w w
p la .
4
s p to
M_A_RAS# TP19 TP22 M_A_WE# 17,19 17,19
m e h c
INTEL945
SYSTEM
DDR
DDR
SYSTEM
a
MEMORY B
ic t
SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE# AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 AU23 AK16 AK18 AR27
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13
.c s
M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS# M_B_DM[7..0] M_B_A[13..0] M_B_RAS# TP21 TP20 M_B_WE#
18,19 18,19 18,19 18,19 18
m o
18 18
D
M_B_DQS[7..0]
MEMORY
A
M_B_DQS#[7..0]
C
18,19
TP_MB_RCVENIN# TP_MB_RCVENOUT#
18,19 18,19
B
A
3
2
5
4
3
2
1
+V1.05S U33G AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16 VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 +V1.05S U33F VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107 AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1 VCCSM_LF4 VCCSM_LF5 C471 0.47u C0603 C478 0.47u C0603 CP15 + 330u C7343 CP2 + 330u C7343 C73 10u C0805 C74 C75 C69 0.22u C0603 C63 0.22u C0603 C57 0.22u C0603 AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72 1 1
D
1uF,0805,X7R 10u C0805 C0805
POP = NA
PVT 1130
C
C114 0.47u C0603
VCC
B
A
w
5
w w
INTEL945
p la .
4
s p to
+V1.8 C115 10u C0805 C112 10u C0805 C113 0.47u C0603 C96 0.47u C0603 2 1 CP7 + 330u C7343
m e h c
a
ic t
.c s
VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12
m o
AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17 +V1.5S AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15
D
2
2
NCTF
VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57
C
B
INTEL945
VCCSM_LF2 VCCSM_LF1 C89 0.47u C0603
3
2
5
4
3
2
1
+V1.5S
+V3.3S_TVDAC +V2.5S +V1.05S +V1.5S_DPLLA +VCCA_TVDAC FB2 CP13 + 330u C7343 C451 0.1u C0402 10u C0805 0.1u C0402 0.022u C0603 +V3.3S_TVDACB +V2.5S +V1.5S_DPLLB +V2.5S_CRTDAC C67 0.1u C0402 C65 10u C0805 C13 4.7u C0805 C34 +V1.5S_PCIE 0.1u C0402 +V1.5S_3GPLL 180R FB0603 C15 C29 C24 C30 B30 A30 AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41 +V3.3S_TVDACA C53 0.1u C0402 U33H H22 VCCSYNC VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS VCCA_MPLL VCCA_TVBG VSSA_TVBG VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76 AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
+V1.5S L4 1 1 2 10uH L0805 OUGHT 470U 2 +V2.5S C82
D
L1 1
1
2 10uH L0805 OUGHT 470U
C26 C36 0.1u C0402 0.1u C0402
C23 0.022u C0603 C43 +V3.3S_TVDACC C47
CP14 + 330u C7343
+V1.5S_HPLL FB12 120R FB1206 1 CT11 22u C3216 C465 0.1u C0402
+V2.5S
0.1u C0402
F21 E21 G21 0.022u +V1.5S_DPLLA C0603 +V1.5S_DPLLB B26 +V1.5S_HPLL C39 AF1 C45 +V1.5S_MPLL 0.1u C0402 A38 B39 AF2 H20 G20 +V3.3S_TVDACA
C27 0.1u C0402
C32 C18 0.022u C0603 0.01u C0402
+V1.5S_MPLL FB13 120R FB1206 1 CT12 22u C3216 C469 0.1u C0402 +V1.5S
C28 0.1u C0402
C22 +V3.3S_TVDACB 0.022u C0603 +V3.3S_TVDACC E19 F19 C20 D20 E20 F20 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
2
+V1.5S C38 10u C0805
C
+V2.5S
+V1.05S C42 +V1.5S_QTVDAC D4 BAT54 sot95p280-3n-123 2 +V2.5S_CRTDAC FB1 180R FB0603 C30 0.1u C0402 0.1u C0402 1 C40 0.022u C0603 C21 0.022u C0603
R21 1
10 2
VCCGFOLLOW R0603
3
FB9
180R FB0603
+V1.5S +V1.5S_PCIE L8 1 2 0.15uH L1210
CP4 + 330u C7343
C72 10u C0805
C78 10u C0805
B
+V1.5S_3GPLL L7 1 2 1uH L1210 R66 1 1_1% 2 R0603
+V1.5S +V3.3S
A
D2 BAT54 3 V1_5SFOLLOW sot95p280-3n-123 2
w
R19 1 C3
5
0.1u C0402
w w
+V3.3S_TVDAC 10 R0805 2 2 1 CT1 22u C3216
p la .
4
s p to
+V1.5S C60 0.1u C0402
m e h c
+V1.5S
POWER
AH1 AH2
C41
0.1u C0402
A28 B28 C28 D21 A23 B23 B25
+V3.3S C11
VCCD_TVDAC VCC_HV0 VCC_HV1 VCC_HV2
a
ic t
VTTLF_CAP3 VTTLF_CAP2 VTTLF_CAP1 C464
.c s
C25 0.22u C0603
0.1u C0402
+V2.5S C37
2
0.1u C0402
m o
C79 10u C0805 C12 C33 4.7u C0805 0.1u C0402 C447 0.22u C0603 C58 4.7u C0805 C59 2.2u C0603
D
+V1.05S
2
Place on the edge
Place in cavity
C
C14
10u C0805
0.1u C0402
H19
VCCD_QTVDAC VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
C456 0.47u C0603
2
1
0.47u C0603
B
INTEL945
1
A
3
2
5
4
3
2
1
U33I AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 INTEL945 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11
U33J VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
D
VSS
C
B
A
w
5
w w
p la .
4
s p to
m e h c
a
VSS
ic t
.c s
m o
D
C
B
INTEL945
3
2
5
4
3
2
1
D
DDR2 SODIMM0
J5A 12,19 12,19 M_CKE0 M_CKE1 M_CKE0 M_CKE1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 M_A_BS#0 M_A_BS#1 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_BS#2 79 80 30 32 164 166 107 106 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 110 115 108 113 109 198 200 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 114 119 CKE0 CKE1 CK0 CK0# CK1 CK1# BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 S0# S1# RAS# CAS# WE# SA0 SA1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SCL SDA 5 M_A_DQ0 7 M_A_DQ1 17M_A_DQ2 19M_A_DQ3 4 M_A_DQ4 6 M_A_DQ5 14M_A_DQ6 16M_A_DQ7 23M_A_DQ8 25M_A_DQ9 M_A_DQ10 35 M_A_DQ11 37 M_A_DQ12 20 M_A_DQ13 22 M_A_DQ14 36 M_A_DQ15 38 M_A_DQ16 43 M_A_DQ17 45 M_A_DQ18 55 M_A_DQ19 57 M_A_DQ20 44 M_A_DQ21 46 M_A_DQ22 56 M_A_DQ23 58 M_A_DQ24 61 M_A_DQ25 63 M_A_DQ26 73 M_A_DQ27 75 M_A_DQ28 62 M_A_DQ29 64 M_A_DQ30 74 M_A_DQ31 76 M_A_DQ32 123 M_A_DQ33 125 M_A_DQ34 135 M_A_DQ35 137 M_A_DQ36 124 M_A_DQ37 126 M_A_DQ38 134 M_A_DQ39 136 M_A_DQ40 141 M_A_DQ41 143 M_A_DQ42 151 M_A_DQ43 153 M_A_DQ44 140 M_A_DQ45 142 M_A_DQ46 152 M_A_DQ47 154 M_A_DQ48 157 M_A_DQ49 159 M_A_DQ50 173 M_A_DQ51 175 M_A_DQ52 158 M_A_DQ53 160 M_A_DQ54 174 M_A_DQ55 176 M_A_DQ56 179 M_A_DQ57 181 M_A_DQ58 189 M_A_DQ59 191 M_A_DQ60 180 M_A_DQ61 182 M_A_DQ62 192 M_A_DQ63 194 M_A_DQ[63..0] 13 M_CLK_DDR0 12 M_CLK_DDR0 12 M_CLK_DDR#0 C188
Place 10p C0402 POP = NA M_CLK_DDR#0
Layout Note: near SO-DIMM
12 M_CLK_DDR1 12 M_CLK_DDR#1 13,19 M_A_BS#[2..0] 13,19 M_A_A[13..0]
+V1.8
C186 2.2u C0805
C177 2.2u C0805
C187 2.2u C0805
C185
M_CLK_DDR1
Layout Note: Place these Caps near SO-DIMM
C189
10p C0402 POP = NA M_CLK_DDR#1
Layout Note: Place near SO-DIMM
C
12,19 12,19 13,19 13,19 13,19
M_CS#0 M_CS#1
M_CS#0 M_CS#1 M_A_RAS# M_A_CAS# M_A_WE# SA0_DIM1 R0402 SA1_DIM1 R0402 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_RAS# M_A_CAS# M_A_WE# 10K 2 10K 2
R171 R170 1 1 13 M_A_DM[7..0]
13 M_A_DQS[7..0]
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
13 M_A_DQS#[7..0]
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_ODT0 M_ODT1 M_ODT0 M_ODT1
B
12,19 12,19
A
w
5
w w
p la .
4
s p to
DQS_0 DQS_1 DQS_2 DQS_3 DQS_4 DQS_5 DQS_6 DQS_7 DQS_#0 DQS_#1 DQS_#2 DQS_#3 DQS_#4 DQS_#5 DQS_#6 DQS_#7 ODT0 ODT1 197SMB_CLK_S2 195SMB_DATA_S2 SODIMM0 DDR-SODIMM
m e h c
+V1.8 C175 C176 0.1u C0402 0.1u C0402 +V1.8 C106 0.1u C0402 C107 0.1u C0402
Layout Note: Place these Caps near SO-DIMM
a
C174 0.1u C0402 C86 0.1u C0402 C103 0.1u C0402
2.2u C0805
C173
0.1u C0402
ic t
C170 2.2u C0805
.c s
+V3.3S
m o
+V1.8 J5B 112 111 117 96 95 118 81 82 87 103 88 104 199 VDD_01 VDD_02 VDD_03 VDD_04 VDD_05 VDD_06 VDD_07 VDD_08 VDD_09 VDD_10 VDD_11 VDD_12 VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF 83 120 50 69 163 1 0.1u C0402 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 E2 E3 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
D
DVT 0919
R784 0 POP = NA2 1 12,18,40 M_VREF
C171 0.1u C0402 R0603
C169 2.2u C0805
C
12,19 PM_EXTTS#0
M_VREF C168 C172 2.2u C0805
E2 E3
DDR-SODIMM
SMB_CLK_S2 8,18,19,23 SMB_DATA_S2 8,18,19,23
E5 E6 SODIMM0
E5 E6
B
Layout Note: Place these Hi-Freq Decoupling Caps near the GMCH
A
3
2
5
4
3
2
1
D
DDR2 SODIMM1
J6A 12,19 12,19 M_CKE2 M_CKE3 M_CKE2 M_CKE3 79 80 30 32 164 166 M_B_BS#0 M_B_BS#1 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_BS#2 12,19 12,19 13,19 13,19 13,19 M_B_RAS# M_B_CAS# M_B_WE# R204 R205 1 1 13 M_B_DM[7..0] 10K 2 10K 2 M_CS#2 M_CS#3 M_CS#2 M_CS#3 M_B_RAS# M_B_CAS# M_B_WE# SA0_DIM0 R0402 SA1_DIM0 R0402 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 107 106 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 110 115 108 113 109 198 200 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 114 119 CKE0 CKE1 CK0 CK0# CK1 CK1# BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 S0# S1# RAS# CAS# WE# SA0 SA1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SCL SDA 5 M_B_DQ0 7 M_B_DQ1 17 M_B_DQ2 19 M_B_DQ3 4 M_B_DQ4 6 M_B_DQ5 14 M_B_DQ6 16 M_B_DQ7 23 M_B_DQ8 25 M_B_DQ9 35 M_B_DQ10 37 M_B_DQ11 20 M_B_DQ12 22 M_B_DQ13 36 M_B_DQ14 38 M_B_DQ15 43 M_B_DQ16 45 M_B_DQ17 55 M_B_DQ18 57 M_B_DQ19 44 M_B_DQ20 46 M_B_DQ21 56 M_B_DQ22 58 M_B_DQ23 61 M_B_DQ24 63 M_B_DQ25 73 M_B_DQ26 75 M_B_DQ27 62 M_B_DQ28 64 M_B_DQ29 74 M_B_DQ30 76 M_B_DQ31 123M_B_DQ32 125M_B_DQ33 135M_B_DQ34 137M_B_DQ35 124M_B_DQ36 126M_B_DQ37 134M_B_DQ38 136M_B_DQ39 141M_B_DQ40 143M_B_DQ41 151M_B_DQ42 153M_B_DQ43 140M_B_DQ44 142M_B_DQ45 152M_B_DQ46 154M_B_DQ47 157M_B_DQ48 159M_B_DQ49 173M_B_DQ50 175M_B_DQ51 158M_B_DQ52 160M_B_DQ53 174M_B_DQ54 176M_B_DQ55 179M_B_DQ56 181M_B_DQ57 189M_B_DQ58 191M_B_DQ59 180M_B_DQ60 182M_B_DQ61 192M_B_DQ62 194M_B_DQ63 M_B_DQ[63..0] 13 +V1.8 M_CLK_DDR3 12 M_CLK_DDR3 12 M_CLK_DDR#3 12 M_CLK_DDR2 12 M_CLK_DDR#2 C210 C221 2.2u C0805 C193 2.2u C0805 C192 2.2u C0805 C191 2.2u C0805
Place 10p C0402 POP = NA M_CLK_DDR#3
Layout Note: near SO-DIMM
13,19 M_B_BS#[2..0] 13,19 M_B_A[13..0]
Layout Note: Place these Caps near SO-DIMM
+V1.8
M_CLK_DDR2
C214
C
Place 10p C0402 POP = NA M_CLK_DDR#2
Layout Note: near SO-DIMM
+V3.3S
13 M_B_DQS[7..0]
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
13 M_B_DQS#[7..0]
B
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_ODT2 M_ODT3 M_ODT2 M_ODT3
A
w
5
w w
p la .
12,19 12,19
4
s p to
DQS_0 DQS_1 DQS_2 DQS_3 DQS_4 DQS_5 DQS_6 DQS_7 DQS_#0 DQS_#1 DQS_#2 DQS_#3 DQS_#4 DQS_#5 DQS_#6 DQS_#7 ODT0 ODT1 197SMB_CLK_S2 195SMB_DATA_S2 SODIMM1 DDR-SODIMS
m e h c
C219 C216 0.1u C0402 0.1u C0402 C610 0.1u C0402 POP = NA C153 C611 1u C0603 0.1u C0402 POP = NA POP = NA +V1.8 C88 0.1u C0402 C108 0.1u C0402
C217
0.1u C0402
Layout Note: Place these Caps near SO-DIMM
a
C218 0.1u C0402 C155 1u C0603 POP = NA
ic t
C220 2.2u C0805 12,19 PM_EXTTS#1 +V1.8 +V0.9S
.c s
+V3.3S C197 0.1u C0402 R0603 R785 0 POP = NA2 1
m o
+V1.8 J6B 112 111 117 96 95 118 81 82 87 103 88 104 199 VDD_01 VDD_02 VDD_03 VDD_04 VDD_05 VDD_06 VDD_07 VDD_08 VDD_09 VDD_10 VDD_11 VDD_12 VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF 83 120 50 69 163 1 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 E2 E3 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
D
C195 2.2u C0805
DVT 0919
12,17,40 M_VREF
M_VREF C194C196 2.2u 0.1u C0805 C0402
C
E2 E3
E5 E6
E5 E6
SODIMM1 DDR-SODIMS
B
SMB_CLK_S2 8,17,19,23 SMB_DATA_S2 8,17,19,23
C97 0.1u C0402
C102 0.1u C0402
Layout Note: Place these Hi-Freq Decoupling Caps near the GMCH
A
3
2
5
4
3
2
1
D
DDR2 Termination
+V0.9S 0.1u C181 C0402 C180 C0402 0.1u C178 C0402 0.1u C0402 C0402 0.1u C0402 0.1u C0402 0.1u C506 C510 C507 C508 0.1u C509 0.1u C520 0.1u C521 0.1u C516 0.1u C517 0.1u C518 C0402 0.1u C0402 0.1u C0402 C0402 C0402 C0402 C0402 C0402
Layout note: Place one cap close to every 2 pullup resistors teminated to +0.9S
0.1u C179 C0402 0.1u C182 C183 0.1u C504
C
C505
C519 0.1u C209 0.1u C208 0.1u C207 0.1u C206 C205
B
C204
+V3.3S
SOT-23-BCE MMBT3904 Q56 C POP = NA
B
A
Layout note: Place it under DIMM0
w
5
w w
U6 1 2 3 4 VDD D+ DSCLK 8 SDATA 7 ALERT# 6 T_CRIT_A# GND 5 LM86CIM,SOIC-8 M08A POP = NA
Layout note: Place it under DIMM1
PM_EXTTS#0_D
p la .
SMB_CLK_S2 8,17,18,23 SMB_DATA_S2 8,17,18,23 R151 0 1 2 POP = NA R152 0 1 2 POP = NA
4
C203
s p to
C0402 0.1u C0402 C0402 C0402 C0402 C0402 0.1u C0402 0.1u C0402 0.1u C0402 0.1u C0402 M_B_A0 R0402 M_B_A1 R0402 M_B_A2 R0402 M_B_A3 R0402 M_B_A4 R0402 M_B_A5 R0402 M_B_A6 R0402 M_B_A7 R0402 M_B_A8 R0402 M_B_A9 R0402 M_B_A10 R0402 M_B_A11 R0402 M_B_A12 R0402 M_B_A13 R0402 PM_EXTTS#0 12,17 PM_EXTTS#1 12,18
R165 R673 1 R686 1 R196 1 1 R661 R156 1 R183 1 R677 1 1 R166 R674 1 R687 1 R191 1 1 R670 R163 1 R662 1 1 R671 R672 1 R164 1 1 R195 R684 1 R184 1 1 R189 R190 1 R685 1 1 R162 R668 1 R161 1 R667 1 R160 1 R666 1 R159 1 R158 1 R665 1 R664 1 R669 1 R157 1 R663 1 R167 1 1 R683 R193 1 R682 1 R192 1 R681 1 R188 1 R680 1 R679 1 R187 1 R185 1 R194 1 R678 1 R186 1 R688 1 1
56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2 56 2
R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 M_A_BS#0 R0402 M_A_BS#1 R0402 M_A_BS#2 R0402 R0402 R0402 R0402 M_B_BS#0 R0402 M_B_BS#1 R0402 M_B_BS#2 R0402 R0402 R0402 R0402 M_A_A0 R0402 M_A_A1 R0402 M_A_A2 R0402 M_A_A3 R0402 M_A_A4 R0402 M_A_A5 R0402 M_A_A6 R0402 M_A_A7 R0402 M_A_A8 R0402 M_A_A9 R0402 M_A_A10 R0402 M_A_A11 R0402 M_A_A12 R0402 M_A_A13 R0402
M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_ODT0 M_ODT1 M_ODT2 M_ODT3
12,17 12,17 12,18 12,18 12,17 12,17 12,18 12,18 12,17 12,17 12,18 12,18
M_A_WE# 13,17 M_A_CAS# 13,17 M_A_RAS# 13,17
M_B_WE# 13,18 M_B_CAS# 13,18 M_B_RAS# 13,18 M_A_A[13..0]
m e h c
M_A_BS#[2..0] 13,17 M_B_BS#[2..0] 13,18 M_A_A[13..0] 13,17 M_B_A[13..0] 13,18
a
ic t
.c s
m o
D
C
B
M_B_A[13..0]
E
R0603
A
PM_EXTTS#1_D
R0603
3
2
5
4
3
2
1
+V3.3S
ought to install 2.5v
3
D25 BAT54S 3 sot95p280-3n-123 1 1
D24 BAT54S 3 sot95p280-3n-123 1
D23 C473 BAT54S sot95p280-3n-123 0.1u C0402
D
J4 R G B MS0 DATA MS2 CLK VCC HS VS VSS1 VSS2 VSS3 VSS4 VSS5 CASE1 CASE2 1 2 3 11 12 4 15 9 13 14 5 6 7 8 10 16 17 CRT_R CRT_G CRT_B DAC1_DDC1DATA_B
FB14 FB16 FB19 DAC1_DDC1CLK_B DAC1_HSYNC_B DAC1_VSYNC_B C90 C93 C105
47R FB0603 47R FB0603 47R FB0603 C87 22p C0603 C94
FB15 FB17 FB18 C104 22p C0603
47R FB0603 47R FB0603 47R FB0603 C92 C98 10p C0603 C111 10p C0603 R86 1 GM_CRT_R 12 GM_CRT_G 12 GM_CRT_B 12 R77 150_1% R0603 R75 150_1% R0603 150_1% R0603 2 1 2 1 2
10p 10p 10p C0603 C0603 C0603
22p C0603
10p C0603
C116
C134
33p 33p C0603 C0603 POP = NAPOP = NA
CRT_DB15 CRT-DB15_B
change 0803
+V5S
+V3.3S
DVT 0920
R92 1 2 2.2K 2 R104 2.2K 1 2 Q13 S BSS138 sot95p280-3n-gsd +V3.3S G R0603 R0603
D7 BAT54S 3DAC1_DDC1DATA_B sot95p280-3n-123
C
D
R121 1
2 D
+V5S 1
D11 BAT54S 3 DAC1_DDC1CLK_B sot95p280-3n-123
G
2
2.2K
R0603
R122 2.2K 1 2 Q14 S BSS138 sot95p280-3n-gsd
R0603
FB20
47R FB0603
C137 0.1u C0402 1
FB21
B
47R FB0603
A
w
5
w w
p la .
4
s p to
D8 BAT54S 3 sot95p280-3n-123 R110 1 39 R0603 4 2 C131 0.1u C0402 3 D10 BAT54S 3 sot95p280-3n-123 1 5 R119 1 39 R0603 4 2 C142 0.1u C0402 3
m e h c
GM_CRT_DDC_DATA 12 GM_CRT_DDC_CLK 12 U3 74HCT1G126GW sot95p190-5 2 GM_CRT_HSYNC 12 C119 0.1u C0402 U4 74HCT1G126GW sot95p190-5 2 GM_CRT_VSYNC 12
CHANGE 0808
a
ic t
.c s
m o
2
2
2
D
C
2
1
2
1
1 5
B
3
2
5
4
3
2
1
D
Where: 1). Cload = Crystal's load capacitance. This value can be obtained from Crystal's specification. 2). Cin1, Cin2 = input capacitances at RTCX1,RTCX2 pins of the ICHn. These values can be obtained in the ICHn's data sheet. 3). Ctrace1, Ctrace2 = Trace length capacitances measured from the Crystal terminals to RTCX1,RTCX2 pins. These values depend on the characteristics of board material, the width of signal traces and the length of the traces. The typical value of this capacitance is approximately equal to: Ctrace = trace length * 2 pF/inch 4). Cparasitic = Crystal's parasitic capacitance. This capacitance is created by the existence of electrode plates and the dielectric constant of the crystal blank inside the crystal part. Refer to the crystal's specification to obtain this value.
C396 RTC_X1
+V3.3S
RTCRST# requeres 18-25ms delay. Use the RC circuit delay the signal .
22p C0402 1 X5 3 R589 1 32.768KHZ osc-b720x127-3 RTC_X2 22p C0402 1M 2 RTC_RST# +V3.3A_RTC R0402 R769 1 SM_INTRUDER# 332K_1% R0603 2 R768 1 Pull down POP = NA UNSTUFF STUFF 0 2 R0402 W1 Y1 Y2 W3 V3 U3 U5 V4 T5 U7 V6 V7 32 ACZ_BITCLK_C 34 ACZ_BITCLK_M 32 ACZ_SYNC_C 34 ACZ_SYNC_M 32 ACZ_RST#_C 34 ACZ_RST#_M 32 ACZ_SDATAIN0 34 ACZ_SDATAIN1 R587 R586 1 R778 1 R779 1 R771 1 R772 1 1 R776 R777 1 1 2 2 2 2 2 2 39 39 39 39 39 39 R0603 R0603 R0603 R0603 R0603 R0603 U1 R6 R5 T2 T3 T1 T4 AB1 AB2 AA3 Y5 W4 10M 2 R0402
DVT 0920
U27A RTXC1 RTCX2 LAD0 LAD1 LAD2 LAD3 AA6 AB5 AC4 Y6 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
+V3.3A_RTC
R595 1
20K 2
C412 R0402 1uF,0805,X7R C0805
C399
RTCRST#
C411 1uF,0805,X7R C0805
C
R766 1
INTRUDER# INTVRMEN EE_CS EE_SHCLK EE_DOUT EE_DIN LAN_CLK
ICH7 internal VR enable strap
INTVRMEN Enable (default) Disable 1 0 Pull up STUFF UNSTUFF
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
LAN CPU
LAN_RSTSYNC
+V3.3S
Forrin modify,2005.07.03,Can be NC
TP61
32 ACZ_SDATAOUT_C 34 ACZ_SDATAOUT_M ICH_SATA_LED# R244 C233 1 0.1u C0402 U10 SN74LVC1G08DCKR sot65p190-5 1 2 3 HDD_LED# 25 5 10K 2 R0603
26 SATA_RXN0 26 SATA_RXP0 26 SATA_TXN0 26 SATA_TXP0 Distance between the ICH-7 M and cap on the "P" signal should be identical distance between the ICH-7 M and cap on the "N" signal for same pair.
B
53
ATA_LED#
4
A
w
5
w w
p la .
4
Place within 500mils of ICH ball
25 IDE_PDIOR# 25 IDE_PDIOW# 25 IDE_PDDACK# 25 INT_IRQ14 25 IDE_PDIORDY 25 IDE_PDDREQ
s p to
ACZ_SDATAIN2 R0603 39 2 39 R0603 2 R532 0 1 2 R0402 AF18 AF3 AE3 AG2 AH2 C392 C390 3900p C0603 3900p C0603 C376 C385 C384 C382 3900p 3900p 3900p 3900p C0603 C0603 C0603 C0603 POP = NA POP = NA POP = NA POP = NA SATA_RXN2 AF7 SATA_RXP2 AE7 AG6 AH6 AF1 AE1 8 CLK_PCIE_SATA# 8 CLK_PCIE_SATA R549 1 24.9_1% R0402 AH10 AG10 2 AF15 AH15 AF16 AH16 AG16 AE15 SATA_RXN2 SATA_RXP2 2 1K R560 1 R0402 1K 2 R0402
AC-97/AZALIA
ACZ_BIT_CLK ACZ_SYNC ACZ_RST#
ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
ACZ_SDOUT SATALED#
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP
m e h c
RTC LPC
LDRQ0# LDRQ1#/GPIO23 LFRAME# A20GATE A20M# AC3 AA5 AB3 ICH_DRQ#0 ICH_DRQ#1 AE22 AH28 CPUSLP# AG27 TP1/DPRSTP# TP2/DPSLP# FERR# AF24 AH25 R469 R489 1 1 AG26 GPIO49/CPUPWRGD AG24 IGNNE# INIT3_3V# INIT# INTR RCIN# AG22 AG21 AF22 AF25 TP50 AG23 AH24 AF23 NMI SMI# H_SMI#_R STPCLK# AH22 THERMTRIP# DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DA0 DA1 DA2 DCS1# DCS3# AF26 AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15 AH17 AE17 AF17 AE16 AD16 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_PDA0 IDE_PDA1 IDE_PDA2
a
R317 1 2 R206 1 0 2
10K
POP = NA
ic t
R0603 LPC_AD[3..0] R0603 10K 2 ICH_DRQ#0 35 H_A20GATE H_A20M# 35 9 H_PWRGD H_IGNNE# H_INIT# H_INTR 9 9 9 9 H_NMI R0402 H_SMI# H_STPCLK# 9 9 9 IDE_PDD[15..0] 25
27,35,51,54
.c s
+V1.05S +V1.05S 5656 2 2 POP = NA H_DPRSTP# H_DPSLP# 9,42 9 R0402 R0402 R96 1 56 2 H_RCIN# R479 1 2
m o
R0402 9 +V1.05S 35 56 2 R0402
D
2
Within 2" from the series resistor without stub
LPC_FRAME# 27,35,51,54 R472 R484 1 1
C
TP112 0 R0402 R0402 2 0 2 Within 2" from the ICH
POP = NA
H_