Text preview for : vprMatrix laptop schematic diagram.pdf part of vprMatrix vprMatrix laptop schematic diagram
Back to : vprMatrix laptop schemati | Home
m
A B C D
4
.c o
s
CPU VIA C3
ic
EBGA
PAGE 3,4
t
CLOCK
SO-DIMM HOST BUS GENERATOR
PAGE 10 133 MHz CY28317 PVC-2
a
MEMORY PAGE 2
ON BOARD LCD/CRT
MEMORY BUS (Twister T) LVDS LVDS
256MB PAGE 13, 32
PAGE 5,6
X'TAL
m
PAGE 8, 9 133 MHz
14.318MHz
e
3 3
PCI BUS 33 MHz IEEE1394
uPD72872
h
PAGE 16
c
MDC VT82C686B MINI-PCI CARDBUS LAN USB 2.0
LAN CARD R5C476II RTL8139CL NEC
uPD720100
INDICATOR
PAGE 21 PAGE 14 PAGE 11 PAGE 20
PAGE 32 PAGE 17, 18
-s
X'TAL
FAN, LOGIC 32KHz Cardbus RJ11/RJ45 USB Port*3
CF_conn
PAGE 25
p
PAGE 15 PAGE 11 PAGE 20
FINGER PRINT
ISA BUS
TOUCH SCREEN COM
to
GPS
2 PAGE 22 2
BLUE TOOTH USB
p
FLASH KBC
PAGE 26 BIOS H8/3437
PAGE 24 PAGE 23
la
HDD IDE
PAGE 19
.
AC-LINK
TOUCH
PAD
PAGE 24
w
AUDIO CODEC
BUZZER
PAGE 27
w
1
AUDIO AMP
PAGE 29
w
AUDIO CONN
PAGE 28
A B C D
m
A B C D E
Frequency table for CY28317PVC-2
o
BSEL(1:0)
133MHz : 1 1 +3VS PLANE 4 3 2 1 0
CPU PCI CPU/PCI
+3VS 100MHz : 0 1
+3VS +3VS 1 0 0 1 1 133.90 33.47 +/-0.25%Center Spread
RP501 +3VS 1 0 1 1 1 133.60 33.40 +/-0.25%Center Spread
.c
BSEL0 1 8 RJ10 RJ11 1 1 1 1 1 133.30 33.33 0 TO -0.5% down spread
2 7 1 1 1
CPU_BSEL0 3
3 6
A A BSEL1 BSEL0
BSEL1 4 5 2 FS2 2 FS3 R584 FIX
CPU_BSEL1 3
B B 10K
4 3 3 4
10KX4
s
10KJA 10KJA 2 CPU PCI CPU/PCI
FS4 4 3 2 1 0
1 0 0 0 1 100.50 33.50 +/-0.25%Center Spread
FS0 and FS1 STRAPPING. FS2 = HIGH (A) FS3 = HIGH (A) FS4 = HIGH
ic
1 0 1 0 1 100.20 33.40 +/-0.25%Center Spread
1 1 0 0 1 90.00 30.00 +/-0.25%Center Spread
1 1 1 0 1 100.00 33.33 0 TO -0.5% down spread
t
+2.5VS
+3VS FIX BSEL1 BSEL0
1
a
1 1
L26
1.8UH_0805 L27 C225
+3VS FOR CLOCK GEN. 1.8UH_0805 0.1UF_Y5V
2
2
3VSCLKGN 2
m
1
1
1
1
1
1
C185 C184 C207 C224 C206 C223
0.01UF_X7R 22UF/10V 0.01UF_X7R 0.01UF_X7R 0.01UF_X7R 22UF/10V
2
2
2
2
2
2
1 1
C183 C205
e
3 10PF 10PF 3
NA NA
U504 2 2
CLKPWR_25S
0
h
R219 5 48 HCK 1 R572 20
10K VDD_REF CPUCLK0 HCLKNB 6
1 2 -CG_CPU_STOP 9 47 CPU_CK+ 1 2
+3VS VDD_PCI CPUCLK1 HCLK_C0 3
29 CURRENT DRIVING
35 VDD_SDRAM 44 R594
VDD_SDRAM CPUCLKT MODIFY CPU
c
R246 28 43
10K AVDD48 CPUCLKC CLK 7/9
1 2 45 ROUTING PARALLEL
+3VS VDD_CPU3.3
D16
5/15 mils
46 10 FS4 R590 1 2 22
VDD_CPU2.5 FS4/PCICLK_F SBCLK 17
3 2 -PD 11 FS3 R585 1 2 22
s
5,17,25 SUSA# FS3/PCICLK0 NBCLK 6
13 CLK10 R591 1 2 22
RB420D PCICLK1 PCLK_USB20 20
R218 21 14 CLK11 R587 1 2 22
NA PD# PCICLK2 PCLKMDM 21
1 0 2 -CG_CPU_STOP 19 15 CLK12 R586 1 2 22
-
7 -GCPUSTP CPU_STOP# PCICLK3 PCLKCB 14
24_48M/FS1 NEED SET TO 48MHz 20 16 CLK13 R588 1 2 22
17 -PCISTP PCI_STOP# PCICLK4 PCLKLAN 11
1 2 IREF 40 17 CLK16 R619 1 2 22 CLK14
IREF PCICLK5 PCLK1394 16
10 MULT_SEL 22
FOR USB (SB) USE! R621 221_1% R217 MULTISEL
USBCLK 1 2
18 USBCLK 24
10 1 1 1 1 1 1 1
p
R620 SDATA I2CDA686 10
USB_48MHz FOR USB 2.0 USE! 1 2 25
I2CCK686 10
C212
20 USB_48MHZ FS0 27 SCLK C211 C214 C213 C208 C209 C227
R568 10 BSEL0
1 2 FS1 26 48M/FS0 18
5 NB_14MHz
BSEL1
24_48M/FS1 SDRAM_IN
(SDRAM_IN) DCLKO 6 10PF 10PF 10PF 10PF 10PF 10PF 10PF
10 FS2 2 2NA 2 NA 2 NA 2 NA 2 NA 2 NA 2 NA
R589 REF1/FS2
1 2 SB_CLK 3 37 CLK4 R592 1 2 22
SDCLK0 8
to
18 SB_14MHz REF0 SDRAM0 36 R593 1 2 22
CLK5 SDCLK1 SDCLK1 9
SDRAM1 34 R598 1 2 22
CLK6 SDCLK2 10
6 SDRAM2 33 R596 1 2 22
2 1 1 1 1 CLK15 SDCLK3 10 2
C565 C564 C189 C210 12 GND SDRAM3 31
GND SDRAM4 1 1 1 1
23 30 C201 C199 C203 C200 SDCLK0/1 for ON-BOARD SDRAM
42 GND SDRAM5 39
10PF 10PF 10PF 10PF CLK8 1
38 GND SDRAM6 +3VS C204
NA 2 NA 2 NA 2 NA 2 GND 10PF 10PF 10PF 10PF SDCLK2/3 for SO-DIMM
1 41 -RST_CLK
p
GND RESET# 2NA 2NA 2NA 2NA 10PF
32 1 NA
GND 4
VTT_PWRGD# 2
CKGENX1 7 R599 R597
8 X1 1 2 22
X2 DCLKI 6
la
Y4 10K
CY28317PVC-2 0
1 3CKGENX2 2 1 R600 2
10-028317-9800 -PCIRST 11,14,16,18,20,21,22,23
2 4
NA
IC CY28317PVC-2 CLOCK GENERATOR SSOP-48
.
1 1 +3VS
U506A
C187 C186
14
14.318MHz 74LVC14
10PF 10PF
2 2
+3VS +3VS 1 2
w
MULT_SEL 1 R615 2 1
1 NA 10K
R569
7
10K
R618
10K
w
2 CLK_VTPGD
1 2 3
R570
100K
1 2 2
12,34 VTTPWRGD B C
'E
MULT_SEL : (DEFAULT LOW FOR 1.0V)
LOW : FOR 1.0V OUTOUT SWING CHANGE TO 100K Q502 P12
w
HIGH : FOR 0.7V OUTPUT SWING 1 MMBT3904 1
PLACE CLOSE TO NET "DCLK0"
CLOCK GENERATOR
A B C D
CLK12
m
A B C D E
HD[0:63]
U525A
o
5 HA[3:31] HA[3:31] HD[0:63] 5
HA3 AD6 R3 HD0 +1.5VS
AD9 A3 D0 N1
HA4 HD1
AD5 A4 D1 H3
HA5 HD2
AD7 A5 D2 F2 C626 56PF/50V
HA6 HD3 330
.c
AF10 A6 D3 P1 1 2 NA R733
1 2
HA7 HD4 -IGNNE -IGNNE
A7 D4
HA8
HA9
HA10
AE8
AF6
AE3
A8
A9
VIA C3 EBGA 376 D5
D6
M2
N2
D3
HD5
HD6
HD7
-A20M
C627
1
C628
56PF/50V
2 NA
56PF/50V
-A20M R734
1
330
2
A10 D7 R735 330
HA11 AE9 M3 HD8 GINTR 1 2 NA GINTR 1 2
AD4 A11 D8 J1 C629 56PF/50V
4 HA12 HD9 330 4
AF5 A12 D9 K1 1 2 NA R736
1 2
HA13 HD10 -GSMI -GSMI
A13 D10
s
HA14 AE10 GND VCC2 G3 HD11 C630 56PF/50V
A14 D11 R737 330
HA15 AF4 K2 HD12 -GSTPCLK 1 2 NA -GSTPCLK 1 2
AE6 A15 AF1 N4 AF3 J24 D12 F1 C263 56PF/50V
HA16 HD13
AA2 A16 AF7 N5 AF8 H1 D13 H2 1 2 NA
HA17 HD14 -DPSLP
U2 A17 AF11 N25 AF12 H22 D14 P2 C632 56PF/50V
HA18 HD15
ic
A18