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RX_GSM_PCS
A1
RX275_DCS
RX MID CHANNELS GSM: CH 62 -- 947,4 MHz EGSM: CH 37 -- 942,4Mhz DCS: CH 700 -- 1842,8MHz PCS: CH 661 -- 1960MHz -2,5dB FL400
A9 RF_V2 RX LOCAL OSCILLATOR 4 RX_EN
GSM LNA
+13 dB C Q400 B
-3,5dB FL401 925-960MHz B +10dB Q450 E +10dB C B Q450 E C
3 Q112 2 RX275
Osc. discrete circuty
Q203 CR249 RF_V1
800MHz D9
PLL
C8
U200 MAGIC
F7 ( SCLK_OUT ) BCLKR ( SDFS ) BFSR ( SDRX ) BDR to WhiteCap
4 U150 10 EXT ANT SW_RF from J600 Pin2 3 V1 9 -0,6dB
7 6 5
925-960MHz
-5dB B FL457 400 MHz
+12dB C Q480 C F2 SWITCH SW_VCC C7 A7 STEP ATT.
RXI DEMODULATION RXQ
RX275_GSM RVCO_PCS -2,5dB 1930-1990MHz FL2400 6 1 U400 3 FL1400 1805-1880MHz -2,5dB 4 5 RX275_DPCS
RX SPI
G9 G8
V2 2 7 V2
2
+12dB B Q1400 C
-2dB FL1401 1805-1990MHz
5 V1 U401 U151 SWITCH CONTROL 2 1 TX_EN RF_V1 4 RX_EN 3 FILTERED_-5V 6
2,75V RF_V2 B+ Q252 2,75V RF_V1
D Q242 S S Q240 D
G
F1 REG. H1 H2
PHASE DET Divider 200KHz
G1
VRef
13MHz VCO
DCS_PCS LNA
RVCO_DCS
J7 H9, J9
G
CR248
13MHz RX VCO MID CHANNELS GSM: CH 62 -- 1347,4 MHz EGSM: CH 37 -- 1342,4Mhz DCS: CH 700 -- 1442,8MHz PCS: CH 661 -- 1560MHz
SUPER FILTER
H7, C8, J1, B3 RVCO_DCS C1 SF_OUT 1,5V - 3,2V A1 B1 RVCO_275 Q1102 6 SW_V1 J8 GP04 F4 C4 A4 A3
MUX Startup Ref. 1 /2
Prog. Divider 200KHz REF. REF. OSC. 26 MHz
J6 G6
MAGIC_13MHz CLK_SELCT
to WhiteCap from WhiteCap
B+ RX VCO FRQ. RANGE EGSM: 1325 - 1360Mhz DCS: 1405 - 1480MHz PCS: 1530 - 1590MHz 0db 1 +21dB 4,10-15 7 C Q331 +6bB CR330 B -5dB R336 +11,5dB -2 dB C Q330 B R333
RVCO_PCS 3 4 5
1-3 TX FRQ. RANGE EGSM: 880-915Mhz DCS: 1710-1785MHz PCS:1850-1910MHz Q380 -0,2dB 5-8 PA_B+
4
DM_CS
PHASE DET
Divider AFC
E1 Y200 E2 26MHz ( CE ) MQSPI_CS1 ( SPI_CLK ) MOSPI_CLK1 ( SPI_DATA ) DX1 J3 from WhiteCap
U250 RX VCO
PLL G5
11-14
U300 PA
2, 8
Tri Band Jade
SPI LOGIC CONTROL FACE
TX_275 FILTERED_-5V
INTER H4
GATE CTRL CIRCUIT EXC
DM_CS 6 7 +6-8dBm TX VCO FRQ. RANGE EGSM: 880-915Mhz DCS: 1710-1785MHz PCS:1850-1910MHz TX VCO MID CHANNELS
SF_OUT
U390 PAC
RF_IN 2 TX_275
U350 TX VCO
2 5 3 TX275_GSM TX275_DPCS TX_DCS
4
1,5V - 3,2V
TX LOOP FILTER
DET SAT.
1, 3
RF_V2 *GSM_SEL 2 *PCS_SEL 4 Q100 3 *DCS_SEL DETECT_SW AOC_DRIVE SAT_DETECT TX_KEY_OUT A5 1 MODULATION
TXI TXQ
TX SPI
J2 ( TX_CLK ) BCLKX G7
( SDTX ) BDX
4, 14 10 12 8 11 DETECT_SW AOC_DRIVE SAT_DETECT RX275_DCS RX_GSM_PCS RVCO_PCS RVCO_DCS RX275_GSM RX275_DPCS TX_275 TX275_GSM TX275_DPCS TX_DCS FILTERED_-5V TX_KEY_OUT
GSM: CH 62 -- 902,4MHz EGSM: CH 37 -- 897,4Mhz DCS: CH 700 -- 1747,8MHz PCS: CH 661 -- 1880MHz
H8 B6 B4 C5 PA CONTROL LOGIC J4 CONTROL H5
RX_ACQ DM_CS TX_KEY from WhiteCap
GSM SERVICE SUPPORT GROUP GSM / DPCS SELECT CIRCUIT
For description of GSM / DPCS Select Circuit see document on: emeacs.fle.css.mot.com
06.04.00 Rev. 1.0
RX SIGNAL PATH TX SIGNAL PATH
REFERENCE CLOCK Orderable Part Non - Orderable Part
LEVEL 3 RF Block Diagram Tri Band Jade Michael Hansen, Ray Collins, Ralf Lorenzen,
Page 1
MAIN VCO SIGNAL PATH TUNING VOLTAGES
KBR0, KBR1, KBR2 to Keyboard KBC0, KBC1, KBC2 BKLT_EN to Display DP_EN_L SIMPD0 V2 BATT_THERM_AD U905 LS1_IN LS2_IN SIM_TX SIM_RX IrDA_EN VIB_EN EXT_CHG_EN HEAD_INT_L CLK_SELCT TX_EN DM_CS TX_KEY RX_EN RX_ACQ RESET ( SDTX ) BDX ( TX_CLK ) BCLKX from / to MAGIC BCLKR ( SDFS ) BFSR ( SDRX ) BDR
H2, H1, H3 J5, J3, J2 KEYPAD K3 DISPLAY A11 INTERFACE A4 E9 SIM E7 F3 INTER B5 FACE B2 K1 C2 A1 N3 C1 A1 C1 E2 CTM E2 E1 E1 MODULE E3 E3 E4 E4 P2 P2 B6 B3 B4 D4 A3 K2 SERIAL INTER FACE DSP
C14, F10, G4, H4, K5, P13 A9, A10, C5, K6, K10, M8, M11
WHITE_CAP
SPI INTERFACE
VDDS VCC_MEMIF VDD VCCA
V2 V3
MAGIC SPI ADDRESS BUS DATA BUS
SR_VCC
to MAGIC J902
A0 3
U700
V1-V5
CPU
I N T E R F A C E CTM
C702-C706
D6, E1 B2 U702 A1 SRAM G5 V2 RESET A4, E1, F5 B4
C9 E10 B11 D9 B9 F1 STBY_DL BATT_SER_DATA
CE2 CE3 R_W
R_W CE0 CE1
U701 EPROM B3 EEPROM
D7 F8 4 1
V2 RESET GND R_W DP_EN_L ( -10V )
13 2 14 4 15 1
INT. DIV.
15 PIN EXT CONN. J 600 DSC_EN 13 RS232_RX 7 RS232_TX 6 BATT_FDBK 4
DSC
H5 PB6 CHARGE L7 L6 SPI INTERFACE TIMER B7 P4 H10 MAGIC_13MHz
BATT CON. GND For description of Midrate Charger 1 see document on: emeacs.fle.css.mot.com J604 2 4 3 B+ CHRG_EN BATT+ 4 BATT_SER_DATA
Q902 3 1,2,5,6 Q905 3 1-3 Q901 4 2 4,6 Q909 5 3 R913 Q900 4 7,8 BATT_THERM_AD
U904 U903
-10V -5V KBR0, KBR1, KBR2 to WhiteCap KBC0, KBC1, KBC2
V1 2
1
KEYPAD
UART A5 INTERF. A6 from Charger URXD
BATT_FDBK to J600 EXT_B+
2
CR903 4
PWR_SW from G CAP2 6-8 VREF STBY_DL V1 V2
AUDIO SPI
GCAP SPI
UTXD 6
DEEP SLEEP CIRCUIT
V1_SW
V_BOOST from G CAP2 ALERT_VCC from G CAP2 BKLT_EN from WhiteCap
DISP B/LIGHTS K/PAD B/LIGHTS
B C Q907
GCAP_CLK 13 MHz
32.768 KHz
GCLK
V2 IrDA_EN 5
U500 IRDA
RTC_BATT +
3,8
7
MIDRATE_1 MIDRATE_2
4
2 Q904
SW_RF EXT_CHG_EN
Tri Band Jade
EXT_B+ MAN_TEST_AD GND GND GND GND
2 8 14 5 1 3 10 15 9
F5 to Antenna Switch KBR3 EXT_B+ A1 DSC_EN_AD DOWNLINL_AD BATT_THERM_AD ISENSE B2 SENSE A2 B3 CNTL. D9
Y900
ISENSE D9
A7 B7 C7 REAL TIME CLOCK
ANCILLARY PCB CONNECTOR J5006
2 4 V_BOOST 1 to WhiteCap to / from WhiteCap 3 5 CARD_PD DATA_TX 7 DATA_RX READER_RST 9 13 READER CLK Vibrator Smart Card Reader
CR900
SPI INTERFACE
D6 CHARGE E8 SELECT F10 F7 SENSE D10 F6 LEVEL J7 SHIFT J8 K7 G6 K10 H8 C8 G4
VREF REG. V3 REG. V2 REG. V1 REG.
CHRGC MAIN_FET BATT+ EXT_B+ CLK RESET SIM_I/O 1 2 6 LS1_IN LS2_IN SIM_TX SIM_RX PWR_SW STBY_DL G9 B5 J5 A6 C6 VREF 2.775V,for Magic V3 1,8V, for WhiteCap V2 2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM V1 5.0V, for DSC Bus, Negative Voltage Regulator VSIM1 3.0 or 5.0V, for SIM Card Circuit J803 SIM Con. 4 3 VSIM1
U900 G_CAP2
from WhiteCap from WhiteCap
To GCAP II
14
RTC BATT+ 1,6,8,10,11, 12,15 & 16 E
RTC Battery
ON_2 G5 RESET C4 D2 C2 Logic Control
ON / OFF
RX SIGNAL PATH TX SIGNAL PATH MAIN VCO SIGNAL PATH TUNING VOLTAGES REFERENCE CLOCK Orderable Part Non - Orderable Part
UPLINK DOWNLINK
11 12
MIC
J2 PA_DRV Interface Audio Codec H6 H7 K9 J9 SPR+
2
VSIM REG.
U902
1
K1
H9
E18 A5 K6
VBOOST1 REG.
C5, B6 A10, C10 ( WhiteCap ) VIB_EN B+ U501
E1 B10
J504
SPR-
ALRTOUT
GSM SERVICE SUPPORT GROUP
SR_VCC 4
Q938 CR902 L901
06.04.00 Rev. 1.0 Page 2
HEADSET CON.
V2
SPKR
LEVEL 3 AL Block Diagram Tri Band Jade
V_BOOST1 Internal GCap use only (VSIM1, LS_V1)
R976
ALRT HEAD_INT_L
5-8
1-3
ALRT_VCC B+ ALRT_VCC to Backlight
Michael Hansen, Ray Collins, Ralf Lorenzen,
R977
DISPLAY
M E M O R Y
D0-D7 5-12