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TC9432AF/ TC9462AF (Digital Signal Processor)
PIN No. NAME I/O FUNCTIONAL DESCRIPTION REMARKS
1 TEST0 - Test mode terminal. Normally, keep at open. With pull-up resistor.
Playback speed mode flag output terminal.
2 HSO O UHSO HSO PLAYBACK SPEED
H H Normal -
H L 2 times
3 UHSO O L H 4 times
L L -
Subcode Q data emphasis flag output terminal.
4 EMPH O Emphasis ON at "H" level and OFF at "L" level. -
The output polarity can invert by command.
Channel clock output terminal. (44.1 kHz)
5 LRCK O L-ch at "L" level and R-ch at "H" level. -
The output polarity can invert by command.
6 VSS - Digital GND terminal. -
7 BCK O Bit clock output terminal. (1.4112 MHz) -
8 AOUT O Audio data output terminal. -
9 DOUT O Digital data output terminal. -
Buffer memory over signal output terminal.
10 MBOV O -
Over at "H" level.
Correction flag output terminal.
11 IPF O At "H " level, AOUT output is made to correction -
impossibility by C2 correction processing.
Subcode Q data CRCC check adjusting result output
12 SBOK O -
terminal. The adjusting result is OK at "H" level.
Subcode P~W data readout clock input/output termi-
13 CLCK I/O -
nal. This terminal can select by command bit.
14 VDD - Digital power supply voltage terminal. -
15 VSS - Digital GND terminal. -
16 DATA O Subcode P~W data output terminal. -
17 SFSY O Playback frame sync signal output terminal. -
18 SBSY O Subcode block sync signal output terminal. -
19 SPCK O Processor status signal readout clock output terminal. -
20 SPDA O Processor status signal output terminal. -
21 COFS O Correction frame clock output terminal. (7.35 kHz) -
Internal signal (DSP internal flag and PLL clock) output
22 MONIT O -
terminal. Selected by command.
23 VDD - Digital power supply voltage terminal. -
24 TESIO0 I Test input/output terminal. Normally, keep at "L" level. -
25 P2VREF - PLL double reference voltage supply terminal. -
26 HSSW O 2/4 times speed at "VREF" voltage. 2-state output (PVREF,HiZ)
27 ZDET O 1 bit DA converter zero detect flag output terminal. -
Phase difference signal output terminal of EFM signal 3-state output
28 PDO O
and PLCK signal. (P2VREF,PVREF,VSS)
TMAX detection result output terminal. Selected by
29 TMAXS O -
command bit (TMPS).
TMAX detection result output terminal. Selected by
command bit (TMPS).
30 TMAX O 3-state output
DIFFERENCE RESULT TMAX OUTPUT
(P2VREF,HiZ,VSS)
Longer than fixed ferq. "P2VREF"
Shorter than fixed freq. "VSS"
Within the fixed freq. "HiZ"
3
SERVICE MANUAL
PIN No. NAME I/O FUNCTIONAL DESCRIPTION REMARKS
31 LPFN I LPF amplifier inverting input terminal for PLL. Analog input.
32 LPFO O LPF amplifier output terminal for PLL. Analog output.
33 PVREF - PLL reference voltage supply terminal. -
VCO center frequency reference level terminal.
34 VCOREF I -
Normally, keep at "PVREF" level.
35 VCOF O VCO filter terminal. Analog output.
36 AVSS - Analog GND terminal. -
37 SLCO O Data slice level output terminal. Analog output.
38 RFI I RF signal input terminal. Analog input (Zin : selected by command)
39 AVDD - Analog power supply voltage terminal. -
40 RFCT I RFRP signal center level input terminal. Analog input (Zin : 50k)
41 RFZI I RFRP zero cross input terminal. Analog input.
42 RFRP I RF ripple signal input terminal. Analog input.
43 FEI I Focus error signal input terminal. Analog input.
44 SBAD I Sub-beam adder signal input terminal. Analog input.
45 TSIN I Test input terminal. Normally, keep at "VREF" level. Analog input.
Tracking error signal input terminal.
46 TEI I Analog input.
Track in at tracking servo on.
47 TEZI I Trcaking error zero cross input terminal. Analog input (Zin : 10k)
48 FOO O Focus servo equalizer output terminal. Analog output (2VREF~AVSS)
49 TRO O Tracking servo equalizer output terminal.
50 VREF - Analog reference voltage supply terminal. -
51 RFGC O RF amplitude adjustment control signal output terminal.
52 TEBC O Tracking balance control signal output terminal. 3-state PWM signal output.
53 TEBC O Feed equalizer output terminal. (2VREF, VREF, VSS)
Speed error signal or feed search equalizer output ter- (PWM carrier = 88.2 kHz)
54 TEBC O
minal.
Disk equalizer output terminal. (PWM carrier = 88.2 kHz 3-state PWM signal
55 DMO O
for DSP, Synchronize to PXO) output.(2VREF, VREF, VSS)
56 2VREF - Analog double reference voltage supply terminal. -
APC circuit ON/OFF indication signal output terminal.
57 SEL O At the laser on time, UHF = L at "HiZ" level and -
UHF = H at "H" level.
Extemal flag output terminal for internal signal.
58 FLGA O Can select signal from TEZC, FOON, FOK and RFZC by
-
command.
Extemal flag output terminal for internal signal.
59 FLGB O Can select signal from DECT, FOON, FMON and RFZC -
by command.
Extemal flag output terminal for internal signal.
60 FLGC O Can select signal from TRON, TRSR, FOK and SRCH by -
command.
Extemal flag output terminal for internal signal.
61 FLGD O Can select signal from TRON, DMON, HYS and SHC by
command. -
62 VDD - Digital power supply voltage terminal. -
63 VSS - Digital GND terminal. -
64 IO0 General I/O terminal. Can change over input port or
65 IO1 output port by command. At the input mode time can
I/O readout a state of terminal (H/L) by read command. At
66 IO2 the output mode time can control a state of terminal -
67 IO3 (H/L/HiZ) by command.
4
SERVICE MANUAL
PIN No. NAME I/O FUNCTIONAL DESCRIPTION REMARKS
This terminal controls IO0~IO3 terminal.
68 DMOUT At "L" level time, IO0, 1 out feed equalizer signal of With pull-up resistor.
I
2-state PWM. IO2, 3 out disk equalizer signal of 2-state
PWM.
69 CKSE I Normally, keep at open. With pull-up resistor.
70 DACT I DAC test mode terminal. Normally, keep at open. With pull-up resistor.
71 TESIN I Test input terminal. Normally, keep at "L" level. Analog input.
72 TESIO1 I Test input/output terminal. Normally, keep at "L" level. Analog input.
73 VSS - Digital GND terminal. -
Crystal oscillator connecting input terminal for DSP.
74 PXI I Normally, keep at "L" level. -
75 PXO O Crystal oscillator connecting output terminal for DSP.
76 VDD - Digital power supply voltage terminal. -
77 XVSS - Oscillator GND terminal for system clock. -
Crystal oscillator connecting input terminal for system
78 XI I clock. -
Crystal oscillator connecting output terminal for sys-
79 XO O tem clock. -
Oscillator power supply voltage terminal for system
80 XVDD - clock. -
81 DVSR - Analog GND terminal for DA converter. (R-ch) -
82 RO O R channel data forward output terminal. -
83 DVDD - Analog supply voltage terminal for DA converter. -
84 DVR - Reference voltage terminal for DA converter. -
85 LO O L channel data forward output terminal. -
86 DVSL - Analog GND terminal for DA converter. (L-ch) -
87 TEST1 I Test mode terminal. Normal, keep at open. With pull-up resistor.
88 TEST2 I Test mode terminal. Normal, keep at open. With pull-up resistor.
89 TEST3 I Test mode terminal. Normal, keep at open. With pull-up resistor.
90 BUS0 I/O
91 BUS1 I/O Schmit input.
Micom interface data input/output terminal.
92 BUS2 I/O With pull-up resistor.
93 BUS3 I/O
94 VDD - Digital Ppower supply voltage terminal. -
95 VSS - Digital GND terminal. -
96 BUCK I Micom interface clock input terminal. Schmit input.
Command and data sending/receiving chip enable sig-
97 CCE I nal input terminal. The bus Schmit input.
line becomes active at "L" level.
98 TEST4 I Test mode terminal. Normal, keep at open. With pull-up resistor.
99 TSMOD I Local test mode selection terminal. With pull-up resistor.
100 RST I Reset signal input terminal. Reset at "L" level. With pull-up resistor.
5
SERVICE MANUAL
TES IO1
DMOUT
TES I/N
2VREF
RFGC
XVDD
CKSE
XVSS
FLGD
FLGC
TEBC
DACT
FLGB
FLGA
DM/O
FMO
VDD
PXO
VDD
FVO
VSS
VSS
SEL
PXI
IO3
IO2
IO1
IO0
XO
XI
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DVSR 81 50 VREF
RO 82 Servo PWM D/A 49 TRO
DAC
generator
1bit
LPF
Clock
DVDD 83 48 FOO
control
DVR 84 47 TEZI
LO 85 46 TEI
DVSL 86 45 TSIN
TEST1 87 44 SBAD
SERVICE MANUAL
TEST2 88 43 EF1
Address ROM Digital equalizer
TEST3 89 42 RFRP
A/D
circuit
Automatic adjustment
BUS0 90 RAM circuit
41 RFZI
Interface
Micom
BUS1 91 Correction 40 RFCT
circuit
BUS2 92 39 AVDD
BUS3 93 38 RF1
slicer
Data
VDD 94 CLV servo 37 SLCO
RAM
16K
Synchronous
VSS 95 guarantee 36 AVSS
EFM decode
BUCK 96 35 VCOF
CCE 97 VCO 34 VCOREF
Audio out
circuit
TEST4 98 33 PVREF
Digital out Sub code Status
TSMOD 99 decoder 32 LPFO
TMAX
PLL
RST 100 31 LPFN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TEST 0
HSO
UHSO
EMPH
LRCK
VSS
BCK
AOUT
DOUT
MBOV
IPF
SBOK
CLCK
VDD
VSS
DATA
SFSY
SBSY
SPCK
SPDA
COFS
MONIT
VDD
TESIO 0
P2VREF
HSSW
ZDET
PDO
TMAXS
TMAX
6
7
SERVICE MANUAL
TA2150FN
PIN No. SYMBOL I/O FUNCTION DESCRIPTION REMARKS
Reference signal (VRO) output terminal. -
19 VRO O
VRO = 2.1 V when Vcc = 5 V
20 RFRP O Track count signal output terminal. -
Time constant adjustment terminal for bottom
21 BTC l Adjusted by capacitance.
detection.
22 RFCT O RFRP signal center level output terminal. -
Time constant adjustment terminal for peak detec- Adjusted by capacitance.
23 PKC l
tion.
24 RFRPIN l Input terminal for track count signal output amp. -
Output terminal for RF signal amplitude adjust- -
25 RFGO O
ment amp.
Amp (AGC, FE, TE) gain switching terminal.
GVSW MODE
26 GVSW l Low (GND) is for 5 times gain.
GND CD-RW
Hiz Normal
Vcc Normal
AGCIN l Input terminal for RF signal amplitude adjustment Connected to RFO through capac-
27
amp. itance.
28 RFO O Output terminal RF signal amp. -
29 GND - Ground terminal. -
Connected to pin-diode out-
30 RFN2 l input terminal for RF signal amp. put A + B + C + D (through
resistor).
8
SERVICE MANUAL
20µA 36pF
60k 60k
90k 20k 10k 50k
FEO 16 150k
15k
15 SBAD
15k
10pF
40pF 30k 16.7k
36k
FEN 17 10k 14 TEO
60k
20k
10k
10pF
40pF
15k
SEB 18 13 TEN
30k
VRO 19 12 2VRO
20k 20k
20k 50µA
3 STATE
RFRP 20 12k 48k
DET. 11 TEB
24k
2VRO
11k
100 12k 83k
BTC 21 10 SEL
20k
2.9k
100k
1k
RFCT 22 9 LDO
100k
1.4k
238k
PKC 23 15pF 13k 2.26k 8 MDI
11k
1(1/4)
BOTTOM
RFRPIN 24 PEAK 238k
1-1
7 TNI
20k
1(3/4)
15pF
1(1/4)
RFGO 25 1-1
6 TPI
1(3/4)
GVSW 26 5 FPI
AGCIN 27 AGC Amp 4 FNI
RFO 28 3 GMAD
GND 29 2 RFGC
RFN2 30 1 Vcc
9
SERVICE MANUAL
TA7291S (Bridge Driver)
VCC Vref
7 / 2 / 11 4 / 8 / 5
8 / 6 / 15 VS
REG
2/7/4
M
PROTECTOR 10 / 3 / 13
CIRCUIT OUT2
(TSD)
5/9/7 6/1/9 1/5/1
IN1 GND
TA7291P / TA7291S / TA7291F
IN2
PIN No.
SYMBOL FUNCTIONAL DESCRIPTION
P S
7 2 VCC Supply voltage terminal for Logic
8 6 VS Supply voltage terminal for motor drive
4 8 Vref Supply voltage terminal for control
1 5 GND GND terminal
5 9 IN1 Input terminal
6 1 IN2 Input terminal
2 7 OUT1 Output terminal
10 3 OUT2 Output terminal
P Type : PIN 3 9 : NC
S Type : PIN 4 : NC
F Type : PIN 2 3 6 8 10 12 14 and 16 : NC
For F Type, We recommend FIN to be connected to the GND.
11
SERVICE MANUAL
EXPLODED VIEW-1
12
EXPLODED VIEW-1
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INCLUDED ACCESSORIES
13
SERVICE MANUAL
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14
SERVICE MANUAL
EXPLODED VIEW-2
15
SERVICE MANUAL
MAIN PCB ASSY FRONT PCB ASSY
POWER PCB ASSY
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16
SERVICE MANUAL
17
SCHEMATIC DIAGRAM PD-H303
1 2 3 4 5 6 7 8
A
B
C
D
E
NOTES:
1. Resistor values are in ohms (k=kilo-ohms, M=megohms).
2. Capacitor values are in microfarads (p=picofarads).
3. £Parts marked with this sign are safety critical components.
They must always be replaced with identical components-refer
to the appropriate parts list and ensure exact replacement.
PD-H303
3CD PLAYER
1 st Issue; May 2001
SCHEMATIC DIAGRAM PD-H303
1 2 3 4 5 6 7 8
A
B
C
D
E
INSTRUCTIONS FOR SERVICE PERSONNEL
BEFORE RETURNING APPLIANCE TO THE CUSTOMER, MAKE LEAKAGE-
CURRENT OR RESISTANCE MEASUREMENTS TO DETERMINE THAT EXPOSED
NOTES:
1. Resistor values are in ohms (k=kilo-ohms, M=megohms).
2. Capacitor values are in microfarads (p=picofarads).
3. £Parts marked with this sign are safety critical components.
PD-H303
PARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT.
They must always be replaced with identical components-refer
to the appropriate parts list and ensure exact replacement. 3CD PLAYER
1 st Issue; May 2001