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L26H01U, L32H01U
Service Manual
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No. 0234
L26H01U L32H01U
SERVICE MANUAL MANUEL D'ENTRETIEN WARTUNGSHANDBUCH
CAUTION:
Before servicing this chassis, it is important that the service technician read the "Safety Precautions" and "Product Safety Notices" in this service manual. Data contained within this Service manual is subject to alteration for improvement. Les données fournies dans le présent manuel d'entretien peuvent faire l'objet de modifications en vue de perfectionner le produit. Die in diesem Wartungshandbuch enthaltenen Spezifikationen können sich zwecks Verbesserungen ändern.
ATTENTION:
Avant d'effectuer l'entretien du châssis, le technicien doit lire les «Précautions de sécurité» et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die ,,Sicherheitshinweise" und ,,Hinweise zur Produktsicherheit" in diesem Wartungshandbuch zu lesen.
Contents Introduction Tuner Audio Amplifier Stage Power Stage Microcontroller (VCTP) DRX 3961A Serial 64K I2C EEPROM Class AB Stereo Headphone Driver 9. SAW Filter X6966M 10. IC Descriptions
1. 2. 3. 4. 5. 6. 7. 8.
11. Service Menu Settings 12. Software Update Description 13. Block Diagrams 14. Troubleshooting Guide 15. Connectors 16. Concept ICs 17. Replacement Parts 18. Assembly Drawing 19. Schematic Diagrams 20. PCB Layout Diagrams
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
Colour Television August 2007
1. INTRODUCTION
17MB22 Main Board consists of Micronas concept, VCTP as controller. This IC is capable of handling Audio processing, video processing, motion adaptive upconversion(MAU), Scaling-Display processing and FPD control (DPS),unified memory for audio video and Text, 3D comb filter-PC connectivity , OSD and text processing. TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as B/G, D/K, I/I', and L/L' including German and NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8 Supported peripherals are: 1 RF input VHF1, VHF3, UHF @ 75Ohm 1 FAV input 2 SCART sockets 1 SVHS input 1 Stereo Headphone input 1 YPbPr 1 PC input 2 HDMI input 1 Stereo audio input for PC speakers.
2. TUNER
As the thickness of the TV set has a limit, a horizontal mounted tuner is used in the product, which is suitable for CCIR systems B/G, H, L/ L', I/I', and D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on the Tuner in use.
2.1 General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L', I and I'. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient.
2.2 Features of UV1316:
Member of the UV1300 family small sized UHF/VHF tuners Systems CCIR: B/G, H, L, L', I and I'; OIRT: D/K Digitally controlled (PLL) tuning via I2C-bus Off-air channels, S-cable channels and Hyper band Compact size Complies with the requirements of radiation, signal handling capability and immunity conforming to European standards "CENELEC EN55020" and "EN55013".
2.3 Pinning:
3. AUDIO AMPLIFIER STAGE WITH MP7722
3.1 General Description
The MP7722 is a stereo 20W Class D Audio amplifier, intended for use as low frequency power amplifier in a wide range of applications in radio and TV sets. It uses a minimum number of external components to complete a stereo Class D audio amplifier.
3.2 Features
2 x 20W Output at VDD = 24V into a 4 load THD+N = 0.06% at 1W, 8 93% Efficiency at 20W Low Noise (190µV Typical) Switching Frequency Up to 1MHz 9.5V to 24V Operation from a Single Supply Integrated Startup and Shutdown Pop Elimination Circuit Thermal and Short Circuit Protection Integrated 180m Switches Mute/Standby Modes (Sleep) Thermally Enhanced 20-Pin TSSOP Package with Exposed Pad
3.3 Applications
Surround Sound DVD Systems Televisions Flat Panel Monitors Multimedia Computers Home Stereo Systems
3.4 Absolute Ratings
3.5 Pinning
4. POWER STAGE
The DC voltages required at various parts of the chassis and inverters are provided by a main power supply unit and power interface board. The main power supply unit is designed for 24V and 12V DC supply. Power stage which is on-chasis generates +24V for audio amplifier, 1.8V and 3.3V stand by voltage and 8V, 12V, 5V and 3.3Vsupplies for other different parts of the chassis.
5. MICROCONTROLLER (VCTP)
5.1 General Features
The VCT 6wxyP is dedicated to high-quality FPD and double-scan TV sets. The VCT 6wxyP family is based on functional blocks contained and approved in existing products like VCT 49xxI, VSP 94x5B, and DPS 94xxA. Each member of the family contains the entire audio, video, up-conversion processing for 4:3 and 16:9 50/ 60 Hz progressive or 100/120 Hz interlaced stereo TV sets and the control/data interface for flat-panel displays. The integrated microcontroller is supported by a powerful OSD and graphics generator with integrated teletext acquisition. Controller: High-performance 8-bit microcontroller, 8051 compatible Up to 512 kByte in system program Flash WST, PDC, VPS, and WSS acquisition Closed caption and V-chip acquisition Up to 10 page on chip teletext memory Up to 1000 pages with internal memory Up to 30 GPIO Audio: Multistandard TV-sound demodulation: -All A2/NICAM standards -BTSC/SAP with DBX -EIA-J Baseband sound processing for loudspeaker channel: -Volume, bass, treble, loudness, balance -Spatial effect (e.g. pseudo stereo) -Micronas AROUND (Virtual Dolby Surround optional) -Micronas BASS -BBE -SRS WOW -SRS TruSurround XT -Lipsync function Video: CVBS, S-VHS, YCrCb and RGB inputs HDTV YPrPb and RGB inputs ITU656 input Linedoubling with vertical detail enhancement (without internal memory) State of the art motion adaptive up conversion (with internal memory) 4H adaptive comb filter for PAL/NTSC (without internal memory) 3D comb filter for PAL/NTSC (with internal memory) (Optional) Internal SDR RAM interface Powerful horizontal and vertical scaling inclusive Nonlinear horizontal scaling "panorama vision" picture adaptive image improvements (DCE, LSE, CTI, SCE, NCE)
non-linear colorspace enhancement (NCE) with 32 programmable slopes and sections per RGB component (blue stretch, static black stretch, gamma correction). Dynamic contrast enhancement (DCE) (histogram based black stretch with peak black and activity detection and contrast adaption) Luma sharpness enhancement (LSE) Color transient improvement (CTI) Selective color enhancement (SCE) for skin tone correction, blue and green stretch
5.2 Multistandard Sound Processor (MSP) Features
The MSP receives the analog Sound IF signal from the tuner and converts it to digital with its internal SIF-AD converter. The MSP is able to demodulate all TV sound standards worldwide including the digital NICAM system. TV stereo sound standards that are unavailable for a specific VCTP version are processed in analog mono sound of the standard. In that case, stereo or bilingual processing will not be possible. Sound IF input Worldwide FM/AM-mono sound demodulation FM stereo sound demodulation (A2, EIA-J) BTSC/SAP demodulation with DBX NICAM demodulation FM radio & RDS/RBDS demodulation Automatic standard detection automatic volume correction (AVC) Automatic sound select Baseband processing for loudspeaker channel: volume, bass, treble, loudness, balance -spatial effect (e.g. pseudo stereo) -Micronas AROUND -Micronas BASS -SRS WOW (optional) -SRS TruSurround XT (optional) -delayline for lipsync function (shared memory) -Virtual Dolby Surround (optional) 1 I2S input for external ATSC/DVD decoder 1 I2S interface for audio delayline 1 SPDIF output Audio i/o switches -4 analog stereo line inputs and 2 analog stereo line outputs (configurable 5 analog stereo line inputs and 1 analog stereo line output) -1 analog stereo loudspeaker output -1 analog subwoofer output -1 analog stereo headphone output
5.3 Video Features
The TVT is a Teletext decoder for decoding World System Teletext data, as well as Video Programming System (VPS), Program Delivery Control (PDC), and Wide-Screen Signalling (WSS) data used for PALplus transmissions (line 23). The device also supports Closed Caption acquisition and decoding.
The TVT provides an integrated general-purpose, fully 8051-compatible microcontroller with television-specific hardware features. The microcontroller has been enhanced to provide powerful features such as memory banking, data pointer, additional interrupts, shared memory access etc. The TVT has an internal XRAM of 32 KB and a BOOT ROM of 4 KB. For operation the code is fetched from a 16bit FLASH, which can be addressed up to 1 MByte. The controller with dedicated hardware does most of the internal TTX acquisition processing, transfers data to/from external memory interface, and receives/transmits data via I2C-bus interface. In combination with dedicated hardware, the slicer stores TTX data in a VBI buffer of 1 KB. The microcontroller firmware performs all the acquisition tasks (hamming and parity checks, page search, and evaluation of header control bits) once per field. Additionally, the firmware can provide high-end Teletext features like Packet-26 handling, FLOF/TOP and list-pages. The interface-to-user software is optimized for minimal overhead. TVT is realized in deep submicron technology with 1.8 V supply voltage and 3.3 V I/O (TTL compatible). 16 analog video inputs (4xCVBS/Y/C + 3xRGB/YCrCb/YPrPb) Video input switch matrix 3 analog video outputs (integrated Y+C adder) 24-bit RGB/H/V/clk input (e.g. ext. DVI decoder) or 656 8bit input 656 8bit input/output (e. g. for external high-end up conversion by FRCA) Multi-standard color decoder PAL/NTSC/SECAM including all substandards 2D adaptive comb filter for PAL/NTSC with vertical peaking 3D-comb filter for PAL/NTSC (Optional) Macrovision compliant multi-standard sync processing Trilevel sync slicer for HDTV Macrovision detection High-quality soft mixer controlled by Fast Blank (alpha blending) Fastblank monitor via I2C Noise measurement Letterbox detection (auto-wide) Split screen (OSD and video side by side) and AV PIP
5.4 Controller Features
The TVT is a Teletext decoder for decoding World System Teletext data, as well as Video Programming System (VPS), Program Delivery Control (PDC), and Wide-Screen Signalling (WSS) data used for PALplus transmissions (line 23). The device also supports Closed Caption acquisition and decoding. The TVT provides an integrated general-purpose, fully 8051-compatible microcontroller with television-specific hardware features. The microcontroller has been enhanced to provide powerful features such as memory banking, data pointer, additional interrupts, shared memory access etc. High performance 8-bit microcontroller, 8051 instruction set compatible 81 MHz system clock, two machine cycles per instruction On-chip debug support (OCDS) Up to 512 kByte in system program Flash 256 byte on-chip program RAM 128 byte on-chip extended stack RAM
4-level, 24-input interrupt controller Patch module for 16 ROM locations Two 16-bit reloadable timers Capture compare timer for infrared decoding Watchdog timer Uart Real time clock PWM units (2 channels 14-bit, 6 channels 8-bit) 8-bit ADC (4 channels) I2C bus master/slave interface Up to 32 programmable I/O ports
5.5 OSD and Teletext Features
The on-chip display unit for displaying Level 1.5 Teletext data can also be used for customer-defined onscreen displays. The TVT has an internal XRAM of 32 KB and a BOOT ROM of 4 KB. For operation the code is fetched from a 16bit FLASH, which can be addressed up to 1 MByte. In combination with dedicated hardware, the slicer stores TTX data in a VBI buffer of 1 KB. The microcontroller firmware performs all the acquisition tasks (hamming and parity checks, page search, and evaluation of header control bits) once per field. Additionally, the firmware can provide high-end Teletext features like Packet-26 handling, FLOF/TOP and list-pages. The interface-to-user software is optimized for minimal overhead.
5.6 Port Allocation
6. DRX 3961A
6.1 General Desription
The DSP-based Analog TV IF Demodulator DRX 396xA performs the entire multistandard Quasi Split Sound (QSS) TV IF processing, AGC, video demodulation, and generation of the sound IF (SIF), requiring only one SAW filter. The IC is designed for applications in TV sets, VCRs, PC cards, and TV tuners. The alignment-free DRX 396xA does not need special external components. All control functions and status registers are accessible via I2C bus interface.
6.2 Features
Multistandard QSS IF processing with a single SAW Highly reduced amount of external components (no tank circuit, no potentiometers, no SAW switching)
Programmable IF frequency (38.9 MHz, 45.75 MHz, 32.9 MHz, 58.75 MHz, 36.125 MHz etc.) Digital IF processing for the following standards: B/G, D/K, I, L/L', and M/N Standard specific digital post filtering Standard specific digital video/audio splitting Standard specific digital picture carrier recovery: -Alignment-free -Quartz-stable and accurate -Stable frequency lock at 100% modulation and overmodulation up to 150% -Quartz-accurate AFC information Programmable standard specific digital group delay equalization Automatically frequency-adjusted Nyquist slope, therefore optimum picture and sound performance over complete lock in frequency range Standard-specific digital AGC and delayed tuner AGC with programmable tuner take-over point Fast AGC due to linear structure Adaptive back porch control, therefore fast positive modulation AGC No sound traps needed at video output SIF output with standard-dependent pre-filtering and amplitude-controlled output level Optimal sound SNR due to carrier recovery without quadrature distortions FM radio capability without external components and with standard TV tuner Prepared for digital TV (DVB-C, DVB-T, ATSC) I2C bus interface
7. SERIAL 64K I2C EEPROM M24C64WBN6
7.1 General Description
M24C64WBN6 is a 64 Kbit Electrically Erasable PROM. These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192x8 bits. It supports 400kHz Protocol I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The M24C64WBN6 is available in the standard 8-pin (Vcc, WC, SDA (i2c data), SCL (i2c clock), Vss,E0,E1,E2). WC pin is critcal pin. If WP is high, writing is not possible to EEPROM. If WP is low, writing is possible to EEPROM.
7.2 Features
Two-Wire I2C Serial Interface Supports 400kHz Protocol Single Supply Voltage: 4.5 to 5.5V for M24Cxx 2.5 to 5.5V for M24Cxx-W 1.8 to 5.5V for M24Cxx-R Write Control Input BYTE and PAGE WRITE (up to 32 Bytes)
RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40-Year Data Retention
7.3 Absolute Maximum Ratings
7.4 Pinning
8. CLASS AB STEREO HEADPHONE DRIVER TDA1308
8.1. General Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications. It gets its input from two analog audio outputs (DACA_L and DACA_R) of MSP 34x0G. The gain of the output is adjustable by the feedback resistor between the inputs and outputs.
8.2 Features
Wide temperature range No switch ON/OFF clicks Excellent power supply ripple rejection Low power consumption Short-circuit resistant High performance High signal-to-noise ratio
High slew rate Low distortion Large output voltage swing. Power supply maximum 60 mW to 32 (THD<0.1%) 5V single supply SNR 110 dB Power supply ripple rejection Typically 3 mA supply current at no load
8.3. Pinning
9. SAW FILTER X6966M
9.1 Features:
- IF filter for digital cable TV - Plastic package SIP5K
9.2 Pin configuration:
1 2 3 4 5 Input Input - ground Chip carrier - ground Output Output
9.3 Frequency response:
10. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM
LM1117 LM1086 MP1593 FDC642P SIL9011 24LC02 PA672T M74HC4052 Max809 24LC21
10.1. LM1117
10.1.1. General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor's industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability.
10.1.2. Features
Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions Space Saving SOT-223 Package Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0.2% (Max) Load Regulation 0.4% (Max) Temperature Range LM1117 0°C to 125°C LM1117I -40°C to 125°C
10.1.3. Applications
2.85V Model for SCSI-2 Active Termination Post Regulator for Switching DC/DC Converter High Efficiency Linear Regulators 15 32" TFT TV Service Manual 10/01/2005 Battery Charger Battery Powered Instrumentation
10.1.4. Absolute Maximum Ratings
10.1.5. Pinning
10.2. LM1086
10.2.1. General Description
The LM1086 is a low dropout three terminal regulator with 1.5A output current capability. The output voltage is adjustable with the use of a resistor divider. Dropout is guaranteed at a maximum of 500 mV at maximum output current. It's low dropout voltage and fast transient response make it ideal for low voltage microprocessor applications. Internal current and thermal limiting provides protection against any overload condition that would create excessive junction temperature.
10.2.2. Features
Low Dropout Voltage 500mV at 1.5A Output Current Fast Transient Response 0.015% Line Regulation 0.1% Load Regulation Current Limiting and Thermal Protecion. Adjustable or Fixed Output Voltage(1.8, 2.5, 2.85, 3.0, 3.3, 3.45, 5.0V) Surface Mount Package SOT-223 & TO-263 (D2 Package) 100% Thermal Limit Burn-in
10.2.3. Applications
Battery Charger Adjustable Power Supplies Constant Current Regulators Portable Instrumentation High Efficiency Linear Power Supplies
High Efficiency "Green" Computer Systems SMPS Post-Regulator Power PC Supplies Powering VGA & Sound Card
10.2.4. Absolute Maximum Ratings
10.2.5. Pinning
10.3. MP1593
10.3.1. General Description
The MP1593 is a step-down regulator with an internal Power MOSFET. It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. Adjustable soft-start reduces the stress on the input source at turnon. In shutdown mode the regulator draws 20µA of supply current. The MP1593 requires a minimum number of readily available external components to complete a 3A step down DC to DC converter solution.
10.3.2. Features
3A Output Current Programmable Soft-Start 100m Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 95% Efficiency 20µA Shutdown Mode Fixed 385KHz Frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 4.75 to 28V Operating Input Range Output Adjustable from 1.22V Under Voltage Lockout Available in 8-Pin SOIC Package
10.3.3. Applications
Distributed Power Systems Battery Chargers Pre-Regulator for Linear Regulators Flat Panel TVs Set-Top Boxes Cigarette Lighter Powered Devices DVD/PVR Devices
10.3.4. Absolute Maximum Ratings
10.3.5. Electrical Characteristics
10.3.6. Pinning
Pin1:BS High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET switch. Connect a 10nF or greater capacitor from SW to BS to power the high side switch. Pin2:IN Power Input. IN supplies the power to the IC, as well as the step-down converter switches. Drive IN with a 4.75V to 28V power source. Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC. Pin3:SW Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to power the high-side switch. Pin4:GND Ground. Pin5:FB Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a resistive voltage divider from the output voltage. The feedback threshold is 1.222V. Pin6:COMP Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required. Pin7:EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive EN low to turn it off. An Under Voltage Lockout (UVLO) function can be implemented by the addition of a resistor divider from VIN to GND. For complete low current shutdown its needs to be less than 0.7V. For automatic startup, leave EN unconnected. Pin8:SS
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1µF capacitor sets the soft-start period to 10ms. To disable the soft-start feature, leave SS unconnected.
10.4. FDC642P
10.4.1. General Description
This p-channel 2.5V specified MOSFET is produced using Fairchild's advanced PowerTrench process that has been especially tailored to minimize on state resistance and yet maintain low gate charge for superior switching performance.
10.4.2 . Features
10.4.3. Absolute Maximum Ratings
10.4.4. Pinning
10.5. SIL9011
The Sil 9011 is a third generation HDMI receiver compatible with the HDMI 1.1 specification. Backwards compatibility with DVI 1.0 allows HDMI systems to connect to existing DVI 1.0 hosts over a single cable. The Sil 9011 is capable of receiving and outputting 2 to 8 channels of digital audio of up to 192kHz. An industry-standard I2S port allows direct connection to low-cost audio DACs. An S/PDIF port supports up to 96kHz audio. Silicon Image's HDMI receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores pass all HDMI compliance tests.
10.5.1 Features
HDMI 1.1, HDCP 1.1 and DVI 1.0 compliant receiver Integrated PanelLink core supports: DTV resolutions (480i/576i/480p/576p/720p/1080i) PC resolutions (VGA, SVGA, XGA, SXGA, UXGA) up to 165MHz. Digital video interface supports video processors: 24-bit and 48-bit RGB/ YCbCr 4:4:4 16/20/24-bit YCbCr 4:2:2 8/10/12-bit YCbCr 4:2:2 (ITU BT.656) S/PDIF output supports bothIEC 60958 and IEC 67937 for PCM, Dolby Digital, DTS digital or any S/PDIF type audio transmission (32-96kHz Fs) Four Programmable I2S outputs for connection to low-cost audio DACs. Sample rates up to 192kHz Auto audio error detection with programmable soft mute. Integrated HDCP decryption engine for receiving protected audio and video content Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing
10.6. 24LC02
10.6.1. General Description
24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.8V, with standby and active currents of only 1µA and 1mA, respectively. The 24XX02 also has a page write capability for up to 8 bytes of data.
10.6.2 Features
Single supply with operation down to 1.8V Low-power CMOS technology -1mA active current typical -1µA standby current typical (I-temp)
Organized as 1 block of 256 bytes (1 x 256 x 8) 2-wire serial interface bus, I2CTM compatible Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounce 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility Self-timed write cycle (including auto-erase) Page write buffer for up to 8 bytes 2ms typical write cycle time for page write Hardware write-protect for entire memory Can be operated as a serial ROM Factory programming (QTP) available ESD protection > 4,000V 1,000,000 erase/write cycles Data retention > 200 years 8-lead PDIP, SOIC, TSSOP and MSOP packages 5-lead SOT-23 package Pb-free finish available Available for extended temperature ranges: -Industrial (I): -40°C to +85°C -Automotive (E): -40°C to +125°C
10.6.3 Pinning
10.7. PA672T
10.7.1. General Description
N-channel Mos-Fet array for switching.The µPA672T is a super-mini-mold device provided with two MOS FET elements. It achieves high-density mounting and saves mounting costs.
10.7.2. Features
Two MOS FET circuits in package the same size as SC-70 Automatic mounting supported
10.7.3 Absolute Maximum Ratings
10.7.4 Pinning
10.8. M74HC4052
10.8.1. General Description
The M74HC4052 is a dual four-channel analog MULTIPLEXER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology and it is pin to pin compatible with the equivalent metal gate CMOS4000B series. It contains 8 bidirectional and digitally controlled analog switches.
10.8.2. Features
LOW POWER DISSIPATION: ICC = 4mA(MAX.) at TA=25°C LOGIC LEVEL TRANSLATION TO ENABLE 5V LOGIC SIGNAL TO COMMUNICATE WITH ±5V ANALOG SIGNAL LOW "ON" RESISTANCE:
70W TYP. (VCC - VEE = 4.5V) 50W TYP. (VCC - VEE = 9V) WIDE ANALOG INPUT VOLTAGE RANGE: ±6V FAST SWITCHING: tpd = 15ns (TYP.) at TA = 25 °C LOW CROSSTALK BETWEEN SWITCHES HIGH ON/OFF OUTPUT VOLTAGE RATIO WIDE OPERATING SUPPLY VOLTAGE RANGE (VCC - VEE) = 2V TO 12V LOW SINE WAVE DISTORTION: 0.02% at VCC - VEE = 9V HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4052
10.8.3 Absolute Maximum Ratings
10.8.4 Pinning
VEE supply pin is provided for analog input signals. It has an inhibit (INH) input terminal to disable all the switches when high. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND. A and B control inputs select one channel out of four in each section. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
10.9. Max809
10.9.1. General Description
The MAX809 and MAX810 are cost effective system supervisor circuits designed to monitor VCC in digital systems and provide a reset signal to the host processor when necessary. No external components are required. The reset output is driven active within 10 _sec of VCC falling through the reset voltage threshold. Reset is aintained active for a timeout period which is trimmed by the factory after VCC rises above the reset threshold. The MAX810 has an active high RESET output while the MAX809 has an active low RESET output. Both devices are available in SOT 23 and SC 70 packages.
10.9.2. Features
Precision VCC Monitor for 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps Four Guaranteed Minimum Power On Reset Pulse Width Available (1 ms, 20 ms, 100 ms, and 140 ms) RESET Output Guaranteed to VCC = 1.0 V. Low Supply Current Compatible with Hot Plug Applications VCC Transient Immunity No External Components Wide Operating Temperature: 40°C to 105°C Pb Free Packages are Available
10.9.3 Absolute Maximum Ratings
10.9.4 Pinning
10.10. 24LC21
10.10.1. General Description
The 24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK.
10.10.2. Features
1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION 2.5V to 5.5V SINGLE SUPPLY VOLTAGE 400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES
10.10.3 Absolute Maximum Ratings
10.10.4 Pinning
11.SERVICE MENU SETTINGS
In order to reach service menu, First Press "MENU" Then press the remote control code, which is "4725"
11.1. Video Setup
Panel Select <..................................> CHI MEI 16/9 26 inch LG 16/9 26 inch SAMSUNG 16/9 26 inch Picture Mute <.....> If "Yes" selected, "Picture mute" feature is active. Blue Screen <.....> If "Yes" selected, "Blue Background" item is seen in "Feature" menu. YC Delay <...........> Tuner PAL <.....> Value between -8 to+7 Ext PAL <.....> Value between -8 to+7 SECAM <.....> Value between -8 to+7 NTSC <.....> Value between -8 to+7 AGC (dB) <.....> Value between 0 to+8
11.2. AudioSetup
Equalizer <.....> If "Yes" selected, "Equalizer" item is seen in "Sound" menu.
BBE SRS WOW Virtual Dolby Surround <.....> If "Yes" selected, Virtual Dolby Surround feature is seen in "Sound" menu with selected Virtual Dolby Text. Virtual Dolby Text The selected item is seen as Virtual Dolby Srround Text. 3DS Virtual Dolby 3D Panorama AVL <.....> If "Yes" selected, "AVL" item is seen in "Sound" menu. Carrier Mute <.....> If "Yes" selected, "Carrier mute" feature is active. Audio Delay Offset Prescale FM Presc. AVL On <.......> Value between 0 to +127 AM Presc. AVL On <.......> Value between 0 to +127 NICAM Presc. AVL On <.......> Value between 0 to +127 I2S Presc. AVL On <.......> Value between 0 to +127 SCART Presc. AVL On <.......> Value between 0 to +127 FM Presc. AVL Off <.......> Value between 0 to +127 AM Presc. AVL Off <.......> Value between 0 to +127 NICAM Presc. AVL Off <.......> Value between 0 to +127 I2S Presc. AVL Off <.......> Value between 0 to +127 SCART Presc. AVL Off <.......> Value between 0 to +127 Dynamic Bass <.....> If "Yes" selected, "Dynamic Bass" item is seen in "Sound" menu. Subwoofer <.....> If "Yes" selected, "Subwoofer" item is seen in "Sound" menu.
11.3. Options 1
VCTP Version <.......> Basic+ Basic Double Digit <.....> If "Yes" selected, "Double Digit" button is active for channel selection. TEA6415C Available <.....> If "Yes" selected, video switch IC is active on hardware. TEA642X Available<.....> If "Yes" selected, audio switch IC is active on hardware. Power-Up Mode <.......> StandBy If selected, TV opens in stand by mode. L.State If selected, TV opens in Last State mode. TV Open Mode <.......> Source 1st TV Last TV
Select Languages <.......> "Yes" selected languages are seen as option under the "Language" item in "Feature" menu Language Set 1 o German <.......> o French <.......> o Spanish <.......> o Italian <.......> o Danish <.......> o Finnish <.......> o Swedish <.......> Language Set 2 o Greek <.......> o Norwegian <.......> o Dutch <.......> o Portuguse <.......> o Polish <.......> o Turkish <.......> o Russian <.......> o Czech <.......> Language Set 3 o Hungarian <.......> o Slovak <.......> o Slovenian <.......> o Romanian <.......> o Bulgarian <.......> o Croatian <.......> o Serbian <.......> o Hebrew <.......> First APS <.......> If "Yes" selected, first time TV opens by asking APS. APS Volume <.......> value between 0 to+63 Burn In Mode <.......> If "Yes" selected, TV opens with Burn-In mode. This mode is used in manufacturing. APS Test HDMI WP <.......> If "Yes" selected, HDMI EDID ROM is write protected.
11.4. Options 2
Autostore <.......> If "Yes" selected, Channel is automatically stored. Led Type <.............................> 1 Led 1 Colour 1 Led 2 Colours 2 Led 2 Colours PC PIP <.......> PC Stand By <.......>
11.5. Service Scan/Tuning Setup
Search for L/L' <.......> Pref. Search Standard <...........> BG, DK, I L/L' M Station Ident <.......> ATS Delay Time (ms) <.......> Value between 20 to 250 Color Killer Threshold <.......> Value between 0 to +255 Tuner Options <.......> Control Byte <.......> Value between 0 to +255 Low-Mid Low Byte <.......> Value between 0 to +255 Low-Mid High Byte <.......> Value between 0 to +255 Mid-High Low Byte <.......> Value between 0 to +255 Mid-High High Byte <.......> Value between 0 to +255 BSW1 <.......> Value between 0 to +255 BSW2 <.......> Value between 0 to +255 BSW3 <.......> Value between 0 to +255
11.6. External Source Settings
DTV <.......> DVD <.......> Ext 2 S-Video <.......> Ext 3 <.......> Ext 3 S-Video <.......> FAV <.......> BAV <.......> S-Video <.......> HDMI 1 <.......> HDMI 2 <.......> YPbPr <.......> PC <.......>
11.7. Picture Mode
Sources <.......> Tuner CVBS RGB SVHS HDMI YPbPr PC PIP Picture Mode <.......> Dynamic Natural Cinema
Colour Temp <.......> Cool Normal Warm Contrast <.......> Value between 0 to +63 Brightness <.......> Value between 0 to +63 Sharpness <.......> Value between 0 to +15 Colour <.......> Value between 0 to +63 Backlight <.......> Value between 0 to +255 R <.......> Value between -63 to +63 G <.......> Value between -63 to +63 B <.......> Value between -63 to +63
11.8. Reset TV-Set
Initialize NVM from ROM Press green button to reset the NVM from ROM
12. SOFTWARE UPDATE DESCRIPTION
12.1 Analog Software Update Via I2C
Step.1 Short the second and third pins of PL_406. Power ON and keep shorting the pins 3-5 seconds. Step.2 Then connect the I2C update tool to parallel port of PC. Step.3 Connect the other end of the tool to PL_406. Step.4 Run Cosima_VCTP Visual I2C software update program. Step.5 When you click to box near "0" at "Bootloader Version" item, you will see "40". If you couldn't see "40" or a "No Acknowledge from Slave!" is appeared, There may be a connection problem sourced from PC port, or update tool. Or you may forget to power ON. Step.6 After "40" is seen, Click "Erase Flash" Step.7 Select the bin. file from near the "Load Bin" Step.8 Click "Load Bin" and load the required bin. file. Step.9 Unpick the I2C cable from Chasis
Step.10 Power off and on again TV set to produce hard reset. Step.11 Initialize the NVM from "Reset TV-set" item from service menu
12.2 Analog Software Update Via UART
Step.1 Connect the serial cable from PC Com port to PL104 connector on 17PRG01 module card. Step.2 Connect the programming cable from PL 102 connector on 17PRG01 module card to PL408 connector on TV chassis side. The arrow sign " " on the connector must see the PCB side of the chassis. If TV is seen from the back cover, arrow sign must see the TVs back cover Step.3 Run a RS232 terminal tool like Hyper Terminal. Step.4 Following settings of the terminal tool are necessary: Protocol: Xmodem Port: COMx Baud Rate: 115200 Data Bits: 8 Parity: none Stop Bits: 1 Com. Control: none Step.5 Load the bin file from "Browse" and Click "Send" Step.6 Power off and on again TV set to produce hard reset.
12.3. Software Update Procedure
SOFTWARE UPDATE PROCEDURE FOR 17MB22 CHASSIS : 12.3.1 Hardware connection 12.3.2 Digital Software Update 12.3.2.1 Software setup 12.3.2.2 Flashing Sequence 12.3.3 Analog Software Update 12.3.3.1 Software setup 12.3.3.2 Flashing Sequence
Software update to 17MB22 is possible using the UART protocol. PL408 connector shown in below figure is used to update the software.
Fig1: Position of the software update connector at the backside of TV
12.3.1 Hardware connection
17PRG01 module, which is also able to update software of 17MB24 and 17MB15 chassis, is used as a level converter in order to regulate voltage levels. PL101 and PL102 connectors of module card are used to software update of DTV and ATV of 17MB22 chassis respectively (See Fig4). Data is sent from a PC using RS-232 standard via RS232 terminal tool such as Hyper Terminal, to module card. Cables used in the process are shown in figure 2 and figure 5. Cable in figure 2 must be plugged to PL101 connector for Digital software update and PL102 connector for Analog software update on module card side and PL408 connector on TV chassis side. The arrow sign " " on the connector must see the PCB side of the chassis. If TV is seen from the back cover, arrow sign must see the TVs back cover (See also Fig3).
Fig2: Cable from programming module board to chassis
Fig3: Programming Cable Plugging Direction
PL104 on the module board must be connected to PC COM port by the cable shown in Fig5.
Fig4: 17PRG01 Module Board
Fig5: Cable from module board to PC COM port
12.3.2 Digital Software Update
12.3.2.1 Software setup
Data transfer from PC to 17MB22 is established by a RS232 terminal tool like Hyper Terminal. Following settings of the terminal tool are necessary:
Protocol: 1K Xmodem Port: COMx Baud Rate: 115200 Data Bits: 8 Parity: none Stop Bits: 1 Com. Control: none
12.3.2.2 Flashing Sequence
· Switch TV on and wait at stand by mode. Then connect UART module as described above. Open terminal emulation on PC (e.g. "Hyper Terminal") · Check the settings given above and correct if necessary. Select the TV software from the browsing PC (e.g. newrelease.img). Select the 1K Xmodem protocol. "Send" button Before flashing the DTV, switch on TV and exit from stand by mode in order to check whether there is any connection or setting problem. Terminal window displays the message shown in figure 6, if all settings and connections are correct.
Fig6: Checking the connection
Fig7: Sending procedure · After preparing the sending data, Press "Send" button and immediately exit from stand by mode. · The "Terminal Window" of the PC displays the data transfer as shown in Fig8.
Fig8: Data transfer
Fig9: Data transfer · At the end of the data transfer TV erases the flash and writes the new software to flash. Terminal window displays this process as shown in figure 9. · Power off and on again TV set to produce hard reset.
12.3.2 Analog Software Update
12.3.2.1 Software setup
Data transfer from PC to 17MB22 is established by a RS232 terminal tool like Hyper Terminal. Following settings of the terminal tool are necessary: Protocol: Xmodem Port: COMx Baud Rate: 115200 Data Bits: 8 Parity: none Stop Bits: 1 Com. Control: none
12.3.2.2 Flashing Sequence
· Switch TV off and connect UART module as described above. Open terminal emulation on PC (e.g. "Hyper Terminal")
· Check the settings and correct if necessary. Select the TV software from the "Send" button browsing PC (e.g. newrelease.bin). Select the Xmodem protocol. Prepare for sending data but do not yet press "Send" button.
Fig10: Sending procedure · Press "Send" button and immediately switch on TV chassis while pressing "Volume-" (Volume minus) button on the keyboard ("Volume"- must be pressed before switching on TV), and keep button pressed until TV starts to receiving data from PC. · The "Terminal Window" of the PC displays the data transfer (Fig11). When TV starts receiving data from the PC "Volume-" button may be released. It needs about 2 minutes to upload the whole software. At the end "Flash Programming Complete" will be displayed at the HyperTerminal window (Fig12).
Fig11: Data transfer
Fig12: Flash Programming Complete (End of operation) · Power off and on again TV set to produce hard reset. *NOTE: To proceed with this procedure software versions must be compatable. Otherwise software will not overwitten to avoid uncontrolled flashing. *17MB22_STD_0.0.31 or newer releases(0.0.32, 0.0.33 ...) cannot be flashed via HyperTerminal to TV sets which has 17MB22_STD_0.0.30 or older versions (software is not compitable).
13. TROUBLESHOOTING GUIDE
NO DEFECT APPEARANCE
1 When the TV is operated for the first time, STANDBY LED lights but the TV switches on Standby LED does not ligh ever.
DEFECT IDENTIFICATION AND SOLUTIONS
IC403 E2Epron is plugged empty, after the programming process of the first values has finished, TV will switch on by itself. Are there 3.3V on IC001's bottomright pin? If no, 3.3V are not drawing in, there can be an error in PW board; underneath VCTP, SMD material can be disintegrated. Are there 1.8V in IC001 solder area? If no,1.8V are not drawing in; IC001 can be defective or underneath VCTP, SMD material can be disintegrated. Are there 3.3V on IC406's top left pin? If no, IC406 can be defective. Are there 1.8V on S719? If no, IC001 can be defective. Are there 3.3V on S700? If no, there can be an error in PW board. Are there 5V on pin PL409 5? If no, there can be a problem in PW board or SMD material can be disintegrated. Are there 24V on the pin, which is indicated as number 1, of PL001 socket. If no, there can be a problem in PW board. L603 can be cold soldering. PL406 can be cold soldering. Is there display voltage in Q005's top points? (for LG 12V, for other displays 5V). If no; L007 for LG, L006 for other displays can be unplugged. Q005 can be defective. Are there 5V in 7th pin of tuner? If no, IC007 and surrounding equipment can be defective, L101 can be defective. Are there 33V in 9th pin of tuner? If no, there can be a problem in PW board. Are there 3.3V in L104 inductor? If no, there can be a problem in PW board. Are there 12V in pin 8 of the PL003 socket? If no, there can be a problem in PW board. Q410 and Q411 can be defective. Are there 10V in the mid pin of IC004? If no, IC004 can be defective. Are there 8V on L200? If no, there can be a problem in D004, D005, D006 or there could be cold soldering. Are there 1.8V on S719? If no, IC001 can be defective. Are there 3.3V on S700? If no, PW board can be defective. IC702 can be defective. S705 and S706 can be cold soldering. IC905 or surronding equipment can be defective. IC 905 supply voltage may not be drawing in 10V.
2
3 Standby LED does not light and/or IR receiver does not work. Picture is available but there is no sound. 4 Sound is available but there is no picture. 5
Neither picture nor sound is available.
6
7
TV switches on but constantly switches to HDMI input. While trying to tune a channel, always switches to C05.
8
No sound from PC or YPbPr.
9
TFT backlight level cannot be controlled, it's level is fixed. Q002, Q003, 1006 or surrounding eqipment can be defective or SMD material can be disintegrated. When the TV is switched on; there should be displayed voltages as following: 5V on C074, 3.3V on PL004 pin 4, 8V on IC004 mid pin and Q005 top points. If one is missing, TV may shut down after a short while after it is switched on.
TV switches on; however, after a short break, it 10 switches off again by itself.
14. BLOCK DIAGRAMS
14.1. General Block Diagram
14.2. Power Management
14.3. DRX (IF Demodulator) Block Diagram
14.4. VCTP
14.4.1. General Block Diagram
14.4.2. MSP Block Diagram
14.4.3
Video Processor of VCT 6wxyP Block Diagram
14.5. TDM1300 HARDWARE DESCRIPTION (IDTV)
Item
PCB MPEG decoder FLASH DDRAM Audio DAC Video AMP COFDM Demodulator Tuner VCXO Buck Regulator 3.3V Regulator 1.8V Regulator 1.5V Regulator 74LVC16244 (x4) 74LVC245 74LVC00
4 layer EMMA2LL (NEC) 29LV160TE (Spansion, Eon) 2MB EDD1216AATA ( Elpida, Nanya) 16MB CS4335 (Crystal) FMS6145 (Fairchild) DRX3973D (Micronas) DTT7103 (Thomson) DTOS401TH17XA (Samsung) PI6CX100-27 (Pericom) MP1593 (MPS) NCP1117-3.3V (Onsemi) NCP1117-1.8V (Onsemi) NCP1117-1.5V (Onsemi) 16 bit buffer with OE (Various) Octal Bus Transceiver (Various) NAND Gate (Various)
Description
14.5.1
IDTV Module Block Diagram
IF INPUT CON
I2C,UART,4 GPIO, IF AGC
ANALOG AV CON
POWER CON 5V BUCK
SAW Filter
VIDEO AMP
AUDIO DAC
3.3V 1.8V 1.5V LIN.REGULATOR
COFDM DEMOD
VCXO
EMMA2LL
CPU + MPEG DECODER
S/PDIF CON
16 MB DDRAM 2 MB FLASH
PROGRAM CON (UART) JTAG CON
NEC
DIGITAL AV CON BUFFERS & GATES
PCMCIA CON
15. CONNECTORS
15.1.
Pin 1 2 3 4
POWER Connector
Description +12/24V +12/24V GND GND
15.2.
Pin 1 2 3 4 5 6 7 8 9 10
EMMA2LL JTAG Connector
Description
GND JTCLK 3.3V JTDO NC JTMS NC JTRST GND JTDI
15.3.
Pin 1 2 3 4 5 6 7 8 9 10 11 12
ANALOG AV Connector
Description Pin 13 14 15 16 17 18 19 20 21 22 23 24 Description GND GND DVB_R_AUDIO DVB_L_AUDIO GND DVB_IN_CVBS GND DVB_IN_B / DVB_IN_C GND DVB_IN_G / DVB_IN_Y GND DVB_IN_R
DVB_SCL DVB_SDA GND GND IRQ DVB_RX DVB_TX GPIO4 GPIO3 GPIO2 GPIO1 IF_AGC_DVB
15.4.
Pin 1 2 3
IF Connector
Description IF + IF GND
15.5.
Pin 1 2 3
PROGRAMMING Connector
Description TXD GND RXD
15.6.
Pin 1 2
S/PDIF Connector
Description S/PDIF GND
15.7.
Pin 1 2 3 4 5 6 7 8 9 10
DIGITAL AV Connector
Pin 11 12 13 14 15 16 17 18 19 20 Description GND Digital Video Pixel Clock Digital Video Y/Cb/Cr DATA7 Digital Video Y/Cb/Cr DATA6 Digital Video Y/Cb/Cr DATA5 Digital Video Y/Cb/Cr DATA4 Digital Video Y/Cb/Cr DATA3 Digital Video Y/Cb/Cr DATA2 Digital Video Y/Cb/Cr DATA1 Digital Video Y/Cb/Cr DATA0
Description I2S Word Select I2S Serial Clock I2S Serial Data GND GND GND Internal Vertical SYNC Internal Horizontal SYNC GND GND
15.8.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
PCMCIA Connector
Signal GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# IREQ# VCC VPP MIVAL MCLKI A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND Description Ground Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Card Enable Address bit 10 Output Enable Address bit 11 Address bit 9 Address bit 8 Address bit 13 Address bit 14 Write Enable Interrupt Request Supply Voltage Programming and Peripheral Supply MPEG Data In Valid MPEG Data Clock Input Address bit 12 Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit 1 Address bit 0 Data bit 0 Data bit 1 Data bit 2 I/O Port Is 16-bit Ground Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal GND CD1# MDO3 MDO4 MDO5 MDO6 MDO7 CE2# VS1# IORD# IOWR# MISTRT MDI0 MDI1 MDI2 MDI3 VCC VPP MDI4 MDI5 MDI6 MDI7 MCLKO RESET WAIT# INPACK# REG# MOVAL MOSTRT MDO0 MDO1 MDO2 CD2# GND Description Ground Card Detect MPEG Data Out 3 MPEG Data Out 4 MPEG Data Out 5 MPEG Data Out 6 MPEG Data Out 7 Card Enable Voltage Sense 1 I/O Read I/O Write MPEG Data In Start MPEG Data In 0 MPEG Data In 1 MPEG Data In 2 MPEG Data In 3 Supply Voltage Programming and Peripheral Supply MPEG Data In 4 MPEG Data In 5 MPEG Data In 6 MPEG Data In 7 MPEG Data Clock Output Card Reset Extend bus cycle Input Port Acknowledge Register select & I/O Enable MPEG Data Out Valid MPEG Data Out Start MPEG Data Out 0 MPEG Data Out 1 MPEG Data Out 2 Card Detect Ground
16. CONCEPT ICs
16.1. PD61115
16.1.1 Description
The PD61115 device is a member of the second generation of multimedia processors based on NEC's Enhanced MultiMedia Architecture (EMMArchitecture). These devices provide nearly all the functionality required to realise a high performance and cost-effective digital set-top box or integrated digital TV.
16.1.2 Features
MPEG1 and MPEG2-TS/PS compliant High performance MIPS32TM 4KcTM main CPU core High performance MIPS32TM 4KmTM sub-CPU core Integrated DVB descrambling with family options for Irdeto and Multi2 36 PID filters, 32 section filters Video Outputs: 4 DACs for RGB, Component video, S-video and composite output with support for PAL, NTSC and SECAM 4 graphics planes Audio Output: 2-channel PCM and SPDIF Peripherals support two fast UARTs with 16byte FIFOs I2C interface infrared receiver three wire clocked serial interface System timers, RTC and Watchdog timer Motorola/Intel Bus.
16.2. DRX 3973D Fourth-Generation COFDM Demodulators
16.2.1 Introduction
The DRX 3973D and the DRX 3977D are fourth-generation COFDM demodulators that offer today's highest level of front-end integration resulting in ultimate DVB-T digital reception, compliant to ETS 300 744, DTG D-Book, EICTA E-Book, and Nordig Unified v1.0.2 . The DRX 3973/77D applies cutting-edge digital filtering techniques in combination with a highperformance A/D-converter and PLL configuration, resulting in superior performance figures in the presence of digitaland analog adjacent channels. Progressive channel estimator algorithms provide exceptional performance in multipath- and dynamicecho conditions an especially important feature for single-frequency networks and indoor reception. The state-of-the-art impulsive noise cruncher suppresses interferences originating from sources such as cars, electrical motors, and household appliances.
16.2.2 Features
Highest level of front-end integration and flexibility: Integrated PGA (programmable gain amplifier) 30 dB Single 8 MHz SAW filter operation 2 AGC control signals available for RF and IF amplifier control Flexible clock reference options Re-use of 4 MHz tuner clock reference Pre-SAW sense input for optimal RF AGC setting and RF-level measurement Excellent digital reception performance: Superior digital and analog adjacent channel performance (> 40dB for QEF) Impulsive noise cruncher Multipath and dynamic echoes The input IF frequency ranging up to 44 MHz ensures upward compatibility for new tuner topologies Integrated microprocessor to perform autonomous detection and operation of all possible DVB-T modes, without interaction with the host processor Fully automatic and fast signal acquisition: UHF and VHF band-scan in <20 seconds Meets all international DVB-T receiver specifications: Nordig Unified, DTG, EICTA Comfortable software drivers for integration of tuner and COFDM demodulator Secondary serial interface for tuner control 5 V tolerant AGC and secondary serial protocol outputs 2 general purpose I/O pins (GPIO) Configurable parallel or serial MPEG-TS output PMQFP64-2 package: footprint 10 10 mm (DRX 3973D) PQFN48-1 package: small footprint 7 7 mm (DRX 3977D) IEEE 1149.1 boundary scan
16.2.3 Applications
IDTV / hybrid TV Set-top boxes PVR / DVDR Network interface modules (NIM) PC-TV applications
16.3. PI6CX100-27 27 MHz 3.3V VCXO for Set-Top Box Applications
16.3.1 Features
· 3.3V operating voltage · Uses an inexpensive external crystal · On-chip VCXO with pull range of 240ppm · VCXO tuning voltage from 0 to 3.3V · 10mA output drive at CMOS levels · Available in SOIC package
16.3.2 Description
The PI6CX100-27 is a low-cost, high-performance 3.3V VCXO, designed to replace expensive VCXO modules. The on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3V input voltage to cause clocks to vary by ±120ppm. This device uses an inexpensive external pullable crystal at 27 MHz to produce the same output frequency.The PI6CX100-27 is designed for Set-Top Box applications.
16.4. 74V1G08 SINGLE 2-INPUT AND GATE
HIGHSPEED: tPD = 4.3 ns (TYP.) atVCC= 5V LOWPOWERDISSIPATION: ICC =1 A (MAX.) at TA =25 oC HIGHNOISEIMMUNITY: VNIH=VNIL =28%VCC (MIN.) POWERDOWN PROTECTIONON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA(MIN) BALANCEDPROPAGATIONDELAYS: tPLH tPHL OPERATINGVOLTAGERANGE: VCC (OPR)= 2V to 5.5V IMPROVEDLATCH-UP IMMUNITY
16.4.1 Description
The 74V1G08 is an advanced high-speed CMOS SINGLE 2-INPUT AND GATE fabricated with submicron silicon gate and double-layer metal wiring C2MOS technology.
16.5. FMS6145 Low Cost Five Channel 4th Order Standard Definition Video Filter Driver
16.5.1 Features
Five fourth-order 8MHz (SD) filters Transparent input clamping Dual video load drive (2Vpp, 75 ) AC or DC-coupled inputs AC or DC-coupled outputs DC-coupled outputs eliminate AC-coupling capacitors 5V only Lead (Pb) Free TSSOP-14 package
16.5.2 Applications
Cable set top boxes Satellite set top boxes DVD players HDTV Personal video recorders (PVR) Video on demand (VOD)
16.5.3 Description
The FMS6145 Low Cost Video Filter (LCVF) is intended to replace passive LC filters and drivers with a low-cost integrated device. Five 4th order filters provide improved image Quality compared to typical 2nd or 3rd order passive solutions. The FMS6145 may be directly driven by a DC-coupled DAC output or an AC-coupled signal. Internal diode clamps and bias circuitry may be used if AC-coupled inputs are required. The outputs can drive AC or DC-coupled single (150 ) or dual(75 ) loads. DC-coupling the outputs removes the need for output coupling capacitors. The input DC levels will be offset approximately +280mV at the output.
16.6. MP1593 3A, 28V Step-Down Converter
16.6.1 Description
The MP1593 is a step-down regulator with an internal Power MOSFET. It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown mode the regulator draws 20µA of supply current. The MP1593 requires a minimum number of readily available external components to complete a 3A step down DC to DC converter solution.
16.6.2 Features
3A Output Current Programmable Soft-Start 100m Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 95% Efficiency 20µA Shutdown Mode Fixed 385KHz Frequency
Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 4.75 to 28V Operating Input Range Output Adjustable from 1.22Vs Under Voltage Lockout Available in 8-Pin SOIC Package
16.6.3 Applications
Distributed Power Systems Battery Chargers Pre-Regulator for Linear Regulators Flat Panel TVs Set-Top Boxes Cigarette Lighter Powered Devices DVD/PVR Devices
THE UPDATED PARTS LIST FOR THIS MODEL IS AVAILABLE ON ESTA
18. ASSEMBLY DRAWING
17
15 16 11 14 10
13 12
9
1
6
5 4 3
8
19
9 18
2
No. 0234
EXPLODED VIEW (26 INCH VERSION)
17
16
14 13 11 12
9
10
14 7
8
6
5
4 3
19
1 18
2
No. 0234
EXPLODED VIEW (32 INCH VERSION)
19. SCHEMATIC DIAGRAMS
L103 VCC_5V 10u 50V 47u C115 C116 L117 L112 VCC_12V C139 100n 25V 100u C140 10u 12V_IF 10u 330R_100MHZ_3A L114 100n 16V 5V_DRX 27p C123 27p C124 R138 1k2
3V3_DRX
3V3_DRX R108 6k2 R110 6k2 R111 6k2 R112 6k2
50V
SHEET 8 VGA_MUX_SW YPBPR_MUX_SW
PL100
DIGITAL IF CONNECTOR 12V_IF 12V_IF
L116 R139 3k3 PTC RES N.C. S100 C101
1UF 16V
X100 L108 VCC_3V3 10u L104 10u C114 C117 100n 10V 50V 47u 3V3_DRX C134
10u L102 VCC_5V 10u 100n 50V 47u 10V C110 C111 5V_TUNER
1
2
3
5V_TUNER
DRX_CLK
20.25MHz 1n 50V 16V C122 100n C125
AUDIO_MUX_SW SYNC_SW1
47k R128
R130
TU100
AGC 1 SHORT
10n 50V N.C. R102 5k1
DRX POWER SUPPLY SHEET3 VCTP PIN80 47k
44
43
42
XTALIN 41
40
39
100n 16V
SHEET3
38
37
36
35
34
PORT5
PORT3
SGND
DVDD_ADC
DVSS_ADC
C100
10n 25V
TU
2
R127 47k
1UF 16V
S101 S102
C118
100n 10V
R136 47R R132 470R
R135 47R R131 470R R129 47k L105
C135 S111 S112
C136
1
L106
AVSS_ADC AVDD_ADC ANATSTX ANATSTY AVDD_FE8 AVSS_FE8 AVSS_FE401 IFINX AVDD_FE40
TUNER_AGC 33 PORT1 32 PORT0 31 DVSS_CAP 30
SYNC_SW2 SW_ENABLE2 SHEET 3
AS
3 50V
39p R104 100R
5V_DRX
10u
2 3 4
C120 100n 16V
TECH2949PG40B
SCL
4
C102
SDA
5
39p
R105 100R 16V
S117 Z100 X6966M 1 IN1
AN_IF
16V 100n
6 7
NC
6
50V 1u C103 C104 R100 3k3 C107 100n 16V
IC100 DRX3960A
C129
100n 16V
5V_DRX
R125 150R R126 150R
5
DVSS 29
L110
33n 50V
C138
C137
C130
R103 5k1
R106 5k1 N.C.
50V 1n
50V 1n
ADR_SEL
XTALOUT
PORT4
PORT2
VREF
50V 1n
Q102 BF799
Q103 BF799
50V 1n
R118 6k2
R116 6k2
R117 6k2
3 V 3 V 3 5 3_ _D V _ DR RX D X R X
3V3_DRX
L111 R119 100R R120 100R
DVDD 28 DVDD_CAP 27 SCL 26 SDA 25 RESETQ 24 21 AVDD_DAC 22 AVSS_DAC
C127
C132
100n 16V
3V3_DRX
SCL_3V3_IC SDA_3V3_IC SHEET 3,5,6
R123 150R
C119 600R_100MHZ_200mA C141 L113 100n 16V
OUT1 4
8 9
33p 25V
5V_DRX
L101 5V_TUNER R124 150R 2 IN2 OUT2 5 GND S119 3
R140 5k1
VS
7
PTC RES S113
BLM21A601S IF_AGC
10 IFINY 13 AVSS_SYN 11 AVSS_FE402 12 AVDD_SYN
TEST_EN 23
25V 33p C128
3V3_DRX
R121 C131 100n 16V 1k
15 TEST0
16 TEST1
17 TEST2
NC/ADC
8 R101 4k7
AN_IF C108 100n 16V C109 5V_TUNER 47u 50V
19 REF_SW
14 SHIELD
18 CVBS
VST
9 S103 S118
R107 1k VCC_33V IF_AGC
20 SIF
100n 16V
Q101 BC848B C133
R122 470R RESET_IC SHEET3
S115
L107
S116
L100
1u
L109
IF2 10
C126 C121
IF1 11
5V_DRX
R137 47R
VCC_8V_VIDEO C142
100n 16V
3V3_DRX
100n 16V
R109 100R
QSS
5V_DRX
10u 16V Q100 BC848B R114 75R
SHEET 3
1k R113
IC101
SCL_DVB
TUNER_CVBS_IN
1
2Y1
VCC 16
5V_TUNER
R115 75R TUNER_CVBS_SW
SCL_5V_IC
SHEET3 S120 S121
SHEET 8
2
2Y0
S105
2Z 15
AGC_DVB IF_AGC
3
3Y1
1Z 14
SDA_DVB
S104
S109
4
3Z
1Y1 13
5
3Y0
1Y0 12
SDA_5V_IC
S110
6
E
S1 11
S106 S107 C113 100n 10V
5V_TUNER
R134 4k7
5V_TUNER
TUNER/DRX DEMODULATOR
SYNC_SW2
7
VEE
S2 10
S108 Q104 BC848B TV/DVB_SWITCH C112 100n 10V R133 1k S114
8
GND
S3 9
74HCT4053
AGC_TV
No. 0234
MAIN BOARD CIRCUIT - SHEET 1
VCC_5V_VIDEO
VCC_8V
R332 47R C208 50V 47u
VCC_8V
R333 47R C256 50V 47u R293 1k
R221
1k
C266 SC3_AUDIO_R_OUT R290 100R 22u 50V C267 SC1_AUDIO_R_OUT 22u 50V C268 VCTP_AOUT1L SC3_AUDIO_L_OUT R291 100R 22u 50V C269 SC1_ AUDIO_ L_OUT R326 75R R327 75R R328 75R 1k
C229 C250 100n 10V R259 18k R269 470R SC2_AUDIO_R_OUT R206 100R SHT3 22u 50V
TO SHT7
IR_DMP/DVD TO SHT3 L235
DMP_DVD_G
DMP_DVD_R
DMP_DVD_AUDIO_R_IN
R295
DMP/DVD_SWITCH
LINE_R_OUT
1n 50V
R218 1k
VCTP_AOUT2R
1n 50V
22u 50V
Q205 BC848B R273 150R
C223
C227
SHT3 R278 75R VCC_5V_VIDEO
VCTP_AOUT2L 150R R270 C231 SC2_AUDIO_L_OUT R207 100R 22u 50V BC858B Q202
SC2_CVBS_OUT
BC858B Q209
TO SHT3
R232 330R
L211
VCTP_AOUT1R
TO SHT7
C218
BC858B Q200 C219 C224 R233 330R C228 1n 50V L212 1n 50V
22u 50V
11
13
15
17
19
1
3
5
7
9
LINE_L_OUT TO SHT3 VOUT2 R267 470R R260 18k C249 100n 10V
10u
VCC_5V
BC858B Q207
DMP_DVD_B
BC858B Q201
BC858B Q208
DMP CON
22u 50V
10
12
TO SHT3
SW_UPDATE_EN
R325 75R
VOUT1
14
16
18
20
2
4
6
8
PL210
3V3_STBY
UART_RX
VCC_3V3
DMP_DVD_CVBS_IN
TO SHT7 SC3_AUDIO_R_IN SC3_AUDIO_L_IN
TO SHT3
TO SHT7
R271 150R 150R R268 BC858B Q203
R274 75R SC1_CVBS_OUT
SC3_AUDIO_R_OUT
SC3_AUDIO_L_OUT
R275 75R
SC3_SVHS_C
TV_LINK_3V3
DMP_DVD_AUDIO_L_IN
SC3_CVBS_IN
SC3_PIN8
S210
S209
IRQ
Q204 BC848B
UART_TX
BC858B Q206
R324 75R
R237 47R
SC2_FB
47R R253
C213
C220
TO SHT7 IDTV_AUDIO_R_IN IDTV_CVBS_IN IDTV_AUDIO_L_IN
R321 3k3
BSN20 Q214 Q212 BSN20 Q211 TO SHT1 SDA_DVB SCL_DVB
IDTV_R
IDTV_B
SC2_R/C ILE PARALEL
R238D209 15k
AGC_DVB
IF_AGC
TO SHT1
R228 330R
330R R219
C5V6
R243 5k6
1n 50V C201 1n 50V R200 330R C203 1n 50V C204 1n 50V L201
47R R254
R301 47R
D214
75R
L206
L210
1n 50V
1n 50V
C5V6
R329 75R
R322
C233 27p 50V R251 75R
R303 3k3
5V_STBY
R330 75R
R313 47R
C214
C221
3V3_STBY
D217
S200
C5V6
75R R323
1n 50V C225 100n 16V
IDTV_G
R331 75R
BSN20
D224
C265
100n 16V
R298 5k6
C5V6
PL207
21
23
15
13
11
20
22
19
18
17
16
R201 330R
24
14
10
9
7
5
3
8
6
L202
4
2
1
41 42 40
39 38
37 36
35 34
33 32
31 30
29 28
27 26
25 24
23 22 C5V6
12
C205 1n 50V
BSN20 R304 100R
SC3_SVHS_C
R302 15k
R309 4k7
L208
Q210
R314 47R
C235 27p 50V
PL203
IDTV_FFC_CON[ANALOG]
L221
L224
C200
C206 1n 50V
PL208
2 C254 1n 50V 4 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
1n 50V
L209 R256 47R 1 75R R252 C236 27p 50V
D218 16 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 R261 47R SC1_CVBS_IN TO SHT3 SHT7 [TO VIDEO SW] R285 330R
330R R203 R204 330R C207 50V 1n
L203 21 L204
20 19
18
1 L222
27p
47R C222
C257
C270
C273
15k R234
C277
D208
47R R239
C259
50V 1n
D207
D210
D213
R217 330R
R222 330R
R292 330R
C263
1n 50V
R306 47R
C5V6
C5V6
C5V6
R294 330R
R311 47R
C215
C5V6
C216 R231 47R
R244 47R
R248 47R
R286 330R
1n 50V
1n 50V
50V 1n
50V 1n
C226 100n 16V
C280
R229 75R
R230
R318
27p 50V
R319
D215
C5V6
D216
R235 47R
47R R240
R245 47R
5k6 R236
R249 47R
C5V6
C210
50V 1n
C253
R299 47R
D229
47R
C5V6
D230
C260
1n 50V
C264
1n 50V
D225
D226
C5V6
C5V6
D227
50V 1n C255
C5V6
1n 50V
C217
R300 47R
R307 47R
SC1_AUDIO_R_OUT
SC1_AUDIO_L_OUT
SC1_PIN8
SC1_AUDIO_R_IN
SC1_AUDIO_L_IN
SC1_CVBS_OUT
FAV_CVBS SVHS_Y PARALEL
BAV_CVBS_IN
SC1_G
SC1_B
SC1_FB
SC1_R
SC2_AUDIO_R_OUT
SC2_AUDIO_L_OUT
SC2_AUDIO_R_IN
SC2_AUDIO_L_IN
R255 75R
R312 47R
PL204
C239 27p 50V R265 47R
C5V6 D220 R276 47R
S201
TO SHT3
BAV99 D205 VCC_5V BAV99 D203 BAV99 D200
TO SHT3
1 2 3
C237 27p 50V
FAV_CVBS_IN
TO SHT3
NC3
NC2
NC1
VSS
5
ST24LC21 IC200
PL200
6 7 8
FAV VIDEO
L215 330R R272 L216 C241 1n 50V C243 R264 330R C246 C248 1n 50V 1n 50V 1n 50V FAV_AUDIO_R_IN
TO SHT7
4
4
3
2
1
C211
R202 75R
R205 75R
R208 75R
FAV SVHS/C SC2 RED ILE PARALEL
27p 50V
SC2_CVBS_OUT
TO SHT3 VCTP
SC2_CVBS_IN
SC2_G
SC2_B
SC2_R/C
R320 47R
C5V6
27p 50V
50V
75R
C202
C230 27p 50V
C232 27p 50V
C234 27p 50V
C274
75R R241
75R R246
75R R250
R297 75R
R305 75R
R310 75R
L205
L207
L223
L226
27p 50V
27p 50V
27p 50V
1n 50V
TO SHT3
BSN20
SC2_PIN8
SC3_CVBS_OUT
Q213
TO SHT7
C5V6 D228
R315 75R
C281
50V 47u
1 2 3
C209 27p 50V
R213 47R R214 47R R215 47R
R223 47R R224 47R R225 47R
PC_R PC_G
TO SHT7 YPBPR_AUDIO_R_IN YPBPR_AUDIO_L_IN FAV_AUDIO_L_IN TO SHT7 YPBPR_PR YPBPR_PB YPBPR_Y VCC_5V TO SHT7 PC_AUDIO_R_IN PC_AUDIO_L_IN
VCLK
SDA
4 5 6 7 8 9 10 11 12 13 14 15
DSUB_VGA_CONN
TO SHT7 RGB SW 27p 50V
VCC
PC_B
SHT4 HP_OUT_R HP_OUT_L
VCC_5V D206 BAV99 D219 D212
BAV_L_IN R279 47R R282 47R R287 47R
PL205
D201 BAV99
DDC_5V
2
PC_VSYNC DDC_5V
D222
1
LINE_R_OUT
BAV99
L218
D221 BAV99
BAV_R_IN
C212
SCART, VGA, DMP, IDTV, FAV CONNECTORS
C278
5
SCL 6
7
8
BAV_L_IN
VCC_5V R209 47R R210 1k R211 1k R212 47R R227 47R R226 47R DDC_SDA
4
R283 47R R288 47R R280 47R FAV AUDIO L219 C242 1n 50V R262 330R C247 1n 50V SUBW TO SHT3
BAV_R_IN
D223 BAV99
3
L217 LINE_L_OUT
S208 C261 C271 S207 C275
330R R296
330R R308
1n 50V
1n 50V
R316 330R
PC_HSYNC PC_VSYNC
C262 R281 75R C251 R284 75R C252 R289 75R C258
C272
TO SHT3 SYNC SW
S205
L227
L228
1n 50V
1n 50V
C276 S206
R317 330R
1n 50V
1n 50V
C279
L229
C238
3k3 R216
R220 10k
C244
1n 50V
PC VIDEO GND TO CHASIS GND S213 S211 S212 BAV99 D202
VCC_3V3 BAV99 D204 C5V6 D211
PL206
TO SHT4
1 2 3
C240 1n 50V R247 47R
L213
1n 50V
FAV_HP
27p 50V 2 3 1 S202 S203 A
27p 50V 2 3 1 S204 A
27p 50V 2 3 1 2 3 1 A
HP_OUT_R
L225
1 2 3 A
2 3 1 HEADPHONE JACK PC
L214 HP_OUT_L C245 1n 50V
JK200
1P_RED_FAV
WHITE_FAV JK201
YELLOW_FAV JK202 BAV_CVBS_IN
TO SHT3 VCTP HP_DETECT
R242 47R
4
1P_RED_FAV JK205
WHITE_FAV JK206 YPBPR AUDIO
JACK-AK16 JK204
YPBPR/LINE_IN[R/L] CVBS JACK
No. 0234
MAIN BOARD CIRCUIT - SHEET2
L230
L231
DDC_SCL
1n 50V
1n 50V
A
VGA_DVDDMP_G _IN
VGA_DVDDMP_R _IN
VGA_DVDDMP_B _IN
TUNER_CVBS_IN
VSUP_3V3_CO M
SHEET 1,2,8
BACKLIGHT_DIM
PIP_CVBS_OUT
PR_IDTV_R_IN
PB_IDTV_B_IN
SC1_CVBS_IN
L415 KEYBOARD C487 R543 47R D406 100n 16V C5V6 R487 47R
Y_IDTV_G_IN
VCTP_VIN2
PDP_GO/BL_ON_OFF
VSUP_3V3_COM E2EPROM
PC STANDBY MODE SYNC DETECTION
5V_STBY IRQ_PDP
VCTP_VIN5
2 1
PL403
5V_COM 10V 100n C492 1kV 1n C493
VCC_5V
SC2_R/C
SC1_FB
SC2_FB
VOUT1
VOUT2
SC1_G
SC2_G
SC1_R
SC1_B
SC2_B
PARITY
SDA_3V3
SCL_3V3
15
13
11
20
19
18
17
16
14
12
10
9
5
3
8
7
6
4
2
1
VSUP_3V3_COM
R545 10k
PL402 IDTV DIGITAL INTERFACE [FFC TYPE]
R467 1k5 VSUP_3V3_COM
KEYBOARD CONN.
IDTV_HSYNC VSUP_3V3_COM
IC405
1 Y0 VCC 16
5V_COM
S414
SHEET POWER
S415
KEYBOARD SDA_3V3_IC
VSUP_3V3_COM
AC_INFO
S409
S410
75R R547 C501
R430 47R R431 1 R1 8
R441 R1 8
27p
7
6
5
7
6
5
R2
R3
R4
R2
R3
R4
50V
75R R442
75R R443
SC1_PIN8
SC2_PIN8
R402 10k
D401
C5V6
KEYBOARD
IDTV_ODD
IDTV_HSYNC
50V 27p
R551
C5V6
C500
R456 10k
R461 10k
DMP/DVD_SWITCH
75R R445
50V 27p
50V 27p
1
2
3
4
C497
C498
D400
C495
C5V6
50V 10u
VSUP_3V3_VO
PC_VSYNC
PIP_DATA5 PIP_DATA4 10k R426 PIP_DATA3 VSUP_3V3_COM PIP_DATA2
HSYNC
C5V6
S412
16V 220n
16V 220n
S413
R437 10k R438 10k R439 10k S411
16V 220n
16V 220n
C478
C480
C476
C483
VSUP_3V3_DAC
16V 220n
16V 220n
C468
C470
HDMI_DETECT
R471 1k8
R436 10k
D402
Q419 BC848B
27p 50V
R553 10k
R435 10k
C499
5
PIP_DATA6
R434 10k
75R R548
S444
R420 10k
Q404 BC848B
PIP_DATA7
50V 27p
75R
R433 10k
R464 10k
PL407
R505 1k
4 Y3
COM_X_OUT_IN 13
S456
PC_HSYNC
R554 10k
D403
C496
PIP_CLK
R432 10k
HSYNC KEYBOARD
3 COM_Y_OUT_IN
X1 14
S462
VSUP_3V3_COM
VSUP_3V3_COM
S461
2
3
4
1
2
3
4
R544 10k
75R R549
SHEET 2
SCL_3V3_IC
75R R550
75R R552
HDMI_HSYNC
2 Y2
X2 15
HDMI_VSYNC
PC_VSYNC
VSYNC
PC_HSYNC
5 Y1
X0 12
IDTV_VSYNC
3V3_STBY
VCC_3V3
C486
100n 10V
R405 47k
16V 220n
16V 220n
220n 16V
16V 220n
16V 220n
16V 220n
16V 220n
16V 220n
16V 220n
16V 220n
C471
C467
C469
C474
C477
C479
C481
C482
C484
7
6
VSUP_3V3_IO3
10k R422
2 3 4
R2 R3 R4
7 6
5
PIP_DATA0 SHEET 6
R440 10k
R468 47R
1
R1
8
PIP_DATA1
VSUP_1V8_FE R462 1 R1 8
VSUP_1V8_FE C472
R403 10k
220n VSUP_3V3_FE 16V
C485
Q401 BC848B
R472 1k
S427 R495 4k7 Q406 BC848B S416 R488 4k7 HDMI_MUTE R485 4k7 HDMI_SCDT R489 4k7 VSUP_3V3_COM SHEET 5 VSUP_3V3_COM
6 INH
X3 11
R528 1k BC848B Q418
R423
R473 4k7
7 VEE
A 10
R535 4k7 R539 4k7
5V_COM SYNC_SW1
2 R2
3 R3
4 R4
Q405 BC848B
*NC
*NC
5
*NC
8 GND
B 9
R529 4k7 R533 47k
S466
VIN21