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8. IC Block Diagrams
8-1 Main
1. AK4355
AK4355
192kHz 24-Bit 6ch DAC for DVD-Audio
GENERAL DESCRIPTION ESCRIPTION The AK4355 offers the perfect mix for cost and performance based multi-channel audio systems. AKM's advanced multi-bit architecture delivers a wide dynamic range and low outband noise. The AK4355 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part sampling ideal for a wide range of application including DVD-Audio. FEATURES Sampling Rate: 8kHz to 192kHz 24Bit 8 times Digital Filter with Slow roll-off option THD+N: -90dB DR, S/N: 106dB High Tolerance to Clock Jitter Low Distortion Differential Output Digital De-emphasis for 32, 44.1 & 48kHz sampling Zero Detect Pin Channel Independent Digital Attenuator with soft-transition Soft Mute I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S Master Clock Normal Speed: 256fs, 384fs, 512fs or 768fs Double Speed: 128fs, 192fs, 256fs or 384fs Quad Speed: 128fs, 192fs Power Supply: 4.75 to 5.25V 28pin VSOP Package
DZF LOUT1+ LOUT1ROUT1+ ROUT1LOUT2+ LOUT2ROUT2+ ROUT2LOUT3+ LOUT3ROUT3+ ROUT3-
SCF
DAC
DATT
Audio I/F
AK4355
MCLK LRCK BICK CSN CCLK CDTI
SCF
DAC
DATT
SCF
DAC
DATT
Control Register
SCF
DAC
DATT
SCF
DAC
DATT
SCF
DAC
DATT
SDTI1 SDTI2 SDTI3
Samsung Electronics
8-1
2. TDA7440D
[
TDA7440D
TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER - 4 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7440D is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in Hi-Fi systems. BLOCK DIAGRAM
MUXOUTL L-IN1 4 100K 5 L-IN2 100K 6 100K 7 100K 0/30dB 2dB STEP 100K 2 100K 1 G VOLUME 8 INL 9
SO28 ORDERING NUMBER: TDA7440D
Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained
TREBLE(L) 18
BIN(L) 14 RB
BOUT(L) 15
L-IN3
TREBLE
BASS
SPKR ATT LEFT
27
LOUT
L-IN4
21 I CBUS DECODER + LATCHES
2
SCL SDA DIG_GND
R-IN1
3
22 20
R-IN2
G
VOLUME
TREBLE
BASS
SPKR ATT RIGHT VREF
26
ROUT
R-IN3
100K 28 R-IN4 100K INPUT MULTIPLEXER + GAIN 10 MUXOUTR INR 11 19 TREBLE(R) 12 BIN(R) SUPPLY RB 13 BOUT(R) 23 CREF
D98AU883
24 25
VS AGND
8-2
Samsung Electronics
3. TDA7449L
[
TDA7449L
LOW COST DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER - 2 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7449L is a volume control and balance (Left/Right) processor for quality audio applications in TV systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor netBLOCK DIAGRAM
MUXOUTL 8 100K 9 100K G VOLUME 10
DIP20
ORDERING NUMBER: TDA7449L
works and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
L-IN1
L-IN2
SPKR ATT LEFT
5 LOUT
19 R-IN1 7 100K 6 G 100K VOLUME SPKR ATT RIGHT VREF 2 INPUT MULTIPLEXER + GAIN 11 MUXOUTR SUPPLY 3 0/30dB 2dB STEP I CBUS DECODER + LATCHES
2
20 18
SCL SDA DIG_GND
R-IN2
4
ROUT
VS AGND
1 CREF
D98AU868
Samsung Electronics
8-3
4. M62463AFP
8-4
Samsung Electronics
Samsung Electronics
8-5
8-2 DVD
1. ZIVA- 5 DVD CONTROLER
DA-IEC958 DA-DATA3 DA-DATA2 VSS VDD_3.3 DA-DATA1 DA-DATA0 DA-BCK DA-LRCK DA-XCK VSS VDDC A_VSS1 A_VDD1 A_VDD2 A_VSS2 XVDD XTAL/VCLK216BP XTAL XVSS VSS_RREF VDAC_RREF VDD_RREF VDAC_DVDD VDAC_DVSS VDAC_0 VDAC_VDD0 VDAC_0B VDAC_1 VDAC_VDD1 VDAC_1B VDAC_2 VDAC_VDD2 VDAC_2B VDAC_3 VDAC_VDD3 VDAC_3B VDAC_4 VDAC_VDD4 VDAC_4B HSYNC/IRQ2 VDATA0 VDATA1 VDATA2 VSS VDD_3.3 VDATA3 VDATA4 VDATA5 VDATA6 VDATA7 VCLK DAI-DATA DAI-BCK/SYSCLKBP DAI-LRCK/IEC958BP I2C_CL I2C_DA RTS1 RXD1 TXD1 CTS1 VSS VDD_3.3 SD-DATA7 SD-DATA6 SD-DATA5 SD-DATA4 VSS VDDC SD-DATA3 SD-DATA2 SD-DATA1 SD-DATA0 SD-REQ SD-EN VSS VDD_3.3 SD-ERROR SD-CLK VSYNC/HIRQ1 RTS2/SPI_CLK RXD2/SPI_MISO TXD2/SPI_MOSI CTS2/SPI_CS VDD_5 HCS4 HCS3 HCS2 HCS1 HCS0 VSS VDD_3.3 TRST TDO TDI TMS TCK RESET ALE VSS VDDC HAD3 HAD2 VSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
ZiVA-5 Controller Top View
VDD_3.3 VSS MDATA31 MDATA30 MDATA29 MDATA28 VDD_3.3 MDQM3 VSS MDATA27 MDATA26 MDATA25 MDATA24 MDATA23 MDATA22 MDATA21 MDATA20 VDD_3.3 MDQM2 VSS MDATA19 MDATA18 MDATA17 MDATA16 VDDC VSS MDATA15 MDATA14 MDATA13 MDATA12 VDD_3.3 MDQM1 VSS MDATA11 MDATA10 MDATA9 MDATA8 MDATA7 MDATA6 MDATA5 MDATA4 VDD_3.3 MDQM0 VSS MDATA3 MDATA2 MDATA1 MDATA0 MCLK VDD_3.3 VSS MWE
Table 1
Pin No. 1 2 3 4 5 6
ZiVA-5 controller Pin List
Pin Name VDDP HA1 HA15 HA14 HA13 HA12 I/O Voltage 3.3V 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* I/O Type
8-6
VDD_3.3 HA1 HAD15 HAD14 HAD13 HAD12 HAD11 HAD10 HAD9 HAD8 HAD7 VDD_3.3 VSS HAD6 HAD5 HAD4 HAD3 HAD2 HAD1 VDD_3.3 VSS HAD0 HDTACK/WAIT HIRQ0 UDS/UWE LDS/LWE R/W IRRX1 VSS VDDC VSS VDD_3.3 MADDR9 MADDR8 MADDR7 MADDR6 MADDR5 MADDR4 MADDR3 MADDR2 MADDR1 MADDR0 VSS VDD_3.3 MADDR10 MADDR11 BA1 BA0 MCS0 MCS1 MRAS MCAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Figure 1
ZiVA-5 controller Pinout (208-pin PQFP)
ó
I/O I/O I/O I/O I/O
Samsung Electronics
Table 1
Pin No. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
ZiVA-5 controller Pin List (Continued)
Pin Name HA11 HA10 HA9 HA8 HA7 VDDP GNDP HA6 HA5 HA4 HA3 HA2 HA1 VDDP GNDP HA0 HDTACK/WAIT HIRQ0 HUDS/UWE HLDS/LWE HREAD IRRX1/GPIO[0] GND VDD GND25 VDD25 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 GND25 VDD25 MA10 MA11 BA1 BA0 MCS0 MCS1 MRAS MCAS MWE I/O Voltage 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V GROUND 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V GROUND 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* GROUND 1.8V GROUND 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V GROUND 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I/O Type I/O I/O I/O I/O I/O
Table 1
Pin No. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
ZiVA-5 controller Pin List (Continued)
Pin Name GND25 VDD25 MCLK MD0 MD1 MD2 MD3 GND25 MDQM0 VDD25 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 GND25 MDQM1 VDD25 MD12 MD13 MD14 MD15 GND VDD 3.3V 3.3V 3.3V 3.3V GROUND 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V GROUND 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V GROUND 3.3V 3.3V 3.3V 3.3V I/O Voltage GROUND 3.3V I/O Type
ó ó
O I/O I/O I/O I/O
ó ó
I/O I/O I/O I/O I/O I/O
ó
O
ó
I/O I/O I/O I/O I/O I/O I/O I/O
ó ó
I/O I/OD I/O I/O I/O I/O I
ó
O
ó
I/O I/O I/O I/O
O O O O O O O O O O
ó ó
O O O O O O O O O
Samsung Electronics
Ad va Co nc n e P fi r d
GROUND
ó ó ó ó
ó ó
MD16 MD17 MD18 MD19
I/O I/O I/O I/O O
GND25 VDD25 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27
GROUND
ó ó
MDQM2
I/O I/O I/O I/O I/O I/O I/O I/O
GND25 MDQM3 VDD25 MD28 MD29
ó
O
ó
I/O I/O
8-7
Table 1
Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147
ZiVA-5 controller Pin List (Continued)
Pin Name MD30 MD31 GND25 VDD25 VCLK VDATA7/GPIO[1] VDATA6/GPIO[2] VDATA5/GPIO[3] VDATA4/GPIO[4] VDATA3/GPIO[5] VDDP GNDP VDATA2/GPIO[6] VDATA1/GPIO[7] VDATA0/GPIO[8] HSYNC/HIRQ2/GPIO[9] VDAC_4B VDAC_VDD4 VDAC_4 VDAC_3B VDAC_VDD3 VDAC_3 VDAC_2B VDAC_VDD2 VDAC_2 VDAC_1B VDAC_VDD1 VDAC_1 VDAC_0B VDAC_VDD0 VDAC_0 VDAC_DVSS VDAC_DVDD VAC_REFVDD VDAC_REF VDAC_REFVSS XVSS XOUT XIN/bypass clk_216 XVDD AVSS2 AVDD2 AVDD1 AVSS1 VDD GND XCK 3. I/O Voltage 3.3V 3.3V GROUND 3.3V 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V GROUND 3.3V* 3.3V* 3.3V* 3.3V* ANALOG 3.3V ANALOG ANALOG ANALOG 3.3V ANALOG ANALOG ANALOG 3.3V ANALOG ANALOG ANALOG 3.3V ANALOG ANALOG ANALOG 3.3V ANALOG ANALOG GROUND 3V 3.3V ANALOG GROUND GROUND ANALOG ANALOG 3.3V GROUND 3.3V 3.3V GROUND 1.8V GROUND 3.3V* I I/O Type I/O I/O
Table 1
Pin No. 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169
ZiVA-5 controller Pin List (Continued)
Pin Name LRCK BCK ADATA0/GPIO[10] ADATA1/GPIO[11] VDDP GNDP ADATA2/GPIO[12] ADATA3/GPIO[13] IEC958/GPIO[14] DAI_DATA/GPIO[15] DAI_BCK/bypass_sysclk/ GPIO[16] DAI_LRCK/iec958bp/GPIO[17] I2C_CL/GPIO[18] I2C_DA/GPIO[19] RTS1/GPIO[20] RXD1/GPIO[21] TXD1/GPIO[22] CTS1/GPIO[23] GNDP VDDP SDDATA7/VDATA2[7]/ HDMARQ/GPIO[24] SDDATA6/VDATA2[6]/HXCVR_ EN/ GPIO[25] SDDATA5/VDATA2[5]/ HDMACK/GPIO[26] SDDATA4/VDATA2[4]/GPIO[27] GND VDD SDDATA3/VDATA2[3]/GPIO[28] SDDATA2/VDATA2[2]/GPIO[29] SDDATA1/VDATA2[1]/GPIO[30] SDDATA0/VDATA2[0] /GPIO[31] SDREQ/GPIO[32] SDEN/GPIO[33] GNDP VDDP SDERROR/GPIO[34] SDCLK/GPIO[35] VSYNC/HIRQ1/GPIO[36] RTS2/SPI_CLK/GPIO[37] RXD2/SPI_MISO/GPIO[38] TXD2/SPI_MOSI/GPIO[39] CTS2/SPI_CS/GPIO[40] VNW 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* GROUND 3.3V 3.3V 3.3V* I I/OD I/OD O I O I I/O Voltage 3.3V* 3.3V* 3.3V* 3.3V* 3.3V GROUND 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* I/O Type O O O O
ó ó
I/O I/O I/O I/O I/O I/O
ó ó
O O O I I
ó ó
I/O I/O I/O I/O O
ó
O O
ó
O O
ó ó
I I
ó
O O
ó
O O
170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
3.3V* 3.3V* GROUND 1.8V 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* GROUND 3.3V 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 5V
I I
ó
O
ó ó
I I I I O I
ó ó
I I I/O O I O I
ó ó
I/O
187 188 189
ó
8-8
Samsung Electronics
Table 1
Pin No. 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
ZiVA-5 controller Pin List (Continued)
Pin Name HCS4/GPIO[41] HCS3/GPIO[42] HCS2/GPIO[43] HCS1 HCS0 GNDP VDDP TRST TDO TDI/GPI[0] TMS/GPI[1] TCK RESET ALE GND VDD HA3 HA2 GNDP I/O Voltage 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* GROUND 3.3V 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* 3.3V* GROUND 1.8V 3.3V* 3.3V* GROUND I/O Type I I I I/O I/O
ó ó
I O I I I I I/O
ó ó
I I
ó
Note: The ZiVA-5 core operates at 1.8V ± 10%. Most I/O interface pins can be interfaced with 3.3-V or 5-V devices depending on the voltage applied to the VDD pins associated with them. Refer to the Application Note for more information.
32-128Mbit
SDRAM Controller CCIR 656 Track Buffer Processor Audio Input Unit Decryption ZiVA A/V Core Graphics Engine Interlaced/ Progressive Prog Video Encoder
Five 10-bit Video DACs
System Control Bus SPARC Microprocessor Bus Interface Unit Phase Lock Loop 13.5 MHz Crystal
Audio Output Unit
ASYNC BUS IR
GPIO SPI UART1& 2 ATAPI IDC
Samsung Electronics
8-9
2.W986432DH
BLOCK DIAGRAM
CLK CLOCK BUFFER CKE
CONTROL
CS
SIGNAL
RAS CAS
GENERATOR
COMMAND
DECODER WE ROW DECODER COLUMN DECODER COLUMN DECODER ROW DECODER
A10
CELL ARRAY BANK #0
CELL ARRAY BANK #1
A0 ADDRESS BUFFER
MODE REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A9 BS0 BS1
DATA CONTROL CIRCUIT COLUMN COUNTER
DQ BUFFER
DQ0 DQ31
REFRESH COUNTER
DQM0~3
COLUMN DECODER ROW DECODER ROW DECODER
COLUMN DECODER
CELL ARRAY BANK #2
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 2048 * 256 * 32
8-10
Samsung Electronics
3. M6759 ; 8BIT MTP micro controller
4. M5701/M5705 ; DVD ROM controller
M5701/M5705
Samsung Electronics
8-11
5. FAN8082
Pin Assignments
GND VO1
1
8
VO2
2
7
PVCC
VCTL
FAN8082
3 6
SVCC
VIN1
4
5
VIN2
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 Pin Name GND VO1 VCTL VIN1 VIN2 SVCC PVCC VO2 I/O O I I I O Ground Output 1 Motor speed control Input 1 Input 2 Supply voltage (Signal) Supply voltage (Power) Output 2 Pin Function Description
Internal Block Diagram
GND VO1
1
DRIVER OUT
8
VO2
2
7
PVCC
PRE DRIVER VCTL
3
TSD
BIAS
6
SVCC
VIN1
4
LOGIC SWITCH
5
VIN2
8-12
Samsung Electronics
6. M11B416256A
Samsung Electronics
8-13
7. SST39LF800A ; Multi Purpose Flash
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
EEPROM Cell Array
Memory Address
Address Buffer & Latches Y-Decoder
CE# OE# WE# DQ15 - DQ0
360 ILL B1.1
Control Logic
I/O Buffers and Data Latches
SST39LF/VF800A SST39LF/VF400A SST39LF/VF200A A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# NC NC NC NC NC A17 A7 A6 A5 A4 A3 A2 A1 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# NC NC NC NC NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SST39LF/VF200A SST39LF/VF400A SST39LF/VF800A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
Standard Pinout Top View Die Up
SST39LF200A/400A/800A SST39VF200A/400A/800A
360 ILL F01.2
8-14
Samsung Electronics