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DVD4250D
DVD PLAYER
SERVICE MANUAL
1
1. G ENERAL DESCRIPTION
1.1 ES66x8
The ES66x8 Vibratto II processor is a highly integrated single-chip DVD solution that integrates read channel, ECC, Servo DSP, MCU, and MPEG-2/MPEG-4/DivX decoder that has a state-of-the-art 480p/576p progressive-scan video feature to provide brilliant and sharp, flicker-free video output to the display, and with built-in gamma correction and S/PDIF input and output support. The 66x8 performs audio/video stream data processing, TV encoding, Macrovision copy protection, DVD system navigation, system control, and housekeeping functions. The Vibratto II DVD processor is built on the ESS proprietary dual CPU Programmable Multimedia Processor (PMP) core consisting of 32-bit RISC and 64-bit DSP processors and offers the best DVD feature set. These features can be listed as follows:
General Features: - - - - - - - - - Single -chip DVD processor incorporating all front-end and back-end functions. Unified memory architecture. Built-in ADCs and DACs for servo control signals . DVD-Video, DVD-VR, VCD 1.1 and 2.0 and SVCD Proven ECC, EFM/EFM+ demodulation, and EDC circuit. Direct interface of 16-bit DRAM up to 128-Mb capacity. Direct interface of 8- or 16-bit SDRAM up to 128-Mb capacity. Direct interface for up to 4 banks of 8-bit EPROM or Flash EPROM for up to 4 MB per bank. Direct interface to the ES6603 servo AFE chip.
Video Related Features: - - - - - - - - - Integrated NTSC/PAL encoder with pixel-adaptive de-interlacer and five 10-bit 54 MHz video DACs . DivX and MPEG-4 Advanced Simple Profile at full screen. Media playback with CD-ROM, CD-R/RW, DVD-R/RW and DVD+R/RW. Macrovision 7.1 for NTSC/PAL interlaced video. Macrovision NTSC/PAL (480p/576p) progressive scan video. Simultaneous composite, S-video and YUV outputs. CCIR656/601 YUV 4:2:2 output. OSD controller supports 256 colors in 8 degrees of transparency. JPEG digital photo CD support ( Kodak Picture CD and Fujifilm FujiColor CD ).
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Audio Related Features: - - - - - - - - Full DVD-Audio support including MLP and LPCM decode, CPPM decryption, and watermark detection. Up to 7.1 channel audio outputs . Bass management. Dolby Digital ( AC-3 ), Dolby Pro Logic, and Pro Logic II. DTS surround ( ES6698 only ). S/PDIF digital audio input and output. SRS TruSurround. Professional karaoke with full scoring scheme.
1.2 M EMORY
1.2.1 System SRAM Interface The system SRAM interface controls access to optional external SRAM, which can be used for RISC code, stack, and data. The SRAM bus supports four independent address spaces, each having programmable bus width and wait states. The interface can support not only SRAM, but also ROM/EPROM and memory-mapped I/O ports for standalone applications are supported. 1.2.2 DRAM Memory Interface The Vibratto II provides a glueless 16-bit interface to DRAM memory devices used as video memory for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous DRAM (SDRAM). The memory interface is configurable in depth to support 128-Mb addressing. The memory interface controls access to both external SDRAM or EDO memories, which can be the sole unified external read/write memory acting as program and data memory as well as various decoding and display buffers.
1.3 FRONT PANEL
The front panel is based around an Futaba VFD and a common front panel controller chip, (uPT6311). The ES66x8 controls the uPT6311 using several control signals, (clock, data, chip select). The infrared remote control signal is passed directly to the ES66x8 for decoding.
1.4 REAR PANEL
A typical rear panel is included in the reference design. This rear panel supports: - six channel and two channel audio outputs - Optical and coax S/PDIF outputs. - Composite, S-Video, and SCART outputs The six-video signals used to provide CVBS, S-Video, and RGB are generated by the ES66x8's internal video DAC. The video signals are buffered by external circuitry. Six channel audio output by the ES66x8 in the form of three I2 S (or similar) data streams. The S/PDIF serial stream is also generated by the ES66x8 output by the rear panel. A six channel audio DAC are used for six channel audio output with ES66x8, and similarly one Audio DAC is used for two channel audio output with ES66x8.
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2. System Block Diagram and ES66x8 Pin Description 2.1 ES66x8 Pin Description
4
5
6
7
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2.1 SYSTEM BLOCK DIAGRAM A sample system block diagram for the ES66x8 Vibratto II DVD player board design is shown in the following figure:
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3. AUDIO OUTPUT
The ES66x8 supports two-channel analog audio output while ES66x8 supports six-channel analog audio output. In a system configuration with six analog outputs, the front left and right channels can be configured to provide the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel surround system. The ES6008 also provides digital output in S/PDIF format. The board supports both optical and coaxial S/PDIF outputs.
3. AUDIO DACS
The ES66x8 supports several variations of an I2 S type bus, varying the order of the data bits (leading or no leading zero bit, left or right alignment within frame, and MSB or LSB first) is possible using the ES66x8 internal configuration registers. The I2 S format uses four stereo data lines and three clock lines. The I2 S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The two-channel DAC is an CS4392. The DACs support up to 192kHz sampling rate. The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuits use National LM833 op-amps to perform the low-pass filtering and the buffering.
5 VIDEO INTERFACE
5.1 Video Display Output The video output section controls the transfer of video frames stored in memory to the internal TV encoder of the Vibratto II. The output section consists of a programmable CRT controller capable of operating either in Master or Slave mode.
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The video output section features internal line buffers which allow the outgoing luminance and chrominance data to match the internal clock rates with external pixel clock rates, easily facilitating YUV4:2:2 to YUV4:2:0 component and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and interpolation. Video Bus The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in CCIR1656 pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y) pixels; there are as many chrominance lines as luminance. Video Post-Processing The Vibratto II video post-processing circuitry provides support for the color conversion, scaling, and filtering functions through a combination of special hardware and software. Horizontal up-sampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in accordance with the applicable scaling ratio. Video Timing The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. The double clock typically is used for TV displays, the single for computer displays.
6 SDRAM MEMORY
The memory bus interface generates all the control signals to interface with external memory. The Vibratto II supports different configurations using the memory configuration bits SDCFG[1:0] (bits 12:11), the SD8BIT bit (bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROL register. Configurations can be implemented in many ways. The following table lists the typical SDRAM configurations used by the Vibratto II. Typical SDRAM Configurations:
The memory interface controls access to both external SDRAM or EDO memories, which can be the sole unified external read/write me mory acting as program and data memory as well as various decoding and display buffers. At high clock speeds, the Vibratto II memory bus interface
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has sufficient bandwidth to support the decoding and displaying of CCIR1656/601 resolution images at full fra me rate.
7 FLASH MEMORY
The decoder board supports AMD class Flash memories. Currently 4 configurations are supported: FLASH_512K_8b FLASH_1024K_8b FLASH_512Kx2_8b FLASH_512Kx2_16b The Vibratto II permits both 8- and 16-bit common memory I/O accesses with a removable storage card via the host interface.
8 S ERIAL EEPROM MEMORY
An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup, etc.) and software configuration.. Industry standard EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or equivalent.
9 AUDIO INTERFACE AUDIO SAMPLING RATE CONFIGURATION
AND
PLL COMPONENT
The ES66x8 Vibratto II audio mode configuration is selectable, allowing it to interface directly with low-cost audio DACs and ADCs. The audio port provides a standard I2 S interface input and output and S/PDIF (IEC958) audio output. Stereo mode is in I2 S format while six channels Dolby Digital (5.1 channel) audio output can be channeled through the S/PDIF. The S/PDIF interface consists of a bi-phase mark encoder, which has low skew. The transmit I2 S interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where sampling frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the I2 S transmit interface can be 16, 18, 20, 24, and 32-bit samples. For Linear PCM audio stream format, the Vibratto II supports 48 kHz and 96 kHz. Dolby Digital audio only supports 48 kHz. The ES6008/18 Vibratto II incorporates a built-in programmable analog PLL in the device architecture in order to generate a master audio clock. The MCLK pin is for the audio DAC clock and can either be an output from or an input to the ES66x8 Vibratto II . Audio data out (TSD) and audio frame sync (TWS) are clocked out of the Vibratto II based on the audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is used to clock in audio data in (RSD) and audio receive frame sync (RWS).
10 FRONT PANEL
10.1 VFD CONTROLLER
The VFD controller is a PTC PT6311. This controller is not a processor, but does include a simple state machine which scans the VFD and reads the front panel button matrix. The 6311 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 6311 need only be accessed when the VFD status changes and when the button status is read. The ES66x8 can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD.
11 MISCELLANEOUS FUNCTIONS
11.1 RESET CIRCUITRY
Two different chips are supported to provide the power-on-reset and pushbutton reset function: AAT3521 or V6300.
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12 CONNECTORS
12.1 SCART CONNECTORS
Pinout of the scart connector: 1 ? Audio Right Out 2 ? Audio Right In 3 ? Audio Left / Monu Out 4 ? Audio Gnd 5 ? Blue Gnd 6 ? Audio Left / Mono In 7 ? Blue 8 ? Control Voltage 9 ? Green Gnd 10 ? Comms Data 2 11 ? Green 12 ? Comms Data 1 13 ? Red Gnd 14 ? Comms Data Gnd 15 ? Red 16 ? Fast Blanking 17 ? Video Gnd 18 ? Fast Blanking Gnd 19 ? Composite Video In 20 ? Composite Video Out 21 ? Shield
Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths. For longer lengths, shielded coax cable become essential.
Scart Signals:
Audio signals 0.5V RMS, <1K output impedance, >10K input impedance. Red, Green, Blue 0.7Vpp ? 2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the S-VHS Chrominance signal, which is 0.3V. Composite Video / CSync 1Vpp including sync, ?2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV Video de-emphasis to CCIR 405.1 (625-line TV) Fast Blanking 75R input and output impedance. This control voltage allows devices to over-ride the composite video input with RGB inputs, for example when inserting closed caption text. It is called fast because this can be done at the same speeds as other video signals, which is why it requires the same 75R impedances.
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0 to Left
0.4V: TV unconnected,
is it
driven is
by the pulled
composite to 0V
video by
input its
signal 75R
(pin 19). termination.
1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V) negative sync pulse is available, this will be high during the display periods, so this can drive the blanking signal via a suitable resistor. Control Voltage 0 to 2V = TV, Normal. 5 to 8V = TV wide screen 9.5 to 12V = AV mode
13. CIRCUIT DESCRIPTION
13.1 POWER SUPPLY: - - - - - - Socket PL2 is the 220VAC input. Socket PL3 is used for the power button on the front panel. 3.15A fuse F1 is used to protect the device against short circuit. Voltage is rectified by using diodes D1, D2, D3 and D4. Using capacitor C33 (47?f) a DC voltage is produced. (310- 320VDC). The current in the primary side of the transformer TR2 comes to the SMPS IC (TNY267P). It has a built-in oscillator, over current and thermal protection circuitry and runs at 133kHz. It starts with the current from the primary side of the transformer and follows the current from the feedback winding. Voltages on the secondary side are as follows: 12 Volts at pin11 at C42, 5 Volts at C40,3.3 Volts at C38, -22Volts at C44,-12 Volts at D22. - D14 TL431 is a constant current regulator. TL431 watches the 5 volts and supplies the required current to IC2. There are a LED and a photo transistor in IC2. The LED inside the IC2 transmits the value of the current from D25 to phototransistor. Depending on the current gain of the phototransistor IC3 keeps the voltage on the 5-volt-winding constant. 22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on the front panel.
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Functional Block Diagram of Switcher
13.2 FRONT PANEL: - - - - -
-
All the functions on the front panel are controlled by U1 (ES66x8) on the mainboard. U1 sends the commands to IC2 PT6311 via socket J2 (pins 3,4 and 5). There are 48 keys scanning function, 5 LED outputs, 1 Stand-by output and VFD drivers on PT6311. Vacuum fluorescent display is specially designed for DVD. The scanned keys are transmitted via PT6311 to U1 on the mainboard.
IR remote control receiver module sends the commands from the remote control directly to U1.
13.3 BACK PANEL: - - - - There are 1 SCART connector (con24), 2 pieces RCA audio jacks for audio output, 1 coaxial digital audio output and 1 laser digital audio output on the back panel. MOFT3C2 is used for laser output. Left and right audio outputs are on RCA Conn 6. LUMA and CHROMA signals of S-Video are transmitted to P1 via transistors Q39 and Q37 respectively.
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CD Update Procedure of 4250D
1. 2. Download the update file from the convenient link according to your default language choice. While there is no CD in the DVD (No Disc Mode) , press "Menu 1 3 5 7" buttons on the remote control in order to reach the Service Menu of DVD Player:
3.
2.1. Note the software version described as "b.xx " to be able to compare the sw. Version after update process. Copy the update file to the desktop and rename it according to the update file name in the hidden menu of the device. For example If C2M1AS__ is written then rename it like C2M1AS__.rom If P6M1AS__ is written then rename it like P6M1AS__.rom (If you receive the update file already renamed (with addition of .rom) from the customer technical support department by giving the SAP code of the product then burn the already renamed file with nero program as it is shown below.)
4.
Burn the renamed files by Nero program with below set up.
5. 6.
After burning process is completed, place the update CD into the DVD tray and press play button. Wait to see the update process steps as shown below. When the sw. Update is completed unit will switch itself to standby mode.
7. 8.
Finally, press the eject button and take out the update CD while DVD Player remains at stand by Mode. Updating process has been completed. To check whether it is updated correctly or not, repeat the first step for comparing software version If the previous and letter names are different, CD is update has completed successfully. If the name remains same than go through the steps from the beginning.
9.
IMPORTANT NOTE: If the AC source breaks down while the updating the unit (main board) will be totally out of order. This kind of units/boards is out of Warranty.
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Brief Information of Naming the File
Software version differs from each other depending on front models. 23xx and 24xx are called Old VFD and 25xx and 26xx are called Mini VFD. Each character in the file name is an abbreviation of a description as illustrated below.
C2M1AS__ Progressive Option (with progressive : P, without progressive: _ )
DMR option (with DMR:R, without DMR:_ ) Loader Type (S loader:s W loader:w)
Flash Type ( AMD:A, Intel:I ) Language group
VFD type
DAC channel (2, 6)
DAC Type
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Pay attention the left side. Select CD and CD_ROM (ISO) on the upper left side of screen
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Select No Multisession
19
Format is Mode 1
20
21
Leave the dates as it is
22
Leave it as it is
23
Click the "New" on the upper right corner of the screen
24
Select your file from file browser then you will see your file in the "Name" section on the right side and then copy the files to under "Name" section on the left side.(this is just an example you will see your file name when you are doing this process)
25
Click the "Burns the current compilation"
26
Then you will see this screen and click the "Burn" on the right upper side of screen
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You will see this screen and tray will open itself on computer ,then place the CD in CD-ROM And it will start writing. At the end you will see "burn complited"
.
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VCC33 XFLAG0 XFLAG1 XFLAG2 XFLAG3 RFO TESTAD DA RFRP DIP DIN TRACK FOCUS SLEGP SLEGN SPINDLE MIRR TEI FEI CEI SPDON SFGIN TP1 FLAG0 TP3 FLAG2 TP5 RFO TP7 DA TP9 DIP TP11 STRACK TP13 SSLEGP TP15 SSPINDLE TP17 TEI TP19 CEI TP21 FGIN 0 SVREF21 (3) DIN DEFCT SPDON SLDC SDEFCT (3) SPDON (3) SLDC (3) RF33V 10x4 VCC33 8 7 6 5 RN4 RR10 (3) MIRR (3) ATR_OP RR15 RR12 0 33K R CC20 1U TR2 RR87 0 RR17 RR18 10K 5.1K TR1 TR2 CC27 0.1U SVREF15 (3) OPEN (3) SPINDLE (3) FOCUS (3) SLEGN (3) TRACK SPINDLE FOCUS SLEGN TRACK DA CC28
AM5868 CC28 7.5nF BA5954 0.015U
VCC33
VCC33
VCC33 R4 OPEN
PLL2 0 0 0 0 1 1 1 1 PLL1 0 0 1 1 0 0 1 1 PLL0 0 1 0 1 0 1 0 1 MULTI Frequency S-CHIP DEFAULT DEFAULT S-CHIP 4.5 114.75 4.25 121.5 NA 135 reserved 5 bypass 27 NA bypass 101.25 108 4 3.75 4.5 121.5 4.25 114.75 reserved 128.25 4.75 NA 94.5 3.5 5.5 148.5 6 4 108 162
TP2 FLAG1 TP4 FLAG3 TP6 TESTAD TP8 RFRP TP10 DIN TP12 SFOCUS TP14 SSLEGN TP16 MIRR TP18 FEI TP20 XSPDON
VCC33
RR1 RR2
4.7K 4.7K TXD RS232_DET RXD JJ1 1 2 3 4 5
PLL3 1 0 CLK SOURCE DCLK INPUT CRSTAL OSC
VCC
SERVO MCU DEBUG HEADER
R1 OPEN
R2 OPEN
R3 OPEN
VIDEO OUTPUT TABLE
VDAC YDAC CDAC UDAC FDAC CVBS + S-VIDEO or CVBS + YUV CVBS Y V U C CVBS + YUV CVBS Y V U CVBS S-VIDEO + RGB Y G R B C CVBS + RGB CVBS G R B CVBS
SPDIF (5) TBCK (4) MCLK (4) CC1 CC2 1000P CC3 1000P 1000P CC4 1000P 3.3K 3.3K 3.3K 3.3K CC5 0.1U RR7 CC8 CC46 SVREF15 1U CC12 1U R59 RR9 20K SVREF09 SVREF21 C7 R50 TSD1 TSD0 TWS UDAC1 CDAC1 YDAC1 GNDV VCC33V VDAC1 FDAC1 RSET COMP VREF VS33_PL2 VCC20 XFLAG3 XFLAG2 XFLAG1 XFLAG0 RXD TXD RFRP SPDIF TBCK MCLK 4.7U TP36 TP37 TP38 10K TSD2 TSD1 TSD0 TWS R7 4.7K R8 4.7K R9 4.7K R10 4.7K (4) (4) (4) (4)
VCCV D1 1
GND RS232 CONNECTOR 2.54MM RFGND (3) SBAD (3) FEI (3) CEI (3) TEI (3) DIP SBAD FEI CEI TEI DIP RFO CC58 4700P CC59 C CC61 C CC55 4700P RR8 68K RR3 RR4 RR5 RR6
1N6263 VCCV FB1 FERB VCC VCCV 1 D3 21 D2 R6 1N6263 2 75 OHM
L1 2.4UH C1 470PF L2 UDAC (5) C2 470PF GNDV 2.4UH
R5 4.7K
1N6263 GNDV UDAC1 CDAC1 YDAC1 VDAC1 FDAC1 VCC33V 21 GND GND GND GND GND D4 VCCV 1N6263 2 1 D13
GNDV R11
GNDV
CDAC (5)
(3) MOCTL (3) SVREF21
R51
RS232_DET
(3) RFO
75 OHM
C3 470PF
C4 470PF GNDV 2.4UH
DIN
XS XS XS
GNDV VCCV
1N6263 GNDV 21 D11 R63
GNDV L3 C5 470PF
YDAC (5)
CC13 CC14 CC15 1 2 3 4 EAUX40 EAUX41 EAUX42 EAUX43 0.1U 0.1U 0.1U
CC16 C CC17 6800P
0.1U C8 0 OHM
390 VCC33V 0.1U
D12
1N6263 2
75 OHM
C6 470PF GNDV 2.4UH
1
1N6263 GNDV 21 GNDV GND TESTAD TSD2 D8 VCCV
GNDV R62
GNDV L4 C9 470PF
VDAC (5)
RFGND RFRP TESTAD SVREF15 TR1 RR16 1.2K RR14 R CC18 C CC19 C CC21 0.047U CC23 560P PLL33V
RFGND
VCC33
1N6263 2
D9
75 OHM
C10 470PF GNDV 2.4UH
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
U1 ES66x8 FB2 FERB
GNDV
1
1N6263 GNDV 21 D10 R61 1N6263 2
GNDV L5 C11 470PF
FDAC (5)
XSDSSLV XSRFIP XSRFIN XSIPIN AVDD3_DS XSIREF XSVREF[15] XSVREF[09] XSVREF[21] AVDD3_AD XSRFRP XSTEI XSCEI AVSS_AD XSFEI XSSBAD XSTESTAD XSTEXI VDD VSS XSFLAG[3] XSFLAG[2] XSFLAG[1] XSFLAG[0] XSIP1 XSIP2 XSLG XSWBL XSWBLCLK VS33 VD33 SPDIFIN SPDIF/SEL_PLL3 TBCK MCLK TSD3 TSD2 VS33 TSD1/SEL_PLL1 TSD0/SEL_PLL0 TWS/SEL_PLL2 YUV0/UDAC YUV2/CDAC YUV5/YDAC VS33_DA VD33_DA YUV6/VDAC YUV7/FDAC YUV4/RSET YUV3/COMP YUV1/VREF VS33_PL
75 OHM
CC22 0.1U 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
C12 470PF GNDV
CC24 CC25 CC26 RFGND PLLGND 0.1U 47P 0.1U
RR96 RR21 RR22 RR24 RR25 RR26
0 6.8K 6.8K SLEGP 5.1K 6.8K 6.8K SFGIN 33 33 33 XSCSJ XSDATA XSCLK DEFCT SLDC SPDON
CC30 CC32 0.015U 560P CC33 560P CC31 0.015U RR27 RR28 RR29
0.015U
(3) SVREF15 (3) SCSJ (3) SDATA (3) SCLK VCC
SVREF15 SCSJ SDATA SCLK CC35 CC36 CC37 33P 33P 33P R52 1K R53 1K RFGND R23 R65 R64 R26 33 33 33 33 VCC33 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VCC VCC VCC VCCQ VCCQ VCCQ VCCQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 6 12 46 52 28 41 54 C13 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15
SERIAL EEPROM U3
1 2 3 4 GND S0 S1 S2 GND VCC WC SCL SDA 24C01A 8 7 6 5
(3) INSW (3) HOMESW (3) CLOSE (3) OUTSW (3) DRVSB (4) (4) (4) (4) EAUX43 EAUX42 EAUX41 EAUX40
RS232_DET
(5) NN
GND (5) SCART-ON U5
4.7K 33 33 33 33
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 DSCK DOE# CS0# RAS0# CAS# DWE# DQM
23 24 25 26 29 30 31 32 33 34 22 35 R33 R69 R58 R57 R40 R41 R44 R46 R47 33 33 33 33 33 33 33 33 33 38 37 19 18 17 16 15 39 20 21 36 40
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 CLK CKE CS RAS CAS WE DQML DQMH BA0 BA1 NC NC
RESET#
VD33 XIN XOUT DCLK DMA0 DMA1 DMA2 DMA3 VS33 VD33 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 DMA10 VS33 VD33 DMA11 DCAS DCS0 DCS1 DRAS0 DBANK0/ DRAS1 VSS VDD DBANK1/ DRAS2 DCKE/DOE/TDMTSC DWE DB0 DB1 DB2 VS33 VD33 DB3 DB4 DB5 DB6 DB7 DB15 DB14 VS33 VD33 DB13 DB12 DB11 DB10 DB9 DB8 DSCK VS33
AVSS_DS AVSS_PL XSPDOFTR1 XSFDO XSFTROPI AVDD3_PL XSPLLFTR1 XSPLLFTR2 XSVREF0 XSAWRC AVSS_DA XSRFRPCTR XSTRAY AVDD3_DA XSSPINDLE XSFOCUS XSSLEGP XSSLEGN XSTRACK XSTESTDA XSFGIN XSPHOI SXCSJ XSDATA XSCLK XSDFCT XSLDC XSSPDON VD33 VS33 XGPIO[9] XGPIO[8] XGPIO[7] XGPIO[6] XGPIO[5] XGPIO[4] EAUX03 EAUX02 EAUX01 EAUX00 VSS VDD AUX0 AUX1 AUX2/ HSYNC AUX3/ VSYNC AUX4 AUX5 AUX6 AUX7 RESET VS33
Vibratto-II
VD33_PLL RWS/TDMFS RBCK/TDMCLK RSD/TDMDR LD7 LD6 LD5 LD4 VD33 VS33 LD3 LD2 LD1 LD0 LOE LWRLL LCS3 VDD VSS LCS2 LCS1 LCS0 LA0 LA1 LA2 VD33 VS33 LA3 LA4 LA5 LA6 LA7 LA8 VDD VSS LA9 LA10 LA11 LA12 LA13 LA14 LA15 VD33 VS33 LA16 LA17 LA18 LA19 LA20 LA21 DQM VD33
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
VD33_PL1
GNDV
GNDV
GNDV
LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LOE# WRLL# LCS3# VCC20 LCS2# LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LCS2# LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 DQM LCS3# LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA20 WRLL# RESET#
VCC VCC33 U2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
R17 R18
0 OPEN
LA19 LA18 LA8 LA7 LA6 LA5 LA4 LA3 LA2
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP VPP DU/WP NC NC A17 A7 A6 A5 A4 A3 A2 A1
A16 BYTE GND DQ15/A_1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G GND E A0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
LA17 LA0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LOE# LA1
TMS28F400Axy
GND
U4 LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 OPEN 0 OHM OPEN 0 OHM LCS3# LOE#
TYPE EPROM FLASH
JP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
WRLL# LA18 LA19
R32 R34 R35 R68
REMOVE R32, R35 R34, R68
12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 31 1 22 24
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 CE OE
D0 D1 D2 D3 D4 D5 D6 D7
13 14 15 17 18 19 20 21
LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7
1 2 3
VCC
VCC
32
GND
16 GND
INSTALL R34, R68 R32, R35
R60 R56 R54 R55 R31
27C040/080-90 U7
VCC IR VFD-CLK VFD-CS VFD-DATA R42 Y1 100K FB4 3.3UH DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 DMA10 DMA11 CAS# CS0# RAS0# RAS1# RAS2# DOE# DWE# DB0 DB1 DB2 XIN XOUT DCLK DMA0 DMA1 DMA2 DMA3 DB13 DB12 DB11 DB10 DB9 DB8 DSCK DB3 DB4 DB5 DB6 DB7 DB15 DB14 RESET# WRLL# VCC GND R43 0 VCC R19 8 7 6 5 8 7 6 5 8 7 6 5 U10 RESET GND NC EN VCC 1 2 3 4 5 RESET# R37 OPEN\0 R36 OPEN\0 10x4 RESET# (3) 10x4 10x4 100K IR VCC VFD-DATA VFD-CLK VFD-CS J2 1 2 3 4 5 6 IR +5V VFD-DATA VFD-CLK VFD-CS GND LA20 LCS2# R48 R45 0 ROM EMULATOR SOCKET OPEN 1 3 RESET CLK/CE1 WE ADDR/CE1 2 4 LA21
4-PIN EXTENSION FOR ROM EMULATOR INTERFACE
RAS1# RAS2#
RN1
RN2
RN3
27M C14 27PF C15 1000PF 1 2 3 4
EM-MARIN RESET IC
GND
U10 AAT3521 V6300 R36 OPEN 0 R37 0 OPEN
HDR6-100
27PF
GND
GND
GND
GND
MA8 MA9 MA10 MA11
MA0 MA1 MA2 MA3
MA4 MA5 MA6 MA7
4Mx16 SDRAM (9ns)
32/64MBIT SDRAM
AAT3521 SOT-23(5pin) U11 GND 1 RESET 2 VCC 3 AAT3520 SOT-23(3pin) GND
VESTEL
Title
1 2 3 4
1 2 3 4
Vibratto-ll ES66X8
Size C Date: Document Number
VESTEL-4250H-A1
Wednesday, March 03, 2004 Sheet 2 of 5
Rev A1
DIN (2) DIP (2) CC40 0.1U CC42 0.1U RFOUT CC48 820P RF50V CC44 0.1U RR34 RF50V CC45 0.01U 12K(1%) CC41 470P CC43 470P
RF50V
CC38 0.1U CC39 0.1U
RR52 (2) SVREF15 33 CC75 0.1U RFGND RR53 12K MVCC (2) SPDON RR98 RR88 RR97 MGND (2) DRVSB RR60 0 1 OPEN DD2 R 1K R
RFO (2)
UU3 BA5954FP/AM5868(OPEN) (2) FOCUS (2) SLEGN RR56 1K RR47 RR49 33K 47K FOCUS1 CON2 CON1 1 2 3 3.3K CC73 4700P MVCC RR108 DCLOADRR107 0 0(OPEN) 0(OPEN) 0 SLEDSLED+ MGND FOCUSFOCUS+ RR66 RR68 1(0805) FOCUS-1 1(0805) S12V DD4 LL6 1 FB 2 MGND 1 OPEN 8 9 10 11 12 13 14 VCC PVCC1 PGND VOSLVOSL+ VOFCGND GND VOFC+ PVCC2 VNFTK PGND VOLDVOLD+ VOTKVOTK+ 21 20 19 18 17 16 15 MVCC RR103 MVCC MGND MIRR (2) SLDC (2) J12 RR80 R HOMESW CC82 LOAD-/DCMOLOAD+/DCMO+ DCLOADDCLOAD+ SLEDSLED+ C RR78 OPEN CC80 MGND INSW (2) RR81 JJ2 0 OUTSW (2) 0.1U BA6287F ROHM MGND OPEN OPEN (2) HOMESW (2) MVCC DCLOAD+ 1 2 3 4 UU5 OUT1 VM VCC FIN GND OUT2 VREF RIN 8 7 MGND 6 5 CLOSE-1 RR89 1K CLOSE (2) DCLOADMVCC 0 RR104 OPEN LOAD-/DCMOLOAD+/DCMO+ TRACK-1 RR67 RR69 1(0805) 1(0805) MGND TRACKTRACK+ RR102 0 TRACKCC77 0.1U + CC78 100U/10V 4 5 6 7 VINFC CFCERR1 CFCERR2 VINSL+ VINSLVOSL VNFFC STBY BIAS VINTK CTKERR1 CTKERR2 VINLD PREGND 28 27 26 25 24 23 22 SPINDLE1 RR58 RR101 TRACK1 RR51 RR54 33K 47K CC72 100P 0 OPEN TRACK (2) STBY RR48 22K
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
UU2
RFGND RF33V CC50 0.1U
RFDC RFSIN ATOP ATON AIN AIP VPA RFAC BYP DIN DIP FNP FNN VNA MEV RX
OP2OUT SDEN SDATA SCLK V33 LCP LCN MNTR CE FE TE PI V25 V125 TPH DFT LINK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RFGND SCSJ SDATA SCLK CC54 0.047U CE FE TE SBA SVREF15 CC60 RF50V 0.1U RR41 0 LINK CEI (2) FEI (2) TEI (2) SBAD (2) TP23 MNTR SCSJ (2) SDATA (2) SCLK (2) MVCC OPEN FOCUSCLOSE-1
RR112 RR113 RR114 RR115
OPEN OPEN 0 OPEN
RR109 RR116
CC70 100P 0(OPEN) 0
CC51 2200P CC52 2200P CC53 2200P CC56 2200P CC57 120P
RR55
D C B A F E
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DVDFRP DVDRFN A2 B2 C2 D2 CP CN D C B A CD_D CD_C CD_B CD_A
SPINDLE (2) SVREF15 MVCC
ES6603
CD_F CD_E VPB VC DVDLD CDLD DVDPD CDPD VNB LDON MIRR MP MB MLPF MIN MEVO
1 DD5 OPEN
DCLOAD+ RR106 TP24 DEFCT SDEFCT (2) TP25 LINK RR105
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DD1 1 DVDLDO LL13 CC85 C FB (0805) QQ1 2SB1132 3 2
IN4148 RFGND CC64 1000P PVC DVDLD CDLD DVDMDI CDMDI 1K
MEVO CC63 0.22U RF50V CC65 CC66 160P CC67 33000P 0.01U
1
RR43
RFGND RR45 RR46 10 10
CC68 100U/16V RF50V CC69 100U/16V 1 1000P CC71 RFGND IN4148 RR50 5.1K
RFGND
2SB1132 QQ2 CDLDO LL10 CC84 C 1 FB (0805) 2
1 2 3 4 5 6 7 8 9 10 11 2.0MM
3
1 2
1 2
SLED+ SLED-
MGND
DD3 RFGND
2.0MM SBA SDATA SCSJ SCLK SVREF21 SVREF15 TP30 SBAD TP32 SCSJ TP34 SVREF09 TP31 SDATA TP33 SCLK TP35 SVREF15
RR11 BEFR_OP (2) RF50V RR83 LINK CN1 HOP-1200 PUH (JP24-0.5MM) CC6 0.1U CC9 100U/16V MEVO RR59 RR72 0 R RR75 R SVREF15 CC10 0 RR84 10K 470K CC29 RR85 0.47U R 2 3 CC34
56K 33P UU4A 4 TL3472 1 + ATR_OP (2) (2) SVREF21
28 26
RFGND 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TRACKTRACK+ FOCUSFOCUS+ DVDMDI RR35 100 DVDLDO CDLDO 100
GND GND
TRTR+ FOFO+ PD(MONITOR) VCC VR GND LD(DVD) LD(CD) VR GND(NC) PD GND RFOUT C B A D F E VCC VS(VCC) GND 25 27
GND GND
8
LOAD-/DCMORR70 10K
RR36 CDMDI
RR37 RR39 PVC RR40
RFOUT C B A D 3.3K F 3.3K E R SVREF21 (2)
RR71 1.5K RR73 1M OP2OUT MVCC
RR74 22K
RF50V 8 UU4B 7 TL3472 RR79 1.5K 4 RF50V RFGND CC81 0.1U RR82 22K RFGND
RR76 4.7K
CC62 0.1U MGND LOAD+/DCMO+ RR77 10K RFGND
OP2IN+ OP2IN-
5 6
+ -
MOCTL (2)
29 30
VESTEL
Title
ES6603 & Motor Drivers
Size C Document Number
VESTEL-4250H-A1
Wednesday, March 03, 2004 Sheet 3 of 5
Rev A1
MGND
Date:
A
B
C
D
E
6-CHANNEL AUDIO OUT
+3.3V
WOLFSON 6-CHANNEL AUDIODAC 2-CHANNEL AUDIO OUT
C272 0.1UF U38 1 2 3 4 5 6 7 8 9 10 RST VL SDATA SCLK LRCK MCLK M3 M2 M1 M0 AMUTEC AUTAAUTA+ VA GND AOUTB+ AOUTBBMUTEC CMOUT FILT+ 20 19 18 17 16 15 14 13 12 11 AOUT0L- (5) AOUT0L+ (5) AOUT0R+ (5) AOUT0R- (5) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 B50 0.1UF
B55 10UF
WOLFSON 2-CHANNEL AUDIODAC
VCCA
VCCA VCCA U31 CS4360 (2) TSD0 (2) TSD1 (2) TSD2 (2) TBCK (2) TWS (2) MCLK VLS SDIN1 SDIN2 SDIN3 SCLK LRCK MCLK VD GND RST DIF1 DIF0 M1 VLC MUTC1 AOUTA1 AOUTB1 MUTC2 AOUTA2 AOUTB2 VA GND AOUTA3 AOUTB3 MUTEC3 VQ FILT+ M2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AOUT0R- (5) AOUT0L- (5) AOUT1R- (5) AOUT1L- (5) AOUT2R- (5) AOUT2L- (5) U1 U2 TSD0 TSD1 TSD2 EAUX40 EAUX41 1 2 3 4 5 6 7 8 9 10
GNDA (2) EAUX43 (2) (2) (2) (2) TSD0 TBCK TWS MCLK
U32 PCM1606 DATA1 DATA2 DATA3 FMT1 FMT2 ZEROA AGND VOUT5 VOUT6 VOUT1 SCKI BCK LRCK DEMP1 DEMP0 VCC VCOM VOUT4 VOUT3 VOUT2 20 19 18 17 16 15 14 13 12 11 MCLK TBCK TWS EAUX43 EAUX42 U1 AOUT1R- (5) AOUT1L- (5) AOUT0R- (5) AOUT0L- (5) AOUT2R- (5) AOUT2L- (5)
4
4
(2) EAUX42 (2) EAUX41 (2) EAUX40 GNDA
CS4392 U1 U2 C273 0.1UF C258 10UF C259 10UF C274 C260 0.1UF 10UF
(2) (2) (2) (2)
EAUX43 EAUX42 EAUX41 EAUX40
GNDA
GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA
GNDA
T1 TP
T2 TP
T3 TP
T4 TP
GNDA VCCA C256 U30 CS4340
3
GND
GND
RFGND
GND
0.1UF 16 15 14 13 12 11 10 9 AOUT0L- (5) AOUT0R- (5) U1 U2
3
(2) EAUX43 (2) TSD0 (2) TBCK (2) TWS (2) MCLK (2) EAUX42 (2) EAUX41 (2) EAUX40
R71
33
1 2 3 4 5 6 7 8
RST MUTEC AOUTL SDATA SCLK/DEM1 VCCA VSS LRCK MCLK AOUTR DIF1 REF-GND DIF0 VQ DEM0 FILT+
GNDA
VCCA 1 B51 D23 10UF IN4148 D24 IN4148 1
+3.3V
3.3V REGUALTOR
VCC Q2 VCC33 RF50V +5V LL2 FERB 2 B15 0.1UF B16 0.1UF B17 0.1UF B18 0.1UF B19 0.1UF B20 0.1UF B21 0.1UF B22 0.1UF B31 10UF B33 10UF + CC7 100/10 CC11 0.1 GND RFGND RFGND LL1 FERB PLL33V 2 LL5 FERB RF33V GND VCC33 2 LL15 FERB VCC33V 2 U9 AMS1117 ADJ 2 4 OUT OUT IN 3 VCC33 +5V +12V -12V S12V VCC33 VCC33 MGND GND GNDA GND VCC33 GNDV LL3 2 OPEN VCC33 LL7 2 OPEN GND No need to install EZ1085 circuitry if J12 provide +3.3V GND LL8 3 C23 OPEN (10UF) IN ADJ OPEN OUT 2 R38 OPEN 1% (412 OHM) B2 OPEN (100UF) VCC33
FRONT
ES66x8
2
EZ1085
(EZ1085)
1
2
ADJ
INP
R39 OPEN 1% (681 OHM) GND
OUT
B23 0.1UF
B24 0.1UF
B25 0.1UF
B28 0.1UF
B29 0.1UF
B30 0.1UF
B32 10UF
2 OPEN GND 2 OPEN
RFGND LL9
SDRAM
VCC
VCC20 0.1UF B60
B34 0.1UF
B35 0.1UF
B36 0.1UF
B37 0.1UF
B38 0.1UF
B40 10UF
B43 0.1UF
B41 0.1UF
B62 10UF
B61 0.1UF
R67 412(1%) VCC20 TYP 2.5V ( 2.3V -- 2.7V )
1
1
MVCC GND GND VCC CC125 0.1 CC126 0.1 CC127 0.1 CC128 0.1 CC129 0.1 CC130 100U GND B45 0.1UF GND GNDA VCCA
LL14 2 LL11
FERB 2 FERB 2 FERB
24C01
R66 250(1%)
C16 0.1UF(OPEN)
LL12 VCC B3 220UF B4 220UF
8 7 6 5 4 3 2 1 B1 220UF GND GND 2.54MM JS3
1
+
GND
VESTEL
GND Title
ESS CONFIDENTIAL
A B
MISC
Size C Date:
C D
The information has been checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies. Circuit diagrams are provided as a means of illustrating typical applications; consequently complete information for construction purposes is not necessarily given. ESS reserves the right to make changes at any time in order to improve the design.
Document Number
VESTEL-4250H-A1
Wednesday, March 03, 2004
E
Rev A1 Sheet 4 of 5
A
B
C
D
E
1
3
(4) AOUT2R+
3 C275 680PF 4 2
C220 1 Rs_OUT 1 10UF R160 100K C224 22PF 1 R157 10 OHM RS (2) VDAC 1 C297 100uF/25 1
3
C263 10UF
U25-1 OPA2134UA
8
R331 10K R353 10K C276 3300PF
R337 680
V+ V-
R421 2K2 2
1 R430 2K2 Q36 BC848B 1 R427 75 R424 75 CVBS-OUT 1 (2) YDAC 1 C300 100uF/25 1 R433 1K8 2 1
+12V
VCCV
VCCV
R441 75 Q39 BC848B 1 1 R436 75 R434 75
4
G-OUT LUMA-OUT
1
-12V
4
R423 1K8 3
R12 (4) AOUT2RC261 10UF C262 10UF (4) AOUT1R+ 1 10K C189 open 1
R25
C178 680PF 1 R154 10K +12V U25-2 OPA2134UA 8 QUIET0 1 R163 470 2
680
Q23 2SC3327 1
GNDV
GNDV GNDV VCCV GNDV
R338 10K 1 R339 10K C278 3300PF
R397 680 5 C277 680PF 6
1
VCCV C214 R30 1 10 OHM (2) FDAC R150 100K C217 22PF 1 10UF LS 1 C298 100uF/25
1
1
3
7
Ls_OUT
3
V4
2 1
1
Q37 BC848B 1 R428 75 R426 75 CHROMA-OUT
(2) CDAC
1 C301 100uF/25 1
2
Q40 BC848B 1 R-OUT R444 75 R445 75
6 CVBS-OUT LUMA-OUT CHROMA-OUT 5 4 3
6 5 4 3 2 GNDV 2
1
-12V C279 (4) AOUT1R10UF 1 10K C235 open R175 1 680 1 10K R399 680 1 10K R400 10K
3
1
R186 R195
C211 QUIET0 680PF +12V U24-1 OPA2134UA 8
R153 1 470
R425 1K8 Q20 2SC3327
2 1
3
R437 1K8
GNDV GNDV GNDV
GNDV
1
(2) SCART-ON C221 1 VCCV 1 1 10UF R161 100K C225 22PF (2) UDAC 1 C299 100uF/25 1 3 R431 1K8 R158 10 OHM SUB 21 3 R429 2K2 2 1 VCC 10K R402 Q31 2N3904 1 C232 0.1UF GND +12V 1 R406 10K Q35 2N3904 1 1 2 D25 IN4148 R401 10K 3 1 FL FR R403 3 330 2 +5VA Q30 8550 1 3 CVBS-OUT R-OUT G-OUT B-OUT J1 1 2 3 4 5 6 7 8 9 10 11 CON24 GND R405 100K
C281 (4) AOUT1L+ 10UF 1
R398
3 C282 680PF 4 2
V+
1 LFE_OUT
V-
C283 3300PF R197 1 C177 open 680 1 10K R410 680 1 5 C286 680PF 6 R13 C172
1
Q38 BC848B 1 R435 75 R432 75 B-OUT
+5VA FB3 FB
2
1
V+
R422 2K2
R438 2K2
1
P1
3
-12V C284 (4) AOUT1L10UF 1 11K R196
1
QUIET0 680PF +12V U24-2 OPA2134UA
1
R164 470
Q32 8550 3 1 1 1
Q33 8550
2 1
Q24 2SC3327
1 1
GNDV
GNDV
(2) NN
R408 10K
3
1 2
R404 10K
8
C285 (4) AOUT2L+ 10UF 1
R409
2 R420 1 10K
V+
7 C_OUT
C215 1 1
R148 CC 10 OHM R151 100K C218 22PF
+12V
1
1 1 R165 6.8K 1 D5 IN4148 R167 2.2K 1 +5VA QUIET0 R171 1K 1 1 2 3 Q26 8550 1 D7 Q27 2N3904 1 IN4148 100K VCC 1 R174 1 -12V 2 3 1 C226 470uF Q25 8550 +12V
1
R412 10K C287 3300PF 1
3
10K
GND 1 R411 820 R413 1.2K
GND 2 1
V4
10UF
IN4148 D6 1 C227 220uF/25 R170 1K 1 1 R173 OPEN
Q34 2N3904 1
R407 10K
SCART-ON (2)
-12V C180 R16 C181 open 1 10K 680PF 3 C288 (4) AOUT2L10UF 1 10K R14 1 R15 680 QUIET0 1 R155 470 2 1
GND
GND
Q21 2SC3327 +5VA
+12V U23-1 OPA2134UA
3
R176 470 R156 1 10 OHM 1 10UF R159 100K C223 22PF FR
U27A 1 7404 U27B C228 (2) SPDIF 0.1UF 7404 1 7404 7404 7404 U27F R172 1M 13 P9 RCA CONN 4 1 3 1 330 OHM R179 91 OHM +5VA 1 2 0.1UF R178 C230 7404 12 3 4 5 6 9 8 11 10 U27C U27D U27E 2
2
1 2
2
C289 (4) AOUT0R+ 10UF 1
R414 1 10K R416 10K 1
R415 680 3 C290 680PF 2
8
V+
1
C219
R166 10M
C291 3300PF
V4 -12V
(4) AOUT0R10UF
1 10K C185 open
1 1 R22 10K 680PF
QUIET0
1
R162 470
3 2 1 Q22 2SC3327 +12V
C292
R20
R21 680
C184
P3 RCA CONN 6
+12V U23-2 OPA2134UA C236 0.1UF R29 1 10 OHM R149 100K C216 22PF -12V 1 10UF FL GND P2 GND 1 2 3 4 5 6 7 8 9 VCC VIN QUIET0 1 R28 10K 680PF R152 1 470 3 2 1 Q13 2SC3327 C173 0.1UF C174 0.1UF C193 0.1UF C175 10UF C176 10UF MOFT3C2 3 2 1 1 1
1
C128 0.1UF
C191 0.1UF
C169 10UF
C170 10UF
C293 (4) AOUT0L+ 10UF 1
R417
R418680 1 R419 10K 1 C295 3300PF C294 680PF
8
5 6
V+
7
C213
GND
10K
V4
L21 47UH
-12V
1
C296 (4) AOUT0L10UF 1
R24 1 10K C190 open
R27 680
C188
R187 68 OHM C280 0.1UF
CC SUB
RS LS
FR FL
GND
GND
VESTEL
Title
OUTPUT
Size C Date:
A B C D
Document Number
2
VESTEL-4250H-A1
Wednesday, March 03, 2004
E
Rev A1 Sheet 5 of 5