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San Antonio
VP BUILD
2005 1215

EE DRAWER DESIGN CHECK RESPONSIBLE 3 SIZE = FILE NAME : XXXX-XXXXXX-XX XXXXXXXXXXXX P/N

DATE

POWER

DATE

INVENTEC
TITLE

San Antonio 10
DOC. NUMBER REV

VER :

SIZE CODE

A3

CS
SHEET

TC8703
1 OF 65

A03

DATE

CHANGE NO.

REV

TABLE OF CONTENTS

PAGE 1.COVER PAGE 2.INDEX 3.BLOCK DIAGRAM 4.POWER SEQUENCE BLOCK 5-12.SYSTEM POWER 13.CLOCK GENERATOR 14.CPU Yonah1 15.CPU Yonah2 16.CPU Yonah3 17.CPU Yonah4 18.FAN & THERMAL CONTROLLER 19.N/B Calistoga 1 20.N/B Calistoga 2 21.N/B Calistoga 3 22.N/B Calistoga 4 23.N/B Calistoga 5 24.N/B Calistoga 6 25.DDR2 DIMM0 26.DDR2 DIMM1 27.DDR DAMPING 28.VGA CONN 29.CRT CONN 30.SVIDEO CONN 31.LCD CONN

PAGE

PAGE

56.LINE IN & LINE OUT 32.S/B ICH7 1 57.MDC 1.5 CONN 33.S/B ICH7 2 58.DOCKING 1 34.S/B ICH7 3 59.DOCKING 2 35.S/B ICH7 4 36.S/B ICH7 5 60.SWITCH & LED (MB) 37.CARDBUS CONTROLLER 61.SWITCH & LED (DB) 38.PCMCIA & EXPRESS CARD 62.PICK BUTTON BOARD 39.5 IN 1 CARD SLOT 63.PARALLEL PORT BOARD 40.1394 CONTROLLER 64.USB BOARD 65.DRILL HOLE 41.LAN CONTROLLER-1 42.LAN CONTROLLER-2 43.RJ45 & TRANSFORMER 44.MINI CARD CONN 45.3D Sensor & SATA HDD CONN 46.ODD CONN 47.USB CONN 48.BLUE TOOTH CONN 49.TPM 1.2 50.SUPER I/O 51.Serial & Parallel port CONTROLLER 52.K/B & D/B CONN 53.CIR & FIR 54.AZALIA CODEC 55.AUDIO AMP & MIC & HP

INVENTEC
TITLE

San Antonio 10
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
2 OF 65

A03

Yonah
(uFCPGA)

ICS9LPR316 Clock generator

S-video LCM CRT

FSB, 533/667 MHz

DDR2_SODIMM0
1.8V, DDR2 Interface, 533/667 MHz 1.8V, DDR2 Interface, 533/667 MHz

DDR2_SODIMM1

Calistoga
945GM/PM 1466 uFCBGA
SATA DMI x4

HDD ODD
FINGER PRINT

Primary_IDE

Express Card

CONN D (DB)

CONN A (MB)

CONN B (MB)

CONN C (DB)

DOCKING

3.3V, PCI_Interface,33MHz

Bluetooth

USB3

USB2

USB6

USB7

USB0

USB1

USB4

USB5

ICH7-M
652 BGA

PCI_EXPRESS

3.3V, AZALIA

PORT REPLICATOR
MDC / Modem Module 56K AZALIA

3.3V, LPC_Interface,33MHz

INTEL 10/100 82562GZ 1G 82573E(AMT) 82573L(w/o AMT)

MINI CARD Wireless LAN

CARD BUS TI_PCI7412/PCI4512 (CO-LAYOUT)
EXPRESS CARD

RJ45

ANT

ANT

Cardbus SLOT A

Card reader CONN

1394 CONN

BATTERY RJ11 System Charger & DC/DC System power (IMVP-6 VR) MIC JACK HP JACK SPEAKER

SMSC KBC1122

3-AXIS SENSOR

TPM 1.2

SMSC SIO 1036

BIOS FLASH ROM

SERIAL PORT

PARALLEL PORT

FIR

INVENTEC
TITLE

CIR
A3
CHANGE by Drawer_Name 28-Nov-2005

San Antonio 10
DOC. NUMBER REV

SIZE CODE

CS
SHEET

TC8703
3 OF 65

A03

DSKDC

+VBAT
5V

+V5S +V5A +V3S
SKIP#

+VADPTR 3V +V3A

+V2.5S

+VPACK
SCL SDA ACOK

+V1.5S
EN_PSV

1.5V

+V0.9S
EN_PSV

1.8V

+V1.8

+VCCP
EN_PSV

VCCP

+VCC_CORE

INVENTEC
TITLE

San Antonio 10
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
4 OF 65

A03

Q512 +VADPTR
5-

1 1 C569 2 1uF_25v 2 R601 47K_5%

1 2 3 4

S

D

CN503 1 1 2 2 3 3 4 4 JST_S4B_EH_4P

G

8 7 6 5

FUSE503 1 2 10A_125V

59-,58-

DCOUT

AM4825P_AP C570

1 C1 2 10pF_50v

1 2

C2 0.1uF_25v

1 R602 4.7K_5% Q509 2 SSM3K17FU D S

1 2 0.1uF_25v

+VBAT
28-,10-,9-,8-,7-,6-

DSKDC
58-

DCPWEN 1 2 D509 3

50-

GG

D

L3007 NFM60R30T222

1 4 2 3 4 3

1

L3006 NFM60R30T222

S

2

PDS1040_10A_40V +VADPTR
5-

1 D508 3 2 PDS1040_10A_40V

FUSE502 1 2 10A_125V

1 R616 2 0.01_1%_1W C599 C596 1 0.1uF_25v 2 1 2 0.1uF_25v 1 2 C597 0.1uF_25v 1 C568 1 C576 2 10uF_25v_K_X5R 2 1 C567 1 C575

Q519 AM4825P_AP 1 S D 8 2 7 3 6 4 5 G

2 10uF_25v_K_X5R 2 0.1uF_25v 10uF_25v_K_X5R

CHARGE_GND

CHARGE_GND

U511
ACDRV# 2 23 24 32

1

R619 10_5%

2

12

VCC SYS

1 DTA143EKA 1 B 2 C E Q513 3 Q514 D510 1 3 2
B C E 1

1 C578 R618 432K_1% 2 2.2uF_25v +V5LA
CHARGE_GND 53-,18-,7-,6-

3 4 6

ACN ACP BYPASS#

BATDRV# PVCC

Q511 1 2 8 10_5% R635 2 C595 1 3 BAT54 3
D1 S1_D2

+VPACK
6-

2

HIDRV 5 11 10 ACDET VREF5 AGND TS PH BTST REGN LODRV PGND SYNP SYNN SRP SRN BAT EAO

30 29 31 1

G1

5 6 7 4

D512 28
27 26 22 21 20 19 18 7 8 9 16 33

0.1uF_25v C598 1 2 1 2 1uF_25v

G2 S2

L512 1 2 PCMB104T_100MS 1 C594 2 10uF_25v_K_X5R

Q518 8 7 6 5
D S

1 R634 2 0.01_1%_1W 1 C593

G

1 2 3 4

2 AM4825P_AP 10uF_25v_K_X5R C602 1 2 0.1uF_25v

1 R637 47K_5% 2 C606 1 1

RLZ18C 2 DTC124EK 1

2

1 C577 R617 42.2K_1%2 OPEN

1

SP8K10SFD5_ROHM

R641 8.06K_1%
2 1 6-

15

THRM1
1 CHGEN#

1uF_10v 2 R642 100K_5%
2 1

R639 39.2K_1%
50-

BATT_IN

1 2 1 R640 18K_5% 1 R638 100K_5% 1 2 R643 200K_5% 2 1 2 C607 100pF_50v 1 C579 2 56pF_50v 1 C580 2 1500pF_50v 2 1

C601 0.1uF_25v

1 2

C604 0.1uF_25v

1 2

C603 0.1uF_25v

ACPRES

50-

2
2

R6676 22.6K_1%

14 13 25 17

SCL SDA ALARM# IOUT

EAI FBO ISYNSET TML

CHARGE_GND

CHARGE_GND

CHARGE_GND

CHARGE_GND CHARGE_GND

TI_BQ24721_QFN_32P

R620 10K_5%

NEAR IC

+V3A
60-,58-,50-,47-,44-,43-,38-,35-,34-,33-,14-,12-,11-,71 R695 2

2

10K_5% R636 0_5%

CHG_EN

50-

1

2

BATT_CLK BATT_DATA

50-,18-,650-,18-,6-

CHARGE_GND

INVENTEC
TITLE

San Antonio 10
DC &BATTERY CHANGER
DOC. NUMBER REV

SIZE CODE

A3
Drawer_Name 1-Dec-2005

CS
SHEET

TC8703
5 OF 65

A03

+VPACK
5-

FUSE501 1 2
550-,18-,550-,18-,51

CN6 G G2 7 7 G G1 6 6 5 5 4 4 3 3 2 2 1 1 TYCO_1747602_1_7P

THRM1 BATT_DATA BATT_CLK

R5002

2

1K_5%

LITTLEFUSE_R451012_12A_65V

1 3 D503 AZ23C6V2 2 1 C541

2 1000pF_50v

+VBAT
28-,10-,9-,8-,7-,5-

1 R8 1M_5% 2 U1 3 2 1 R7 56.2K_1% 2 1 LTH GND HTH RESET# VCC 4 5
7-

+V5LA
53-,18-,7-,5-

+V5AUXON

GMT_G680LT1_SOT23_5P 1 2 C10 0.1uF_10v

1 R6 180K_1% 2

INVENTEC
TITLE

San Antonio 10
BATTERY CONN
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
6 OF 65

A03

1

R9

2

4.7_5% 1 2 1 C12 4.7uF_25v 2 C11 2.2uF_25v
1

R18

2

C13 1 2 0.1uF_25v

1 C629 1 C25 2 4.7uF_25v Q2 2 1 4.7uF_25v 2 1 2 8 3 C63 68uF_25v +V3LA
60-,50-,47-,32-,18-,7-

2.2_5%

1

SLP_S3#_3R

50-,47-,33-,12-,112 1

R627 0_5% 1 C586 2 4700pF_50v
1

D1

G1

S1_D2

5 6 7 4

2 1 MPLC0730_4R7

L513

PAD500 2 1 POWERPAD_2_0610 1

R626 29.4K_1%
2

G2 S2

R630 10K_1% +VBAT
28-,10-,9-,8-,6-,5-,72 2 1

2

1

1

C18
2

R15

1

10K_1%

2

15.8K_1% R10

R625 330_5%

SP8K10SFD5_ROHM
2

C612

1 2 C613 1uF_10v

R11

2 330uF_6.3v

R13 100K_5%
1

C17 0.01uF_16v 2 1

1 2 2.7K_5% 0.033uF_16v

U2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INV1 COMP1 SSTRT1 SKIP# VO1_VDDQ DDR# GND REF_X ENBL1 ENBL2 VO2 PGOOD SSTRT2 COMP2 INV2 VBST1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN TRIP2 VREG5 REG5_IN OUTGND2 OUT2_D LL2 OUT2_U VBST2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

+V5LA
53-,18-,6-,5-,7-

+VBAT 1 2 C15 1uF_6.3v +V5A
28-,10-,9-,8-,6-,5-,7-

+V5AUXON

6-

1

R6685 2 1 2

C588 0.1uF_16v 1 2 C16 0.01uF_16v 1
2 2

60-,59-,50-,47-,35-,28-,12-,11-,9-,8-,7-

10K_5% 3
1

THRM_SHUTDWN#

50-,28-,18-

5 6 7 8
D G S

D511 BAT54C EC_PW_ON
501

2 R629
2

R17

R14 1

1

2

1.8K_5%

TI_TPS51020DBT_TSSOP_30P

Q4

1 C631 2

1 C27 2 4.7uF_25v L1 1 2 PCMB104E_4R7MS 1 C21 1 2 1uF_10v C20 PAD1
POWERPAD_2_0610

+V5A
60-,59-,50-,47-,35-,28-,12-,11-,9-,8-,7-

R16

2

1M_5%
2 1

10K_5%

R624

1

C19 3900pF_50v
1

0_5%

10K_1%
1

R12

2

C14 1 2 0.1uF_25v

4 3 2 1 RSS090N03_ROHM 56 7 8 D
G S

10uF_25v

2.2_5% 51.1K_1% R628
TPS51020

R623 220_5%
2

2

Q5 FDS6680S

1 2

C587 6800pF_25v

43 2 1

2 330uF_6.3v

1

+V3LA +V5LA
53-,18-,6-,5-,760-,50-,47-,32-,18-,7-

+V3A 4 3 Q521
S D

1

G

1 2 5 6

60-,58-,50-,47-,44-,43-,38-,35-,34-,33-,14-,12-,11-,5-

R646 10K_5%
2

D514 1 3 BAT54 R645 2 1 C611

GG

Q524 D D
S

FDC638P Q522 4 S D 1 2 5 3 6 G FDC638P
1

1

SSM3K17FU S

100K_5%

R644 200_5%
2

2 0.1uF_10v

GG

Q523 D D
S

SSM3K17FU S

INVENTEC
TITLE

CLOSE TO PAD4
CHANGE by Drawer_Name 5-Dec-2005

San Antonio 10
SYSTEM POWER(3V/5V)
DOC. NUMBER REV

SIZE CODE

A3

CS
SHEET

TC8703
7 OF 65

A03

+VBAT
28-,10-,9-,7-,6-,5-

+V5A
60-,59-,50-,47-,35-,28-,12-,11-,9-,710mil

C220 1 2 OPEN
1 1 1

15mil 40mil 15mil

5 6 7 8 SLP_S3#_5R
28-,12-,91

R160 OPEN R157

D G S

1 Q9 2
RSS090N03_ROHM

C147

1

C146

2 2

R155 100K_5%

R153 10_5%
2

R158 232K_1%
2

2 4.7uF_25v 10uF_25v_K_X5R +VCCP
35-,32-,24-,23-,21-,20-,16-,15-,14-,13-,9-

U10
1 10mil 10mil 10mil 101 2 3 4 5 6 7 EN_PSV TON VOUT V5FILT VFB PGOOD GND VBST DRVH LL TRIP V5DRV DRVL PGND 14 13 12 11 10 9 8 15mil 15mil 15mil 10mil 15mil 15mil 15mil 1

PWR_GOOD_3

11-

2

R159

2

C218

4 3 2 1 PAD4

10K_5%

1 2 2.2_5% 0.1uF_25v 1 R156 2 10K_1%
VCCPGND

1 L12 2 PCMB104E_2R2MS 5 6 7 8
D G S 1

12A250mil

12A250mil

MCH_GOOD

C216 1 1uF_6.3v 2
2

1 C219 2 OPEN
10mil

TI_TPS51117PW_TSSOP_14P 1 C217 2 1uF_6.3v

Q10 FDS6676AS

1 R151 2 40.2K_1%

C208
OPEN

POWERPAD_2_0610

2

1 2 C210

1

C221
10uF_6.3v

R154 0_5%

1

4 3 2 1
VCCPGND

2

1

R150 100K_1%
2

220uF_2v_15mR_Panasonic

VCCPGND

+V3S
58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,18-,13-,12-,11-,10-,9-

+V2.5S
28-,23-

1 2

C735 4.7uF_6.3v

Q541 6 D 5 2 1

S

4 3
1

PAD504
POWERPAD_2_0610

G

R775 0_5%

2

AM3446N

1 2

C723 OPEN

1 R772

10.2K_1%
2

+V5S
60-,58-,52-,51-,50-,46-,45-,39-,38-,37-,35-,33-,31-,29-,18-,12-,101 R774 1 R773

1 2 U518
1 REF ANODE 2 CATHODE 3

C724 10uF_6.3v

1 2

C722 OPEN

10K_1%
2

2.4K_1%
2

TEC_AZ431LANTR_E1_SOT23_3P

INVENTEC
TITLE

SYSTEM POWER (+V2.5S / +VCCP)
SIZE CODE DOC. NUMBER REV

San Antonio 10
CS
SHEET

A3
CHANGE by Drawer_Name 28-Nov-2005

TC8703
8 OF 65

A03

+VBAT
28-,10-,8-,7-,6-,5-,9-

R22 143K_1%
1

R23 100K_1%
1 2

2

R26 100K_1%
2 2 1 2

R27 102K_1%
1

1 2 C30 OPEN

R25 OPEN
51124GND 1 51124GND

2 C31

1 OPEN

12-

SLP_S5#_5R +V1.8_VRAM
28-,9-

1

R20 0_5%

2

+V5A
60-,59-,50-,47-,35-,28-,12-,11-,8-,7-,92 1

+V5A
60-,59-,50-,47-,35-,28-,12-,11-,8-,7-,9-

1

R28 0_5%

28-,12-,82

SLP_S3#_5R

10uF_25v_K_X5R 1 1 C628 1 2 C24 98 7 6 5
D G

C29 OPEN

VFB2

TONSEL

VFB1

2 Q527

1 R21 OPEN 2

6

5

4

2

3

1

R24 OPEN

1 R30 OPEN 2
GND 25 24 23 22 21 20 19 1

1 2

C32 OPEN 1 C26 2 1 C630 +V1.5S
44-,38-,35-,33-,28-,24-,23-,20-,16-,11-,9-

VO2

GND

VO1

PAD502
POWERPAD_2_0610

2 4.7uF_25v

7 8

2 10uF_25v_K_X5R 4.7uF_25v

PGOOD2 EN2 VBST2 DRVH2 LL2 DRVL2

PGOOD1 U3 TI_TPS51124RGER_QFN_24P

+V1.8
26-,25-,24-,19-,11-,9-

S

EN1

C28 1 2 0.1uF_25v

1 2 3 4 RQW130N03_PSOP_8P PAD501 1 L515 2

1

R19

2

9 10 11 12

VBST1 DRVH1 LL1 DRVL1 PGND2 PGND1 V5FILT TRIP2 TRIP1 V5IN

R29

2

C33 1 2 0.1uF_25v 1 2 8 3

Q3
D1 S1_D2

2.2_5%

2.2_5%

G1

5 6 7 4

POWERPAD_2_0610

PCMB104E_2R2MS
1

1 L517 2 PCMB104E_4R7MS

PAD503
POWERPAD_2_0610

G2 S2

98 76 5 1 D516 2 SSM34_3A40V
D G S

14

15

16

13

17

1 C640 10uF_6.3v 2

1 2

18

R697 OPEN C627
2

Q528

+V5A

SP8K10SFD5_ROHM

1

R710 OPEN
2

12 3 4 ROHM_RQW200N03FD5_PSOP_8P 1

2

1

1 1 C37 C641 2

1

C654

330uF_2v_15mR_Panasonic 1 C639

1

2 OPEN R34 13.3K_1%
2

2

2

C36 1uF_6.3v

R35 10_5%

2 10uF_6.3v 1 C655 2 OPEN

2 4.7uF_6.3v 220uF_2v_15mR_Panasonic

R36 19.1K_1%
1

1

R33 0_5%

2

51124GND

+V1.8
26-,25-,24-,19-,11-,9-

+V1.8
26-,25-,24-,19-,11-,9-

+V3S

+V1.8

+V1.5S

+V1.8
26-,25-,24-,19-,11-,9-

+VBAT
28-,10-,8-,7-,6-,5-,9-

44-,38-,35-,33-,28-,24-,23-,20-,16-,11-,926-,25-,24-,19-,11-,958-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,18-,13-,12-,11-,10-,8-

C5077 1 2 330pF_50v C5078 1 2 330pF_50v C5079 1 2 330pF_50v C5080 1 2 330pF_50v C5081 1 2 330pF_50v C5082 1 2 330pF_50v

C5083 1 2 0.1uF_10v C5084 1 2 0.1uF_10v C5085 1 2 0.1uF_10v C5086 1 2 0.1uF_10v

C5089 1 2 0.1uF_10v C5090 1 2 0.1uF_10v C5091 1 2 0.1uF_10v

C5092 1 2 0.1uF_25v

+V1.8_VRAM
28-,9-

C5093 +VCCP
35-,32-,24-,23-,21-,20-,16-,15-,14-,13-,8-

1 2 0.1uF_25v

C5087 1 2 0.1uF_10v

FOR EMI

C5088 1 2 0.1uF_10v

INVENTEC
TITLE

San Antonio 10
DOC. NUMBER REV

SYSTEM POWER(+V1.5S / +V1.8)
SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
9 OF 65

A03

+V3S
58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,18-,13-,12-,11-,9-,8-,10-

SLP_S3#_3R

D527 3

BAT54 1 5 U523-A 6

D526 3

BAT54 1 3 1 2 C816 0.22uF_10v

2 1 C779 0.1uF_16v 5 U523-B 4
33-

VR_PWRGD_CK410

18-,13-,10-

1

R858

2

1 1 C817

560K_1%

1 R927 2 511K_1%

+V5S
60-,58-,52-,51-,50-,46-,45-,39-,38-,37-,35-,33-,31-,29-,18-,12-,8-

2 FAIR_NC7WZ17_SC70_6P 2 0.22uF_10v +VBAT
28-,9-,8-,7-,6-,550-,33-,19-

2

PM_PWROK FAIR_NC7WZ17_SC70_6P

SB_3S_VRMPWRGD

MAX8770_VCC

10-

1

R818

2

1 4 1 C725 2 4.7uF_6.3v 3 2

10_5% C738 +V3S 2.2uF_10v 1 2

L3004 NFM60R30T222 10uF_25v_K_X5R C107 1 1 2 2 C108 1

+VBAT_CPU

58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,18-,13-,12-,11-,9-,8-,10-

C105 1

C676

5 6 7 8
D G

1

CPU_GND 1

R857 10K_5%
2

R860 OPEN
2

U519
19 VCC VDD 25

2 2 0.01uF_50v 0.01uF_50v R6672
1 2

Q530 4 3 2 1 FDS6294 0_5% 1 L6 2

S

+VCC_CORE
16-

IMVP_CKEN# VR_PWRGD_CK410 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PSI# H_DPRSTP# PM_DPRSLPVR MCH_GOOD

1318-,13-,1016161616161616-

1

R859 OPEN

2

1 2 TP751 31 32 33 34 35 36 37

TON CLKEN# PWRGD D0 D1 D2 D3 D4 D5 D6 BST1

8

1

R851

2

30

200K_5% 1 R822 2 2.2_5%

C727 1 2 0.22uF_16v Q531 FDS6676AS

56 7 8
D G S

5 6 7 8
D G S

SSM34_3A40V_OPEN
1 1

MPC1040LR45_TOKIN R6668 OPEN
2

1 D523 Q532 2

R42 2.4K_1%
2 1

1
2 1

TP748 TP752 TP749 TP753 TP750 TP754

DH1 LX1 DL1

29 28 26

C110

1

C679

1

C123

1 C5071 2 OPEN

R43

R44

4 3 2 1

4 3 2 1 FDS6676AS

2

1532-,1533-,198-

R856 R825 R823 R824 C778 C739 R852

1 1 1 1

2 2 2 2

0_5% 0_5% 470_5% 0_5% 470pF_50v 0.22uF_6.3v

3 40 39 38

27 PGND1 18 GND 17 CSP1 16 CSN1 FB 12 CCI BST2 10 20 21 22 24 23 1

6.2K_1% 10K_1%_THER_NTC C62 1 2 0.22uF_10v

2 2 330uF_2v_6mR

2 330uF_2.5v_OPEN

330uF_2v_6mR

PSI# DPRSTP# DPRSLPVR SHDN#

1 R821
2

C740

C726 1 2 0.22uF_16v

1

1

2 OPEN

1 2 1 2
1 1 2 2 2

9 11 7 6

CCV DH2 REF LX2 TIME DL2 THRM PGND2

2.2_5%

R820 OPEN 2 470pF_50v 2 1 C777
1

R819 3.24K_1%
2 1

CPU_GND

71.5K_1% 10K_5% OPEN
33-

CPU_GND

MAX8770_VCC

10-

R854

R850 1 C737 20K_5%2 OPEN

1 C736

10uF_25v_K_X5R 5 6 7 8
D G S

R853 1 VRHOT#
1

2

2

R816 2 1000pF_50v C678 C675 C106 C677 10_5% 1 1 1 1
CPU_GND

5 2 4

VRHOT# POUT#

CSP2 14 15 CSN2 GNDS 13 41 THERMAL 16-

2

2

R855 OPEN

VCCSENSE

2 2 0.01uF_50v 0.01uF_50v R6671
1 2

1 C780 2 OPEN

Q533 4 3 2 1 FDS6294 0_5% 1 L10 2

MAX_MAX8770_TQFN_40P 56 7 8
D G G S S

SSM34_3A40V_OPEN 5 6 7 8
D

1

1

MPC1040LR45_TOKIN 1 R141 1 1

1 D524 Q535 2

R6670 OPEN
2

CPU_GND

CPU_GND

R139 2.4K_1%
2

C109

C680

C122

Q536 FDS6676AS

4 3 2 1

4 3 2 1 FDS6676AS

1 C5073 2 OPEN

2 2 2 1 2 1 2 330uF_2v_6mR 330uF_2.5v_OPEN 6.2K_1% 10K_1%_THER_NTC 330uF_2v_6mR C187 1 2 R140 0.22uF_10v

1

R849 0_5%

2

1

R817

2

16-

VSSSENSE

1

C741

10_5% 1 C742

2 OPEN

CPU_GND

2

CPU_GND

1000pF_50v

INVENTEC
CPU_GND

TITLE

San Antonio 10
CPU POWER(VCC_CORE)
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 14-Dec-2005

CS
SHEET

TC8703
10 OF 65

A03

+V5A
60-,59-,50-,47-,35-,28-,12-,9-,8-,7-

+V1.8
26-,25-,24-,19-,9-

+V0.9S U3014 SLP_S5#_3R SLP_S3#_3R
50-,49-,38-,37-,33-,1211 10 9 8 7 6 VDDQSNS GND VIN VLDOIN VTT S5 PGND GND VTTSNS S3 VTTREF 1 2 3 4 5 28-,27-

PAD3
POWERPAD_2_0610

R138 50-,47-,33-,12-,71

0_5%

2

TI_TPS51100_DGQ_10P_OPEN

U8
11 10 9 8 7 6 VDDQSNS GND VIN VLDOIN VTT S5 PGND GND VTTSNS S3 VTTREF 1 2 3 4 5

M_VREF

26-,25-,19-

TI_TPS51100_DGQ_10P

1 C5099 1 C209 2 OPEN

1 C186

1 2

2 0.1uF_10v 2 1uF_10v

1 C185 22uF_6.3v 2

C207 22uF_6.3v

+V3A
60-,58-,50-,47-,44-,43-,38-,35-,34-,33-,14-,12-,7-,51

R846 1K_5%

+V3S
58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,18-,13-,12-,10-,9-,8-

2

+V1.5S
44-,38-,35-,33-,28-,24-,23-,20-,16-,9-

D528 1
1

BAT54 3
2

5 2 C774 0.1uF_10v 3

R845

U527 4 TC7SH14F
1

8-

PWR_GOOD_3

Q543
1 R5005 2

100K_5% 3
C E

2

B

1 2

1K_5%

1 2SC2411K

R6581 100K_5%
2

INVENTEC
TITLE

San Antonio 10
+V0.9S / POWER GOOD
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
11 OF 65

A03

+V3A
60-,58-,50-,47-,44-,43-,38-,35-,34-,33-,14-,11-,7-,5-

+V3
60-,57-,51-,44-

+V3S
58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,18-,13-,11-,10-,9-,8-

1 +V5S
60-,58-,52-,51-,50-,46-,45-,39-,38-,37-,35-,33-,31-,29-,18-,10-,8-,12-

C608 47uF_4v

2

Q520 1 7 D1 8 5 D2 6 3 1 C610 2
S1 S2

C609 47uF_4v R662 200_5%

2

2 G1

4 G2

1

1

R178 200_5%
1 2

FDS6875 3 D513

2 OPEN

1

1

R179 200_5%
2

R622 1 BAT54 220K_5% D
D

D9 3

+V5A
60-,59-,50-,47-,35-,28-,11-,9-,8-,7-,12-

+V5A

R926
1 1

2

60-,59-,50-,47-,35-,28-,11-,9-,8-,7-,12220K_5%

3 R848 200_5%

SSM3K17FU
28-

GG

BAT54 1

2

D8

S

S

2

Q525

SLP_S3_5R

BAT54 1SLP_S5#_5R D10 3

9-

U15-B 4 74ACT14MTC

14 3 7

50-,47-,33-,11-,7-

14 9 7

1 BAT54A

+V5A

+V5S

SLP_S3#_3R

U15-D 8 74ACT14MTC

2

60-,59-,50-,47-,35-,28-,11-,9-,8-,7-,12- 60-,58-,52-,51-,50-,46-,45-,39-,38-,37-,35-,33-,31-,29-,18-,10-,8-,12-

4 3

Q515
S D

+V5A
60-,59-,50-,47-,35-,28-,11-,9-,8-,7-,12-

2

G

1 2 5 6

R847 220K_5%
1

FDC638P 4 3 Q516
S D

SLP_S3#_5R

28-,9-,8-

U15-A 2 74ACT14MTC

14 1 7 C589 OPEN 1 2
G

1 2 5 6

FDC638P

C590

OPEN 1 2 Q517
D

+VAUDIO_5S
55-,54-

+V5A
60-,59-,50-,47-,35-,28-,11-,9-,8-,7-,12-

4 D515 1 2 C814 0.01uF_16v
1 1

S

R648 OPEN R647

2

3 3 1 BAT54_OPEN

G

1 2 5 6

FDC638P

2

220K_5% 2 1 C813 1 U15-C 6 14 5 7
50-,49-,38-,37-,33-,11-

C614

0.1uF_10v 74ACT14MTC

SLP_S5#_3R

2 OPEN

INVENTEC
TITLE

San Antonio 10
POWER(SLEEP)
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
12 OF 65

A03

+V3S
58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,18-,12-,11-,10-,9-,8-,13-

+V3S_CLKVDD NFM40P12C223 4 L524 Layout note: All decoupling 0.047uF disperse closed to pin 3 1 1 L522 2 2 BLM11A121S

1 1 2
35-,32-,24-,23-,21-,20-,16-,15-,14-,9-,8-

C749
0.047uF_10v

1 2

C748
10uF_6.3v

C753
10uF_6.3v

1 2

C734
10uF_6.3v

1 2

C791
0.047uF_10v

1 2

C750
0.047uF_10v

1 2

C751
0.047uF_10v

1 2

C794
0.047uF_10v

1 2

C792
0.047uF_10v

1 2

C752
0.047uF_10v

2

3333-

PCISTOP#_3 CPUSTOP#_3 R874 CLK_R_CPUBCLK CLK_R_CPUBCLK# R876 R877 CLK_R_MCHBCLK CLK_R_MCHBCLK# R930 MCH_CLK_REQ#
1 2

OPEN OPEN OPEN OPEN

R875 R878 R879 R880
VDDREF PCI_SRC_STOP# CPU_STOP# CPUCLKT0 CPUCLKC0 CPUCLKT1 CPICLKC1 CPUCLKT2_ITP_CLKREQC# CPUCLKC2_ITP_CLKREQD# SRCCLKT5 SRCCLKC5 SRCCLKT8 SRCCLKC8 SRCCLKT7 SRCCLKC7 SRCCLKT6 SRCCLKC6 SRCCLKT4 SRCCLKC4 GNDSRC GNDSRC SRCCLKT3 SRCCLKC3 SRCCLKT2 SRCCLKC2 SRCCLKT1 SRCCLKC1 LCDCLK_SST_SRCCLKT0 LCDCLK_SSC_SRCCLKC0 DOTT_96MHZ DOTC_96MHz 55 8 61 52 CLK_CPUBCLK 51 CLK_CPUBCLK# 2 33 R789 R788 R791 R792 1 1 1 1 2 2 2 2 10K_5% 10K_5% 12.1_1% 12.1_1% VDDSRC VDDCPU X1 X2 FSLA_USB_48MHZ FSLB_TEST_MODE REF1_FSLC_TEST_SEL PCICLK6 PCICLK4 PCICLK5 PCI_REFSEL_PCICLK3 SEL_REQ_PCICLK2 REF0_PCICLK1 SDATA SCLK SELSRC_LCDCLK#_PCICLK_F1 Vtt_PwrGd#_PD VREF CLKREQA# CLKREQB# GND GND GNDSRC GND GND GNDSRC GNDSRC GNDCPU 49 CLK_MCHBCLK 48 CLK_MCHBCLK# 45 44 35 34 43 42 39 38 37 36 30 31 28 29 26 27 22 23 20 21 18 19 13 14

1 1

2 2

12.1_1% 12.1_1% 12.1_1% 12.1_1%

1414-

+VCCP
2

1 1

2 2

Please place close to CLKGEN within 500mils R91 OPEN 30PPM
X504 1 2 5 24 41

U521
VDDSRC VDDSRC VDDPCI VDD48 VDD

1 1

2 2

212119-

1

2

+V3S
1 R815

CPU_BSEL1

15-

1 2

+V3S R798 1K_5%

C5033 1 33pF_50v 2

14.31818MHZ

1 2

C790 33pF_50v

DD
S

Q6013
G

10 16

G

10K_5% S R895 R896
1 1 2 2

38-

ICH_NEWCARD_CLKEN

SSM3K17FU 24.9_1% 24.9_1%
2828-

1

MCH_BSEL1 CPU_BSEL2
33-

1919-,15-

2

R751 1K_5%
1

R797
10K_5%
1 2 2 1

CPU_BSEL0 CLK_R3S_ICH48 CLK_R3S_CARD48

19-,153337-

50 CLK_3S_ICH48 57 56 11 15 59 6 2 3 1 62 60 54 53 1 1 1 2 2 2 10K_5% OPEN 24.9_1% CLK_3S_ICHPCI 9 46 64 2 0_5% 63 4 12 40 58 17 25 32 47 7

R892 CLK_R_PEG_REF CLK_R_PEG_REF# R894 R931 CLK_R_PEG_MCH CLK_R_PEG_MCH# R884 R885 CLK_R_PCIE_CARD CLK_R_PCIE_CARD# R886 R888 CLK_R_PCIE_ICH CLK_R_PCIE_ICH# CLK_R_SATA1 CLK_R_SATA1# R890 R811 R812

1

2

OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN

1 1

2 2

CLK_PEG_REF CLK_PEG_REF# CLK_PEG_MCH CLK_PEG_MCH# CLK_PCIE_CARD CLK_PCIE_CARD# CLK_PCIE_ICH CLK_PCIE_ICH# CLK_SATA1 CLK_SATA1# R813 R340
1 1 2 2

R882 R883

1 1

2 2

24.9_1% 24.9_1%

1919-

R868 10K_5%
1 2 2 R867 24.9_1% R872 10K_5% 1 1

CLK_R3S_ICH14

+V3S
R870 1 R869 1 2 10K_5% 2 OPEN

CLK_R3S_CBPCI CLK_R3S_MINICARDPCI CLK_R3S_SIOPCI CLK_R3S_KBPCI CLK_R3S_TPMPCI CLK_R3S_KBC14 CLK_R3S_SIO14 ICH_3S_SMDATA ICH_3S_SMCLK CLK_R3S_ICHPCI

3744515049-

R784 R785 R835 R6591 R836 R837

1 1 1 1 1 1 1 1

2 2 2 2 2 2

OPEN 24.9_1% 24.9_1% 12.1_1% 12.1_1% 24.9_1%

CLK_BSEL1 CLK_BSEL2 CLK_3S_CBPCI CLK_3S_MINICARDPCI CLK_3S_KBPCI CLK_3S_TPMPCI CLK_3S_KBC14

1

2

1

2

R887 R889

2 2

1 1

24.9_1% 24.9_1%

3838-

1 1

2 2

R833 10K_5%
2

R873 50R6586 5133-,26-,2533-,26-,25R834 R787 34R786

2 12.1_1% 2 12.1_1%

R891 R893 0_5% 0_5% R808 R810

2 2

1 1

24.9_1% 24.9_1% 24.9_1% 24.9_1%

3333-

1 1

2 2

2 2

1 1

3232-

IMVP_CKEN# VR_PWRGD_CK410

10-

1

2

Q539 D LAYOUT NOTES : THE IREF(PIN_46) SIGNAL VIA R715 CONNECT TO GND DIRECTLY. D 18-,10GG 41S LAN_CLK_REQ# 1 44CLK_REQB# SSM3K17FU S R881 4.7K_1%
2

CLK_PCIE_MINI1 CLK_PCIE_MINI1# CLK_PCIE_LAN CLK_PCIE_LAN# R838 R839
1 1 2 2

R871 1

24.9_1% 24.9_1%

4444-

R6422 CLK_R_PCIE_MINI1 CLK_R_PCIE_MINI1# R809 R805 CLK_R_PCIE_LAN CLK_R_PCIE_LAN# R806

1

2

1 1

2 2

SSCLK1_DREF SSCLK1_DREF# CLK_DREF CLK_DREF#

R803 R804

2 2

1 1

24.9_1% 24.9_1%

4141-

1

2

ICS_ICS9LPR316_TSSOP_64P

R799 R801 R794 R796

2 2

1 1

24.9_1% 24.9_1% 24.9_1% 24.9_1%

1919-

R800 SSCLK1_R_DREF SSCLK1_R_DREF# CLK_R_DREF CLK_R_DREF# R802 R793 R795

1

2

OPEN OPEN OPEN OPEN

1 1

2 2

BSEL0 BSEL1 BSEL2 FSB FSC FSA 1 1 0 1 0 0

FSB CLOCK FREQUENCY 533 667

HOST CLOCK FREQUENCY 133 166 SRCCLK8 CLKREQA# CLKREQB# CLKREQC# CLKREQD# SRCCLK7 SRCCLK6 SRCCLK5 X X X X SRCCLK4 X SRCCLK3 X SRCCLK2 X SRCCLK1 X

2 2

1 1

1919-

Close to CLKGEN

1

2

SRCCLK0 X

INVENTEC
TITLE

San Antonio 10
CLOCK_GENERATOR
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
13 OF 65

A03

H_A#(31:3)

21-

CN17-1
H_A#(3) H_A#(4) H_A#(5) H_A#(6) H_A#(7) H_A#(8) H_A#(9) H_A#(10) H_A#(11) H_A#(12) H_A#(13) H_A#(14) H_A#(15) H_A#(16)
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 K3 H2 K2 J3 L5 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 A6 A5 C4 D5 C6 B4 A3 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 B25 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD01 RSVD02 RSVD03 RSVD04 RSVD05 RSVD06 RSVD07 RSVD08 RSVD09 RSVD10 RSVD11 ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 D21 A24 A25 C7 R92 1 56_5% 2 21212121212121-

H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BREQ#0 H_INIT# H_LOCK# H_CPURST#
21-

+VCCP
35-,32-,24-,23-,21-,20-,16-,15-,13-,9-,8-,141

ADDR GROUP 0

R93 56_5%
2

CONTROL

IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM# BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# PROCHOT# THERMDA THERMDC

322121-

CLOSED TO CPU

H_REQ#(4:0)

21-

H_ADSTB#0
H_REQ#(0) H_REQ#(1) H_REQ#(2) H_REQ#(3) H_REQ#(4)

21-

H_RS#(0) H_RS#(1) H_RS#(2)

H_RS#(0:2)

+V3A
60-,58-,50-,47-,44-,43-,38-,35-,34-,33-,12-,11-,7-,5-

212121-

H_TRDY# H_HIT# H_HITM#

+VCCP
35-,32-,24-,23-,21-,20-,16-,15-,13-,9-,8-,141 1 1 1

H_A#(17) H_A#(18) H_A#(19) H_A#(20) H_A#(21) H_A#(22) H_A#(23) H_A#(24) H_A#(25) H_A#(26) H_A#(27) H_A#(28) H_A#(29) H_A#(30) H_A#(31)

XDP/ITP SIGNALS

ADDR GROUP 1

R907 240_5%
2

R716 R718 R715 56_5% 56_5% 56_5%
2 2 2

H_BPM5_PREQ# H_TCK TDI_FLEX H_TMS H_TRST# ITP_DBRESET#

33-

+VCCP
35-,32-,24-,23-,21-,20-,16-,15-,13-,9-,8-,14-

THERM

H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#
32323232323232-

21-

1818-

10mils/10mils
32-,19-,18-

H_THERMDA H_THERMDC PM_THRMTRIP#

1

1

R717 56_5%
2

R714 56_5%
2

THERMTRIP#

H CLK

BCLK0 BCLK1

A22 A21

1313-

CLK_R_CPUBCLK CLK_R_CPUBCLK#

RSVD12

T22

RESERVED

RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20

D2 F6 D3 C1 AF1 D22 C23 C24

+VCCP CPU GMCH ICH7

MLX_47170_4787_YONAH_479P

PM_THRMTRIP# should be without T at CPU

INVENTEC
TITLE

San Antonio 10
Yonah-1
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
14 OF 65

A03

H_D#(63:0)

21-,15-

CN17-2
H_D#(0) H_D#(1) H_D#(2) H_D#(3) H_D#(4) H_D#(5) H_D#(6) H_D#(7) H_D#(8) H_D#(9) H_D#(10) H_D#(11) H_D#(12) H_D#(13) H_D#(14) H_D#(15)
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23

21-,15-

H_D#(32) H_D#(33) H_D#(34) H_D#(35) H_D#(36) H_D#(37) H_D#(38) H_D#(39) H_D#(40) H_D#(41) H_D#(42) H_D#(43) H_D#(44) H_D#(45) H_D#(46) H_D#(47)
21212121-,15-

H_D#(63:0)

DATA GRP 0

H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#(63:0)

21212121-,15-

DATA GRP 2

H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#(63:0)

+VCCP
35-,32-,24-,23-,21-,20-,16-,14-,13-,9-,8-,151

H_D#(16) H_D#(17) H_D#(18) H_D#(19) H_D#(20) H_D#(21) H_D#(22) H_D#(23) H_D#(24) H_D#(25) H_D#(26) H_D#(27) H_D#(28) H_D#(29) H_D#(30) H_D#(31)

R760 1K_1%
2 1

H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_GTLREF

212121-

N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26 AD26

D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF

D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3

AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE6 32-,10-

H_D#(48) H_D#(49) H_D#(50) H_D#(51) H_D#(52) H_D#(53) H_D#(54) H_D#(55) H_D#(56) H_D#(57) H_D#(58) H_D#(59) H_D#(60) H_D#(61) H_D#(62) H_D#(63)
212121-

DATA GRP 1

DATA GRP 3

H_DSTBN#3 H_DSTBP#3 H_DINV#3

+VCCP
35-,32-,24-,23-,21-,20-,16-,14-,13-,9-,8-,15-

R761 2K_1%
2

C26

TEST1 TEST2

R767 R766 R720 R719

1 1 1 1

2 2 2 2

27.4_1% 54.9_1% 27.4_1% 54.9_1%
3221-

2

CLOSED TO CPU WITHIN 0.5" CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
19-,131319-,13-

D25

MISC

B22 B23 C21

BSEL0 BSEL1 BSEL2

DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#

H_DPRSTP#

CLOSED TO CPU H_DPSLP# H_DPWR# H_CPUSLP# PSI#

R56 OPEN
1

CLOSED TO CPU

32-

32-,2110-

H_PWRGD

MLX_47170_4787_YONAH_479P

1

1

R771 OPEN
2

R770 51_5%
2

NOTE: COM0, COM2, trace impedance should be 27.4 ohm COM1, COM3, trace impedance should be 55 ohm

INVENTEC
TITLE

San Antonio 10
Yonah-2
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
15 OF 65

A03

+VCC_CORE
10-,16-

+VCC_CORE
10-,16-

CN17-3 C118 C113 22uF_6.3v C114 C112 22uF_6.3v 22uF_6.3v C115
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC001 VCC002 VCC003 VCC004 VCC005 VCC006 VCC007 VCC008 VCC009 VCC010 VCC011 VCC012 VCC013 VCC014 VCC015 VCC016 VCC017 VCC018 VCC019 VCC020 VCC021 VCC022 VCC023 VCC024 VCC025 VCC026 VCC027 VCC028 VCC029 VCC030 VCC031 VCC032 VCC033 VCC034 VCC035 VCC036 VCC037 VCC038 VCC039 VCC040 VCC041 VCC042 VCC043 VCC044 VCC045 VCC046 VCC047 VCC048 VCC049 VCC050 VCC051 VCC052 VCC053 VCC054 VCC055 VCC056 VCC057 VCC058 VCC059 VCC060 VCC061 VCC062 VCC063 VCC064 VCC065 VCC066 VCC067 VCC068 VCC069 VCC070 VCC071 VCC072 VCC073 VCC074 VCC075 VCC076 VCC077 VCC078 VCC079 VCC080 VCC081 VCC082 VCC083 VCC084 VCC085 VCC086 VCC087 VCC088 VCC089 VCC090 VCC091 VCC092 VCC093 VCC094 VCC095 VCC096 VCC097 VCC098 VCC099 VCC0100 VCCP01 VCCP02 VCCP03 VCCP04 VCCP05 VCCP06 VCCP07 VCCP08 VCCP09 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCA AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26

PLACE THESE INSIDE SOCKET CAVITY ON L8 (NORTH SIDE SECONDARY)

1 2

1 2

1 2

1 2

1 2

22uF_6.3v

22uF_6.3v

1 2

C117

1 2

C121 22uF_6.3v

1 2

C111

1 2

C119 22uF_6.3v

1 2 22uF_6.3v

C120

22uF_6.3v

22uF_6.3v

1 2

C687

1 2

C691 22uF_6.3v

1 2

C688

1 2

C681 22uF_6.3v

1 2 22uF_6.3v

C683

+VCCP
35-,32-,24-,23-,21-,20-,15-,14-,13-,9-,8-

PLACE THESE INSIDE SOCKET CAVITY ON L8 SIDE (NORTH SIDE SECONDARY)

PLACE THESE INSIDE SOCKET CAVITY ON L8 (SOUTH SIDE SECONDARY)
1 2

22uF_6.3v

22uF_6.3v

1 2 +VCCP
35-,32-,24-,23-,21-,20-,15-,14-,13-,9-,8-

C154

1 2

C95

1 2

C93

1

C153

1

C94

1

C152

C684

1 2

C690 22uF_6.3v

1 2

C685

1 2

C689 22uF_6.3v

1 2 22uF_6.3v

C682

0.1uF_10v 1 2

0.1uF_10v

2 2 2 0.1uF_10v 0.1uF_10v 0.1uF_10v 0.1uF_10v

22uF_6.3v

22uF_6.3v

C116 330uF_2.5v

1 2

C151 NOTE: NO_STUFF OPEN 22UF X 12

+V1.5S
44-,38-,35-,33-,28-,24-,23-,20-,11-,9-,16-

PLACE THESE INSIDE SOCKET CAVITY ON L1 (NORTH SIDE PRIMARY)
1 2 OPEN C708 1 2 OPEN C706 1 2

C686 OPEN

VID0 VID1 VID2 VID3 VID4 VID5 VID6

AD6 AF5 AE5 AF4 AE3 AF2 AE2

10101010101010-

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

+V1.5S +VCC_CORE
10-,161

44-,38-,35-,33-,28-,24-,23-,20-,11-,9-,16-

1 2

C720 10uF_6.3v

1 2

C719 0.01uF_16v

R55 10_1%
2 10-

PLACE THESE INSIDE SOCKET CAVITY ON L1 (SOUTH SIDE PRIMARY)
1 2

C155

1 2

C705 OPEN

VCCSENSE

AF7

VCCSENSE

OPEN

VSSSENSE

AE7

10-

VSSSENSE

LAYOUT NOTE: PLACE C119 NEAR PIN B26

MLX_47170_4787_YONAH_479P
1

R70 10_1%
2

LAYOUT NOTE: ROUTE VCCSENSE AND VSSSENSE TRACE AT 27.4 OHM WITH 50 MIL SPACING. PLACE PU AND PD WITHIN 1 INCH OF CPU

INVENTEC
TITLE

San Antonio 10
Yonah-3
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
16 OF 65

A03

CN17-4
A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS001 VSS002 VSS003 VSS004 VSS005 VSS006 VSS007 VSS008 VSS009 VSS010 VSS011 VSS012 VSS013 VSS014 VSS015 VSS016 VSS017 VSS018 VSS019 VSS020 VSS021 VSS022 VSS023 VSS024 VSS025 VSS026 VSS027 VSS028 VSS029 VSS030 VSS031 VSS032 VSS033 VSS034 VSS035 VSS036 VSS037 VSS038 VSS039 VSS040 VSS041 VSS042 VSS043 VSS044 VSS045 VSS046 VSS047 VSS048 VSS049 VSS050 VSS051 VSS052 VSS053 VSS054 VSS055 VSS056 VSS057 VSS058 VSS059 VSS060 VSS061 VSS062 VSS063 VSS064 VSS065 VSS066 VSS067 VSS068 VSS069 VSS070 VSS071 VSS072 VSS073 VSS074 VSS075 VSS076 VSS077 VSS078 VSS079 VSS080 VSS081 VSS082 VSS083 VSS084 VSS085 VSS086 VSS087 VSS088 VSS089 VSS090 VSS091 VSS092 VSS093 VSS094 VSS095 VSS096 VSS097 VSS098 VSS099 VSS0100 VSS0101 VSS0102 VSS0103 VSS0104 VSS0105 VSS0106 VSS0107 VSS0108 VSS0109 VSS0110 VSS0111 VSS0112 VSS0113 VSS0114 VSS0115 VSS0116 VSS0117 VSS0118 VSS0119 VSS0120 VSS0121 VSS0122 VSS0123 VSS0124 VSS0125 VSS0126 VSS0127 VSS0128 VSS0129 VSS0130 VSS0131 VSS0132 VSS0133 VSS0134 VSS0135 VSS0136 VSS0137 VSS0138 VSS0139 VSS0140 VSS0141 VSS0142 VSS0143 VSS0144 VSS0145 VSS0146 VSS0147 VSS0148 VSS0149 VSS0150 VSS0151 VSS0152 VSS0153 VSS0154 VSS0155 VSS0156 VSS0157 VSS0158 VSS0159 VSS0160 VSS0161 VSS0162 P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24

MLX_47170_4787_YONAH_479P

INVENTEC
TITLE

San Antonio 10
Yonah-4
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
17 OF 65

A03

+V5S
60-,58-,52-,51-,50-,46-,45-,39-,38-,37-,35-,33-,31-,29-,12-,10-,8-

U4
1 2 FON VIN VO VSET GND GND GND GND 8 7 6 5 1 2

+V3LA
60-,50-,47-,32-,7-,18-

C34
FAN1_DAC0_3 50-

1

3 4

2.2uF_10v 2

U3007
VDD GND BBUS DP 4 DN 5

14-,18-

H_THERMDC

GMT_G995P1U_SOP8_8P
BBUS
58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,19-,13-,12-,11-,10-,9-,8-

50-

3

14-,18-

H_THERMDA

SMSC_EMC1212_SOT23_5P

+V3S 1 2 C38 2.2uF_10v
CN13 1 VCC 2 GND 3 REFENCE

4 G 5 G

1

MLX_53398_0371_3P

R39 10K_5%
2

1 L2 2 BLM11A121S 1 C39

50-

FAN_TACH1

FAN CN

2 0.01uF_50v
VR_PWRGD_CK410 13-,101

R768 2M_5%
2

50-,28-,7-,18-

THRM_SHUTDWN#

+V5LA
53-,7-,6-,51 R6696 2 1 5 VCC

Q540 D D GG U516
SET GND 2 1 4 HYST OT 1 2 3 1
S

R762

2

SSM3K17FU S
32-,19-,14- 1 R769 2

150_5% C5110 1 0.1uF_10v 2

R763 OPEN

24.9K_1%
50-,28-,7-,18-

PM_THRMTRIP#

THRM_SHUTDWN#

Q537 3 2B C E 330_5% 2SC2411K 1

1 2

C718 OPEN

GMT_G708T1U_SOT23_5P

R764 0_5%
2

+V3LA
60-,50-,47-,32-,7-,18-

1 C721
1

R790 OPEN C733 Q6020 D S
D S G

2 0.1uF_16v

2

THRM_SHUTDWN#

50-,28-,7-,18-

H_THERMDA H_THERMDC

14-,1814-,18-

1 2 OPEN

1 2 3 4

U517 VDD D+ DTHERM#

SCLK SDATA ALERT# GND

8 7 6 5

50-,6-,550-,6-,5-

BATT_CLK BATT_DATA

G

SSM3K17FU_OPEN +V3LA
60-,50-,47-,32-,7-,18-

A&D_ADM1032ARM_MICRO_SO_8P_OPEN

Thermal Sensor For CPU

INVENTEC
TITLE

San Antonio 10
DOC. NUMBER REV

THERMAL&FAN CONTROLLER
SIZE CODE

A3
CHANGE by Drawer_Name 14-Dec-2005

CS
SHEET

TC8703
18 OF 65

A03

U7-2
T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A35 A34 D28 D27 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3 AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21 AL20 AF10 BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41 27-,2527-,2527-,2627-,2627-,2527-,2527-,2627-,2627-,2527-,2527-,2627-,262525262625252626-

58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,20-,18-,13-,12-,11-,10-,9-,8-,19-

DDR MUXING

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR0# M_CLK_DDR1# M_CLK_DDR3# M_CLK_DDR4# MCH_CFG(18) MCH_CFG(19) MCH_CFG(20)

+V3S
1

RSVD

CPU_BSEL0 CPU_BSEL2

15-,1315-,131 1

SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

R726 OPEN

1 R728

1 R729

2 1919192

OPEN
2

OPEN

R94 1K_5%
2

R96 1K_5%
2

M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3#
M_OCDCOMP0 M_OCDCOMP1 1 1

MCH_BSEL0 MCH_BSEL2

MCH_BSEL1

13-

CFG

MCH_CFG(20:3)

19-

+V3S
1 1

R59 10K_5%
2

PM CLK

R58 10K_5%
2

MCH_CFG(3) MCH_CFG(4) MCH_CFG(5) MCH_CFG(6) MCH_CFG(7) MCH_CFG(8) MCH_CFG(9) MCH_CFG(10) MCH_CFG(11) MCH_CFG(12) MCH_CFG(13) MCH_CFG(14) MCH_CFG(15) MCH_CFG(16) MCH_CFG(17) MCH_CFG(18) MCH_CFG(19) MCH_CFG(20)
33-

K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

SM_OCDCOMP_0 SM_OCDCOMP_1 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP# SM_RCOMP SM_VREF_0 SM_VREF_1

+V1.8 M_ODT0 M_ODT1 1 M_ODT2 R100 M_ODT3 80.6_1%
2

OPEN R759

26-,25-,24-,11-,9-

MCH_CFG(18) (VCC Select) R754 OPEN

LOW=1.05V HIGH=1.5V

MCH_CFG(19) (DMI LANE REVERSAL)

LOW=Normal HIGH=LANES REVERSED

2

2

MCH_SMRCOMPN

1 26-,25-,11M_VREF 1 C203 0.47uF_6.3v 2

MCH_CFG(20) (PCIE Backward Interpoerability mode) R99 80.6_1%
191919191919191919-

LOW=Only SDVO or PCIE x1 is operational HIGH=SDVO and PCIE x1 are operating simultaneously via the PEG port

2

PM_EXTTS#0 PM_DPRSLPVR

26-,2533-,10-

R60 R57

1 1

2 0_5% 2 0_5%

BM_BUSY#

PM_THRMTRIP# SB_3S_VRMPWRGD PLT_RST#

32-,18-,1450-,33-,1050-,34- 2

G28 F25 H26 G6 AH33 1 AH34

100_5%

PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN#

G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN

AF33 AG33 A27 A26 C40 D41

131313131313-

CLK_R_PEG_MCH# CLK_R_PEG_MCH CLK_R_DREF# CLK_R_DREF SSCLK1_R_DREF# SSCLK1_R_DREF
33-

R52

MISC

MCH_ICH_SYNC# MCH_CLK_REQ#

3413-

H28 H27 K28 H32 D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

AE35 AF39 AG35 AH39

DMI_TXN(0) DMI_TXN(1) DMI_TXN(2) DMI_TXN(3)
33-

DMI_TXN(3:0)

MCH_CFG(12) MCH_CFG(13) MCH_CFG(16) MCH_CFG(11) MCH_CFG(10) MCH_CFG(9) MCH_CFG(7) MCH_CFG(6) MCH_CFG(5)

1

1

1

1

1

1

1

1

1

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC# CLK_REQ# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

AC35 AE39 AF35 AG39

DMI_TXP(0) DMI_TXP(1) DMI_TXP(2) DMI_TXP(3) DMI_RXN(0) DMI_RXN(1) DMI_RXN(2) DMI_RXN(3) DMI_RXP(0) DMI_RXP(1) DMI_RXP(2) DMI_RXP(3)
33-

DMI_TXP(3:0)

R734 OPEN
2

R723 OPEN
2

R724 OPEN
2

R738 OPEN
2

R739 OPEN
2

R735 R722 2.2K_5% OPEN
2 2

R736 OPEN
2

R737 OPEN
2

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

AE37 AF41 AG37 AH41

DMI_RXN(3:0) MCH_CFG(5) LOW=DMIx2 HIGH=DMIx4 LOW=Moby Dick MCH_CFG(6) (DDR) HIGH=Calistoga LOW=RSVD MCH_CFG(7) (CPU Strap) HIGH=Mobile CPU

DMI

NC

33-

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

AC37 AE41 AF37 AG41

DMI_RXP(3:0) MCH_CFG(9) LOW=Reverse Lane PCIE Graphics HIGH=Normal operation Lane MCH_CFG(10) LOW=RESERVED HOST PLL VCO HIGH=MOBILITY SELECT LOW=Calistoga MCH_CFG(11) HIGH=Reserved

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

MCH_CFG(16) (FSB Dynamic ODT)

LOW=Dynamic ODT Disable HIGH=Dynamic ODT Enabled

INVENTEC
TITLE

San Antonio 10
Calistoga-1
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
19 OF 65

A03

58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,23-,19-,18-,13-,12-,11-,10-,9-,8-

+V3S
1 1

R730 10K_5%
2

R731 10K_5%
2

+V1.5S_PCIE
23-

LCM_BKLTEN

31-,281

1

R49 2 0_5%

INV_PWM_3

50-,31-,28-

1

R721 OPEN

U7-3
2 D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 A33 A32 E27 E26 C37 B35 A37 L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LA_CLK# LA_CLK LB_CLK# LB_CLK LA_DATA#_0 LA_DATA#_1 LA_DATA#_2 D40 EXP_A_COMPI D38 EXP_A_COMPO EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15 EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15 EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15 EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40 282828282828282828282828282828282828282828282828282828282828282820202020202020202020202020202020202020202020202020202020202020201

R51 2 24.9_1%

PEG_TXP(0) PEG_TXN(0) PEG_TXP(1) PEG_TXN(1) PEG_TXP(2) PEG_TXN(2) PEG_TXP(3) PEG_TXN(3) PEG_TXP(4) PEG_TXN(4) PEG_TXP(5)

20-

28-

C40
20-

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.1uF_16v
28-

PEG_C_TXP(0) PEG_C_TXN(0) PEG_C_TXP(1) PEG_C_TXN(1) PEG_C_TXP(2) PEG_C_TXN(2) PEG_C_TXP(3) PEG_C_TXN(3) PEG_C_TXP(4) PEG_C_TXN(4) PEG_C_TXP(5) PEG_C_TXN(5) PEG_C_TXP(6) PEG_C_TXN(6) PEG_C_TXP(7) PEG_C_TXN(7) PEG_C_TXP(8) PEG_C_TXN(8) PEG_C_TXP(9) PEG_C_TXN(9) PEG_C_TXP(10) PEG_C_TXN(10) PEG_C_TXP(11) PEG_C_TXN(11) PEG_C_TXP(12) PEG_C_TXN(12) PEG_C_TXP(13) PEG_C_TXN(13) PEG_C_TXP(14) PEG_C_TXN(14) PEG_C_TXP(15) PEG_C_TXN(15)

C42
20-

0.1uF_16v
28-

2

R50 LCM_DDCPCLK 100K_1% LCM_DDCPDATA
1 LCM_3S_VDDEN

31-,2831-,28-

R5006 1 R5007 1
1

2 2

0_5% 0_5%

RS500 LVDS_R_TXCLLVDS_R_TXCL+
31-,2831-,281 2 4 3 2020-

0_5% LVDS_R_TXCULVDS_R_TXCU+
31-,2831-,281 2

R48 1.5K_1%
2

1

LVDS

LVDS_TXCLLVDS_TXCL+

31-,28-

R62 2 0_5% LVDS_TXCLLVDS_TXCL+ LVDS_TXCULVDS_TXCU+
20202020202020-

RS507

R63 100K_5%
2

4 3

2020-

LVDS_TXCULVDS_TXCU+

0_5% RS502 LVDS_R_TXDL0LVDS_R_TXDL0+
31-,2831-,281 2 4 3 2020-

LVDS_TXDL0LVDS_TXDL0+

LVDS_TXDL0LVDS_TXDL1LVDS_TXDL2-

PEG_C_RXN(0) PEG_C_RXN(1) PEG_C_RXN(2) PEG_C_RXN(3) PEG_C_RXN(4) PEG_C_RXN(5) PEG_C_RXN(6) PEG_C_RXN(7) PEG_C_RXN(8) PEG_C_RXN(9) PEG_C_RXN(10) PEG_C_RXN(11) PEG_C_RXN(12) PEG_C_RXN(13) PEG_C_RXN(14) PEG_C_RXN(15) PEG_C_RXP(0) PEG_C_RXP(1) PEG_C_RXP(2) PEG_C_RXP(3) PEG_C_RXP(4) PEG_C_RXP(5) PEG_C_RXP(6) PEG_C_RXP(7) PEG_C_RXP(8) PEG_C_RXP(9) PEG_C_RXP(10) PEG_C_RXP(11) PEG_C_RXP(12) PEG_C_RXP(13) PEG_C_RXP(14) PEG_C_RXP(15) PEG_TXN(0) PEG_TXN(1) PEG_TXN(2) PEG_TXN(3) PEG_TXN(4) PEG_TXN(5) PEG_TXN(6) PEG_TXN(7) PEG_TXN(8) PEG_TXN(9) PEG_TXN(10) PEG_TXN(11) PEG_TXN(12) PEG_TXN(13) PEG_TXN(14) PEG_TXN(15) PEG_TXP(0) PEG_TXP(1) PEG_TXP(2) PEG_TXP(3) PEG_TXP(4) PEG_TXP(5) PEG_TXP(6) PEG_TXP(7) PEG_TXP(8) PEG_TXP(9) PEG_TXP(10) PEG_TXP(11) PEG_TXP(12) PEG_TXP(13) PEG_TXP(14) PEG_TXP(15)

C66
20-

0.1uF_16v
28-

C67
20-

0.1uF_16v
28-

C43
20-

0.1uF_16v
28-

C44
20-

0.1uF_16v
28-

C68
20-

0.1uF_16v
28-

C69
20-

0.1uF_16v
28-

C45
20-

0.1uF_16v
28-

C46
20-

0.1uF_16v
28-

PCI-EXPRESS GRAPHICS

0_5% RS503 LVDS_R_TXDL1LVDS_R_TXDL1+
31-,2831-,281 2 4 3 2020-

C70
20-

0.1uF_16v
28-

PEG_TXN(5) PEG_TXP(6) PEG_TXN(6) PEG_TXP(7) PEG_TXN(7) PEG_TXP(8) PEG_TXN(8) PEG_TXP(9) PEG_TXN(9) PEG_TXP(10) PEG_TXN(10) PEG_TXP(11) PEG_TXN(11) PEG_TXP(12) PEG_TXN(12) PEG_TXP(13) PEG_TXN(13) PEG_TXP(14) PEG_TXN(14) PEG_TXP(15) PEG_TXN(15)

C71
20-

0.1uF_16v
28-

LVDS_TXDL1LVDS_TXDL1+ +V1.5S

0_5% RS501 LVDS_R_TXDL2LVDS_R_TXDL2+
31-,2831-,281 2 4 3 2020-

LVDS_TXDL0+ LVDS_TXDL1+ LVDS_TXDL2+

202020-

B37 B34 A36

LA_DATA_0 LA_DATA_1 LA_DATA_2

C47
20-

0.1uF_16v
28-

C48
20-

0.1uF_16v
28-

LVDS_TXDL2LVDS_TXDL2+

44-,38-,35-,33-,28-,24-,23-,16-,11-,9LVDS_TXDU0-

R98 R742 R741 R72 R97

0_5% RS505 LVDS_R_TXDU0LVDS_R_TXDU0+
31-,2831-,281 2 4 3 2020-

LVDS_TXDU1LVDS_TXDU21 1 1 1 1

202020-

G30 D30 F29

LB_DATA#_0 LB_DATA#_1 LB_DATA#_2

C72
20-

0.1uF_16v
28-

C73
20-

0.1uF_16v
28-

C49
20-

0.1uF_16v
28-

LVDS_TXDU0LVDS_TXDU0+

OPEN OPEN OPEN OPEN OPEN

0_5% RS504 LVDS_R_TXDU1LVDS_R_TXDU1+
31-,2831-,281 2 4 3 2020-

2 2 2 2 2

LVDS_TXDU0+ LVDS_TXDU1+ LVDS_TXDU2+

202020-

F30 D29 F28

LB_DATA_0 LB_DATA_1 LB_DATA_2

C50
20-

0.1uF_16v
28-

C74
20-

0.1uF_16v
28-

LVDS_TXDU1LVDS_TXDU1+ SVID_LUMA SVID_CHROMA
30-,28- 1 30-,28- 1

C75
20-

0.1uF_16v
28-

0_5% RS506 LVDS_R_TXDU2LVDS_R_TXDU2+
31-,2831-,281 2 4 3 2020-

LVDS_TXDU2LVDS_TXDU2+

TV

0_5%

R699 0_5% 2 SVID_R_LUMA 2 SVID_R_CHROMA R698 1 R71 2 0_5% 4.99K_1% 1 R95 2 0_5%

C51
20-

0.1uF_16v
28-

A16 C18 A19 J20 B16 B18 B19 K30 J29

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

C52
20-

0.1uF_16v
28-

C76
20-

0.1uF_16v
28-

C77
20-

0.1uF_16v
28-

C53
20-

0.1uF_16v
28-

+VCCP
2

R745

1

TV_DCONSEL0 TV_DCONSEL1

C54
20-

0.1uF_16v
28-

SVID_R_LUMA SVID_R_CHROMA R65 0_5%

35-,32-,24-,23-,21-,16-,15-,14-,13-,9-,8-,201 1

C78
20-

0.1uF_16v
28-

OPEN

OPEN

120_0.5% 2 R743 1 120_0.5%

CRT_B CRT_G CRT_R

29-,2829-,2829-,28-

R700 R702 R704

1 1 1

2 2 2

0_5% B 0_5% G 0_5% R

VGA

2

2

1

2

E23 D23 C22 B22 A21 B21

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

C79
20-

0.1uF_16v
28-

R753

R64

C82
20-

0.1uF_16v
28-

C83
20-

0.1uF_16v
28-

C80
20-

0.1uF_16v
28-

+VCCP
35-,32-,24-,23-,21-,16-,15-,14-,13-,9-,8-,201 1

R752

R732 OPEN
2

2

CRT_DDCCLK CRT_DDCDATA CRT_HSYNC CRT_VSYNC

58-,29-,28R703 1 58-,29-,28R701 1 29-,28- R705 1 29-,28-

2 0_5% 2 0_5% 2 39_5% 2 39_5%

255_1% R747

R706

1

C26 C25 G23 J22 H23

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC

C81

0.1uF_16v

Place to near NB

2

1

B OPEN G R
1 1

R749

120_0.5% 2 R744 1
1

2

R748

2

R733 0_5%

120_0.5%

2

CLOSE TO CALISTOGA

OPEN

120_0.5% 2 R746 1

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

INVENTEC
TITLE

San Antonio 10
Calistoga-2
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
20 OF 65

A03

H_D#(63:0)

15-

H_D#(63:0)

14-

H_A#(31:3)

+VCCP MCH_HXSCOMP
21-

R144

1

2

54.9_1%

35-,32-,24-,23-,20-,16-,15-,14-,13-,9-,8-,21-

MCH_HXRCOMP

21-

R145

1

2

24.9_1%

+VCCP MCH_HYSCOMP
21-

R146

1

2

54.9_1%

35-,32-,24-,23-,20-,16-,15-,14-,13-,9-,8-,21-

MCH_HYRCOMP

21-

R149

1

2

24.9_1%

+VCCP
35-,32-,24-,23-,20-,16-,15-,14-,13-,9-,8-,211

R142 221_1%

2

MCH_HXSWING

211

R143 C189 1 100_1% 2 0.1uF_10v

2

+VCCP
35-,32-,24-,23-,20-,16-,15-,14-,13-,9-,8-,211

R147 221_1%

2

MCH_HYSWING

21-

R148 C195 1 100_1% 2 0.1uF_10v 2
1

H_D#(0) H_D#(1) H_D#(2) H_D#(3) H_D#(4) H_D#(5) H_D#(6) H_D#(7) H_D#(8) H_D#(9) H_D#(10) H_D#(11) H_D#(12) H_D#(13) H_D#(14) H_D#(15) H_D#(16) H_D#(17) H_D#(18) H_D#(19) H_D#(20) H_D#(21) H_D#(22) H_D#(23) H_D#(24) H_D#(25) H_D#(26) H_D#(27) H_D#(28) H_D#(29) H_D#(30) H_D#(31) H_D#(32) H_D#(33) H_D#(34) H_D#(35) H_D#(36) H_D#(37) H_D#(38) H_D#(39) H_D#(40) H_D#(41) H_D#(42) H_D#(43) H_D#(44) H_D#(45) H_D#(46) H_D#(47) H_D#(48) H_D#(49) H_D#(50) H_D#(51) H_D#(52) H_D#(53) H_D#(54) H_D#(55) H_D#(56) H_D#(57) H_D#(58) H_D#(59) H_D#(60) H_D#(61) H_D#(62) H_D#(63)

U7-1
F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 E1 E2 E4 Y1 U1 W1 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING H_CLKIN H_CLKIN# H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13

H_A#(3) H_A#(4) H_A#(5) H_A#(6) H_A#(7) H_A#(8) H_A#(9) H_A#(10) H_A#(11) H_A#(12) H_A#(13) H_A#(14) H_A#(15) H_A#(16) H_A#(17) H_A#(18) H_A#(19) H_A#(20) H_A#(21) H_A#(22) H_A#(23) H_A#(24) H_A#(25) H_A#(26) H_A#(27) H_A#(28) H_A#(29) H_A#(30) H_A#(31) 141414-

HOST

+VCCP
35-,32-,24-,23-,20-,16-,15-,14-,13-,9-,8-,21-

H_VREF
1414141414141514-

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_HIT# H_HITM# H_LOCK#
14-

100_1%
2 1 R757

1 2

C710
2

200_1%

0.1uF_10v

H_VREF
151515151515151515151515-

J7 H_DINV#_0 W8 H_DINV#_1 U3 H_DINV#_2 AB10 H_DINV#_3 K4 H_DSTBN#_0 T7 H_DSTBN#_1 Y5 H_DSTBN#_2 AC4 H_DSTBN#_3 K3 H_DSTBP#_0 T6 H_DSTBP#_1 AA5 H_DSTBP#_2 AC5 H_DSTBP#_3 D3 H_HIT# D4 H_HITM# B3 H_LOCK#

141414-

NOTE: MCH_HXRCOMP, MCH_HYRCOMP MCH_HXSWING, MCH_HYSWING should be 10 mil wide with 20 mil spacing

MCH_HXRCOMP MCH_HXSCOMP MCH_HXSWING MCH_HYRCOMP MCH_HYSCOMP MCH_HYSWING

212121212121-

H_REQ#(4:0)

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

D8 G8 B8 F8 A8

H_REQ#(0) H_REQ#(1) H_REQ#(2) H_REQ#(3) H_REQ#(4) H_RS#(0) H_RS#(1) H_RS#(2)
32-,1514-

14-

H_RS#(2:0)

Layout notes: Trace need be 10 mils

CLK_R_MCHBCLK CLK_R_MCHBCLK#

1313-

AG2 AG1

B4 H_RS#_0 E6 H_RS#_1 D6 H_RS#_2 E3 H_SLPCPU# E7 H_TRDY#

H_CPUSLP# H_TRDY#

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

INVENTEC
TITLE

San Antonio 10
Calistoga-3
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
21 OF 65

LAYOUT NOTE: Place R675 and R676 close to MCH within 100 mil

1 R758

A03

MA_DATA(63:0)

25-

MB_DATA(63:0) U7-4
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 AU12 SA_BS_0 AV14 SA_BS_1 BA20 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 27-,25TP7 TP8 27-,2527-,2527-,2527-,2527-,25-

26-

U7-5 MA_BS0# MA_BS1# MA_BS2# 25MA_DM(7:0)
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 AT24 AV23 AY28 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 AU23 AK16 AK18 AR27 27-,26TP9 TP10 27-,2627-,2627-,2627-,2627-,2626-

MB_BS0# MB_BS1# MB_BS2# MB_DM(7:0)

MA_CAS#

MB_CAS#

25-

MA_DQS(7:0)

26-

MB_DQS(7:0)

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

25-

MA_DQS#(7:0)

26-

MB_DQS#(7:0)

27-,25-

MA_A(13:0)

27-,26-

MB_A(13:0)

AW14 SA_RAS# AK23 SA_RCVENIN# AK24 SA_RCVENOUT# AY14 SA_WE#

MA_RAS# MA_WE#

SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#

MB_RAS# MB_WE#

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

INVENTEC
TITLE

San Antonio 10
Calistoga-4
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
22 OF 65

A03

+V1.5S
44-,38-,35-,33-,28-,24-,20-,16-,11-,9-,23-

L5
1

+V2.5S NOTE: 28-,8-,23CAPS USED IN +V1.5S_PCIE SHOULD BE WITHIN ON TOP +V1.5S_PCIE 1 R47 LAYER 200_5% 2 C87 1 C100 10uF_6.3v 1 2 C101 1 10uF_6.3v 2
2

1

R750 OPEN U7-8

2

+VCCP
35-,32-,24-,21-,20-,16-,15-,14-,13-,9-,8-,23VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76 AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 VTTLF_CAP3 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 VTTF_CAP2 AB1 VTTF_CAP1 R1 P1 N1 M1

ICB_1206_3.0A +V2.5S
28-,8-,231 35-,32-,24-,21-,20-,16-,15-,14-,13-,9-,8-,23-

H22

VCCSYNC VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS VCCA_MPLL VCCA_TVBG VSSA_TVBG

220uF_2.5v

+VCCP R66
2

1 C668

1 C667 0.1uF_10v

VCCGFOLLOW

10_5%

D3 3

BAT54 1
1

44-,38-,35-,33-,28-,24-,20-,16-,11-,9-,23-

44-,38-,35-,33-,28-,24-,20-,16-,11-,9-,23-

NOTE: CAPS USED IN +V2.5S_CRTDAC SHOULD BE WITHIN 250MILS OF EDGE OF MCH L7 2 1 BLM18PG181SN1J

+V1.5S R61 OPEN
2

L519 BLM11B121SB 1 2

NOTE: 10UF CAPS USED IN +V1.5S_3GPLL SHOULD SHOULD BEPLACED IN CAVITY 1 C129 10uF_6.3v 2 +V1.5S_3GPLL C673 1 2 0.1uF_10v

2 0.1uF_10v 2

C30 B30 A30 AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41 F21 E21 G21 B26 C39 AF1 A38 B39 AF2

35-,32-,24-,21-,20-,16-,15-,14-,13-,9-,8-,23-

+VCCP

+V2.5S
28-,8-,23-

+V1.5S

1 2

C698 4.7uF_6.3v

1 2

C699 2.2uF_10v

1 2

C194 0.22uF_6.3v

1 2

C156 330uF_2.5v

CLOSE TO AF1 CLOSE TO C39 CLOSE TO B26 L518 NFM60R30T222 2 1 1 C665 C197 C671 C64 1 1 1 3 4 2 2 2 2 470uF_2.5v 0.1uF_10v 0.1uF_10v 0.1uF_10v

1 C98 0.022uF_16v 2

+V2.5S_CRTDAC 1 C99 0.1uF_10v 2 +V1.5S_DPLL R45 OPEN

PLACE IN CAVITY

PLACE ON THE EDGE

2 BAT54 D4 1 V1_5SFOLLOW 3 +V3S
2

L11 BLM11A121S 1 1 2

1

2

0_5% C198 0.1uF_10v

1 2

C666 0.01uF_16v

1 2

C65 0.1uF_10v

R75 10_5%

1

1

58-,54-,53-,52-,51-,50-,49-,48-,47-,46-,44-,41-,40-,39-,38-,37-,35-,34-,33-,32-,31-,29-,28-,26-,25-,20-,19-,18-,13-,12-,11-,10-,9-,8-,23-

1 C199 22uF_6.3v 2 R74 OPEN

H20 G20

+V1.5S_MPLL +VCCA_TVDAC C695 0.1uF_10v
E19 F19 C20 D20 E20 F20 AH1 AH2 1 1

L9 2 1 BLM18PG181SN1J 1 NOTE: CAPS USED IN +V3S SHOULD BE WITHIN 250MILS OF EDGE OF MCH

2 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCD_TVDAC VCC_HV0 VCC_HV1 VCC_HV2

1 C126 2 2 10uF_6.3v

C696 0.1uF_10v

1 2

C694 0.1uF_10v

1 2

1 2

C697 0.1uF_10v

CLOSE TO E20

CLOSE TO C20

+V1.5S 1 2

CLOSE TO E19

CLOSE TO H20

44-,38-,35-,33-,28-,24-,20-,16-,11-,9-,23-

C200 10uF_6.3v
44-,38-,35-,33-,28-,24-,20-,16-,11-,9-,231

C201 1 0.1uF_10v 2

R725 0_5%

2

R727 OPEN +V3S 1 2

2

A28 B28 C28 D21 A23 B23 B25

R740

2

+V1.5_TVDAC C97 1 2 0.1uF_10v

+V1.5S

0.5_1% C692 1 0.022uF_16v 2 1 2 BLM18PG181SN1J L8

C693 1 C96 0.1uF_10v 2 10uF_6.3v

+V1.5S_QTVDAC H19 VCCD_QTVDAC C125 1 0.022uF_16v 2 +V1.5S 1C124 2 0.1uF_10v
AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12 VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40

CAPS USED IN +V1.5S_TVDAC AND +V1.5S_QTVDAC SHOULD BE WITHIN 250 MILS OF EDGE

1

R73 OPEN

2

POWER

NOTE: 0.1UF CAPS IN +V1.5_xPLL NEED TO BE LOCATED AS EDGE CAPS WITHIN 200 MILS

44-,38-,35-,33-,28-,24-,20-,16-,11-,9-,23-

+V2.5S R46

1

2

+V1.5S

1 2

C127 0.47uF_6.3v

44-,38-,35-,33-,28-,24-,20-,16-,11-,9-,23-

C713 1 0.1uF_10v 2

1 2

C196

1 2

C191 0.22uF_6.3v

0.47uF_6.3v

INVENTEC
TITLE

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

San Antonio 10
Calistoga-5
DOC. NUMBER REV

SIZE CODE

A3
CHANGE by Drawer_Name 28-Nov-2005

CS
SHEET

TC8703
23 OF 65

A03

U7-7 +VCCP
AA33 VCC_0 W33 VCC_1 P33 35-,32-,23-,21-,20-,16-,15-,14-,13-,9-,8-,24VCC_2 N33 VCC_3 L33 VCC_4 J33 VCC_5 AA32 VCC_6 Y32 VCC_7 W32 VCC_8 V32 VCC_9 P32 VCC_10 N32 VCC_11 M32 VCC_12 L32 VCC_13 J32 VCC_14 AA31 VCC_15 W31 VCC_16 V31 VCC_17 T31 VCC_18 R31 VCC_19 P31 VCC_20 N31 VCC_21 M31 VCC_22 AA30 VCC_23 Y30 VCC_24 W30 VCC_25 V30 VCC_26 U30 VCC_27 T30 VCC_28 R30 VCC_29 P30 VCC_30 N30 VCC_31 M30 VCC_32 L30 VCC_33 AA29 VCC_34 Y29 VCC_35 W29 VCC_36 V29 VCC_37 U29 VCC_38 R29 VCC_39 P29 VCC_40 M29 VCC_41 L29 VCC_42 AB28 VCC_43 AA28 VCC_44 Y28 VCC_45 V28 VCC_46 U28 VCC_47 T28 VCC_48 R28 VCC_49 P28 VCC_50 N28 VCC_51 M28 VCC_52 L28 VCC_53 P27 VCC_54 N27 VCC_55 M27 VCC_56 L27 VCC_57 P26 VCC_58 N26 VCC_59 L26 VCC_60 N25 VCC_61 M25 VCC_62 L25 VCC_63 P24 VCC_64 N24 VCC_65 M24 VCC_66 AB23 VCC_67 AA23 VCC_68 Y23 VCC_69 P23 VCC_70 N23 VCC_71 M23 VCC_72 L23 VCC_73 AC22 VCC_74 AB22 VCC_75 Y22 VCC_76 W22 VCC_77 P22 VCC_78 N22 VCC_79 M22 VCC_80 L22 VCC_81 AC21 VCC_82 AA21 VCC_83 W21 VCC_84 N21 VCC_85 M21 VCC_86 L21 VCC_87 AC20 VCC_88 AB20 VCC_89 Y20 VCC_90 W20 VCC_91 P20 VCC_92 N20 VCC_93 M20 VCC_94 L20 VCC_95 AB19 VCC_96 AA19 VCC_97 Y19 VCC_98 N19 VCC_99 M19 VCC_100 L19 VCC_101 N18 VCC_102 M18 VCC_103 L18 VCC_104 P17 VCC_105 N17 VCC_106 M17 VCC_107 N16 VCC_108 M16 VCC_109 L16 VCC_110

VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107

AU41 VCC_SM_LF4 AT41 +VCCP VCC_SM_LF5 AM41 AU40 C84 35-,32-,23-,21-,20-,16-,15-,14-,13-,9-,8-,241 BA34 1 1 AY34 2 C700 C192 0.47uF_6.3v AW34 C85 1 AV34 2 330uF_2.5v 2 330uF_2.5v AU34 2 0.47uF_6.3v AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 C193 C190 C188 1 1 1 AL29 AK29 2 10uF_6.3v 2 1uF_6.3v 2 10uF_6.3v AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 C711 C672 C712 1 1 1 AV26 AU26 2 0.22uF_6.3v 2 0.22uF_6.3v 2 0.22uF_6.3v AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 C86 1 AJ23 BA22 2 0.47uF_6.3v AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 NEAR PIN BA15 ON LAYER1 BA15 AY15 C128 1 AW15 AV15 2 0.47uF_6.3v AU15 AT15 AR15 AJ15 AJ14 PLACE IN CAVITY AJ13 +V1.8 AH13 AK12 26-,25-,19-,11-,9AJ12 AH12 C130 C157 1 1 AG12 AK11 2 10uF_6.3v 2 10uF_6.3v BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 VCC_SM_LF2 AK6 AJ6 C202 C204 1 1 AV1 AJ1 VCC_SM_LF1

U7-9
AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 +V1.5S AC39 AB39 44-,38-,35-,33-,28-,23-,20-,16-,11-,9AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11

U7-10
VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1

U7-6
AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72 VSS_NCTF0 VSS_NCTF1 VSS_