Text preview for : Sager D87P Service Manual_Part3.pdf part of Sager D870P Service Manual for Sager D870P Notebook
Back to : Sager D87P Service Manual | Home
Part Lists
DVD-RW Drive
Figure A-11
DVD-RW Drive
Part Lists
DVD-RW Drive A - 13
Part Lists
DVD+RW Drive - Pioneer
Figure A-12
Part Lists
DVD+RW Drive Pioneer
A - 14 DVD+RW Drive - Pioneer
Part Lists
DVD+RW Drive - Toshiba
Figure A-13
DVD+RW Drive Toshiba
Part Lists
DVD+RW Drive - Toshiba A - 15
Part Lists
Hard Disk Device
Figure A-14
Part Lists
Hard Disk Device
A - 16 Hard Disk Device
Part Lists
Sub Woofer Speaker
Figure A-15
Sub Woofer Speaker
Part Lists
Sub Woofer Speaker A - 17
Part Lists
Sub Woofer Speaker 8
Figure A-16
Part Lists
Sub Woofer Speaker 8
A - 18 Sub Woofer Speaker 8
Part Lists
TV Tuner
Figure A-17
TV Tuner
Part Lists
TV Tuner A - 19
Part Lists
Card Reader
Figure A-18
Part Lists
Card Reader
A - 20 Card Reader
Schematic Diagrams
Appendix B: Schematic Diagrams for D870P
This appendix has circuit diagrams of the D870P notebook computer's PCBs.
Diagram - Page System Block Diagram - Page B - 2 CPU Northwood & Prescott (1 of 2) - Page B - 3 CPU Northwood & Prescott (2 of 2) - Page B - 4 CPU Decoupling - Page B - 5 CLK409 - Page B - 6 Springdale (HOST, AGP, Hub) - Page B - 7 Springdale (DDR Interface) - Page B - 8 DDR Termination - Page B - 9 DDR SODIMM - Page B - 10 Springdale (Voltage, PLL, VSS) - Page B - 11 Mobility M10-P - Page B - 12 Mobility M10-P MEM A/B - Page B - 13 VGA DDR DRAM Channel A - Page B - 14 VGA DDR DRAM Channel B - Page B - 15
Diagram - Page VGA DDR DRAM Termination - Page B - 16 Mobility M10-P_POW - Page B - 17 DVI, TV Out & LVDS - Page B - 18 ICH5 (1 of 2) - Page B - 19 ICH5 (2 of 2) - Page B - 20 USB Port & RTC - Page B - 21 RAID PDC20265R - Page B - 22 HDD & CD-R/W - Page B - 23 AMP TPA0202 / ALC650 - Page B - 24 Audio Jack & Fan Control - Page B - 25 NS87393 LPC Bridge & Super I/O - Page B - 26 Flash ROM/LPT1 - Page B - 27 I/O, FDD, LED & Debug - Page B - 28 KBC H8 - Page B - 29
Diagram - Page PCMCIA ENE1410 - Page B - 30 IEEE 1394 TSB43AB21 - Page B - 31 LAN RTL8100C/RTL8110S(B)-32 - Page B - 32 Power Plane - Page B - 33 Vcore - Page B - 34 System Power 1 - Page B - 35 System Power 2 - Page B - 36 Charger - Page B - 37 3VH8, VDD1.8 - Page B - 38 S/W Board & Hot-Key - Page B - 39 TouchPad Switchboard - Page B - 40
Schematic Diags
B - 1
Schematic Diagrams
System Block Diagram
D870P
CK 409 Clocking
SCHEMATIC
MOBILITY M10 INT#A/B
B A F D G AD16 AD17 AD18 AD19 AD20
DDR-SDRAM
TV OUT
Northwood & Prescott 478 FC-BGA
Intel Pentium 4
PREQ0# GNT#0 PREQ1# GNT#1 PREQ2# GNT#2
ENE1410 TSB43AB21 RAID
INT#A INT#B/F INT#A/D
INT#C/G PREQ3# GNT#3 LAN RTL8100C LAN RTL8110S(B) PREQ4# GNT#4 MINI PCI
SERIRQ INT#D/E D/E
400/533/800MHz
Schematic Diags
Sheet 1 of 39 System Block Diagram
LVDS
Mobility M10-P
DVI-I 708 BGA
ATI
SPRINGDALE
AGP 8X
932 FC-BGA
Intel
865PE
DDR DRAM CHANNEL A DDR DRAM CHANNEL B
SODIMM0 SODIMM1
USB0
Hub Interface 1.8V , 66MHz
USB1 USB2
CARD READER TV TUNNER CCD BLUE TOOTH
IDE INTERFACE 1
CD-ROM/DVD-ROM MDC MODEM AUDIOCODEC
WIRELESS
USB 2.0
Realtek
RTL8100C/RTL8110S(B)-32
33MHz, 3.3V PCI 2.2 I/F
Intel
ICH5
460 BGA
AC'97 2.1 I/F
CARDBUS (TI1410)
RAID
1394 TSB43AB21
IDE INTERFACE 0
HDD
ALC650
PDC20265R
33MHz, 3.3V LPC I/F
IDE INTERFACE 0
SECOND HDD(OPTION)
IN. K/B
EX. K/B
H8S-2149 HM
KBC H8
LPC SUPER I/O COM
NS87393
IR PORT
EX. PS/2
TOUCH PAD
Flash ROM
B-2
Schematic Diagrams
CPU Northwood & Prescott (1 of 2)
VCORE DP3# DP2# DP1# DP0# A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10 E12 E14 E16 E18 E20 E8 F11 F13 F15 F17 F19 F9 L25 K26 K25 J26 T242 T241 T245 T244
[6] HD[0..63]
DEP3 DEP2 DEP1 DEP0
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
HD[0..63] HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 HRS0# HRS1# HRS2#
U16A B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 F1 G5 F4
HA35 HA34 HA33 HA32
LAYOUT NOTICE: HD[0..63] Data Line lengths: 2"-10" from pin to pin.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 RS0 RS1 RS2
LAYOUT NOTICE: HD[0..15], +/-100mils. HDSTBN0#, HDSTBP0#, HDBI0# , +/-25mils.
LAYOUT NOTICE: HA[17..35], +/-200mils. ADSTB1#, +/-25mils.
LAYOUT NOTICE: HD[16..31], +/-100mils. HDSTBN1#, HDSTBP1#, HDBI1# , +/-25mils.
LAYOUT NOTICE: HA[3..16], +/-200mils. ADSTB0#, HREQ[0..4]#, +/-25mils.
A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 VID0 VID1 VID2 VID3 VID4 VID5 REQ4 REQ3 REQ2 REQ1 REQ0 BPM5 BPM4 BPM3 BPM2 BPM1 BPM0
AB1 Y1 W2 V3 U4 T5 W1 R6 V2 T4 U3 P6 U1 T2 R3 P4 P3 R2 T1 N5 N4 N2 M1 N1 M4 M3 L2 M6 L3 K1 L6 K4 K2 AE5 AE4 AE3 AE2 AE1 AD3 H3 J3 J4 K5 J1 AB4 AA5 Y6 AC4 AB5 AC6 AD25 A6 Y3 W4 U6 AB22 AA20 AC23 AC24 AC20 AC21 AA2 AD24 AD1
T38 T39 T40 T31 HA[3..31] [6]
HA31 HA30 HA29 HA28 HA27 HA26 HA25 HA24 HA23 HA22 HA21 HA20 HA19 HA18 HA17 HA16 HA15 HA14 HA13 HA12 HA11 HA10 HA9 HA8 HA7 HA6 HA5 HA4 HA3 VID0 VID1 VID2 VID3 VID4 VID5 HREQ4# HREQ3# HREQ2# HREQ1# HREQ0# TPREQ# TPRDY# BPM3# BPM2# BPM1# BPM0# R334 1 R382 1 R93 1 R94 1 R95 1 R29 1
LAYOUT NOTICE: HA[3..31] Address Line lengths: 2"-10" from pin to pin.
Schematic Diags
LAYOUT NOTICE: HD[32..47], +/-100mils. HDSTBN2#, HDSTBP2#, HDBI2# , +/-25mils.
VID0 VID1 VID2 VID3 VID4 VID5
[33] [33] [33] [33] [33] [33] [6] [6] [6] [6] [6]
Sheet 2 of 39 CPU Northwood & Prescott (1 of 2)
HREQ4# HREQ3# HREQ2# HREQ1# HREQ0#
TPREQ# [3] TPRDY# [3] BPM3# BPM2# BPM1# [3] BPM0# [3] G_HIGH [18] 2 2 2 2 2 62 62 62 62 62 VCORE VCORE VCORE VCORE
LAYOUT NOTICE: HD[48..63], +/-100mils. HDSTBN3#, HDSTBP3#, HDBI3# , +/-25mils.
AD10 AD12VSS AD14VSS AD16VSS AD18VSS AD21VSS AD23VSS AD4 VSS AD8 VSS AE11 VSS AE13 VSS AE15 VSS AE17 VSS AE19 VSS AE22 VSS AE24 VSS AE26 VSS AE7 VSS AE9 VSS AF1 VSS AF10 VSS AF12 VSS AF14 VSS AF16 VSS AF18 VSS AF20 VSS AF26 VSS AF6 SKTOCC# AF8 VSS B10 VSS B12 VSS B14 VSS B16 VSS B18 VSS B20 VSS B23 VSS B26 VSS B4 VSS B8 VSS C11 VSS C13 VSS C15 VSS C17 VSS C19 VSS C2 VSS VSS
H1 H4 VSS H23 VSS H26 VSS A11 VSS A13 VSS A15 VSS A17 VSS A19 VSS A21 VSS A24 VSS A26 VSS A3 VSS A9 VSS AA1 VSS AA11 VSS AA13 VSS AA15 VSS AA17 VSS AA19 VSS AA23 VSS AA26 VSS AA4 VSS AA7 VSS AA9 VSS AB10 VSS AB12 VSS AB14 VSS AB16 VSS AB18 VSS AB20 VSS AB21 VSS AB24 VSS AB3 VSS AB6 VSS AB8 VSS AC11VSS AC13VSS AC15VSS AC17VSS AC19VSS AC2 VSS AC22VSS AC25VSS AC5 VSS AC7 VSS AC9 VSS VSS
[6] HRS0# [6] HRS1# [6] HRS2#
TESTHI12/DPSLP# TESTHI11/GHI# TESTHI10/BR1# TESTHI9/BR2# TESTHI8/BR3# TESTHI7/MCLKIO1 TESTHI6/MCLKIO0 TESTHI5/MCLK3 TESTHI4/MCLK2 TESTHI3/MCLK1 TESTHI2/MCLK0 TESTHI1/ODT TESTHI0/BYPASSEN# VSS
2 62
R335 1
2 62
VCORE PRE/NOR# [33,35] VCORE
PRE/NOR# 1 2 R91 1K NORTHWOOD478
Prescott Hight
SKTOCC# T10
Northwood Low 1.225V
1.45V
T9
Reserved
PJ1 2mm VID0 VID1 VID2 VID3 VID4 VID5 2 R404 1 2K(R) R384 R385 R391 R402 R403 R392 1 1 1 1 1 1 2 2 2 2 2 2 1K(R) 1K(R) 1K(R) 1K(R) 1K(R) 1K
VCC3S
Place close to cpu
TPREQ# TPRDY# BPM3# BPM2# BPM1# BPM0# R67 R54 R53 R82 R66 R43 62 62 62 62 62 62 VCORE
Line to line spacing: Greater than 3:1 Trace Impedance: 50ohm +/-15%
VCC3S [5,9,10,11,12,16,17,18,19,20,23,25,26,27,28,31,32,37] VCORE [3,4,5,18,19,33]
B - 3
Schematic Diagrams
CPU Northwood & Prescott (2 of 2)
GTLREF GENERATION CIRCUITS
1 1 1 C59 1U_0805_X7R 2 2 C474 220P 2 C526 220P IERR# FERR# HGTLREF 1 1 R380 169_1% 2 2 C518 1U_0805_X7R 2 C470 220P 2 1 C524 220P BR0# PROCHOT# CPUPWRGD R92 R383 R98 R105 R5 2 2 2 2 2 1 62 1 62_1% 1 200 1 120 1 300_1% VCORE
CLOSE TO CPU PIN
R44 1 VCORE [6] HGTLREF 2 200_1% 1
Layout Note: 12mil trace L should be close to c VCCA route parallel and VSSA route
AA21 AA6 F20 F6
C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 C22
U16B AE23 AD20 AD22 VCCIOPLL VCCA VSSA
VCORE IERR MCERR FERR STPCLK BINIT INIT RSP DBSY DRDY TRDY ADS LOCK BR0 BNR HIT HITM BPRI DEFER TCK TDI TMS TRST TDO PROCHOT IGNNE SMI A20M SLP PWRGOOD RESET NC THERMDA THERMDC THERMTRIP BSEL0 BSEL1 AP0 AP1 IERR# AC3 V6 MCERR# T22 FERR# B6 FERR# [18] HSTPCLK# Y4 HSTPCLK# [18] AA3 BINIT# T29 INIT# W5 INIT# [18] RSP# AB2 T28 H5 DBSY# DBSY# [6] H2 HDRDY# HDRDY# [6] HTRDY# J6 HTRDY# [6] G1 ADS# ADS# [6] HLOCK# G4 HLOCK# [6] H6 BR0# BR0# [6] BNR# G2 BNR# [6] HIT# F3 HIT# [6] E3 HITM# HITM# [6] D2 BPRI# BPRI# [6] DEFER# E2 DEFER# [6] D4 TCK C1 TDI F7 TMS E6 TRST# D5 TDO C3 PROCHOT# PROCHOT# [6] B2 IGNNE# IGNNE# [18] B5 SMI# SMI# [18] C6 A20M# A20M# [18] AB26 CPUSLP# CPUSLP# [18] AB23 CPUPWRGD CPUPWRGD [18] AB25 HCPURST# HCPURST# [6] B1 T41 B3 THERMDA C4 THERMDC A2 THERMTRIP# 2 1 THERMTRIP#_ICH R106 0 AD6 FSA FSA [5] AD5 FSB FSB [5] AC1 V5 AF4 AF3 A22 A7 AD2 AE21 AF24 AF25 Y5 Y25 Y22 Y2 W6 W3 W24 W21 V4 V26 V23 V1 U5 U25 U22 U2 T6 T3 T24 T21 R4 T14 T24 VID_PWRGD T13 T11 T8 T45 T30 VCCVID C538 0.1U C546 0.1U THERMDA 10 MILE THERMDC 10 MILE C537 2200P 1 2 3 4 U17 VDD SCLK D+ SDATA DALERT# THERM# GND ADM1032ARM 8 7 6 5 TMP_SMCLK TMP_SMDATA R399 0(R) TMP_SMCLK [28] TMP_SMDATA [28] ATF_INT# [18,28] VCCVID R401 200 TDI TMS HCPURST# R104 R99 R333 2 2 2 1 150 1 39.2_1% 1 62
Schematic Diags
VCORE
L51 1 1 L49
2 2
4.7UH(0805) 4.7UH(0805) + C476 C444 1 1
VCCIOPLL VCCCA 2 10U(0805) VSSA 2 10U(0805)
Sheet 3 of 39 CPU Northwood & Prescott (2 of 2)
+
[5] ITPCLK [5] ITPCLK# [6] HDBI3# [6] HDBI2# [6] HDBI1# [6] HDBI0# [6] HADSTB1# [6] HADSTB0# HDBI3# HDBI2# HDBI1# HDBI0#
AC26 AD26 V21 P26 G25 E21 R5 L5 AE25 E5 D1 AF23 AF22 P1 L24 W23 P23 J23 F21 W22 R22 K22 E22 A5 A4 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5 F8 G21 G24 G3
ITP_CLK0 ITP_CLK1 DB#3 DB#2 DB#1 DB#0 ADSTB1 ADSTB0 DBRESET LINT1 LINT0 BCLK1 BCLK0 COMP1 COMP0 STBP3 STBP2 STBP1 STBP0 STBN3 STBN2 STBN1 STBN0 VCC_SENSE VSS_SENSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
GTLREF0 GTLREF1 GTLREF2 GTLREF3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
TCK TRST#
R103 R100
2 2
1 27.4_1% 1 680
DBR# NMI INTR
[18] NMI [18] INTR [5] CPUCLK# [5] CPUCLK R97 R330 2 2
1 61.9_1% COMP_1 1 61.9_1% COMP_0
[6] [6] [6] [6] [6] [6] [6] [6]
HDSTBP3# HDSTBP2# HDSTBP1# HDSTBP0# HDSTBN3# HDSTBN2# HDSTBN1# HDSTBN0#
THERMTRIP#_ICH [18]
VDD3
[33] VCC_SENSE [33] VSS_SENSE
VCCVID RESERVED5/VCCVIDPRG RESERVED0 RESERVED1 VIDPWRGD RESERVED4 RESERVED6 RESERVED7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
R400
20K
VID_PWRGD [37]
T21 T27 T12 T49 T20 T23 T26 T46 T243 T48 T4 T3 T47 R102 DBR# TDI TMS TRST# HCPURST# TCK
BPM0# [2] BPM1# [2] DBR# [18] TPRDY# [2] TPREQ# [2]
R68
0
D10 C R69 A SCS751(R) 10K DD_ON [18,28,34] VDD3
ITPCLK [5] ITPCLK# [5] 47TDO
G6 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26
TDO TPWR
R101
2 R96
1 51 1.5K_1% VCORE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
All test pin close
NORTHWOOD478 VDD3 [18,19,22,24,26,27,28,31,32,34] VCC3S [2,5,9,10,11,12,16,17,18,19,20,23,25,26,27,28,31,32,37] VCORE [2,4,5,18,19,33]
B-4
Schematic Diagrams
CPU Decoupling
Put the cap on the North side of the processor
VCORE 1 1 1 1 C475 C513 10U(0805) 2 C471 C63 10U(0805) 2 1 C493 10U(0805) VCORE 1 1
BACK SIDE CPU DECOUPING
1
1
1
1
C495 10U(0805)
C497
C517 10U(0805)
C511 10U(0805)
C584 10U(0805)
C608 10U(0805)
1 2
10U(0805) 2 2
10U(0805) 2
C131 10U(0805)
10U(0805) 2 2
2
2
2
VCORE 1 1 1 1 1 1 1 1 1 1 1 1 C52 0.47U 2 2 C65 0.47U 2 C41 0.47U 2 C473 0.47U 2 C515 0.47U 2 C492 0.47U 2 C512 0.47U 2 C494 0.47U 2 C514 0.47U 2 C496 0.47U 2 C516 0.47U 2 C33 0.47U 2 1 C34 0.47U
Put the cap on the South side of the processor
VCORE 1 1 1 C114 10U(0805) 2 2 C121 10U(0805) 2 C122 10U(0805) 2 1 C571 10U(0805)
2
Schematic Diags
Sheet 4 of 39 CPU Decoupling
1 1 1 1 1 1 1 1 1 1 2 1 + C201 220U(D) C53 0.47U C38 0.47U 2 2 C36 0.47U 2 C37 0.47U 2 2 C50 0.47U 2 C51 0.47U 2 C60 0.47U 2 C61 0.47U 2 C39 0.47U + C498 C40 0.47U
VCORE 1 1 1 1 C54 0.47U 2 2 C55 0.47U 2 C64 0.47U 2 C62 0.47U 2 1
POSCAP
330U/3V_D
Put the cap in the processor cavity
VCORE 1 1 1 1 1 1 1 C66 10U(0805) 2 2 C585 10U(0805) 2 C586 10U(0805) 2 C587 10U(0805) 2 C588 10U(0805) 2 C589 10U(0805) 2 C472 1U_X7R 2 1 1 C525 1U_X7R
+2.5V
CLOSE TO SO DIMM 0
1 1 1 1 1 1 C202 10U(0805) 2 2 C204 10U(0805) 2 2 1 C190 10U(0805) 2 1 C205 0.1U_X7R 2 2 C194 0.1U_X7R 2 C193 0.1U_X7R 2 C191 0.1U_X7R 2 C195 1U_0805_X7R 2 C183 1U_0805_X7R 2 1 C187 1U_0805_X7R 10U(0805) C192
+2.5V 1 1 1 1 1 1 1 C207 0.1U_X7R 2 2 C189 0.1U_X7R 2 C188 0.1U_X7R 2 C186 0.1U_X7R 2 C182 0.1U_X7R 2 C185 0.1U_X7R 2 C181 10U(0805) 1
POSCAP
+2.5V
CLOSE TO SO DIMM 1
1 1 1 1 1 1 1 C214 0.1U_X7R 2 2 C732 0.1U_X7R 2 C257 0.1U_X7R 2 C280 0.1U_X7R 2 C274 1U_0805_X7R 2 C279 1U_0805_X7R 1U_0805_X7R 2 2 1 C277 C281 10U(0805) +2.5V [7,9,10,35,36] VCORE [2,3,5,18,19,33] 1 1 2 C730 10U(0805) 2 2 C723 10U(0805) + C273 220U(D)
+2.5V 1 1 1 1 1 1 C278 0.1U_X7R 2 2 C275 0.1U_X7R 2 C758 0.1U_X7R 2 C276 0.1U_X7R 2 C734 0.1U_X7R 2 C731 0.1U_X7R 1
POSCAP
B - 5
Schematic Diagrams
CLK409
VCC3S
L60
BK2125HS601 1 C638 10U(0805) 2
VCC3_CLKA C639 0.1U C640 0.1U
CLOSED CK-409
U20
55 34 VDDA VDD48 VDDREF VDDPCI VDDPCI VDD3V66 VDDSRC VDDCPU VDDCPU SCLK SDATA PD# PCI_STOP# CPU_STOP# 3V66_0/Reset# 3V66_1 3V66_2 3V66_3 3V66_4/VCH_CLK 24_48MHz/SEL24_48# 48MHz_0/FS3 REF0 REF1 CPUCLK_0 CPUCLK_0# FS_A FS_B IREF GND GND GND GND GND GND GND GND GND CPUCLK_1 CPUCLK_1# CPUCLK_2 CPUCLK_2# SRCCLKC SRCCLKT X1 X2 PCICLK0/Reset_EN PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK_FS2 PCICLK_FS4 PCICLK_F2 12 13 14 15 18 19 20 7 8 9 22 23 26 27 29 31 32 1 2 41 40 44 43 47 46 37 38 4 1M(R) 5 R479 Y3 1 1 C651 18P 2 R427 2 1 C680 18P 2 33_1% R426 33_1% R429 33_1% R428 33_1% R431 R430 R125 R124 CPUCLK_0 CPUCLK_0# CPUCLK_1 CPUCLK_1# CPUCLK_2 CPUCLK_2# R488 R489 R490 R491 R492 R493 R494 R486 R487 33 33 33 33 33 33 33 33 33 CLK_ICHPCI PCLK_LAN PCLK_RAID MINIPCICLK PCLK_1394 PCLK_CARDBUS PCLK_H8 PCLK_LPC PCLK_80P CLK_ICHPCI [18] PCLK_LAN [31] PCLK_RAID [21] MINIPCICLK [27] PCLK_1394 [30] PCLK_CARDBUS [29] PCLK_H8 [28] PCLK_LPC [25] PCLK_80P [27]
VCC3S 1 C681 10U(0805)
L18 C682 0.01U
BK2125HS601 1 1 C660 2
VCC3_CLK C160 C164 C163 C162 0.1U 0.1U C161 C142 C141 1U(0805) 0.1U C135 C136 C137 0.1U 0.1U C144 C661 C143 0.1U 0.1U 0.01U
3 10 16 24 36 42 48
10U(0805) 4.7U(1206) 0.1U 2
0.1U 1U(0805)
2
[9,18,31] SMB_ICHCLK [9,18,31] SMB_ICHDATA
28 30 21
T321
T313
R495 R496 R154 C700 1 R467 R466 R484 R485 R462 R463 R460 R461 R458 R459 R465 R464
33 33 33 2 10P(R) 33 33 22 33 33 33 33 33 33 33 33(R) 33(R)
CLK66_ICH_HUB CPU66IN_MCH G_66M_ATI_M10 CLK48_IO CLK48_USB 14.3M_AUDIO 14.3M_ICH5
CLK66_ICH_HUB [19] CPU66IN_MCH [6] G_66M_ATI_M10 [11] CLK48_IO [25] CLK48_USB [19] 14.3M_AUDIO [23] 14.3M_ICH5 [18] ITPCLK ITPCLK# MCHCLK MCHCLK# CPUCLK CPUCLK# SATACLK SATACLK# ITPCLK [3] ITPCLK# [3] MCHCLK [6] MCHCLK# [6] CPUCLK [3] CPUCLK# [3] SATACLK [18] SATACLK# [18]
Schematic Diags
VCC3_CLK
R143
33
49 50
Sheet 5 of 39 CLK409
VR_PWRGD_CK409# 35 [3] FSB [3] FSA [6] BSEL0 [6] BSEL1 R425 R422 2K_1% 2K_1% 51 56 52 R121 R424 2.49K_1% R423 2.49K_1% 1K 1K R146 R421 6 11 17 25 33 39 45 53 54
VTT_PWRGD#
VCC3_CLK
475_1%
CY48209/ICS952605
49.9_1% 49.9_1% 49.9_1% 49.9_1%
14.318MHz
FSB
0 0 1 1
FSA
0 1 0 1
FUNCTION
100 MHz HOST CLK 133 MHz HOST CLK 200 MHz HOST CLK 166 MHz HOST CLK
VCC3_CLK CLK_ICHPCI PCLK_LAN PCLK_RAID MINIPCICLK PCLK_1394 C174 1 C173 1 C172 1 C171 1 C170 1 2 10P 2 10P 2 10P 2 10P 2 10P 2 10P 2 10P 2 10P 2 10P 2 10P 2 10P
PCLK_CARDBUS C169 1 PCLK_H8 PCLK_LPC PCLK_80P R138 10K VR_PWRGD_CK409# C VCORE R477 10K 1 B C652 2.2U(0805) 2 Q4 E 2N3904 R137 0(R) CLK48_IO CLK48_USB C168 1 C176 1 C175 1 C129 1 C130 1
CAP should be placed near CK-409
VCORE [2,3,4,18,19,33] VCC3S [2,9,10,11,12,16,17,18,19,20,23,25,26,27,28,31,32,37]
B-6
Schematic Diagrams
Springdale (HOST, AGP, Hub)
[2] HA[3..31] HA[3..31] HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31 HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HADSTB0# HADSTB1# MCHCLK MCHCLK# HDSTBP0# HDSTBN0# HDBI0# HDSTBP1# HDSTBN1# HDBI1# HDSTBP2# HDSTBN2# HDBI2# HDSTBP3# HDSTBN3# HDBI3# D26 D30 L23 E29 B32 K23 C30 C31 J25 B31 E30 B33 J24 F25 D34 C32 F28 C34 J27 G27 F29 E28 H27 K24 E32 F31 G30 J26 G26 B29 J23 L22 C29 J21 B30 D28 B7 C7 B19 C19 C17 L19 K19 L17 G9 F9 L14 D12 E12 C15 HD[0..63] HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 B23 E22 B21 D20 B22 D22 B20 C21 E18 E20 B16 D16 B18 B17 E16 D18 G20 F17 E19 F19 J17 L18 G16 G18 F21 F15 E15 E21 J19 G14 E17 K17 J15 L16 J13 F13 F11 E13 K15 G12 G10 L15 E11 K13 J11 H10 G8 E9 B13 E14 B14 B12 B15 D14 C13 B11 D10 C11 E10 B10 C9 B9 D8 B8 L20 L13 L12 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 PROCHOT# BSEL0 BSEL1 [11] G_CBE#[0..3] HD[0..63] [2] G_CBE#[0..3] G_CBE#0 G_CBE#1 G_CBE#2 G_CBE#3 [11] G_FRAME# [5] CPU66IN_MCH [11] G_DEVSEL# [11] G_IRDY# [11] G_TRDY# [11] G_STOP# [11] G_PAR [11] G_REQ# [11] G_GNT# VCC1.5S [11] G_RBF# [11] G_WBF# [11] DB_HI [11] DB_LO [11] ST[0..2] R407 G_FRAME# CPU66IN_MCH G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# 62_1% GRCOMP GSWING MCHAGPREF G_RBF# G_WBF# DB_HI DB_LO ST[0..2] ST0 ST1 ST2 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HLSTBF HLSTBS R410 52.3_1% HCOMP HUBSWING HUBREF T275 T264 T287 T261 T271 T260 T273 T262 T272 T274 T263 T265 T266 VCC1.5S R90 51.1_1% WISWING1 WIVREF1 T69 ICHSYNC# T289 T288 T113 T112 T61 Y7 W5 AA3 U2 U6 H4 AB4 V11 AB5 W11 AB2 N6 M7 AC2 AC3 AD2 R10 R9 M4 M5 N3 N5 N2 AF5 AG3 AK2 AG5 AK5 AL3 AL2 AL4 AJ2 AH2 AJ3 AH5 AH4 AD4 AE3 AE2 AK7 AH7 AD11 AF7 AD7 AC10 AF8 AG7 AE9 AH9 AG6 AJ6 AJ5 AG2 AF2 AF4 G4 AP8 AJ8 AK4 AG10 AG9 AN35 AP34 AR1 BGA2D GCBE0 GCBE1 GCBE2 GCBE3 GFRAME GCLKIN GDEVSEL GIRDY GTRDY GSTOP GPAR/ADD_DETECT GREQ GGNT GRCOMP GSWING GVREF GRBF GWBF DBI_HI DBI_LO GST0 GST1 GST2 HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HISTRF HISTRS GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GSBA0# GSBA1# GSBA2# GSBA3# GSBA4# GSBA5# GSBA6# GSBA7# G_AD[0..31] AE6 AC11 AD5 AE5 AA10 AC9 AB11 AB7 AA9 AA6 AA5 W10 AA11 W6 W9 V7 AA2 Y4 Y2 W2 Y5 V2 W3 U3 T2 T4 T5 R2 P2 P5 P4 M2 R6 P7 R3 R5 U9 U10 U5 T7 G_AD0 G_AD1 G_AD2 G_AD3 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD9 G_AD10 G_AD11 G_AD12 G_AD13 G_AD14 G_AD15 G_AD16 G_AD17 G_AD18 G_AD19 G_AD20 G_AD21 G_AD22 G_AD23 G_AD24 G_AD25 G_AD26 G_AD27 G_AD28 G_AD29 G_AD30 G_AD31 SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 G_AD[0..31] [11]
BGA2A HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HADSTB0# HADSTB1# HCLKP HCLKN HDSTBP0# HDSTBN0# DINV0# HDSTBP1# HDSTBN1# DINV1# HDSTBP2# HDSTBN2# DINV2# HDSTBP3# HDSTBN3# DINV3# ADS# HTRDY# ADRDY# DEFER# HITM# HIT# HLOCK# BREQ0# BNR# BPRI# DBSY# RS0# RS1# RS2# CPURST# PWROK# HDRCOMP HDSWING HDVREF SPDG MCH
VCC1.5S
[11] G_PAR
G_PAR
R52 60.4_1% GSWING R51 39.2_1% C529 1U C539 0.1U
AGP
R65 10K(R)
MCHAGPREF R50 30.1_1% 0.1U C71 C72 1U
[19] HL[0..10]
HL[0..10]
Schematic Diags
FSB
[2] HREQ0# [2] HREQ1# [2] HREQ2# [2] HREQ3# [2] HREQ4# [3] HADSTB0# [3] HADSTB1# [5] MCHCLK [5] MCHCLK# [3] HDSTBP0# [3] HDSTBN0# [3] HDBI0# [3] HDSTBP1# [3] HDSTBN1# [3] HDBI1# [3] HDSTBP2# [3] HDSTBN2# [3] HDBI2# [3] HDSTBP3# [3] HDSTBN3# [3] HDBI3# [3] ADS# [3] HTRDY# [3] HDRDY# [3] DEFER# [3] HITM# [3] HIT# [3] HLOCK# [3] BR0# [3] BNR# [3] BPRI# [3] DBSY# [2] HRS0# [2] HRS1# [2] HRS2# [3] HCPURST# PWROK_GMCH R409 20_1%
HUB
SBA[0..7]
SBA[0..7] [11]
Please near GMCH
[19] HLSTBF [19] HLSTBS VCC1.5S VCC1.5S [19] HUBSWING [19] HUBREF
Sheet 6 of 39 Springdale (HOST, AGP, Hub)
HI_RCOMP HI_SWING HI_VREF CI0 CI1 CI2 CI3 CI4 CI5 CI6 CI7 CI8 CI9 CI10 CISTRF CISTRS
R85 226_1% WISWING1 C99 R78 147_1% 1U C98 0.1U
GADSTBF0 GADSTBS0 GADSTBF1 GADSTBS1 GSBSTBF GSBSTBS DDCA_DATA DDCA_CLK
AC6 AC5 V4 V5 U11 T11 H3 F2 F4 E4 H6 G5 H7 G6 G3 E2 D2 A3 A33 A35 AF13 AF23 AJ12 AN1 AP2 AR3 AR33 AR35 B2 B25 B34 C1 C23 C35 E26 M31 R25
AD_STB0 AD_STB0# AD_STB1 AD_STB1# SB_STB SB_STB#
AD_STB0 [11] AD_STB0# [11] AD_STB1 [11] AD_STB1# [11] SB_STB [11] SB_STB# [11]
CLOSE TO GMCH
CSA
F27 ADS# D24 HTRDY# G24 HDRDY# L21 DEFER# E23 HITM# K21 HIT# E25 HLOCK# B24 BR0# B28 BNR# B26 BPRI# E27 DBSY# G22 HRS0# C27 HRS1# B27 HRS2# E8 HCPURST# PWROK_GMCH AE14 HDRCOMP HDSWING HGTLREF E24 C25 F23 C556 0.1U
VGA
WIVREF1 C548 R77 113_1% 1U C549 0.1U
CI_RCOMP CI_SWING CI_VREF DREFCLK EXTTS# ICH_SYNC# RSTIN# RESERVED_1 RESERVED_2 RESERVED_3 RESERVED_4 RESERVED_5
RED RED# GREEN GREEN# BLUE BLUE# HSYNC VSYNC REFSET NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20
T19 T15 REFSET T18 T55 T54 T270 T303 T290 T60 T62 T68 T105 T114 T17 T37 T64 T16 T36 T63 T259 T295 T269 R39 0
PROCHOT# BSEL0 BSEL1
PROCHOT# [3] [11,18,19,22,25,27,28] BSEL0 [5] BSEL1 [5] GMCHVCCP PCIRST#
[18] ICHSYNC# R110 0
C112 10P
R405 200_1% HGTLREF HGTLREF [3]
VCC1.5S
CLOSE TO GMCH
GMCHVCCP VCC3 C540 C89 0.1U 1U
R64 226_1% HUBSWING
HUBSWING [19] SPDG MCH
CLOSE TO GMCH
C100 1U(R)
R81 301_1% HDSWING [18,28] SUSB# SUSB# PWROK
C659 0.1U 5 2 1 3 U4 4 PWROK_GMCH 74AHC1G08(SC-88A)
R80 147_1% HUBREF GMCHVCCP [10,35] VCC1.5S [10,16,19,32] VCC3 [18,19,20,21,22,25,27,29,30,32,33,34,35,36,37]
HUBREF [19]
C97 C88 0.1U 1U R79 113_1%
C547 0.1U
R406 102_1%
[18,32] PWROK
DIVIDER PLACE MIDDDLE BETWEEN GMCH AND ICH
B - 7
Schematic Diagrams
Springdale (DDR Interface)
[8,9] SMAA_A[0..12] SMAA_A[0..12] SMAA_A0 SMAA_A1 SMAA_A2 SMAA_A3 SMAA_A4 SMAA_A5 SMAA_A6 SMAA_A7 SMAA_A8 SMAA_A9 SMAA_A10 SMAA_A11 SMAA_A12 T115 T106 T111 T110 T103 SWE_A# SCAS_A# SRAS_A# SBA_A0 SBA_A1 SCS_A0# SCS_A1# T94 T86 SCKE_A0 SCKE_A1 T85 T84 AJ34 AL33 AK29 AN31 AL30 AL26 AL28 AN25 AP26 AP24 AJ33 AN23 AN21 AL34 AM34 AP32 AP31 AM26 AB34 Y34 AC33 AE33 AH34 AA34 Y31 Y32 W34 AL20 AN19 AM20 AP20 BGA2B SMAA_A0 SMAA_A1 SMAA_A2 SMAA_A3 SMAA_A4 SMAA_A5 SMAA_A6 SMAA_A7 SMAA_A8 SMAA_A9 SMAA_A10 SMAA_A11 SMAA_A12 SMAB_A1 SMAB_A2 SMAB_A3 SMAB_A4 SMAB_A5 SWE_A# SCAS_A# SRAS_A# SBA_A0 SBA_A1 SCS_A0# SCS_A1# SCS_A2# SCS_A3# SCKE_A0 SCKE_A1 SCKE_A2 SCKE_A3 SCMDCLK_A0 SCMDCLK_A0# SCMDCLK_A1 SCMDCLK_A1# SCMDCLK_A2 SCMDCLK_A2# SCMDCLK_A3 SCMDCLK_A3# SCMDCLK_A4 SCMDCLK_A4# SCMDCLK_A5 SCMDCLK_A5# SDQ_A0 SDQ_A1 SDQ_A2 SDQ_A3 SDQ_A4 SDQ_A5 SDQ_A6 SDQ_A7 SDQ_A8 SDQ_A9 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15 SDQ_A16 SDQ_A17 SDQ_A18 SDQ_A19 SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23 SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31 SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39 SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55 SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63 SDQ_A[0..63] AP10 SDQ_A0 AP11 SDQ_A1 AM12SDQ_A2 AN13 SDQ_A3 AM10SDQ_A4 AL10 SDQ_A5 AL12 SDQ_A6 AP13 SDQ_A7 AP14 SDQ_A8 AM14SDQ_A9 AL18 SDQ_A10 AP19 SDQ_A11 AL14 SDQ_A12 AN15 SDQ_A13 AP18 SDQ_A14 AM18SDQ_A15 AP22 SDQ_A16 AM22SDQ_A17 AL24 SDQ_A18 AN27 SDQ_A19 AP21 SDQ_A20 AL22 SDQ_A21 AP25 SDQ_A22 AP27 SDQ_A23 AP28 SDQ_A24 AP29 SDQ_A25 AP33 SDQ_A26 AM33SDQ_A27 AM28SDQ_A28 AN29 SDQ_A29 AM31SDQ_A30 AN34 SDQ_A31 AH32 SDQ_A32 AG34SDQ_A33 AF32 SDQ_A34 AD32 SDQ_A35 AH31 SDQ_A36 AG33SDQ_A37 AE34 SDQ_A38 AD34 SDQ_A39 AC34 SDQ_A40 AB31 SDQ_A41 V32 SDQ_A42 V31 SDQ_A43 AD31 SDQ_A44 AB32 SDQ_A45 U34 SDQ_A46 U33 SDQ_A47 T34 SDQ_A48 T32 SDQ_A49 K34 SDQ_A50 K32 SDQ_A51 T31 SDQ_A52 P34 SDQ_A53 L34 SDQ_A54 L33 SDQ_A55 J33 SDQ_A56 H34 SDQ_A57 E33 SDQ_A58 F33 SDQ_A59 K31 SDQ_A60 J34 SDQ_A61 G34 SDQ_A62 F34 SDQ_A63 SDQS_A[0..7] SDQS_A0 SDQS_A1 SDQS_A2 SDQS_A3 SDQS_A4 SDQS_A5 SDQS_A6 SDQS_A7 AN11 SDQS_A0 AP15 SDQS_A1 AP23 SDQS_A2 AM30SDQS_A3 AF34 SDQS_A4 V34 SDQS_A5 M32 SDQS_A6 H31 SDQS_A7 SDQS_A[0..7] [8,9] SDREFB C623 C125 SDREFB AP9 SDQ_A[0..63] [8,9] [8,9] SMAA_B[0..12] SMAA_B[0..12] SMAA_B0 SMAA_B1 SMAA_B2 SMAA_B3 SMAA_B4 SMAA_B5 SMAA_B6 SMAA_B7 SMAA_B8 SMAA_B9 SMAA_B10 SMAA_B11 SMAA_B12 T301 T302 T312 T311 T297 SWE_B# SCAS_B# SRAS_B# SBA_B0 SBA_B1 SCS_B0# SCS_B1# T283 T284 SCKE_B0 SCKE_B1 T285 T286 AG31 AJ31 AD27 AE24 AK27 AG25 AL25 AF21 AL23 AJ22 AF29 AL21 AJ20 AE27 AD26 AL29 AL27 AE23 W27 W31 W26 Y25 AA25 U26 T29 V25 W25 AK19 AF19 AG19 AE18 BGA2C SMAA_B0 SMAA_B1 SMAA_B2 SMAA_B3 SMAA_B4 SMAA_B5 SMAA_B6 SMAA_B7 SMAA_B8 SMAA_B9 SMAA_B10 SMAA_B11 SMAA_B12 SMAB_B1 SMAB_B2 SMAB_B3 SMAB_B4 SMAB_B5 SWE_B# SCAS_B# SRAS_B# SBA_B0 SBA_B1 SCS_B0# SCS_B1# SCS_B2# SCS_B3# SCKE_B0 SCKE_B1 SCKE_B2 SCKE_B3 SCMDCLK_B0 SCMDCLK_B0# SCMDCLK_B1 SCMDCLK_B1# SCMDCLK_B2 SCMDCLK_B2# SCMDCLK_B3 SCMDCLK_B3# SCMDCLK_B4 SCMDCLK_B4# SCMDCLK_B5 SCMDCLK_B5# SDQ_B0 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B4 SDQ_B5 SDQ_B6 SDQ_B7 SDQ_B8 SDQ_B9 SDQ_B10 SDQ_B11 SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15 SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23 SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31 SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47 SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55 SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63 SDQ_B[0..63] AJ10 SDQ_B0 AE15 SDQ_B1 AL11 SDQ_B2 AE16 SDQ_B3 AL8 SDQ_B4 AF12 SDQ_B5 AK11 SDQ_B6 AG12SDQ_B7 AE17 SDQ_B8 AL13 SDQ_B9 AK17 SDQ_B10 AL17 SDQ_B11 AK13 SDQ_B12 AJ14 SDQ_B13 AJ16 SDQ_B14 AJ18 SDQ_B15 AE19 SDQ_B16 AE20 SDQ_B17 AG23SDQ_B18 AK23 SDQ_B19 AL19 SDQ_B20 AK21 SDQ_B21 AJ24 SDQ_B22 AE22 SDQ_B23 AK25 SDQ_B24 AH26 SDQ_B25 AG27SDQ_B26 AF27 SDQ_B27 AJ26 SDQ_B28 AJ27 SDQ_B29 AD25 SDQ_B30 AF28 SDQ_B31 AE30 SDQ_B32 AC27 SDQ_B33 AC30 SDQ_B34 Y29 SDQ_B35 AE31 SDQ_B36 AB29 SDQ_B37 AA26 SDQ_B38 AA27 SDQ_B39 AA30 SDQ_B40 W30 SDQ_B41 U27 SDQ_B42 T25 SDQ_B43 AA31 SDQ_B44 V29 SDQ_B45 U25 SDQ_B46 R27 SDQ_B47 P29 SDQ_B48 R30 SDQ_B49 K28 SDQ_B50 L30 SDQ_B51 R31 SDQ_B52 R26 SDQ_B53 P25 SDQ_B54 L32 SDQ_B55 K30 SDQ_B56 H29 SDQ_B57 F32 SDQ_B58 G33 SDQ_B59 N25 SDQ_B60 M25 SDQ_B61 J29 SDQ_B62 G32 SDQ_B63 SDQS_B[0..7] SDQS_B0 SDQS_B1 SDQS_B2 SDQS_B3 SDQS_B4 SDQS_B5 SDQS_B6 SDQS_B7 AF15 SDQS_B0 AG13SDQS_B1 AG21SDQS_B2 AH27 SDQS_B3 AD29 SDQS_B4 U30 SDQS_B5 L27 SDQS_B6 J30 SDQS_B7 SDQS_B[0..7] [8,9] SDQ_B[0..63] [8,9]
[8,9] SWE_A# [8,9] SCAS_A# [8,9] SRAS_A# [8,9] SBA_A0 [8,9] SBA_A1
DDR Channel A Interface
[8,9] SWE_B# [8,9] SCAS_B# [8,9] SRAS_B# [8,9] SBA_B0 [8,9] SBA_B1 [8,9] SCS_B0# [8,9] SCS_B1#
Schematic Diags
Sheet 7 of 39 Springdale (DDR Interface)
[8,9] SCS_A0# [8,9] SCS_A1#
[8,9] SCKE_A0 [8,9] SCKE_A1
[8,9] SCKE_B0 [8,9] SCKE_B1
[9] [9] [9] [9] [9] [9]
DDRCLK_A0 DDRCLK_A0# DDRCLK_A1 DDRCLK_A1# DDRCLK_A2 DDRCLK_A2#
DDRCLK_A0 AK32 DDRCLK_A0# AK31 DDRCLK_A1 AP17 DDRCLK_A1# AN17 DDRCLK_A2 N33 DDRCLK_A2# N34 T116 AK33 T107 AK34 T83 AM16 T299 AL16 T281 P31 T296 P32
[9] [9] [9] [9] [9] [9]
DDRCLK_B0 DDRCLK_B0# DDRCLK_B1 DDRCLK_B1# DDRCLK_B2 DDRCLK_B2#
DDRCLK_B0 AG29 DDRCLK_B0# AG30 DDRCLK_B1 AF17 DDRCLK_B1# AG17 DDRCLK_B2 N27 DDRCLK_B2# N26 T310 AJ30 T306 AH29 T298 AK15 T300 AL15 T280 N31 T282 N30
[8,9] SDM_A[0..7]
SDM_A[0..7] SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 AP12 AP16 AM24 AP30 AF31 W33 M34 H32 SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7
[8,9] SDM_B[0..7]
SDM_B[0..7] SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 AG11 AG15 AE21 AJ28 AC31 U31 M29 J31 SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7
SDREFA C119 C120
SDREFA SMXRCOMP SMXVOH SMXVOL
E34 AK9 AN9 AL9
SMVREF_A SMXRCOMP SMXRCOMPVOH SMXRCOMPVOL SPDG MCH
SMVREF_B SMYRCOMP SMYRCOMPVOH SMYRCOMPVOL
SMYRCOMP AA33 SMYVOH SMYVOL R34 R33
10U(0805) 0.1U
10U(0805) 0.1U
SPDG MCH
close to pin E34
close to pin AP9
+2.5V R456
+2.5V R126
+2.5V R133
+2.5V
VSMYRC
VSMYRCO R454
VSMYRCO
C124 10U(0805)
R420
C657 0.1U
R476
C634
R444
42.2_1% SMXRCOMP C592 0.1U R457 C594 0.1U
30.1K_1% SMXVOL R127 C595 0.1U
10K_1% SMXVOH R128
150_1% SDREFB R446 C637 1U C636 0.1U
42.2_1% SMYRCOMP R475 C622 0.1U
30.1K_1% SMYVOL R455
10U(0805) 10K_1% SMYVOH C621 0.1U R445 +2.5V [4,9,10,35,36]
42.2_1%
10K_1%
30.1K_1%
150_1%
42.2_1%
10K_1%
30.1K_1%
B-8
DDR Channel B Interface
Schematic Diagrams
DDR Termination
+1.25V +1.25V SDQ_A0 1 SDQ_A1 2 SDQS_A0 3 SDQ_A2 4 RN63 SDQ_A6 8 SDM_A0 7 SDQ_A5 6 SDQ_A4 5 RN161 SDQ_A3 1 SDQ_A9 2 SDQ_A8 3 SDQS_A1 4 RN64 SDM_A1 8 SDQ_A13 7 SDQ_A12 6 SDQ_A7 5 RN160 SDQS_A2 8 SDQ_A18 7 SDQ_A19 6 SDQ_A24 5 RN75 SDQ_A28 8 SDQ_A23 7 SDQ_A22 6 SDM_A2 5 RN158 SDQS_A3 8 SDQ_A25 7 SDQ_A27 6 SDQ_A26 5 RN76 SDQ_A31 8 SDQ_A30 7 SDM_A3 6 SDQ_A29 5 RN157 SDQ_A32 1 SDQ_A33 2 SDQS_A4 3 SDQ_A34 4 RN69 SDM_A5 8 SDQ_A45 7 SDQ_A44 6 SDQ_A39 5 RN154 SDQ_A35 1 SDQ_A40 2 SDQ_A41 3 SDQ_A43 4 RN70 SDQ_A53 8 SDQ_A52 7 SDQ_A47 6 SDQ_A46 5 RN153 SDQS_A6 1 SDQ_A50 2 SDQ_A51 3 SDQ_A56 4 RN72 SDQ_A60 8 SDQ_A55 7 SDQ_A54 6 SDM_A6 5 RN152 SDQ_A57 1 SDQS_A7 2 SDQ_A59 3 SDQ_A58 4 RN73 SDQ_A63 8 SDQ_A62 7 SDM_A7 6 SDQ_A61 5 RN151 8 7 6 5 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 8 7 6 5 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 8 7 6 5 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 8 7 6 5 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 8 7 6 5 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) 8 7 6 5 8P4R_56(0402) 1 2 3 4 8P4R_56(0402) C754 0.1U SDQ_A11 1 SDQ_A10 2 SDQ_A17 3 SDQ_A16 4 RN65 SDQS_A5 1 SDQ_A42 2 SDQ_A48 3 SDQ_A49 4 RN71 8 C231 0.1U 7 6 5 8P4R_56(0402) 8 C294 0.1U 7 6 5 8P4R_56(0402) SDQ_B2 1 SDQS_B0 2 SDQ_B1 3 SDQ_B0 4 RN140 SDQ_B4 8 SDQ_B5 7 SDM_B0 6 SDQ_B6 5 RN51 SDQS_B1 1 SDQ_B9 2 SDQ_B8 3 SDQ_B3 4 RN139 SDQ_B7 8 SDQ_B12 7 SDQ_B13 6 SDM_B1 5 RN52 SDQ_B24 1 SDQ_B19 2 SDQ_B18 3 SDQS_B2 4 RN137 SDM_B2 1 SDQ_B22 2 SDQ_B23 3 SDQ_B28 4 RN46 SDQ_B27 1 SDQ_B26 2 SDQS_B3 3 SDQ_B25 4 RN136 SDQ_B29 1 SDM_B3 2 SDQ_B31 3 SDQ_B30 4 RN47 SDQ_B34 1 SDQS_B4 2 SDQ_B33 3 SDQ_B32 4 RN133 SDQ_B37 8 SDQ_B36 7 SDQ_B38 6 SDM_B4 5 RN56 SDQS_B5 1 SDQ_B41 2 SDQ_B40 3 SDQ_B35 4 RN132 SDQ_B39 8 SDQ_B44 7 SDQ_B45 6 SDM_B5 5 RN57 SDQ_B56 1 SDQ_B51 2 SDQ_B50 3 SDQS_B6 4 RN130 SDM_B6 8 SDQ_B54 7 SDQ_B55 6 SDQ_B60 5 RN59 SDQ_B59 1 SDQ_B58 2 SDQS_B7 3 SDQ_B57 4 RN129 SDQ_B61 8 SDM_B7 7 SDQ_B62 6 SDQ_B63 5 RN60
+1.25V +1.25V 8 C690 7 6 5 8P4R_56(0402) 1 C688 2 3 4 8P4R_56(0402) 8 C686 7 6 5 8P4R_56(0402) 1 C692 2 3 4 8P4R_56(0402) 8 C696 7 6 5 8P4R_56(0402) 8 C698 7 6 5 8P4R_56(0402) 8 C699 7 6 5 8P4R_56(0402) 8 C695 7 6 5 8P4R_56(0402) 8 C218 7 6 5 8P4R_56(0402) 1 C221 2 3 4 8P4R_56(0402) 8 C220 7 6 5 8P4R_56(0402) 1 C216 2 3 4 8P4R_56(0402) 8 C212 7 6 5 8P4R_56(0402) 1 C213 2 3 4 8P4R_56(0402) 8 C211 7 6 5 8P4R_56(0402) 1 C223 2 3 4 8P4R_56(0402) 0.1U 1 SDQ_B17 2 SDQ_B16 3 SDQ_B11 4 SDQ_B10 RN138 SDQ_B49 1 SDQ_B48 2 SDQ_B43 3 SDQ_B42 4 RN131 8 C689 0.1U 7 6 5 8P4R_56(0402) 8 C687 0.1U 7 6 5 8P4R_56(0402)
C230 0.1U
0.1U
C229 0.1U
0.1U
C232 0.1U SDQ_A21 8 SDQ_A20 7 SDQ_A15 6 SDQ_A14 5 RN159 SDQ_A38 8 SDM_A4 7 SDQ_A37 6 SDQ_A36 5 RN155 1 C753 0.1U 2 3 4 8P4R_56(0402) 1 C289 0.1U 2 3 4 8P4R_56(0402)
0.1U SDQ_B14 SDQ_B15 SDQ_B20 SDQ_B21 RN53 SDQ_B47 SDQ_B46 SDQ_B52 SDQ_B53 RN58 8 7 6 5 8 7 6 5 1 C693 0.1U 2 3 4 8P4R_56(0402) 1 C697 0.1U 2 3 4 8P4R_56(0402)
C288 0.1U
0.1U
Schematic Diags
C291 0.1U
0.1U
C756 0.1U SMAA_A2 8 SMAA_A4 7 SMAA_A6 6 SMAA_A8 5 RN156 1 C757 0.1U 2 3 4 8P4R_47(0402) 8 C292 0.1U 7 6 5 8P4R_47(0402) 8 C240 0.1U 7 6 5 8P4R_47(0402) 47(0402)
0.1U SCS_B0# 1 SBA_B0 2 SMAA_B10 3 SMAA_B1 4 RN134 8 C694 0.1U 7 6 5 8P4R_47(0402) 8 C217 0.1U 7 6 5 8P4R_47(0402) 1 C222 0.1U 2 3 4 8P4R_47(0402) 47(0402)
Sheet 8 of 39 DDR Termination
C755 0.1U
0.1U
[7,9] SCS_B0# [7,9] SBA_B0
C295 0.1U
C238 0.1U
C293 0.1U
SMAA_A3 1 SMAA_A1 2 SMAA_A0 3 SMAA_A10 4 RN67 SMAA_A5 1 SMAA_A7 2 SMAA_A9 3 SMAA_A11 4 RN66 SMAA_A12 R195
0.1U
0.1U
0.1U
SMAA_B3 1 SMAA_B5 2 SMAA_B7 3 SMAA_B9 4 RN135 SMAA_B11 8 SMAA_B8 7 SMAA_B6 6 SMAA_B4 5 RN54 SMAA_B12 R506
C287 0.1U
[7,9] SBA_A0 [7,9] SBA_A1 [7,9] SCS_A0# [7,9] SCS_A1# [7,9] SWE_A# [7,9] SCAS_A# [7,9] SRAS_A#
C236 0.1U
SBA_A0 SBA_A1 SCS_A0# SCS_A1# RN68 SWE_A# SCAS_A# SRAS_A#
1 2 3 4 R196 R546 R547
8 C239 0.1U 7 6 5 8P4R_47(0402) 47(0402) C237 0.1U 47(0402) 47(0402)
0.1U
[7,9] SBA_B1 [7,9] SCS_B1# [7,9] SWE_B# [7,9] SCAS_B# [7,9] SRAS_B#
0.1U
SMAA_B0 8 SMAA_B2 7 SBA_B1 6 SCS_B1# 5 RN55 SWE_B# R176 SCAS_B# R177 SRAS_B# R178
1 C219 0.1U 2 3 4 8P4R_47(0402) 47(0402) C215 0.1U 47(0402) 47(0402)
C235 0.1U
[7,9] SCKE_A0 [7,9] SCKE_A1
SCKE_A0 R548 SCKE_A1 R208
47(0402) 47(0402)
C234 0.1U
0.1U
[7,9] SCKE_B0 [7,9] SCKE_B1
SCKE_B0 SCKE_B1
R175 R507
47(0402) 47(0402)
C691 0.1U
C233 0.1U
+1.25V
0.1U
+1.25V
1
C290 0.1U 2
+ C228 220U(D)
1
C256
C735
4.7U(0805) 4.7U(0805)
0.1U 2
+ C704 220U(D)
C184
C166
4.7U(0805) 4.7U(0805)
Place close to SO-DIMM0
Place close to SO-DIMM1
SDQ_A[0..63] SDQS_A[0..7] SDM_A[0..7] SMAA_A[0..12]
SDQ_A[0..63] [7,9] SDQS_A[0..7] [7,9] SDM_A[0..7] [7,9] SMAA_A[0..12] [7,9]
SDQ_B[0..63] SDQS_B[0..7] SDM_B[0..7] SMAA_B[0..12]
SDQ_B[0..63] [7,9] SDQS_B[0..7] [7,9] SDM_B[0..7] [7,9] SMAA_B[0..12] [7,9]
+1.25V [35]
B - 9
Schematic Diagrams
DDR SODIMM
+2.5V [7,8] SDQ_A[0..63] SDQ_A[0..63]
+2.5V [7,8] SDQ_B[0..63] SDQ_B[0..63]
9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192
U22 [7,8] SMAA_A[0..12] SMAA_A[0..12] SMAA_A0 SMAA_A1 SMAA_A2 SMAA_A3 SMAA_A4 SMAA_A5 SMAA_A6 SMAA_A7 SMAA_A8 SMAA_A9 SMAA_A10 SMAA_A11 SMAA_A12 [7,8] SBA_A0 [7,8] SBA_A1 [7,8] SDM_A[0..7] SBA_A0 SBA_A1 SDM_A[0..7] SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 112 111 110 109 108 107 106 105 102 101 115 100 99 117 116 12 26 48 62 134 148 170 184 78 11 25 47 61 133 147 169 183 77 118 119 120 121 122 96 95 35 37 160 158 89 91 193 195 71 73 79 83 72 74 80 84 1 2 197 199
U21 [7,8] SMAA_B[0..12] DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 13 17 6 8 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 85 123 124 200 86 97 98 194 196 198 SDQ_A0 SDQ_A1 SDQ_A2 SDQ_A3 SDQ_A4 SDQ_A5 SDQ_A6 SDQ_A7 SDQ_A8 SDQ_A9 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15 SDQ_A16 SDQ_A17 SDQ_A18 SDQ_A19 SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23 SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31 SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39 SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55 SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63 SMAA_B[0..12] SMAA_B0 SMAA_B1 SMAA_B2 SMAA_B3 SMAA_B4 SMAA_B5 SMAA_B6 SMAA_B7 SMAA_B8 SMAA_B9 SMAA_B10 SMAA_B11 SMAA_B12 [7,8] SBA_B0 [7,8] SBA_B1 [7,8] SDM_B[0..7] SBA_B0 SBA_B1 SDM_B[0..7] SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 112 111 110 109 108 107 106 105 102 101 115 100 99 117 116 12 26 48 62 134 148 170 184 78 11 25 47 61 133 147 169 183 77 118 119 120 121 122 96 95 35 37 160 158 89 91 193 195 71 73 79 83 72 74 80 84 1 2 197 199
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 BA0 BA1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 RAS# WE# CAS# S0# S1# CKE0 CKE1 CK0 CK0# CK1 CK1# CK2 CK2# SDA SCL CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VREF VREF VDDSPD VDDID
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 BA0 BA1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 RAS# WE# CAS# S0# S1# CKE0 CKE1 CK0 CK0# CK1 CK1# CK2 CK2# SDA SCL CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VREF VREF VDDSPD VDDID
Sheet 9 of 39 DDR SODIMM
+2.5V
+2.5V
R549 [7,8] SDQS_A[0..7]
8.2K SDQS_A[0..7]
[7,8] SDQS_B[0..7]
R174 8.2K SDQS_B[0..7]
SDQS_A0 SDQS_A1 SDQS_A2 SDQS_A3 SDQS_A4 SDQS_A5 SDQS_A6 SDQS_A7
SDQS_B0 SDQS_B1 SDQS_B2 SDQS_B3 SDQS_B4 SDQS_B5 SDQS_B6 SDQS_B7
[7,8] SRAS_A# [7,8] SWE_A# [7,8] SCAS_A# [7,8] SCS_A0# [7,8] SCS_A1# [7,8] SCKE_A0 [7,8] SCKE_A1 [7] [7] [7] [7] [7] [7] DDRCLK_A1 DDRCLK_A1# DDRCLK_A2 DDRCLK_A2# DDRCLK_A0 DDRCLK_A0#
SRAS_A# SWE_A# SCAS_A# SCS_A0# SCS_A1# SCKE_A0 SCKE_A1 DDRCLK_A1 DDRCLK_A1# DDRCLK_A2 DDRCLK_A2# DDRCLK_A0 DDRCLK_A0#
[7,8] SRAS_B# [7,8] SWE_B# [7,8] SCAS_B# [7,8] SCS_B0# [7,8] SCS_B1# [7,8] SCKE_B0 [7,8] SCKE_B1 [7] [7] [7] [7] [7] [7] DDRCLK_B1 DDRCLK_B1# DDRCLK_B2 DDRCLK_B2# DDRCLK_B0 DDRCLK_B0#
SRAS_B# SWE_B# SCAS_B# SCS_B0# SCS_B1# SCKE_B0 SCKE_B1 DDRCLK_B1 DDRCLK_B1# DDRCLK_B2 DDRCLK_B2# DDRCLK_B0 DDRCLK_B0#
[5,18,31] SMB_ICHDATA [5,18,31] SMB_ICHCLK
[5,18,31] SMB_ICHDATA [5,18,31] SMB_ICHCLK
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DU DU DU DU DU/RESET# DU/A13 DU/BA2 SA0 SA1 SA2
5 7 13 17 6 8 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 85 123 124 200 86 97 98 194 196 198
SDQ_B0 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B4 SDQ_B5 SDQ_B6 SDQ_B7 SDQ_B8 SDQ_B9 SDQ_B10 SDQ_B11 SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15 SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23 SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31 SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47 SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55 SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63
Schematic Diags
+2.5V
NEAR DIMM PIN
R193
75_1% DIMM_VREFA R194 C745 75_1% 0.1U VCC3S C258 0.1U R197 DDR SO-DIMM-H 10K
DU DU DU DU DU/RESET# DU/A13 DU/BA2 SA0 SA1 SA2
+2.5V
NEAR DIMM PIN
R162 T173 75_1% DIMM_VREFB R163 C713 75_1% 0.1U VCC3S C196 0.1U R164
T121
VCC3S
R179
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186
DDR SO-DIMM 10K
+2.5V [4,7,10,35,36] VCC3S [2,5,10,11,12,16,17,18,19,20,23,25,26,27,28,31,32,37]
SO DIMM 0
SO DIMM 1
B - 10
3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Schematic Diagrams
Springdale (Voltage, PLL, VSS)
L31 L26 L25 L24 K33 K29 K27 K25 K22 K20 K18 K16 K14 K12 K11 J35 J32 J28 J22 J20 J18 J16 J14 J12 J10 H33 H30 H26 H24 H22 H20 H18 H16 H14 H12 H9 H8 H5 H2 G35 G31 G28 F26 F24 F22 F20 F18 BGA2G VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F16 F14 F12 F10 F8 F5 F3 F1 E3 E1 D35 D33 D31 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D9 D1 C28 C26 C24 C22 C20 C18 C16 C14 C12 C10 C8 C4 A32 A29 A27 A25 A23 A20 A16 A13 A11 A9 A7 AR32 AR29 AR27 AR25 AR23 AR20 AR16 AR13 AR11 AR9 AN32 AN30 AN28 AN26 AN24 AN22 AN20 AN18 AN16 AN14 AN12 AN10 AM35 AM29 AM27 AM25 AM23 AM21 AM19 AM17 AM15 AM13 AM11 AM9 AL32 AL1 AK28 AK26 AK24 AK22 AK20 AK18 AK16 AK14 AK12 AK10 AK8 AK3 AJ35 AJ32 AJ9 AJ4 AJ1 AH33 AH30 AH24 AH22 AH20 AH18 AH16 AH14 AH12 AH10 AH6 AH3 AG35 AG32 AG28 AG26 AG24 AG22 AG20 AG18 AG16 AG14 AG8 AG4 AF33 AF30 AF25 AF24 AF22 AF20 AF18 AF16 AF14 AF11 AF9 AF6 AF3 AE35 AE32 AE26 AE25 AE13 AE12 BGA2F VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AE11 AE10 AE4 AE1 AD33 AD30 AD28 AD10 AD9 AD8 AD6 AD3 AC35 AC32 AC4 AC1 AB33 AB30 AB28 AB27 AB26 AB10 AB9 AB8 AB6 AB3 AA32 AA4 AA1 Y35 Y33 Y30 Y28 Y27 Y26 Y10 Y9 Y8 Y6 Y3 W32 W18 W17 W4 V33 V30 V28 V27 V26 V19 V17 V10 V9 V8 V6 V3 U32 U19 U18 U4 T35 T33 T30 T28 T27 T26 T10 T9 T8 T6 T3 T1 R32 R4 R1 P33 P30 P28 P27 P26 P9 P8 P6 P3 N35 N32 N4 N1 M33 M30 M28 M27 M26 M6 M3 L35
VCCPCAP1 VCCPCAP2 VCCPCAP3 GMCHVCCP
VCC1.5S
VCCA_FSB C477 10U(0805) C478 0.1U
VSMYRC +2.5V
VSMYRC VDDCAP2
VDDCAP5 VDDCAP4 T104
VSMYRCO VCC3S
VDDCAP1 VSMYRCO
AA35 AL35 AL6 AL7 AM1 AM2 AM3 AM5 AM6 AM7 AM8 AN2 AN4 AN5 AN6 AN7 AN8 AP3 AP4 AP5 AP6 AP7 AR15 AR21 AR31 AR4 AR5 AR7 E35 R35 G1 G2
VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DAC VCC_DAC VCCA_AGP VCCA_FSB VCCA_DPLL VCCA_DAC VCCA_DDR1 VCCA_DDR2 VCCA_DDR3
GND
A15 A21 A31 A4 A5 A6 B5 B6 C5 C6 D5 D6 D7 E6 E7 F7
BGA2E VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VSSA_DAC SPDG MCH
J6 J7 J8 J9 K6 K7 K8 K9 L6 L7 L9 L10 L11 M8 M9 M10 M11 N9 N10 N11 P10 P11 R11 T16 T17 T18 T19 T20 U16 U17 U20 V16 V18 V20 W16 W19 W20 Y16 Y17 Y18 Y19 Y20 AG1 J1 J2 J3 J4 J5 K2 K3 K4 K5 L1 L2 L3 L4 L5 Y1 D3
VCC1.5S VCC1.5S L61 2 1 BK2125HS121 VCCA_SM C658 10U(0805) C609 0.1U
L7 2 1 BK2125HS121
Schematic Diags
Sheet 10 of 39 Springdale (Voltage, PLL, VSS)
POWER
SPDG MCH VC15CAP1
VCC1.5S VCCA_FSB
VCCA_SM
Y11 B4 B3 C2 AB25 AC25 AC26
VC15CAP2
+2.5V [4,7,9,35,36] VCC3S [2,5,9,11,12,16,17,18,19,20,23,25,26,27,28,31,32,37] VCC1.5S [6,16,19,32]
Decoupling capacitors (Place near DDR SDRAM DIMM modules)
One 0.1U cap per power pin.
VCC1.5S C520 +2.5V 220U(D)
GMCHVCCP VCCPCAP1 VCCPCAP2 VCCPCAP3 VC15CAP1 VC15CAP2 C73 C90 0.1U 0.1U C35 0.1U
+2.5V C574 0.1U C593 0.1U C610 0.1U C573 0.1U C118 1 C117 1 2 10U(0805) 2 10U(0805)
VCC1.5S C565 C590 C564 C519 C557 C591 C572 1 C501 1 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 2 10U(0805) 2 10U(0805)
C113 0.1U C104 0.1U C58 0.1U
C499 0.1U C527 0.1U C528 0.1U C49 C500 1 0.1U 2 10U(0805)
C728 C725 C726 C724 C729
1 1 1 1 1
2 0.1U_X7R 2 0.1U_X7R 2 0.1U_X7R 2 0.1U_X7R 2 0.1U_X7R +2.5V C736 C733 C727 0.01U 0.01U 0.01U
VSMYRC VSMYRCO VDDCAP1 VDDCAP2 VDDCAP4 VDDCAP5
C650 0.1U C635 0.1U C126 0.1U C165 0.1U C138 0.1U C133 0.1U
SPDG MCH
CLOSE TO GMCH
GND
B - 11
Schematic Diagrams
Mobility M10-P
[6] G_AD[0..31]
G_AD[0..31] G_AD0 G_AD1 G_AD2 G_AD3 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD9 G_AD10 G_AD11 G_AD12 G_AD13 G_AD14 G_AD15 G_AD16 G_AD17 G_AD18 G_AD19 G_AD20 G_AD21 G_AD22 G_AD23 G_AD24 G_AD25 G_AD26 G_AD27 G_AD28 G_AD29 G_AD30 G_AD31 G_CBE#0 G_CBE#1 G_CBE#2 G_CBE#3 H29 H28 J29 J28 K29 K28 L29 L28 N28 P29 P28 R29 R28 T29 T28 U29 N25 R26 P25 R27 R25 T25 T26 U25 V27 W26 W25 Y26 Y25 AA26 AA25 AA27 N29 U28 P26 U26 AG30 AG28 AF28 AD26 M25 N26 V29 V28 W29 W28 AE26 AC26 AE29 M28 V25 AB29 SBA[7..0] SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 ST0 ST1 ST2 AD28 AD29 AC28 AC29 AA28 AA29 Y28 Y29 AF29 AD27 AE28 AB28 M29 V26 BGA3A AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE#0 C/BE#1 C/BE#2 C/BE#3 PCICLK RST# REQ# GNT# PAR STOP# DEVSEL# TRDY# IRDY# FRAME# INTA# WBF# Part 1 of 6 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 DVOMODE ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8 ZV_LCDDATA9 ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23 ZV_LCDCNTL0 ZV_LCDCNTL1 ZV_LCDCNTL2 ZV_LCDCNTL3 (NC)VREFG
VCC3S AJ5 R135 10K(0402) AH5 R136 10K(0402) AJ4 T92 AK4 T91 AH4 R140 10K(0402) AF4 R145 10K(0402) AJ3 R142 10K(0402) AK3 R141 10K(0402) GPIO8 AH3 GPIO9 AJ2 GPIO10 AH2 AH1 R730 10K(0402) AG3 R731 10K(0402) AG1 R732 10K(0402) AG2 T101 AF3 T102 MCLK_SREAD AF2 AE10 AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10 AJ10 AK10 AJ11 AH11 AG4 AK16 AH16 AH17 AJ16 AH18 AJ17 AK19 AH19 AK18 AJ18 AG16 AF16 AG17 AF17 AF18 AE18 AH20 AG20 AF19 AG19 AE12 AG12 AJ13 AH14 AJ14 AH15 AJ15 AK15 AH13 AK13 AE13 AE14 AF12 AK27 AJ27 AJ26 AG25 AH25 AF25 AF24 AH26 AF26 AG26 AH30 AH29 AG29 AE11 AF11 TXOUT-LN0 TXOUT-LP0 TXOUT-LN1 TXOUT-LP1 TXOUT-LN2 TXOUT-LP2 TXOUT-LN3 TXOUT-LP3 TXCLK-LN TXCLK-LP TXOUT-UN0 TXOUT-UP0 TXOUT-UN1 TXOUT-UP1 TXOUT-UN2 TXOUT-UP2 TXOUT-UN3 TXOUT-UP3 TXCLK-UN TXCLK-UP DIGON BLON T80 T82 T93 T79 T81 T75 T73 T307 T77 T304 T315 T314 T308 R120 R119 T305 R470 R451 R469 T74 T72 T71 T76 33(0402) 33(0402) 0(0402) 0(0402) 0(0402) LTGIO0 [17] LTGIO1 [17] LTGIO2 [17] VCC3S VCC3S R481 1K(0402) R733 R468 10K(0402)(R) R449 10K(0402)(R) R432 R117 0(0402) 0(0402)(R)
R374 MCLK_SREAD R373 XTALIN R47 R48 VCC3S 150 VCC3S
8.2K(R) 8 22 T248 75 15 14 11 10 2 3 9
R22 U15
8.2K(R) 16 6 5 12 13 1 7 4 T251 T252 C19 0.1U C20 0.1U C489
VCC3S VCC1.8S L6 R38 C488 0 10
CLKOUT VDDREF VDDO1 VDDO0 VDD VDDA
DVO / EXT TMDS / GPIO
I2CCLK I2CDATA OSC3.3 R49 8.2K(R)
SCLK PD# SDATA REF_STOP X1 X2 SS_ENA ICS91719 GND GND GNDA
10U(0805) 10U(0805)
VCC3S R123 10K(0402) VCC3S R122 10K(0402) SIZE_SEL
MEM_SEL Etron Samsung SIZE_SEL 256M 128M 1 0
OSC3.3 VCC3S 2 MHz 3 27.0000MHZ-OSC R74 0(0402) R75 210(R) XTALIN R76 120(R)
1 0
Close to Mobility M10-P VCC3S
1 Y2 4 C87 0.01U
Schematic Diags
Sheet 11 of 39 Mobility M10-P
[5] G_66M_ATI_M10 [6] G_CBE#[0..3] R73
G_CBE#[3..0]
PCI / AGP
MEM_SEL
0(0402) C543 10P [5] G_66M_ATI_M10 [6,18,19,22,25,27,28] PCIRST# [6] G_REQ# [6] G_GNT# [6] G_PAR [6] G_STOP# [6] G_DEVSEL# [6] G_TRDY# [6] G_IRDY# [6] G_FRAME# [18,21,29] INT#A [18,30] INT#B [6] G_WBF# [6] G_RBF# [6] AD_STB0 [6] AD_STB1 [6] SB_STB [6] SBA[0..7]
G_66M_ATI_M10 PCIRST#
R433 2.21K R447 2.21K I2CDATA I2CCLK
PLACE C83 CLOSE TO ASIC PIN
R387 R58 G_WBF# R394
0(0402)(R) 0(0402) 33(0402)
AGP2X
AGP MODE
AGP 2.0 (4X) .75V AGP 3.0 (8X) .35V
Ra
Rb
1.02K_1% 1.02K_1% 324_1% 100_1%
RBF# AD_STBF_0 AD_STBF_1 SB_STBF SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 ST0 ST1 ST2 SB_STBS ADSTBS_0 ADSTBS_1
Close to Mobilty M10-P
C67 0.1U
AGP_VDDQ
[6] ST[0..2]
ST[0..2]
Ra
R71 324_1% 1/30 ATI CHANGE
[6] SB_STB# [6] AD_STB0# [6] AD_STB1# AGP_VDDQ R56 R389 [6] DB_LO [6] DB_HI [17] C/R [17] Y/G [17] COMP/B C/R Y/G COMP/B T58 T59 T277 T278 T52 T53 XTALIN T35 R408 1K(0402) T268
Rb
8X
R395 100_1%
C84 0.1U
C544 10U(0805)
AGP_VDDQ
VCC3S
AGP
Rc
R55 0(0402)(R) 0(0402)(R)
47 R388 R57 R116
TMDS
M26 M27 10K(0402)(R) AB26 AB25 AC25 10K(0402) 715 AK21 AJ23 AJ22 AK22 AJ24 AK24 AG23 AG24 AK25 AJ25 AH28 AJ29 AH27 E8 B6 AE25
AGPREF AGPTEST
4X
TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP DIGON BLON TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP DDC2CLK DDC2DATA HPD1 R G B HSYNC VSYNC DDC1DATA DDC1CLK RSET AUXWIN SUS_STAT# STP_AGP# AGP_BUSY# RSTB_MSK(NC) DMINUS DPLUS
TXOUT-LN0 [17] TXOUT-LP0 [17] TXOUT-LN1 [17] TXOUT-LP1 [17] TXOUT-LN2 [17] TXOUT-LP2 [17] TXOUT-LN3 [17] TXOUT-LP3 [17] TXCLK-LN [17] TXCLK-LP [17] TXOUT-UN0 [17] TXOUT-UP0 [17] TXOUT-UN1 [17] TXOUT-UP1 [17] TXOUT-UN2 [17] TXOUT-UP2 [17] TXOUT-UN3 [17] TXOUT-UP3 [17] TXCLK-UN [17] TXCLK-UP [17] DIGON [17] BLON [17]
R480 1K(0402) GPIO8 GPIO9
10K(0402) VCC3S R510 R508 33(0402) 33(0402) 33(0402) 33(0402) 10K(0402) 5 6 1 7 U5 SI SCK CE# HOLD# SO WP# VCC GND
2 3 8 4
GPIO10 R509 [12] ROMCS# VCC3S R512 R511
LVDS
C705 0.1U
PM25LV512
CLOSE TO ASIC
R450 R435 R434 R452 330(0402) 330(0402) 330(0402) 330(0402) TMDS_TX0N [17] TMDS_TX0P [17] TMDS_TX1N [17] TMDS_TX1P [17] TMDS_TX2N [17] TMDS_TX2P [17] TMDS_TXCN [17] TMDS_TXCP [17] VGADDCCLK [17] VGADDCDATA [17] MONDET [17] R G B HSY VSY R [17] G [17] B [17] HSY [17] VSY [17] R734 10K(0402) LTGIO0 R735 10K(0402) LTGIO1 R736 10K(0402) LTGIO2 VCC3S
DBI_LO DBI_HI AGP8X_DET# R2SET C_R Y_G COMP_B
AGP_TEST RESISTOR SELECTION AGP MODE
AGP 2.0 (4X) AGP 3.0 (8X)
Rc
40R 40R
MAN DAC1 PWR
DDC3CLK DDC3DATA SSIN SSOUT XTALIN XTALOUT TESTEN TEST_YCLK(NC) TEST_MCLK(NC) PLLTEST(NC) M10-P
CLK SS DAC2
H2SYNC V2SYNC
T267 T276 R88 R411 R83 R60 R59 R72
499 10K(0402) 10K(0402) 10K(0402) 10K(0402) 1K(0402)
VCC3S VCC3S AGP_VDDQ [16] VCC3S [2,5,9,10,12,16,17,18,19,20,23,25,26,27,28,31,32,37]
REMOVE PULL DOWN FOR OPTIONAL TEST MODE ENABLE REFER TO DATA BOOK FOR JTAG AND SCAN SIGNAL SOURCES
THERM
B - 12
Schematic Diagrams
Mobility M10-P MEM A/B
DMAA[0..13] [15] DMAB[0..13] [15]
M10 MEMORY CHANNEL A
OPTIONAL SERIES TERMINATION FOR MEMORY ADDR & CNTRL INSTALL RESISTORS CLOSER TO M10 [14,15] DQMB#[7..0] [14] MEM_MAB[13..0] [15] MDB[63..0] MDB[63..0]
M10 MEMORY CHANNEL B
DQMB#[7..0] MEM_MAB[13..0]
OPTIONAL SERIES TERMINATION FOR MEMORY ADDR & CNTRL INSTALL RESISTORS CLOSER TO M10
[13,15] DQMA#[7..0] [13] MEM_MAA[13..0] [15] MDA[63..0] MDA[63..0]
DQMA#[7..0] MEM_MAA[13..0]
MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63
L25 L26 K25 K26 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8
BGA3B DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63 M10-P Part 2 of 6 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 (MAA13)MAA12 (MAA12)MAA13 (NC)MAA14 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 RASA# CASA# WEA# CSA0# CSA1# CKEA CLKA0 CLKA0# CLKA1 CLKA1#
E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19 J25 F29 E25 A27 F15 C15 C11 E11 J27 F30 F24 B27 E16 B16 B11 F10 A19 E18 E19 E20 F20 B19 B21 C20 C18 A18
DMAA0 DMAA4 8 DMAA2 7 DMAA1 DMAA1 6 DMAA2 DMAA8 5 DMAA3 DMAA6 1 DMAA4 DMAA5 2 DMAA5 DMAA0 3 DMAA6 DMAA7 DMAA7 4 DMAA8 DMAA10 8 DMAA11 7 DMAA9 DMAA10 DMAA3 6 DMAA11 DMAA9 5 DMAA12 R415 DMAA13 R111 T67 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 RASA# CASA# WEA# CSA0# CSA1# CKEA CLKA0 CLKA0# CLKA1 CLKA1# R439 R438 R418 R417 R416 R112 4 3 4 3
1 MEM_MAA4 2 MEM_MAA2 3 MEM_MAA1 4 MEM_MAA8 8 MEM_MAA6 7 MEM_MAA5 6 MEM_MAA0 5 MEM_MAA7 1 MEM_MAA10 2 MEM_MAA11 3 MEM_MAA3 4 MEM_MAA9 10(0402) MEM_MAA12 10(0402)MEM_MAA13
RN15 8P4R_10(0402) RN105 8P4R_10(0402)
RN14 8P4R_10(0402)
MEMORY INTERFACE A
QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 10(0402) 10(0402) 10(0402) 10(0402) 10(0402) 10(0402) 1 2 4P2R_10 1 2 4P2R_10
[13,15] [13,15] [13,15] [13,15] [13,15] [13,15] [13,15] [13,15]
MEM_RASA# [13] MEM_CASA# [13] MEM_WEA# [13] MEM_CSA0# [13] MEM_CSA1# [13] MEM_CKEA [13] MEM_CLKA0 [13] MEM_CLKA0# [13] MEM_CLKA1 [13] MEM_CLKA1# [13]
RP1 RP2
2.8/2.5VS R504 800_1%
DIMA_0 DIMA_1 MVREFD MVREFS
D30 B13 B7 B8
DIMA_0 DIMA_1
T34 T70
VREF = .50*VDDQ 2.8/2.5VS R436 800_1% R437 C630 0.01U 1K_1% 10U(0805) C632 C702 0.01U C701 10U(0805)
R503 1K_1%
MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63
D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3
BGA3C DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63 M10-P Part 3 of 6 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 (MAB13)MAB12 (MAB12)MAB13 (NC)MAB14 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 RASB# CASB# WEB# CSB0# CSB1# CKEB CLKB0 CLKB0# CLKB1 CLKB1# DIMB_0 DIMB_1 ROMCS# MEMVMODE_0 MEMVMODE_1 MEMTEST
N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2 E6 B2 J5 G3 W6 W2 AC6 AD2 F6 B3 K6 G1 V5 W1 AC5 AD1 R2 T5 T6 R5 R6 R3 N1 N2 T2 T3 E3 AA3 AF5 C6 C7 C8
DMAB0 DMAB1 DMAB2 DMAB3 DMAB4 DMAB5 DMAB6 DMAB7 DMAB8 DMAB9 DMAB10 DMAB11 DMAB12 DMAB13 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 RASB# CASB# WEB# CSB0# CSB1# CKEB
DMAB2 8 DMAB5 7 DMAB1 6 DMAB8 5 DMAB7 8 DMAB0 7 DMAB6 6 DMAB11 5 DMAB10 8 DMAB9 7 DMAB3 6 DMAB4 5 R502 R159 T96
1 2 3 4 1 2 3 4 1 2 3 4 10(0402) 10(0402)
MEM_MAB2 MEM_MAB5 MEM_MAB1 MEM_MAB8 MEM_MAB7 MEM_MAB0 MEM_MAB6 MEM_MAB11 MEM_MAB10 MEM_MAB9 MEM_MAB3 MEM_MAB4 MEM_MAB12 MEM_MAB13
RN44 8P4R_10(0402)
RN128 8P4R_10(0402) RN43 8P4R_10(0402)
Schematic Diags
MEMORY INTERFACE B
Sheet 12 of 39 Mobility M10-P MEM A/B
QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 [14,15] [14,15] [14,15] [14,15] [14,15] [14,15] [14,15] [14,15]
R498 R497 R499 R500 R501 R160 4 3 4 3
10(0402) 10(0402) 10(0402) 10(0402) 10(0402) 10(0402) 1 2 4P2R_10 1 2 4P2R_10 T318 T97
MEM_RASB# [14] MEM_CASB# [14] MEM_WEB# [14] MEM_CSB0# [14] MEM_CSB1# [14] MEM_CKEB [14] MEM_CLKB0 [14] MEM_CLKB0# [14] MEM_CLKB1 [14] MEM_CLKB1# [14]
CLKB0 CLKB0# CLKB1 CLKB1# DIMB_0 DIMB_1 R482
RP3 RP4
10K(0402)(R) R478 R471
VCC3S ROMCS# [11] 4.7K(0402) 4.7K(0402)(R) VCC1.8S
R472 R453
R473 4.7K(0402)(R)
4.7K(0402) 47(0402)
MEMVMODE[1:0]
MEMORY IO VOLTAGE
2.5V (DDR) 1.8V (DDR) 2.8V (DDR)
0
1.25VS CASB# RASB# WEB# CSB0# CKEB CLKB0# CLKB0 CLKB1 CLKB1# 1 2 3 4 R151 R149 R148 R152 R153 8 RN126 7 6 5 8P4R_56(0402) 56(0402) 56(0402) 56(0402) 56(0402) 56(0402) 2.8/2.5VS C670 0.1U C153 0.1U
1 0 1
RN107 CSA0# WEA# CASA# RASA# CLKA0 CLKA0# CKEA CLKA1 CLKA1# VCC1.8S [11,16,35] 1.25VS [15,37] 2.8/2.5VS [13,14,15,16,37] 8 7 6 5 R108 R109 R114 R115 R118
1.25VS 1 2 3 4 8P4R_56(0402) 56(0402) 56(0402) 56(0402) 56(0402) 56(0402)
2.8/2.5VS C583 0.1U C109 0.1U
1 1
Close to ASIC
B - 13
Schematic Diagrams
VGA DDR DRAM Channel A
2.8/2.5VS C108 C101 C92 0.1U 0.1U 0.1U C77 0.1U C91 C619 2.8/2.5VS 2.8/2.5VS C684 C648 C685 C655 C649 0.1U 0.1U 0.1U 0.1U C664 C620 C79 0.1U 0.1U 2.8/2.5VS C75 0.1U C78 0.1U C80 C76 2.8/2.5VS 2.8/2.5VS C710 C708 C678 C647 C709 0.1U 0.1U 0.1U 0.1U C145
10U(0805) 10U(0805)
10U(0805) 10U(0805)
10U(0805) 10U(0805)
10U(0805) 10U(0805)
E12 C12 K11 J11 G11 F11 C10 C8 C7 C5 K4 J4 G4 F4 E3 C3
C3 E3 F4 G4 J4 K4 C5 C7 C8 C10 F11 G11 J11 K11 C12 E12
E12 C12 K11 J11 G11 F11 C10 C8 C7 C5 K4 J4 G4 F4 E3 C3
BGA7
BGA8
BGA1
C3 E3 F4 G4 J4 K4 C5 C7 C8 C10 F11 G11 J11 K11 C12 E12 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 M5 N4 M13 L9 M10 N2 M2 L2 L3 B3 H12 H3 B12 M11 MEM_MAA0 MEM_MAA1 MEM_MAA2 MEM_MAA3 MEM_MAA4 MEM_MAA5 MEM_MAA6 MEM_MAA7 MEM_MAA8 MEM_MAA9 MEM_MAA10 MEM_MAA11 MEM_MAA13 MEM_MAA12 T108 T50 T109 T51 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 M5 N4 M13 L9 M10 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
BGA4
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
E4 L4 D7 L7 D8 L8 E11 L11
VDD VDD VDD VDD VDD VDD VDD VDD
Schematic Diags
Sheet 13 of 39 VGA DDR DRAM Channel A
MEM_MDA24 B7 MEM_MDA25 C6 MEM_MDA26 B6 MEM_MDA27 B5 MEM_MDA28 C2 MEM_MDA29 D3 MEM_MDA30 D2 MEM_MDA31 E2 MEM_MDA8 K13 MEM_MDA9 K12 MEM_MDA10 J13 MEM_MDA11 J12 MEM_MDA12G13 MEM_MDA13G12 MEM_MDA14 F13 MEM_MDA15 F12 MEM_MDA16 F3 MEM_MDA17 F2 MEM_MDA18 G3 MEM_MDA19 G2 MEM_MDA20 J3 MEM_MDA21 J2 MEM_MDA22 K2 MEM_MDA23 K3 MEM_MDA0 E13 MEM_MDA1 D13 MEM_MDA2 D12 MEM_MDA3 C13 MEM_MDA4 B10 MEM_MDA5 B9 MEM_MDA6 C9 MEM_MDA7 B8 L10 E10 K9 J9 H9 G9 F9 K8 J8 H8 G8 F8 E8 K7 J7 H7 G7 D11 B11 K10 J10 H10
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 NC/A9 NC/A10 NC/A11 BA1 BA0 DSF,MCL RFU1 RFU2 CS# RAS# CAS# WE# DQM0 DQM1 DQM2 DQM3 CK
N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 M5 N4 M13 L9 M10 N2 M2 L2 L3 B3 H12 H3 B12 M11
MEM_MAA0 MEM_MAA1 MEM_MAA2 MEM_MAA3 MEM_MAA4 MEM_MAA5 MEM_MAA6 MEM_MAA7 MEM_MAA8 MEM_MAA9 MEM_MAA10 MEM_MAA11 MEM_MAA13 MEM_MAA12 T95 T43 T320 T258
N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 M5 N4 M13 L9 M10
A0 A1 A2 A3 A4 A5 A6 A7 A8 NC/A9 NC/A10 NC/A11 BA1 BA0 DSF,MCL RFU1 RFU2 CS# RAS# CAS# WE# DQM0 DQM1 DQM2 DQM3 CK
VDD VDD VDD VDD VDD VDD VDD VDD
E4 L4 D7 L7 D8 L8 E11 L11
E4 L4 D7 L7 D8 L8 E11 L11
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD VDD VDD VDD
EM6AA320BI-3.3MS
N2 MEM_CSA0# M2 MEM_RASA# L2 MEM_CASA# L3 MEM_WEA# VDQMA#6 B3 VDQMA#3 VDQMA#1 VDQMA#4 H12 VDQMA#5 H3 VDQMA#2 VDQMA#7 B12 VDQMA#0 MEM_CLKA1 M11 MEM_CLKA0
EM6AA320BI-3.3MS
CK# CKE DQS0 DQS1 DQS2 DQS3 VREF NC NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS
M12 MEM_CLKA0# N12 B2 H13 H2 B13 N13 L13 L12 H11 C11 M4 N3 M3 H4 C4 E5 L5 F6 G6 H6 J6 K6 E7 F7 T256 T255 T254 T257 T279 T294 T293 T292 T291
M12 MEM_CLKA1# N12 VQSA6 VQSA4 VQSA5 VQSA7 B2 H13 H2 B13 N13 T309 T317 T316 T319 T323 T325 T324 T326 T322 L13 L12 H11 C11 M4 N3 M3 H4 C4 E5 L5 F6 G6 H6 J6 K6 E7 F7
CK# CKE DQS0 DQS1 DQS2 DQS3 VREF NC NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS
MEM_CKEA VQSA3 VQSA1 VQSA2 VQSA0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ
B7 C6 B6 B5 C2 D3 D2 E2 K13 K12 J13 J12 G13 G12 F13 F12 F3 F2 G3 G2 J3 J2 K2 K3 E13 D13 D12 C13 B10 B9 C9 B8 L10 E10 K9 J9 H9 G9 F9 K8 J8 H8 G8 F8 E8 K7 J7 H7 G7 D11 B11 K10 J10 H10
MEM_MDA55 MEM_MDA54 MEM_MDA53 MEM_MDA52 MEM_MDA51 MEM_MDA50 MEM_MDA49 MEM_MDA48 MEM_MDA32 MEM_MDA33 MEM_MDA34 MEM_MDA35 MEM_MDA36 MEM_MDA37 MEM_MDA38 MEM_MDA39 MEM_MDA47 MEM_MDA46 MEM_MDA45 MEM_MDA44 MEM_MDA43 MEM_MDA42 MEM_MDA41 MEM_MDA40 MEM_MDA56 MEM_MDA57 MEM_MDA58 MEM_MDA59 MEM_MDA60 MEM_MDA61 MEM_MDA62 MEM_MDA63
MEM_MDA7 B7 MEM_MDA6 C6 MEM_MDA5 B6 MEM_MDA4 B5 MEM_MDA3 C2 MEM_MDA2 D3 MEM_MDA1 D2 MEM_MDA0 E2 MEM_MDA23 K13 MEM_MDA22 K12 MEM_MDA21 J13 MEM_MDA20 J12 MEM_MDA19G13 MEM_MDA18G12 MEM_MDA17 F13 MEM_MDA16 F12 MEM_MDA15 F3 MEM_MDA14 F2 MEM_MDA13 G3 MEM_MDA12 G2 MEM_MDA11 J3 MEM_MDA10 J2 MEM_MDA9 K2 MEM_MDA8 K3 MEM_MDA31 E13 MEM_MDA30D13 MEM_MDA29D12 MEM_MDA28C13 MEM_MDA27 B10 MEM_MDA26 B9 MEM_MDA25 C9 MEM_MDA24 B8 L10 E10 K9 J9 H9 G9 F9 K8 J8 H8 G8 F8 E8 K7 J7 H7 G7 D11 B11 K10 J10 H10
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 NC/A9 NC/A10 NC/A11 BA1 BA0 DSF,MCL RFU1 RFU2 CS# RAS# CAS# WE# DQM0 DQM1 DQM2 DQM3 CK
A0 A1 A2 A3 A4 A5 A6 A7 A8 NC/A9 NC/A10 NC/A11 BA1 BA0 DSF,MCL RFU1 RFU2 CS# RAS# CAS# WE# DQM0 DQM1 DQM2 DQM3 CK
VDD VDD VDD VDD VDD VDD VDD VDD
E4 L4 D7 L7 D8 L8 E11 L11
EM6AA320BI-3.3MS
N2 MEM_CSA1# M2 MEM_RASA# L2 MEM_CASA# L3 MEM_WEA# VDQMA#7 B3 VDQMA#0 VDQMA#5 H12 VDQMA#2 VDQMA#4 H3 VDQMA#1 VDQMA#3 VDQMA#6 B12 MEM_CLKA1 M11 MEM_CLKA0
EM6AA320BI-3.3MS
CK# CKE DQS0 DQS1 DQS2 DQS3 VREF NC NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS
M12 MEM_CLKA0# N12 B2 H13 H2 B13 N13 L13 L12 H11 C11 M4 N3 M3 H4 C4 E5 L5 F6 G6 H6 J6 K6 E7 F7 T65 T56 T66 T57 T42 T32 T33 T25 T44
M12 MEM_CLKA1# N12 VQSA7 VQSA5 VQSA4 VQSA6 B2 H13 H2 B13 N13 T118 T117 T120 T119 T87 T88 T89 T78 T90 L13 L12 H11 C11 M4 N3 M3 H4 C4 E5 L5 F6 G6 H6 J6 K6 E7 F7
CK# CKE DQS0 DQS1 DQS2 DQS3 VREF NC NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS
MEM_CKEA VQSA0 VQSA2 VQSA1 VQSA3
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ
B7 C6 B6 B5 C2 D3 D2 E2 K13 K12 J13 J12 G13 G12 F13 F12 F3 F2 G3 G2 J3 J2 K2 K3 E13 D13 D12 C13 B10 B9 C9 B8 L10 E10 K9 J9 H9 G9 F9 K8 J8 H8 G8 F8 E8 K7 J7 H7 G7 D11 B11 K10 J10 H10
MEM_MDA63 MEM_MDA62 MEM_MDA61 MEM_MDA60 MEM_MDA59 MEM_MDA58 MEM_MDA57 MEM_MDA56 MEM_MDA40 MEM_MDA41 MEM_MDA42 MEM_MDA43 MEM_MDA44 MEM_MDA45 MEM_MDA46 MEM_MDA47 MEM_MDA39 MEM_MDA38 MEM_MDA37 MEM_MDA36 MEM_MDA35 MEM_MDA34 MEM_MDA33 MEM_MDA32 MEM_MDA48 MEM_MDA49 MEM_MDA50 MEM_MDA51 MEM_MDA52 MEM_MDA53 MEM_MDA54 MEM_MDA55
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
G10 F10 D10 E9 D9 E6 D6 K5 J5 H5 G5 F5 D5 D4 B4
B4 D4 D5 F5 G5 H5 J5 K5 D6 E6 D9 E9 D10 F10 G10
G10 F10 D10 E9 D9 E6 D6 K5 J5 H5 G5 F5 D5 D4 B4
8*32 DDR
8*32 DDR
8*32 DDR
B4 D4 D5 F5 G5 H5 J5 K5 D6 E6 D9 E9 D10 F10 G10 1K_1%(0402) R443 C115 C607 0.1U R155 C703 C167 R505 1K_1%(0402) 1K_1%(0402) 2.8/2.5VS 0.1U 10U(0805) 10U(0805)
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
8*32 DDR
2.8/2.5VS
R70
1K_1%(0402) R398 C74 0.1U C555
C656 C132
R12