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TABLE OF CONTENTS
1.INTRODUCTION .......................................................................................................1 2.TUNER Specification .................................................................................................1 3. IF/Audio&Video Switching/AD Converter PART (PNX3000(called as MPIF)) ...........2 4.SOUND OUTPUT STAGE WITH TDA7480L .............................................................4 5.VERTICAL OUTPUT STAGE WITH TDA8177F&STV9379FA ..................................4 6.VIDEO OUTPUT AMPLIFIER TDA6108JF ................................................................4 7.POWER SUPPLY Part...............................................................................................4 8.SERIAL ACCESS 64K EEPROM...............................................................................5 9.Headphone amplifier Stage........................................................................................5 10.SAW FILTER Specification ......................................................................................6 11.IC DESCRIPTIONS .................................................................................................6 12.1.TDA6108JF........................................................................................................7
12.1.1.General Description.................................................................................................................7 12.1.2.Features...................................................................................................................................7 12.1.3.Pinning.....................................................................................................................................7
14.3.PNX3000............................................................................................................8
14.3.1.General Description.................................................................................................................9 14.3.2.Features...................................................................................................................................9
14.4.CS51033 ..........................................................................................................13
14.4.1.General Description...............................................................................................................13 14.4.2.Features.................................................................................................................................13 14.4.3.Pin Description ......................................................................................................................13
14.5.SDRAM 64MBIT ..............................................................................................14
14.5.1.General Description...............................................................................................................14 14.5.2.Features.................................................................................................................................14 14.5.3.Functional Block Diagram........................................................Error! Bookmark not defined. 14.5.4.Pin Description ......................................................................................................................14
14.6.FLASH 32MBIT ................................................................................................15
14.6.1.General Description...............................................................................................................15 14.6.2.Features.................................................................................................................................15 14.6.3.Pin/Ball Descriptions..............................................................................................................16
14.7.NE56610-29.....................................................................................................18
14.7.1.General Description...............................................................................................................18 14.7.2.Features.................................................................................................................................18 14.7.3.Pin Description ......................................................................................................................18
14.8.STS5PF30L .....................................................................................................19
14.8.1.Description.............................................................................................................................19 14.8.2.Features.................................................................................................................................19
14.9.PNX300X .........................................................................................................20
14.9.1.General Description of the Digital One Chip System ............................................................20 14.9.2.Features of the ADOC Processor..........................................................................................21
14.10.M24C64WBN6 ...............................................................................................26
14.10.1.Features ..............................................................................................................................26 14.10.2.Description...........................................................................................................................26
14.11.TDA7480L......................................................................................................27
14.11.1.Description...........................................................................................................................27 14.11.2.Features ..............................................................................................................................27 14.11.3.Pin Functions.......................................................................................................................27
14.12.LM7808 ..........................................................................................................28
14.12.1.Description...........................................................................................................................28 14.12.2.Features ..............................................................................................................................28
14.13.TDA8177F&STV9379FA................................................................................29
14.13.1.Description...........................................................................................................................29 i AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.13.2.Features ..............................................................................................................................29 14.13.3.Pin connections ...................................................................................................................29 14.13.4.Block Diagram .....................................................................................................................29
14.15.MC44608 .......................................................................................................30
14.15.1.Description...........................................................................................................................30 14.15.2.General Features.................................................................................................................30 14.15.3.Pin Connections ..................................................................................................................30
14.16.TCET1102G...................................................................................................32
14.16.1.Description...........................................................................................................................32 14.16.2.Applications .........................................................................................................................32 14.16.3.Features ..............................................................................................................................32
14.17.TL431.............................................................................................................33
14.17.1.Description...........................................................................................................................33 14.17.2.Features ..............................................................................................................................33 14.17.3.Pin Configurations ...............................................................................................................33
14.18.TFMS5360 .....................................................................................................33
14.18.1.Description...........................................................................................................................33 14.18.2.Features ..............................................................................................................................33
15.AK53 CHASSIS MANUAL ADJUSTMENTS PROCEDURE ..................................34 15.1.PRELIMINARY.................................................................................................34 15.2.SYSTEM VOLTAGE ADJUSTMENTS .............................................................34 15.3.AFC ADJUSTMENTS ......................................................................................34 15.4.FOCUS ADJUSTMENTS .................................................................................34 15.5.SCREEN ADJUSTMENTS...............................................................................34 16.AK53 CHASSIS PRODUCTION SERVICE MODE ADJUSTMENTS.....................35 16.1.PRELIMINARY.................................................................................................35 16.2.H/V (HORIZONTAL AND VERTICAL GEOMETRY ALIGNMENTS) ................37 16.3.VIDEO ALIGNMENTS......................................................................................42 16.4.SERVICE ALIGNMENTS ................................... Error! Bookmark not defined. 17.BLOCK DIAGRAM .................................................................................................46 18.CIRCUIT DIAGRAMS ............................................................................................47
ii AK53 D.O.C. Service Manual- Preliminary 12/12/2003
1.INTRODUCTION
11AK53 is a 100Hz colour television DIGITAL ONE CHIP SYSTEM (DOC) capable of driving 28"4:3/16:9 SF/RF, 29"4:3 real flat, 32" 16:9 SF/RF, 33"4:3 and 34` 4:3 real flat picture tubes. The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I', and L/L´. Sound system output is supplying 2x10W (10%THD) for left and right outputs of 8ohm speakers. TV supports the level 1.5 teletext standard. It is possible to decode transmissions including high graphical data. The chassis is equipped with two full EuroScarts, one SCART for AV input/output, one front-AV input, one back-AV input, one headphone output, one SVHS input (via SCART and SVHS connector), two external speaker outputs (left and right), one audio line output.
2.TUNER SPECIFICATION
The hardware and software of the TV is suitable for tuners, supplied by different companies, which are selected from the Service Menu. These tuners can be combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L´, I/I´, and D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on one of the Tuners in use. General description of UV1316 MK3(Philips) /CTF55XX (Thomson): UV1316 MK3(Philips) /CTF55XX (Thomson) tuners, which are designed to meet a wide range of applications are PLL tuners, It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L', I and I'. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient. Features of Tuner: 1. Those tuners are small sized UHF/VHF tuners 2. Systems CCIR: B/G, H, L, L', I and I'; OIRT: D/K 3. Digitally controlled (PLL) tuning via I2C-bus 4. Off-air channels, S-cable channels and Hyperband 5. World standardized mechanical dimensions and world standard pinning 6. Compact size 7. Complies to "CENELEC EN55020" and "EN55013" Pinning: 1. Gain control voltage (AGC) 2. Tuning voltage 3. I²C-bus address select 4. I²C-bus serial clock 5. I²C-bus serial data 6. Not connected 7. PLL supply voltage 8. ADC input 9. Tuner supply voltage* 10. Symmetrical IF output 1 11. Symmetrical IF output 2 : : : : : : 4.0V, Max: 4.5V Max: 5.5V Min:-0.3V, Max: 5.5V Min:-0.3V, Max: 5.5V 5.0V, Min: 4.75V, Max: 5.5V 33V, Min: 30V, Max: 35V
*33V is obtained from FBT of large signal board.
1 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
3.IF/AUDIO&VIDEO SWITCHING/AD CONVERTER PART (PNX3000(CALLED AS MPIF))
MPIF IC consists of following OVERALL blocks; (1)-Video/Audio switching (2)-IF processing (3)-A/D conversion for digital TV (DTV) processor (ADOC-PNX300X) Main building blocks: _ Vision PLL-IF, auto-calibrated, selectable IF frequency, 4 selectable AGC time constants, built-in sound trap and selectable group delay. The demodulated CVBS signal is fed outside for use with SCART. _ Synthesizer mode, meant for downmixing of DTV signals to a suitable 2nd IF which can be handled by a digital DTV decoder. Using a suitable SAW filter at the input the synthesizer mode can also be used to downmix FM radio frequencies from the Tuner to a suitable 2nd IF frequency for the FM demodulator. _ Two Video IF inputs, selectable by internal switch to enable use of optimised SAW filters _ Sound QSS IF, demodulated 2nd SIF can be either from SIF input (QSS) or Video IF (intercarrier). The Sound IF also contains an AM demodulator for SECAM L/L' _ CVBS and Y/C crossbar switch, with 2 video outputs for further processing in the Digital TV Signal Processor after A/D conversion and 2 selectable video outputs which are available on output pins for external connections 2 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
_ Two YUV / RGB inputs, which can handle also YPrPb and sync on Y for DVD players Also 2Fh YUV / RGB signals can be handled by the A/D convertors. _ An audio stereo crossbar switch with two outputs (one stereo, one stereo or mono) for further processing in the processor after A/D conversion and three stereo outputs for external connections. Extra inputs are provided to enable also the selection of demodulated RF sound (mono, NICAM, 2CS) from the Digital TV Signal Processor for use on external connections. _ Low pass filtering and A/D conversion. The audio and video sampling clocks use the same reference so it is possible to interleave video and audio data into one serial data stream. _ For control, I 2 C control is built-in with a selectable address. _ Auxiliary building blocks which perform some functions which have typical better performance in analogue design environment than in digital and are used by the Digital TV Signal Processor: - Reference voltage for vertical deflection and audio ADC's - Voltage to current conversion of the E/W The set-up with an analogue and a digital part has the following advantages: _ High frequent parts (IF) can be included in the concept _ Less A/D and D/A converters needed for source switching _ Better performance for AD converters (realised in analogue design environment, more accurate, less tolerance) _ Critical items like reference voltages can be realised in the analogue environment
4.DIGITAL TV PROCESSOR (PNX300X (CALLED AS ADOC))
The DOC system serves the TV functionality for small signal processing of audio, video, VBI services, graphics and control. This chip implements all TV functions in digital technology.PNX300X is the digital TV processor which consists of; · TV video processor · TV deflection processor · TV audio processor · TV microcontroller
As it is shown in the below block diagram ADOC gets the digital signal which is converted by MPIF and processed in its own blocks and controls the overall system by I2C and the software programme is downloaded into a flash memory which tells microcontroller within ADOC about the software management and the output of ADOC turns into RGB, Main/Headphone audio right/left. Then RGB output of ADOC is processed into a RGB preamplifier circuit to get enough gain for the video output amplifier TDA6108JF (in CRT board) Highlight points of ADOC: (1)-Digital (I2D)data link is conncted from MPIF to ADOC with a swing of about 300mV. The data rate is 594Mbit/s. 3 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
(2)-Only one crystal is used in overall system which is 13.5MHZ.
Functional block diagram of ADOC:
6.SOUND OUTPUT STAGE WITH TDA7480L
The TDA7480L is an audio class-D amplifier assembled in Power DIP package specially designed for high efficiency applications mainly for TV and Home Stereo sets. Mute stand-by function of the audio amplifier can be described as the following; the pin 12 (MUTE/STAND-BY) controls the amplifier status by two different thresholds, referred to ground. When Vpin 12 voltage is lower than 0.7V the amplifier is in Stand-by mode and the final stage generators are off. When Vpin 12 is higher than 4V, the amplifier is in play mode. The TDA7480L is a 10W+10W stereo sound amplifier with mute/stand-by facility. MUTE control signal coming from microcontroller (when it is at high level) activates the mute function. IC is muted when mute pin is at low level (pin12). MUTE pin can also be activated via an external pop-noise circuitry in order to eliminate pop noise when TV is turned off. Just after the TV is turned off, this circuit switches the IC to stand-by mode by pulling the mute pin voltage to ground.
7.VERTICAL OUTPUT STAGE WITH STV9379FA& TDA8177F
The IC STV9379FA& TDA8177F is the vertical deflection booster circuit. Two supply voltages, +14V and 14V are needed to scan the inputs VERT+ and VERT-, respectively. And a third supply voltage, +60V for the flyback limiting are needed. The vertical deflection coil is connected in series between the output and feedback to the input.
8.VIDEO OUTPUT AMPLIFIER TDA6108JF
The TDA6108JF includes three video output amplifiers is intended to drive the three cathodes of a color picture tube.
9.POWER SUPPLY PART
9.1. In Large signal board
The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC MC44608, which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer generates 135V for FBT input, +/-14V for audio amplifier, 8V, 12V, 4 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
V8Stby ( needed for step down converted for small signal board) and 5V supplies for other different parts of the chassis. An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation circuit in secondary side. This circuit produces a control voltage according to the changes in 135V DC voltage, via an optocoupler (TCET 1102G) to pin3 of the IC. During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations.
9.2. In Small signal board
V8Stby and +5V is switched by a discrete circuit to make power consumption effective. · When supply switch port of ADOC IC is HIGH +5V 3.3V via IC103 regulator · When supply switch port of ADOC IC is LOW V8Stby 3.3V via IC103 regulator V8Stby is used to get +5V which is available in Stby.
9.3. Supply voltages available/not-available in stby, IC requirement, supply location
Supply 135V (B+) 14V-A (-)14V-A 14V 8V 5V V8stby 1.8V 3.3V 12V 5V Vert Sup+ (14V) Vert Sup- (14V) 33V In Stby available? Where? For Which ? NO large signal board FBT NO NO NO NO NO YES YES YES NO YES NO NO NO NOTE depends on CRT
large signal board IC401,IC402(Audio amplifier) large signal board IC401,IC402(Audio amplifier) large signal board Horizontal drive transistor small signal board IC400 (MPIF)/Headphone discrete circuit/RGB pre amplifiers/audio saw filter(Z401) small signal board IC400 (MPIF),Tuner(TU200,TU850) large signal board Step down IC and for s+5V small signal board IC313 (ADOC) small signal board IC313 (ADOC),IC309(EEPROM),IC316(Reset IC) small signal board CRT board (IC900) small signal board LED/IR large signal board Vertical IC (IC100) large signal board Vertical IC (IC100) large signal board Tuner (TU200,TU850)
9.4 Important microcontroller ports for supplying
Port On/Off On/Off State low high Function normal operation stand by mode
11.SERIAL ACCESS 64K EEPROM
M24C64WBN6, is the 64Kbit electrically erasable programmable memory. The memory is compatible with the I2C standard, two wire serial interface, which uses a bi-directional data bus and serial clock.
12.HEADPHONE AMPLIFIER STAGE
This stage is designed with discrete components (no IC is used for this purpose)
5 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
13.SAW FILTER SPECIFICATION
Two groups of saw filters are used from EPCOS For picture (Z400) · Pal Secam BG DK L L' K3953M · Pal Secam BG I I' K3953M For sound(Z401) · Pal Secam BG DK L L' K9656M · Pal Secam BG I I' K9356 For sound saw filter it needs to be switched between L' and other standarts for K3953M, a port signal coming from PNX300X(ADOC) called SEL_L/L' is used for this purpose to make pin2 of audio saw filter ground or not. port state Q404 SEL_L/L' High Shorted to ground SEL_L/L' Low open Pin Configuration Pin No 1 2 3 4 5 Definition Input
Input - ground Chip carrier - ground Output Output
Standart L' BG,DK,I,L
Maximum ratings for saw filters Operable temperature range Storage temperature range DC voltage AC voltage TA Tstg VDC Vpp 25/+65 °C
14.IC DESCRIPTIONS
In following chapters you can find details of ICs used in the chassis and the SS B(Small signal board) TDA6108JF PNX3000 SDRAM 64MBIT NE56610-29 PNX300X TDA7480L TDA8177&STV9379FA MC44608 TL431 HT48RA0A CS51033 FLASH 32 MBIT STS5PF30L M24C64WBN6 LM7808 TCET1102G TFMS5360 TFMS5360
6 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.1.TDA6108JF (IC900)
14.1.1.General Description
The TDA6108JF includes three video output amplifiers in one plastic DIL-bent-SIL 9-pin medium power (DBS9MPF) package (SOT111-1), using high-voltage DMOS technology, and is intended to drive the three cathodes of a colour CRT directly. To obtain maximum performance, the amplifier should be used with blackcurrent control.
14.1.2.Features · Typical bandwidth of 9.0 MHz for an output signal of 60 V (p-p) · High slew rate of 1850 V/ms · No external components required · Very simple application · Single supply voltage of 200 V · Internal reference voltage of 2.5 V · Fixed gain of 51 · Black-Current Stabilization (BCS) circuit · Thermal protection 14.1.3.Pinning SYMBOL Vi(1) Vi(2) Vi(3) GND Iom VDD Voc(3) Voc(2) Voc(1) PIN 1 2 3 4 5 6 7 8 9 DESCRIPTION inverting input 1 inverting input 2 inverting input 3 ground (fin) black current measurement output supply voltage cathode output 3 cathode output 2 cathode output 1
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14.2.HT48RA0A
14.2.1.General Description The HT48RA0A is an 8-bit high performance RISC-like microcontroller specifically designed for multiple I/O product applications. The device is particularly suitable for use in products such as infrared remote controllers and various subsystem controllers. A HALT feature is included to reduce power consumption. 14.2.2.Features · Operating voltage: 2.2V~3.6V · Ten bidirectional I/O lines · Six Schmitt trigger input lines · One carrier output (1/2 or 1/3 duty) · On-chip crystal and RC oscillator · Watchdog Timer · 1K_14 program EPROM · 32_8 data RAM · HALT function and wake-up feature reduce power consumption · 62 powerful instructions · Up to 1_s instruction cycle with 4MHz system clock · All instructions in 1 or 2 machine cycles · 14-bit table read instructions · One-level subroutine nesting · Bit manipulation instructions · 20-pin/24-pin SOP package 14.2.3.Pin Descriptions Pin Name PB0, PB1 I/O I/O Code Option Wake-up or None Level or Carrier Crystal or RC Description 2-bit bidirectional input/output lines with pull-high resistors. Each bit can be determined as NMOS output or Schmitt trigger input by software instructions. Each bit can also be configured as wake-up input by code option. Level or carrier output pin PC0 can be set as CMOS output pin or carrier output pin by code option. Positive power supply OSC1, OSC2 are connected to an RC network or a crystal (determined by code option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock (NMOS open drain output). Negative power supply, ground Schmitt trigger reset input. Active low. 6-bit Schmitt trigger input lines with pull-high resistors. Each bit can be configured as a wake-up input by code option. Bidirectional 8-bit input/output port with pull-high resistors. Each bit can be determined as NMOS output or Schmitt trigger input by software instructions.
PC0/REM VDD OSC2 OSC1
O I/O
VSS RES PB2~PB7 PA0~PA7
I I I/O
Wake-up or None -
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14.3.PNX3000 (IC400)
14.3.1.General Description The PNX3000 is an analog front end for digital video processors. It contains an IF circuit for both analog and digital broadcast signals, and input selectors and A to D converters for analog video and audio signals. The digital output signals are made available via three serial data links. The IC has a supply voltage of 5V. The supply voltage of the analog audio part can be 5V or 8V, depending on the maximum signal amplitudes that are required.
14.3.2.Features · Multi-standard vision IF circuit with alignment-free PLL demodulator without external components · Internal (switchable) time-constant for the IF-AGC circuit · DTV IF circuit for gain control of digital broadcast TV signals. · Sound IF amplifier with separate AGC circuit for quasi split sound · IF circuit can also be used for intercarrier sound · Analog demodulator for AM sound · Integrated sound trap and group delay correction · Video ident function detects the presence of a video signal · Video source selector with 4 external CVBS or YC inputs and 2 analog CVBS outputs with independent source selection for each output · Two linear inputs for 1fH or 2fH RGB signals with source selector. The RGB signals are converted to YUV before A to D conversion. Both inputs can also be used as YPB PR input for DVD or set top box · Integrated anti-alias filters for video A to D converters · Four 10-bit video A to D converters for the conversion of CVBS, YC, YUV and down mixed sound IF signals · Up to three different A to D converted video channels are simultaneous available (e.g. CVBS and YC and YUV) · Audio source selector with 5 stereo inputs for analog audio and two microphone inputs · Two microphone amplifiers with adjustable gain · Three analog audio outputs for SCART and Line out with independent source selection for each output · Four 1-bit audio sigma delta A to D converters for the conversion of audio and microphone signals · Three serial data link transmitters for interfacing with the digital video processor. The bit rate is 594 Mbits/sec per data link · Voltage to current converter for driving of external East-West power amplifier · I2C-bus transceiver with selectable slave address and maskable interrupt output
9 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
SYMBOL
CVBS2 VAUDO VAUDS CVBS/Y3 C3 GND_VSW BGDEC CVBS/Y4 C4 fuse GND_FILT CVBS_DTV RREF VCC_FILT YCOMB CCOMB AMEXT TESTPIN3 CVBSOUTA VDEFLO VDEFLS CVBSOUTB fuse TESTPIN2 R1/PR1 /V1 G1/Y1/Y1 B1/PB1 /U1 VCC_RGB GND_RGB R2/PR2 /V2 G2/Y2/Y2 B2/PB2 /U2 fuse GND_VADC VCC_VADC EWVIN EWIOUT REW ADR XREF fuse IRQ SDA SCL HV_SEC HV_PRIM VD2V5 GND_DIG VCC_DIG STROBE3N STROBE3P DATA3N DATA3P fuse STROBE2N STROBE2P DATA2N
PIN
1 2 3 4 5 6 7 8 9
DESCRIPTION
CVBS2 input DC output voltage for supply of audio DACs in digital decoder sense voltage for audio DACs supply external CVBS/Y3 input external CHROMA3 input ground video switch bandgap decoupling external CVBS/Y3 input external CHROMA3 input fused lead ground filters input for CVBS encoded signal from DTV decoder reference current input supply voltage filters (5V) Y signal from 3D Comb filter C signal from 3D Comb filter external AM mono input testpin 3 (leave open) CVBS or Y+CHROMA output A DC output voltage for supply of deflection DACs in digital decoder sense voltage for deflection DACs supply CVBS or Y+CHROMA output B fused lead testpin 2 (connect to ground) R1/PR1 /V1 input G1/Y1/Y1 input B1/PB1 /U1 input supply voltage RGB matrix (5V) ground RGB matrix R2/PR2 /V2 input G2/Y2/Y2 input B2/PB2 /U2 input fused lead ground video ADCs supply voltage video ADCs (5V) East-West input voltage East-West output current East-West voltage to current conversion resistor I2C address selection XTAL reference frequency input fused lead interrupt request output I2C serial data input/output I2C serial clock input horizontal and vertical sync input for secondary video channel horizontal and vertical sync input for primary video channel decoupling of internal digital supply voltage digital ground digital supply voltage (5V) strobex negative datalink3 strobex positive datalink3 data positive datalink3 data positive datalink3 fused lead strobex negative datalink2 strobex positive datalink2 data positive datalink2
10 11 12 13 14 15
16
17 18 19 20 21 22 23 24
25 26 27 28
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
55 56 57
10 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
DATA2P GND_I2D STROBE1N STROBE1P DATA1N DATA1P VCC_I2D SCART2R SCART2L LINER LINEL SCART1R SCART1L fuse DSNDR2 DSNDL2 DSNDR1 DSNDL1 GND_AADC VCC_AADC fuse R4 L4 R3 L3 R2 L2 R1 L1 GND2_ASW VCC2_ASW VAADCREF VAADCN VAADCP MIC2N MIC2P MIC1N MIC1P fuse GND1_ASW VCC1_ASW SIFINP SIFINN SIFAGC DTVIFAGC DTVIFINP DTVIFINN TUNERAGC fuse VIFINP VIFINN DTVIFPLL VCC_IF VIFPLL GND1_IF 2NDSIFEXT 2NDSIFAGC GND2_IF DTVOUTP
58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
data positive datalink2 ground datalinks strobex negative datalink1 strobex positive datalink1 data negative datalink1 data positive datalink1 supply voltage datalinks (5V) audio output for SCART 2 right audio output for SCART 2 left audio line output right audio line output left audio output for SCART1 right audio output for SCART1 left fused lead audio signal from digital decoder right 2 audio signal from digital decoder left 2 audio signal from digital decoder right 1 audio signal from digital decoder left 1 ground audio ADCs supply voltage audio ADCs (5V) fused lead right input audio 4 left input audio 4 right input audio 3 left input audio 3 right input audio 2 left input audio 2 right input audio 1 left input audio 1 ground audio switch supply voltage audio switch (audio output buffers, 5V or 8V) decoupling of reference voltage for audio ADCs 0V reference voltage for audio ADCs (GND) full scale reference voltage for audio ADCs (5V) microphone input 2 neg microphone input 2 pos microphone input 1 neg microphone input 1 pos fused lead ground audio switch supply voltage audio switch (audio input buffers, 5V or 8V) sound IF input positive sound IF input negative control voltage for SIF AGC control voltage for DTV IF AGC DTV IF input positive DTV IF input negative tuner AGC output fused lead vision IF input positive vision IF input negative loop filter DTVIF PLL demodulator supply voltage IF circuit (5V) loop filter VIF PLL demodulator ground IF circuit 2ndSIF input 2ndSIF AGC capacitor ground IF circuit DTV output positive
11 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
DTVOUTN VCC_SUP fuse CVBSOUTIF GND_SUP VCC1_VSW CVBS0 TESTPIN1 VCC2_VSW CVBS1 R5 L5
117 118 119 120 121 122 123 124 125 126 127 128
DTV output negative supply of supply circuit (5V) fused lead CVBS output of IF circuit ground of supply circuit supply of video switch (5V) CVBS0 input (to be used for CVBS from IF part) testpin 1 (connect to ground) supply of video switch (5V) CVBS1 input right input audio 5 left input audio 5
Important pins need to be cheched in case of troubleshooting
Signal CVBS/RGB Input voltage CVBS Output voltage Maximum input audio voltage Maximum output audio voltage Measure Input pins Output pins Input pins Output pins Value 1Vpk-pk 2 Vpk-pk 2 V rms 2 V rms
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14.4.CS51033 (IC 104)
14.4.1.General Description The CS51033 is a switching controller for use in dcdc converters. It can be used in the buck topology with a minimum number of external components. The CS51033 consists of a 1.0 A power driver for controlling the gate of a discrete Pchannel transistor, fixed frequency oscillator, short circuit protection timer, programmable Soft Start, precision reference, fast output voltage monitoring comparator, and output stage driver logic with latch. The high frequency oscillator allows the use of small inductors and output capacitors, minimizing PC board area and systems cost. The programmable Soft Start reduces current surges at start up. The short circuit protection timer significantly reduces the PFET duty cycle to approximately 1/30 of its normal cycle during short circuit conditions. The CS51033 is available in an 8Lead SO package. 14.4.2.Features · 1.0 A Totem Pole Output Driver · High Speed Oscillator (700 kHz max) · No Stability Compensation Required · Lossless Short Circuit Protection · 2.0% Precision Reference · Programmable Soft Start · Wide Ambient Temperature Range: Industrial Grade: 40°C to 85°C Commercial Grade: 0°C to 70°C 14.4.3.Pin Description PIN NUMBER 1 2 3 4 5 6 7 8 PIN SYMBOL VGATE PGND COSC GND VFB VCC CS VC FUNCTION Driver pin to gate of external PFET. Output power stage ground connection. Oscillator frequency programming capacitor. Logic ground. Feedback voltage input. Logic supply voltage. Soft Start and fault timing capacitor. Driver supply voltage.
13 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.5.SDRAM 64MBIT (IC315)
14.5.1.General Description please note that in the following explanation one of the SDRAM alternative is used. The K4S641632D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG¢s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. 14.5.2.Features · JEDEC standard 3.3V power supply · LVTTL compatible with multiplexed address · Four banks operation · MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock · Burst read single-bit write operation · DQM for masking · Auto & self refresh · 64ms refresh period (4K cycle) 14.5.3.Pin Description
PIN CLK CS CKE NAME System clock Chip select Clock enable INPUT FUNCTION Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
A0 ~ A11 BA0 ~ BA1 RAS CAS WE L(U)DQM DQ0 ~ 15 VDD/VSS VDDQ/VSSQ N.C/RFU
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
14 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.6.FLASH (IC 314)
14.6.1.General Description The MT28F128J3 is a nonvolatile, electrically block-erasable (Flash), programmable memory containing 134,217,728 bits organized as 16,777,218 bytes (8 bits) or 8,388,608 words (16 bits). This 128Mb device is organized as one hundred twenty-eight 128KB erase blocks. The MT28F640J3 contains 67,108,864 bits organized as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits). This 64Mb device is organized as sixty-four 128KB erase blocks. Similarly, the MT28F320J3 contains 33,554,432 bits organized as 4,194,304 bytes (8 bits) or 2,097,152 words (16 bits). This 32Mb device is organized as thirty-two 128KB erase blocks. These three devices feature in-system block locking. They also have common Flash interface (CFI) that permits software algorithms to be used for entire families of devices. The software is deviceindependent, JEDEC ID-independent with forward and backward compatibility. Additionally, the scalable command set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant Flash memory devices. The SCS provides the fastest system/device data transfer rates and minimizes the device and system-level implementation costs. To optimize the processor-memory interface, the device accommodates VPEN, which is switchable during block erase, program, or lock bit configuration, or hard-wired to VCC, depending on the application. VPEN is treated as an input pin to enable erasing, programming, and block locking. When VPEN is lower than the VCC lockout voltage (VLKO), all program functions are disabled. Block erase suspend mode enables the user to stop block erase to read data from or program data to any other blocks. Similarly, program suspend mode enables the user to suspend programming to read data or execute code from any unsuspended blocks. VPEN serves as an input with 2.7V, 3.3V, or 5V for application programming. VPEN in this Q-Flash _ family can provide data protection when connected to ground. This pin also enables program or erase lockout during power transition. Micron's even-sectored Q-Flash devices offer individual block locking that can lock and unlock a block using the sector lock bits command sequence. Status (STS) is a logic signal output that gives an additional indicator of the internal state machine (ISM) activity by providing a hardware signal of both status and status masking. This status indicator minimizes central processing unit (CPU) overhead and system power consumption. In the default mode, STS acts as an RY/BY# pin. When LOW, STS indicates that the ISM is performing a block erase, program, or lock bit configuration. When HIGH, STS indicates that the ISM is ready for a new command. Three chip enable (CE) pins are used for enabling and disabling the device by activating the device's control logic, input buffer, decoders, and sense amplifiers. BYTE# enables the device to be used in x8 or x16 read/write mode; BYTE# = 0 selects an 8-bit mode, with address A0 selecting between the LOW and HIGH byte, while BYTE# = 1 selects a 16-bit mode. When BYTE# = 1, A1 becomes the lowest-order address line with A0 being a no connect. RP# is used to reset the device. When the device is disabled and RP# is at Vcc, the standby mode is enabled. A reset time (t RWH) is required after RP# switches HIGH until outputs are valid. Likewise, the device has a wake time (t RS) from RP# high until writes to the command user interface (CUI) are recognized. When RP# is at GND, it provides write protection, resets the ISM, and clears the status register. A variant of the MT28F320J3 also supports the new security block lock feature for additional code security. This feature provides an OTP function for the device. (Contact factory for availability.) The MT28F320J3 and the MT28F640J3 are manufactured using the 0.18µm process technology, and the MT28F128J3 is manufactured using the 0.15µm process technology. 14.6.2.Features · x8/x16 organization · One hundred twenty-eight 128KB erase blocks (128Mb) Sixty-four 128KB erase blocks (64Mb) Thirty-two 128KB erase blocks (32Mb) ·VCC, VCCQ, and VPEN voltages: 2.7V to 3.6V VCC operation 2.7V to 3.6V, or 5V VPEN application programming · Interface Asynchronous Page Mode Reads: 150ns/25ns or 120ns/25ns read access time (128Mb) 120ns/25ns or 115ns/25ns read access time (64Mb) 15 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
110ns/25ns read access time (32Mb) · Manufacturing ID (ManID) Intel® (0x89h) Micron® (0x2Ch) · Industry-standard pinout · Inputs and outputs are fully TTL-compatible · Common Flash Interface (CFI) and Scalable Command Set · Automatic write and erase algorithm · 5.6µs-per-byte effective programming time using write buffer · 128-bit protection register 64-bit unique device identifier 64-bit user-programmable OTP cells · Enhanced data protection feature with VPEN = VSS Flexible sector locking Sector erase/program lockout during power transition ·Security OTP block f eature Permanent block locking (Contact factory for availability) · 100,000 ERASE cycles per block · Automatic suspend options: Block Erase Suspend-to-Read Block Erase Suspend-to-Program Program Suspend-to-Read 14.6.3.Pin/Ball Descriptions
56-PIN TSOP NUMBERS 55 64-BALL FBGA NUMBERS G8 SYMBOL WE# TYPE Input DESCRIPTION Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL) or to the memory array. Addresses and data are latched on the rising edge of the WE# pulse. Chip Enable: Three CE pins enable the use of multiple Flash devices in the system without requiring additional logic. The device can be configured to use a single CE signal by tying CE1 and CE2 to ground and then using CE0 as CE. Device selection occurs with the first edge of CE0, CE1, or CE2 (CEx) that enables the device. Device deselection occurs with the first edge of CEx that disables the device (see Table 4 on page 14). Reset/Power-Down: When LOW, RP# clears the status register, sets the ISM to the array read mode, and places the device in deep power-down mode. All inputs, including CEx, are "Don't Care," and all outputs are High-Z. RP# must be held at VIH during all other modes of operation. Output Enables: Enables data output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Address inputs during READ and WRITE operations. A0 is only used in x8 mode and will be a NC in x16 mode (the input buffer is turned off when BYTE = HIGH). A22 (pin 1, ball A8) is only available on the 64Mb and 128Mb devices. A23 (pin 30, ball G1) is only available on the 128Mb device. BYTE# low places the device in the x8 mode. BYTE# high places the device in the x16 mode and turns off the A0 input buffer. Address A1 becomes the lowest order address in x16 mode. Necessary voltage for erasing blocks, programming data, or configuring lock bits. Typically, VPEN is connected to VCC. When VPEN _ VPENLK, this pin enables hardware write protect.
14, 2, 29
B4, B8, H1
CE0, CE1, CE2
Input
16
D4
RP#
Input
54 32, 28, 27, 26, 25, 24, 23, 22, 20, 19, 18, 17, 13, 12, 11, 10, 8, 7, 6, 5, 4, 3, 1, 30 31
F8 G2, A1, B1, C1, D1, D2, A2, C2, A3, B3, C3, D3, C4, A5, B5, C5, D7, D8, A7, B7, C7, C8, A8, G1 F1
OE# A0 _ A21/ (A22) (A23)
Input Input
BYTE#
Input
15
A4
VPEN
Input
16 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
33, 35, 38, 44, 46, 49, 34, 36, 39, 45, 49, 51, 36, 39, 41, 47, 50, 52 53
40, 51, 41, 34, 45,
F2, E2, G3, E4, E5, G5, G6, H7, E1, E3, F3, F4, F5, H5, G7, E7 E8
DQ0 DQ15
Input/ Output
Data I/O: Data output pins during any READ operation or data input pins during a WRITE. DQ8DQ15 are not used in byte mode (BYTE = LOW).
STS
Output
43 9, 37 21, 42, 48 56 --
G4 H3, A6 B2, H4, H6 H8 B6, C6, D5, D6, E6, F6, F7, H2
VCCQ VCC VSS NC DNU
Supply Supply Supply -- --
Status: Indicates the status of the ISM. When configured in level mode (default), STS acts as a RY/BY# pin. When configured in its pulse mode, it can pulse to indicate program and/or erase completion. Tie STS to VCCQ through a pull-up resistor. VCCQ controls the output voltages. To obtain output voltage compatible with system data bus voltages, connect VCCQ to the system supply voltage. Power Supply: 2.7V to 3.6V. Ground. No Connect: These may be driven or left unconnected. Pin 1 and ball A8 are NCs on the 32Mb device. Pin 30 and ball G1 are NCs on the 32Mb and 64Mb devices. Do Not Use: Must float to minimize noise.
17 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.7.NE56610-29 (RESET IC) (IC 316)
14.7.1.General Description The NE56610-29 is a family of devices designed to generate a reset signal for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions or when ever power supply voltages sag to intolerable levels. The NE56610-29 incorporates an internal timer to provide reset delay and ensure proper operating voltage has been attained. An Open Collector output topology provides adaptability for a wide variety of logic and microprocessor systems. SOT23-5 surface mount package is used. 14.7.2.Features · 3.3V operating voltage (VDDE) · SOT23-5 surface mount package · Offered in reset thresholds 2.9 V DC · Internal reset delay timer is 50ms 14.7.3.Pin Description PIN NUMBER 1 2 3 4 5 SYMBOL M/R SUB GND VOUT Vcc DESCRIPTION Manual Reset input. Connect to ground when not using. Substrate pin. Connect to ground. Ground Reset HIGH output pin Positive power supply input
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14.8.STS5PF30L (IC105)
14.8.1.Description STS5PF30L is a Power MOSFET.
14.8.2.Features · TYPICAL RDS(on) = 0.070 · STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY · LOW THRESHOLD DRIVE TYPE STS5PF30L VDSS 30V RDS(on) <0.080 ID 5A
19 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.9.PNX300X (IC313)
This IC is the heart of the TV set for small signal processing; 14.9.1.General Description of the Digital One Chip System
DOC Hardware The Digital One Chip System (DOC) is a system concept based on a digital processor for double-scan TV receivers.It is a global, multi-standard system primarily designed for the reception and processing of analog broadcast signals. The DOC system serves the TV functionality for small signal processing of audio, video, VBI services, graphics and control. An integrated MIPS 1910 processor runs the DOCware software stack.The Digital One Chip DOCware software is stored in a non-volatile external memory, normally flash memory. The following figure shows the hardware system architecture of a TV chassis based on the DOC system. The dual stream architecture of the DOC system allows audio and video processing of two A/V sources simultaneously. The two video streams can be displayed in several programmable ways (main screen, PIP or DW). The two audio streams are audible via the TV loudspeakers and/or the headphones. If two TV broadcast signals have to be processed simultaneously, an external IF processor and a PIP Mono Sound Demodulator/Decoder is needed. For the memory-based features in the DOC system (like scan rate conversion, dynamic noise reduction and PIP/DW applications) external SDRAM is needed. The memory size requirements are directly related to which memory-based features have to be supported. The amount of SDRAM required varies per feature but also varies with combination of features. The DOC system also has 128kByte of internal SRAM memory. This memory is used to run low latency, timing critical parts of the software. Under these circumstances no external SDRAM is needed. The DOC system is built around the ADOC IC. This chip implements all TV functions in digital technology. Only a few functions (like AD-conversion, IF processing and source select) are implemented in an analog companion IC, the MPIF. The MPIF is meant as an analog video and audio pre-processing unit for the TV processor ADOC. It contains the high frequent IF part and all the analog video and audio source switching for external inand outputs. MPIF can handle CVBS, Y/C, RGB (1Fh/2Fh) and YPrPb (1Fh/2Fh) video signals as well as stereo Left/Right and Second Sound IF (low-IF 5-6MHz, 10.7Mhz) audio signals. MPIF converts the selected video and audio streams from the analog to the digital domain. Via three high-speed serial data links the digitized audio and video signals are streamed to the ADOC IC for further processing. ADOC is a fully integrated, digitally implemented TV processor for audio, video, VBI services, graphics and control. The split-up between an analog (MPIF) and a digital part (ADOC) has the following advantages: · High frequency IF part can be included in the concept · Less A/D and D/A converters needed for source switching 20 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
· Better performance for AD converters (realized in analog design environment, more accurate, less tolerance) · Critical items like reference voltages can be realized in the analog environment · Integrated SCART buffers The DOC system is designed to facilitate a very cost effective TV chassis. Some of the measures taken are: · One crystal design. Only one reference crystal is required for the MPIF and ADOC, · The advanced geometry corrections in the DOP result in a simple horizontal deflection circuitry. Linearity coils are not required 14.9.2.Features of the ADOC Processor 14.9.2.1.Colour Decoder and Sync Processing · Multi standard colour decoder supporting PAL-B, G, D, H, I, N, Combination-PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM · Automatic colour standard recognition and selection (PAL/SECAM/NTSC) · Fully programmable static or Automatic Gain Control (AGC) for all analogue video base band signals. · Resolution of CVBS or Y/C signal after AGC: 9 bits (including sync) · AGC for chrominance (PAL and NTSC only) for CVBS and Y/C sources · Programmable clamp window for selected video base band signal(s) · Horizontal (including 3-level sync for 2Fh) and vertical sync detection. · Adaptive 2/4-line delay Comb filter for two dimensional chrominance/luminance separation · PAL delay line for correcting PAL phase errors · Maskable interrupt generation to MIPS notifying any change of signal conditions · Compliant with and detection of Macrovision up to version 7.1. · Possibility of Fast Blank SCART RGB insertion in CVBS input mode, not in Y/C. · Second multi standard colour decoder for low-cost PIP Supports CVBS standards as listed above No comb filter No Y/C performance (Y and C are being summed before decoding) No fast blanking with Component inputs 14.9.2.2.VBI Data Capture · Two independent data capture units (DCU1 and DCU2) for standard data rate streams · Multi-standard data capture. Both DCUs can always execute the following services: Line 21 Data Services (Closed Caption) European Wide Screen Signalling (WSS line23) PDC A & B (VPS and TeleText packet 8/30) World Standard TeleText. · Services performed by TeleText application: Data Broadcast (packets X/30, X/31) Channel Identification (packet 8/30) · Data type selectable on line-by-line basis independently for odd and even fields · Multi-page acquisition during VBI · Single page acquisition during full field · DMA of packets and status bits to memory (embedded SRAM) · Automatic identification of VBI data standard supported 14.9.2.3.Teletext storage · Error correction and decoding performed by DOCware software · Page management performed by DOCware software · Storage of up to 8 pages of TeleText internally · Storage of more than 8 TeleText pages requires external memory (SDRAM) 14.9.2.4.Picture measurements · Noise measurement in active video · Black Bar detection · Sharpness measurement 14.9.2.5.Picture Improvements · Field based noise reduction (on main only) · Horizontal Dynamic Peaking/ Luminance Transient Improvement (LTI) 21 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
· SCAn VElocity Modulation (SCAVEM or SVM) and Dynamic Contrast Control (DCC) · Dynamic Colour Transient Improvement (DCTI) · Dynamic Skin Tone control · Blue Stretch · Green Enhancement · Black Stretch · 32-bins histogram · Electrical Local Doming Protection 14.9.2.6.Picture in Picture / Double window · Requires external memory to be connected to SDRAM interface · Second input through second color decoder. Can be selected to be either main or sub. · YCrCb storage in 4:2:2 format. 8 bits per component. Dithering adopted to have 9 bits effectively. · No joint line/crossover errors · Supporting Double Window displaying both a PAL (50 Hz) and an NTSC (60 Hz) signal. · Double window text. Displaying a TeleText page next to a TV broadcast. This feature is functional without
the external Memory in 50 Hz mode.
· For proper aspect ratio of Double Window display on 4/3 screen vertical scaling by deflection can be
adopted 14.9.2.7.Scan Rate Conversion
· This requires external memory connected to SDRAM interface · Line flicker reduction · Full interlaced performance (provided sufficient memory) 14.9.2.8.Video H/V Scaling · Horizontal Panorama/customer defined Scaling in video path (not affecting graphics) · Vertical Scaling by vertical deflection 14.9.2.9.Audio Base band Switching and Interfaces · 5x Analogue outputs (Left, Right, Subwoofer, Centre and Surround speaker) · 1x Left and Right Head Phones output 14.9.2.10.Sound Demodulator/Decoder · Two FM/AM Demodulator channels with programmable mixer frequencies and four different filter bandwidths: Multi-standard FM demodulation (B/G, D/K, I, M and N standard) Optional AM demodulation (L/L' standard) FM pilot carrier present detector (for A2 sound systems) · FM-A2 Decoder: Detection of ID signal for second carrier Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound Identification A2 systems (B/G, D/K and M standard) Supporting Korean 2SC standard · BTSC Stereo/SAP Decoder: M/BTSC and N standards supported Processing of MTS/MPX signal Detection of pilot carrier with pilot lock indicator AM demodulation of stereo sub-carrier Detection of SAP sub carrier SAP decoder FM demodulation of SAP carrier (without dbx®) simultaneously with stereo decoding, or mono plus SAP with dbx® dbx® noise reduction on either (L-R) or SAP signal · Japan MTS Decoder: Processing of MPX signal Detection of the Identification signal FM demodulation of sub-carrier for stereo or bilingual reproduction · NICAM demodulator and decoder (B/G, I and L/L' standard): DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation NICAM decoding · Auto Standard Detection Mode (ASD) 22 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
· Demodulator Decoder Easy Programming (DDEP) · FM-Radio decoder · Identification circuit for all standards · Decoding and adaptive de-emphasis for satellite FM (ASTRA) · Monitor selection for FM/AM DC values and signals, with peak detection option · Soft-mute for DEMDEC outputs DEC, MONO and SAP · Sample rate conversion (SRC) for up to three demodulated terrestrial audio signals. It is possible to process SCART signals together with demodulated terrestrial signals. Up to five signals (stereo counting for 2) can be processed at a time. 14.9.2.11.Audio Processing · Virtual Dolby® (`422' mode and `423' mode) (3) · Bass management · Dynamic Bass Boost (4) Automatic volume levelling (AVL) · Programmable Level Adjust at inputs of switch matrix · Volume control: Separate volume control on headphone · Balance control on left/right speaker and on left/right headphone by use of trim control · 5-band graphic equalizer or treble/bass control · Notch filter for acoustic compensation · Soft mute on all outputs · Beeper · Pseudo Hall/Matrix: Pseudo Hall provides (L+R)/2 on Centre and (L+R)/2 with 30ms delay on Surround Pseudo Matrix provides (L+R)/2 on Centre and (L-R)/2 with 30ms delay on Surround 14.9.2.12.Character Based Graphics · Characters Based Display: 1440 pixels per line of which 5% in over-scan. · Level 1.5 WST TeleText compliant · Double Window TeleText display: Display of two 40 character wide Level 1.5 TeleText pages side by side. Display of 40 character wide Level 1.5 TeleText and Video side by side. · Line 21 Data Services compliant · Supports OSD with up to 8 colours out of a palette of 4096 colours · Selectable character size · Dynamically Redefinable Characters (DRCs) Internal memory up to 64 characters 14.9.2.14.RGB Processing · Fully programmable YCrCb to RGB matrix · Saturation control done using matrix · Contrast and brightness control with 8 bits resolution · D/A converters for RGB and Scan Velocity Modulation: Clock frequency 81MHz (fixed) Sample Rate Conversion to convert from orthogonal pixels 10 bits resolution (11 bits virtual using dithering of LSB) 2160 interpolated pixels per line · 1440 pixels per line (of which 5% in over scan) at graphics blender (clock frequency 54 MHz) · Forced super blanking during start-up or fault conditions · Programmable horizontal and vertical retrace blanking via line and pixel number · Separate beam current control on video and graphics · Peak White limiter for video path · Soft clipping for video path · Hard clipping for graphics path · Advanced Scan Velocity Processing: Scan Velocity modulation working on both Video and Graphics Dynamic contrast · Continuous Cathode Calibration (=cut off control): System allows both for one-point and two-point calibration 23 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
· Graphics/video blender with mixture level (0% to 100% in 16 steps) 14.9.2.15.AD Converters for Display Functions · 3x Sigma Delta ADC for Black Current, EHT, Beam Current Limiting measurement Clock frequency 54MHz 14.9.2.16.Deflection & Geometry · Horizontal time base for display based on digital PLL · Very good jitter performance of about. +/- 300 ps of the horizontal drive pulse · Low power start-up mode from standby · Slow start/stop · Fixed beam-current switch-off · Vertical and horizontal geometry processing. Special features of the horizontal geometry processor are: inner-pincushion correction horizontal non-linearity correction · Auxiliary output can be used to generate waveform with frequency of vertical deflection (for example quadrupole correction for flat picture tubes) · Vertical guard input · Flash detection input · EHT overvoltage protection (X-Ray) input · Horizontal drive output 14.9.2.17.Microprocessor · TV control by embedded 32 bit RISC processor Philips MIPS PR1910, 54MHz · Cache Structure Unified 8Kbyte Instruction/Data Cache · Co-Processor: 2x 32bit system clock Count/Compare (Timer1,2) Registers 1x 32bit system clock Count/Compare (Timer3) configurable as Watchdog Timer · Debug Support: MIPS JTAG compliant Software / Hardware Breakpoint Single Stepping Real Time Trace 14.9.2.18.TV Control Peripherals · General Purpose IO (GPIO): 32 total GPIO pins, 28 with secondary functions stated bellow (4 GPIO free pins) · Two I 2 C Interface units · Two General Purpose Counter/Compare (Timer) units · Universal Asynchronous Receiver Transmitter (UART) · Eight external interrupts · Analogue to Digital converter: 6 multiplexed inputs Programmable resolution of up to 10 bits · Remote Control Receiver and Transmitter 14.9.2.20.Reset · Reset via external input 14.9.2.21.Internal Memory for SW Code /Data · Data/ Code memory up to 128 Kbytes (SRAM) 14.9.2.22.Memory at SDRAM Interface · Addressable space up to 32Mbyte (SDRAM only, no SRAM, no DDRAM) 16Mbit (1M x 16) Single data rate SDRAM · Memory Functions: PIP/DW, DNR, Scan Conversion, requiring at least 13Mbit 24 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
PIP replay, scalable size 14.9.2.23.Memory at EBIU Interface for SW Code/Data · Addressable space up to 8Mbyte · Memories supported 16bit Standard asynchronous ROM, SRAM, FLASH 16bit Page mode Flash support (AMD, Intel and ST) · Memory Functions Code memory up to 8Mbyte (FLASH/ROM/RAM) Data memory up to 8Mbyte (RAM) 14.9.2.24.Memory at I2C Interface · Software support of external non-volatile memory connected to I2C interface Important pins need to be cheched in case of troubleshooting Port On/Off On/Off Mute Degauss Reset Protection LED LED Supply_switch Supply_switch Measure pin33 of PL402 pin33 of PL402 pin7 of PL402 pin31 of PL402 pin1 of IC316 Base of Q719 pin pin pin pin State low high low low High low high low high low Function normal operation stand by mode Audio amplifier is muted Degaussing is done Resets ADOC TV set goes to stby mode LED light as red (stby) LED light as green (on) 5V is selected via Q106 V8Stby is selected via Q106
25 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.10.M24C64WBN6 (IC309)
14.10.1.Features · Two Wire I 2 C Serial Interface Supports 400 kHz Protocol · 3.3V Supply Voltage · Write Control Input · BYTE and PAGE WRITE (up to 32 Bytes) · RANDOM and SEQUENTIAL READ Modes · Self-Timed Programming Cycle · Automatic Address Incrementing · Enhanced ESD/Latch-Up Behavior · More than 1M Erase/Write Cycles · More than 40 Year Data Retention 14.10.2.Description These I2C -compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192 x 8 (M24C64) .These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit, terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
SIGNAL NAMES E0, E1, E2 Chip Enable SDA Serial Data SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground
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14.11.TDA7480L (IC401,IC402)
14.11.1.Description The TDA7480L is an audio class-D amplifier assembled in Power DIP package specially de-signed for high efficiency applications mainly for TV and Home Stereo sets. 14.11.2.Features 10W Output Power: RL = 8/4; THD = 10% High Frequency No Heatsink Split Supply Overvoltage Protection St-By And Mute Features Short Circuit Protection Thermal Overload Protection 14.11.3.Pin Functions -Vcc=-14.5V +Vcc=+14.5V
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name -VCC -VCC -VCC OUT BOOTDIODE BOOT NC FEEDCAP FREQUENCY SGN-GND IN ST-BY-MUTE NC +VCC SIGN VREG +VCC POW -VCC -VCC -VCC -VCC Function NEGATIVE SUPPLY. NEGATIVE SUPPLY. NEGATIVE SUPPLY. PWM OUTPUT BOOTSTRAP DIODE ANODE BOOTSTRAP CAPACITOR NOT CONNECTED FEEDBACK INTEGRATING CAPACITANCE SETTING FREQUENCY RESISTOR SIGNAL GROUND INPUT ST-BY/ MUTE CONTROL PIN NOT CONNECTED POSITIVE SIGNAL SUPPLY 10V INTERNAL REGULATOR POSITIVE POWER SUPPLY NEGATIVE SUPPLY (TO BE CONNECTED TO PIN 16 VIA C5) NEGATIVE SUPPLY NEGATIVE SUPPLY NEGATIVE SUPPLY
27 AK53 D.O.C. Service Manual- Preliminary 12/12/2003
14.12.LM7808 (IC803)
14.12.1.Description The L7800 series of three-terminal positive regulator.These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type employs