1. Remove the four screws A attaching the top cover (Use an Allen wrench). 2. Lift up the front part of the top cover to release the two joints a and remove the top cover toward the front.
Joints a
A
Top cover
A
Fig.1
Removing the rear cover (See Fig. 3)
Prior to performing the following procedure, remove the top cover. 1. Remove the four screws B attaching the rear cover on the back of the body. Pull out the rear cover backward.
Top cover
Joint a
Removing the right and left side covers (See Fig. 4 and 5)
Prior to performing the following procedure, remove the top cover and the rear cover. 1. Move the left side cover backward to release the five joint hooks b and remove the left side cover outward. 2. Remove the right side cover in the same way.
Fig.2
B
Rear cover
B
B
Fig.3
B
Right side cover
Left side cover
Joints b
Joints b
Fig.5
Fig.4
1-5
TH-A10R/TH-A10 Removing the front panel assembly (See Fig. 6 to 9)
Prior to performing the following procedure, remove the top cover, the rear cover and the side covers. 1. Disconnect the harness from connector CN802 on the main board on the upper side of the body. 2. Remove the two screws C on the upper side of the body. 3. Remove the three screws D on the bottom of the body. 4. Release the five joints c and detach the front panel assembly toward the front.
C Joint c
Joint c CN802 Front panel assembly
C
Fig.6
D
Front panel assembly Joint c D
Fig.7
Joint c
Joint c
Front panel assembly
Front panel assembly
Fig.9
Fig.8
1-6
TH-A10R/TH-A10
Removing the right and left corner covers (See Fig.10 and 11)
Prior to performing the following procedure, remove the top cover, the rear cover, the side covers and the front panel assembly. It is not necessary to remove the front panel assembly. 1. Move the left corner cover backward to release the three joint hooks d. 2. Remove the right corner cover in the same way.
Joint d Left corner cover Joints d
Fig.10
Removing the rear panel (See Fig.12 to 14)
Prior to performing the following procedure, remove the top cover and the rear cover. 1. Remove the eighteen screws E and the one screw F attaching the rear panel. 2. Release the two joints e on both sides of the body.
Joint d Joints d Right corner cover
Fig.11
E
E
E
Rear panel
E
E
F
E
Fig.12
E
Joint e
Joint e
Rear panel
Rear panel
Fig.12
Fig.12
1-7
TH-A10R/TH-A10 Removing the DVD servo control board (See Fig.15 to 17)
Prior to performing the following procedure, remcover and the right side cover.ove the top cover, the rear 1. Remove the three screws G and pull the DVD servo control board case upward. 2. Disconnect the harness from connector CN501 and CN503, and the card wire from CN101, CN103 and CN502 of the DVD servo control board on the underside of the DVD servo control board case.
CN687 DVD servo control board (case) Analog I / O board CN681 CN201
Digital I / O board
G
3. Remove the four screws H attaching the DVD servo control board.
Fig.15
CN501
CN503
CN502
CN103 DVD servo control board case
CN101
Fig.16
H
DVD servo control board
H
H
DVD servo control board case
H
Fig.17
1-8
TH-A10R/TH-A10
Removing the analog I / O board / the digital I / O board (See Fig.18 and 19)
Prior to performing the following procedure, remove the top cover and the rear cover. 1. Remove the two screws E attaching the analog I / O board on the back of the body. 2. Disconnect the card wire from connector CN201 on the analog I / O board. 3. Remove the four screws E attaching the digital I / O board on the back of the body.
Digital I / O board
Analog I / O board CN681 CN201
G
CN687
DVD servo control board (case)
4. Disconnect the card wire from connector CN681 and CN687 on the digital I / O board. Fig.18
Removing the tuner board / the sub board (See Fig.20 and 21)
Prior to performing the following procedure, remove the top cover, the rear cover and the DVD servo control board case. 1. Remove the two screws E attaching the tuner board on the back of the body. 2. Disconnect connector CN111 on the tuner board from the sub board. 3. Disconnect connector CN131 on the sub board from the main board.
E
E
E
Rear panel
Fig.19
Sub board Sub board
CN111
Tuner board
CN131
E
Fig.21 Fig.20
1-9
TH-A10R/TH-A10
Removing the DVD mechanism assembly (See Fig.22 and 23)
Prior to performing the following procedure, remove the top cover, the rear cover, the front panel assembly, the DVD servo control board case, the analog I / O board, the digital I / O board and the tuner board. 1. Disconnect the harnesses from the spacer on the upper side of the DVD mechanism cover. 2. Remove the two screws I and the one screw J attaching the DVD mechanism cover. 3. Remove the two screws K mechanism assembly. attaching the DVD
DVD mechanism cover
K
J
K
I
Spacer
I
Fig.22
DVD mechanism assembly
4. Remove the DVD mechanism assembly upward while pulling it backward.
Removing the power board (See Fig.24 and 25)
Prior to performing the following procedure, remove the top cover, the rear cover, the front panel assembly, the DVD servo control board case and the digital I / O board. 1. Disconnect the harness from the spacer on the upper side of the DVD mechanism cover. 2. Remove the two screws E attaching the power board on the back of the body. 3. Disconnect the harness from connector CN911 and CN912 on the power board. 4. Remove the four screws L board. attaching the power
Fig.23
Rear panel
Fig.24
Power transformer assembly
E
E
CN911,CN912
L M L
Power board
5. Disconnect connector CN913 and CN914 of the power board from the main board by pulling out them respectively.
L
1-10
CN914
CN913
Spacer
Fig.25
TH-A10R/TH-A10
Removing the power transformer assembly (See Fig.24 and 25)
Prior to performing the following procedures, remove the top cover and the rear cover. 1. Disconnect the harnesses from connector CN911 and CN912 on the power board. 2. Remove the two screws M transformer assembly. attaching the power
Rear panel
E
Fig.24
E
3. Remove the screw E attaching the power transformer assembly on the back of the body.
CN911,CN912
L M
Removing the main board (See Fig.26)
Prior to performing the following procedure, remove the top cover, the rear cover, the front panel assembly, the rear panel, the DVD mechanism assembly, the power board and the sub board. 1. Remove the four DVD spacers on the upper side of the main board. 2. Remove the five screws N attaching the main board.
L
Power board
L
Mainboard
CN914
CN913
Spacer
Fig.25
N
N
Prior to performing the following procedure, remove the top cover, the rear cover, the side covers and the front panel assembly.
Removing the power switch board (See Fig.27)
1. Dithe harness from connector CN705 on the power switch board.sconnect 2. Remove the three screws O switch board. attaching the power
CN706 IC board
Fig.26
N
R
Power switch board
O O
S
Fig.27
LED board
1-11
TH-A10R/TH-A10
Removing the eject board (See Fig.28)
Eject board
1. Disconnect the harness from connector CN702 on the eject board. 2. Remove the three screws P board. attaching the eject
Switch board
P
Removing the LCD board (See Fig.29)
1. Remove the four screws Q attaching the LCD board. 2. Unsolder WA701, WA703 and WA704 on the LCD board.
CN702
T
Fig.28
Q
Removing the IC board (See Fig.27)
1. Remove the screw R attaching the IC board. 2. Disconnect the harness from connector CN706 on the IC board.
WA701 LCD board
Q
WA704 WA703
Q
Removing the LED board (See Fig.27)
Prior to performing the following procedure, remove the LCD board and the IC board. 1. Disconnect the harness from connector CN705 on the power switch board. 2. Remove the two screws S attaching the LED board.
CN706 IC board
Q
Fig.29
R
Power switch board
O O
Removing the switch board (See Fig.28)
Prior to performing the following procedure, remove the LCD board. 1. Disconnect the harness from connector CN702 on the eject board. 2. Remove the two screws T board. attaching the switch
S
Fig.27
LED board
1-12
TH-A10R/TH-A10
Removing the clamper base (refer to Figure 1) o Remove the top cover. o Remove the DVD mechanism unit. 1. Remove the two screws at A fixing the clamper base.
Clamper base
Loading tray
Removing the loading tray (refer to Figures 2 - 4) o Remove the clamper base. 1. Turn the up-down cam lever clockwise (in the direction of the arrow in Figure 2) to lower the position of the mechanism. 2. Manually set the loading tray to the fully-open position. 3. Stretch the tray stoppers on both sides of the loading base outward and pull out the tray.
Figure 1
Loading tray (front side)
Loading base
Up-down cam
Tray stopper Lever Loading base Loading tray
Figure 2
Loading tray
Push
Push Tray stopper
Figure 4
Figure 3
1-13
TH-A10R/TH-A10
Traverse mechanism unit
Removing the traverse mechanism unit (refer to Figure 5) o Remove the loading tray. 1. Remove the three screws at B fixing the traverse mechanism unit. B B
Protecting the optical pickup o Solder the flexible ground point on the optical pickup when replacing the pickup or before detaching the mechanism control board. When assembling the unit, remove the solder last.
Removing the mechanism control board (refer to Figures 6 - 7) o Remove the traverse unit. (Can be detached without detaching the T-mechanism unit.) 1. Remove the two screws at C fixing the mechanism control base from the bottom of the traverse unit. 2. Pull out the CN12 connector and detach the mechanism control board. 3. Remove the card wire from the CN13 connector on the mechanism control board. 4. Pull out the FPC holder from the CN12 connector on the reverse side of the mechanism control board and remove the flexible harness, referring to Figure 7.
B Figure 5
Traverse mechanism unit
CN12 Enlargement
C
CN13
Connection area
(Solder the flexible ground point)
Flexible harness
Mechanism control board
Figure 6
3
Flexible harness
Enlargement
2
FPC holder
1
CN12
Figure 7
Mechanism control board
1-14
TH-A10R/TH-A10
Removeing the turntable and spindle motor assemby (refer to Figures 8 - 9) o Remove the traverse mechanism unit. o Solder the flexible ground point on the optical pickup. (Figure 6) o Remove the mechanism control board. 1. Remove the flexible harness from the feed motor connector on the spindle motor board assembly. 2. Remove the three screws at D fixing the spindle motor from the bottom of the traverse chassis.
Traverse chassis
Removing the feed motor unit (refer to Figure 9) o Remove the traverse mechanism unit. o Remove the mechanism control board. 1. Remove the FPC from the feed motor connector on the turntable spindle motor board. 2. Remove the two screws at E fixing the feed motor unit.
D Figure 8
Traverse mechanism unit
F Removing the optical pickup unit (refer to Figure 9) Guide shaft B o Remove the traverse mechanism unit. o Remove the mechanism control board. E o Remove the feed motor unit. 1. Remove the screw at F fixing the guide shaft holder at B, then simultaneously remove the guide shaft at B and the optical pickup unit. While doing so, slide the unit horizontally away from the guide shaft at A. E
Pick-up assembly
Guide shaft A
Feed motor assembly Flexible harness Turn table spindle motor unit Feed motor connector
Figure 9
1-15
TH-A10R/TH-A10
Removeing the loading mechanism parts (refer to Figures 10 - 11) o Remove the clamper base. Up-down cam o Remove the disk tray. 1. Turn the lever counterclockwise until it stops (position 1), while pushing the switch lever in the direction of the arrow and pushing up the pawl at A using a screwdriver. 2. Stretch the two pawls at B outward using a screwdriver and remove the chassis. 3. Turn the lever clockwise (position 2) to remove the up-down cam. Pawl B 4. Remove the pulley gear and the pulley gear belt after removing the screw at G fixing the pulley gear. 5. Pull out drive gear 2 then drive gear 1. G Removing the loading motor board (refer to Figures 11 - 12) o Remove the clamper base. o Remove the disk tray. 1. Remove the loading belt. 2. Remove the two screws at H fixing the loading motor. 3. Remove the screw at I and the three pawls at C fixing the loading motor base from the reverse side of the loading base.
(1)When detaching the chassis. chassis. Lever Loading base
1
2
Pawl A
Chassis
Pawl B
Switch lever (2)When detaching the up-down cam. Up-down cam
G
Up-down cam
Switch lever
G Figure 10
Drive gear 1 Drive gear 2
H
Loading motor unit
H G
Loading base Loading belt Pulley gear
Figure 11
Loading base Loading motor board
I
Pawl C
Figure 12
1-16
TH-A10R/TH-A10
Disassembly method
1. Remove the twelve screws A attaching the amplifier assembly on the back of the body. 2. Move the amplifier assembly backward and disconnect the harness from connector CN109 in the lower part of the amplifier assembly.
CN109
A
Amplifier assembly
A
A
Removing the heat sink cover and the amplifier cover (See Fig.2 and 3)
Prior to performing the following procedure, remove the amplifier assembly. 1. Pull out the volume knob. 2. Remove the four screws B attaching the heat sink cover. 3. Remove the twenty screws C and the one screw D attaching the amplifier cover.
Volume knob
A
Fig.1
B
Amplifier assembly
Heat sink cover Amplifier cover
Fig.2
B C
Amplifier assembly
C D C C
C
Amplifier cover
C
Fig.3
C
1-17
TH-A10R/TH-A10
Removing the front panel assembly (See Fig. 6 to 9)
Prior to performing the following procedure, remove the top cover, the rear cover and the side covers. 1. Disconnect the harness from connector CN802 on the main board on the upper side of the body. 2. Remove the two screws C on the upper side of the body. 3. Remove the three screws D on the bottom of the body. 4. Release the five joints c and detach the front panel assembly toward the front.
C Joint c
Joint c CN802 Front panel assembly
C
Fig.6
D
Front panel assembly Joint c D
Fig.7
Joint c
Joint c
Front panel assembly
Front panel assembly
Fig.9
1-18
Fig.8
TH-A10R/TH-A10
Removing the right and left corner covers (See Fig.10 and 11)
Prior to performing the following procedure, remove the top cover, the rear cover, the side covers and the front panel assembly. It is not necessary to remove the front panel assembly. 1. Move the left corner cover backward to release the three joint hooks d. 2. Remove the right corner cover in the same way.
Joint d Left corner cover Joints d
Fig.10
Removing the rear panel (See Fig.12 to 14)
Prior to performing the following procedure, remove the top cover and the rear cover. 1. Remove the eighteen screws E and the one screw F attaching the rear panel. 2. Release the two joints e on both sides of the body.
Joint d Joints d Right corner cover
Fig.11
E
E
E
Rear panel
E
E
F
E
Fig.12
E
Joint e
Joint e
Rear panel
Rear panel
Fig.12
Fig.12
1-19
TH-A10R/TH-A10
Removing the DVD servo control board (See Fig.15 to 17)
Prior to performing the following procedure, remcover and the right side cover.ove the top cover, the rear 1. Remove the three screws G and pull the DVD servo control board case upward. 2. Disconnect the harness from connector CN501 and CN503, and the card wire from CN101, CN103 and CN502 of the DVD servo control board on the underside of the DVD servo control board case.
Digital I / O board
Analog I / O board CN681 CN201
G
CN687
DVD servo control board (case)
3. Remove the four screws H attaching the DVD servo control board.
Fig.15
CN501
CN503
CN502
CN103 DVD servo control board case
CN101
Fig.16
H
DVD servo control board
H
H
DVD servo control board case
H
Fig.17
1-20
TH-A10R/TH-A10
Main Adjustment
Adjustment and confirmation matter (1) Auto adjustment method
If microprocessor (IC401, IC402, IC714, IC716) or DVD Prek-up is replaced, initialize the DVD player in the following matter: 1. Initialize the DVD player in the following matter: 1) Make sure that no disc is on the tray. 2) Insert the power pulag to the outret while pressing "PLAY" and "OPEN/CLOSE" button at the same time. FL Display indicate ; Region cord. 3) Press Enter button. And EEPROM initialize start. 4) When indicate "96kHz EEPROM" on the display , initialize finished. Note : During the EEPROM initialization the keys may not be operated. Press the "POWER" key to initiate the STAND-BY mode and the test mode will then be cancelled.
(2) Confirmation of DVD RF level
1.The oscilloscope is connected between "1"(RFOP) of CN104 and "2"(GND). 2.Reproduction of the test disc (VT-501) made by JVC. 3.It is confirmed that RF LEVEL is 350mVp-p 150mVp-p. 4.When there is disorder in the waveform road cuts etc, test disk is exchanged and measured. P12 P1 and and GND GND
(3) Confirmation of CD jitter level and RF level
1. The CD jitter meter is connected between "11"(GND) of CN104 and "12"(FLTOUT). The RF level is observed at the same time. 2.The first test disk(CTS-1000) made of JVC is reproduced. 3.It is confirmed that RF LEVEL is 360 100mVp-p. 5. When there is disorder in the waveform road cuts etc, test disk is exchanged and measured.
DVD SERVO CONTROL PWB
FRONT SIDE
1-21
TH-A10R/TH-A10
(4) Flap adjustment of the Pick-up guide shaft
1) Make sure that there is no disc on the tray. 2) Press both the "PLAY" and "OPEN/CLOSE" keys of the main unit to activate the primary power and ( ; Version3, ; Region cord) will be displayed on the FL indicator. Note: If the FL indicator display stops and remains at "TEST 0", unplug the power cord from the outlet and after waiting at least 1 second, plug it in again. After the tray open/close procedure has completed, unplug it again and then perform the initialization procedure again. 3) Press the "OPEN/CLOSE" key of the main unit to draw the tray out. *Place the test disk (VT-501) on the tray and then press the "OPEN/CLOSE" key. (Note: Pushing the tray to close it is not possible.) 4) Press the "PLAY" key of the main unit. 5) The "JIT 0000" is displayed on the FL indicator. Set the FL indicator figure value to its minimum by adjusting the pickup guide shaft flap. * The test mode is cancelled when the power is turned off.
Measurement
Adjustment point Refer to Fig.2
Mode
Reproduction part
Disc VT-501
CN101 of DVD Servo Control PWB
Measurement machine
connections Refer to Fig.1
Extension cord No.
No need
QUQ110-3740AM
General tool : Hex-head wrench (1.27 mm)
"Flap adjustment" of the Pick-up guide shaft adjusts "Tangential adjustment machine screw" A and "Tilt adjustment machine screw" B from the DVD Mechanism A'ssy bottom. 1. The part at the center on the DVD test disc is reproduced. 2.The flap adjustment screws is turned alternately and adjusted like clearly seeing the waveform of CN104"1" to the way. Note 1.The tangential adjustment is done finish and, then, tilt is adjusted. 2.The repeat the adjustment 2-3 times,for best result. 3.The final adjustment should be tilt adjustment.
DVD player
Extension Cord
DVD Mechanism A'ssy
Stand
CN11 of Connection PWB
Stand
200mm
Fig.1
1-22
TH-A10R/TH-A10
Confirmation after adjustment. Confirm to reproduce video CD and CD after the DVD test disc is adjusted and to find abnormality.
A B A
Fig.2
(5) About keeping the disc
As for the DVD test disc, plane accuracy is demanded.Please note the keeping place on the disc. 1. Please do not put the disc directly on the work desk etc. after uses . 2. To keep the planarity of the disc, politely handle ,and please put in a special case and keep the disc vertically after uses . Please keep keeping the disc in a cool place where direct sunshine and the air-conditioning wind do not drive. 3. When the disc curves,an accurate adjustment cannot be done. Please exchange for a new test disc and adjust optics. 4. Other discs might not be able to be reproduced when adjusting on a curved disc. Point of adjustment * Please execute the static electricity protection measures before starting the adjustment. * When the following parts are exchanged,optical adjustment "Adjust the flap of the disc motor" is necessary. 1.The disc motor was exchanged. 2.The laser pick up was exchanged. 3.The traverse motor unit was exchanged. Note Additionally, please adjust the flap of the disc motor when the picture quality deterioration is seen .The basic adjustment though, is unnecessary for part exchange in the traverse. An optical adjustment in the laser pick up cannot be done. Please adjust the flap of the disc motor after exchanging the laser pick up. * When the traverse unit is exchanged, the adjustment is basically unnecessary.
1-23
TH-A10R/TH-A10
Precautions for Service
Handling of Traverse Unit and Laser Pickup
1. Do not touch any peripheral element of the pickup or the actuator. 2. The traverse unit and the pickup are precision devices and therefore must not be subjected to strong shock. 3. Do not use a tester to examine the laser diode. (The diode can easily be destroyed by the internal power supply of the tester.) 4. To replace the traverse unit, pull out the metal short pin for protection from charging. 5. When replacing the pickup, after mounting a new pickup, remove the solder on the short land which is provided at the center of the flexible wire to open the circuit. 6. Half-fixed resistors for laser power adjustment are adjusted in pairs at shipment to match the characteristics of the optical block. Do not change the setting of these half-fixed resistors for laser power adjustment.
Destruction of Traverse Unit and Laser Pickup by Static Electricity
Laser diodes are easily destroyed by static electricity charged on clothing or the human body. Before repairing peripheral elements of the traverse unit or pickup, be sure to take the following electrostatic protection: 1. Wear an antistatic wrist wrap. 2. With a conductive sheet or a steel plate on the workbench on which the traverse unit or the pick up is to be repaired, ground the sheet or the plate. 3. After removing the flexible wire from the connector (CN101), short-circuit the flexible wire by the metal clip. 4. Short-circuit the laser diode by soldering the land which is provided at the center of the flexible wire for the pickup. After completing the repair, remove the solder to open the circuit.
Short-circuit
1-24
TH-A10R/TH-A10
Discription of major IC's
AL4527 (IC601): A/D, D/A Converters
CDTO CDTI CCLK CS PIS XTO XTI AVSS AVDD VREFH VCOM 44 43 42 41 40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
1. Terminal layout
SDOS OCKS MIS BCLK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS
1 2 3 4 5 6 7 8 9 10 11
VREFL RIN+ RINLIN+ LINROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3
2. Block diagram
LIN+ LINRIN+ RIN-
ADC ADC
LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3
LPF LPF LPF LPF LPF LPF
DEM1 DEM0 MCKO DVDD DVSS PD XTS ICKS1 ICKS0 CAD1 CAD0
12 13 14 15 16 17 18 19 20 21 22
HPF HPF
Audio I/F
LRCK
DAC DAC DAC DAC DAC DAC
DATT DATT
BICK MCLK Format Converter DAUX
DATT DATT DATT DATT
SDOUT
SDOS SDTO SDTI1 SDIN1 SDIN2 SDIN3 SDTI2 SDTI3
1-25
TH-A10R/TH-A10
3. Pin function Pin No. Symbol SDOS 1 OCKS 2 MIS 3 BCLK 4 LRCK 5 SDTI1 6 SDTI2 7 SDTI3 8 SDTO 9 DAUX 10 DFS 11 DEM1 12 DEM0 13 MCKO 14 DVDD 15 DVSS 16 PD 17 XTS 18 ICKS1 19 ICKS0 20 CAD1 21 CAD0 22 LOUT3 23 ROUT3 24 LOUT2 25 ROUT2 26 LOUT1 27 ROUT1 28 LIN29 LIN+ 30 RIN31 RIN+ 32 VREF 33 VCOM 34 VREFH 35 AVDD 36 AVSS 37 XTI 38 XTO 39 PIS 40 41 42 43 44 CS CCLK CDTI CDTO
I/O I I I I I/O I I I O I I I I I I I I I I O O O O O O I I I I O O O I I I I I I I I/O I
Functions SDTO source select terminal L: Internal ADC output H: DAUX input Serial control mode select terminal L: 3-wire serial H: IC bus Soft mute terminal H: Starting Soft mute L: Cancel Audio serial data clock terminal Input channel clock terminal DAC1 audio serial data input terminal DAC2 audio serial data input terminal DAC3 audio serial data input terminal Audio serial data output terminal Auxiliary audio serial data input terminal 2x sampling mode terminal L: Ordinal speed H: 2x speed De-emphasize 1 terminal De-emphasize 2 terminal Power terminal for output buffer 2.7 5.5 V Digital power supply terminal 4.5 5.5 V Digital ground terminal 0 V Power down & reset terminal L: Power is down and register is initialized. Input clock selection 2 terminals Input clock selection 1 terminals Input clock selection 0 terminals Chip address 1 terminal Chip address 0 terminal DAC3 L channel analog output terminal DAC3 R channel analog output terminal DAC2 L channel analog output terminal DAC2 R channel analog output terminal DAC1 L channel analog output terminal DAC1 R channel analog output terminal L channel analog reverse input terminal L channel analog non-reverse input terminal R channel analog reverse input terminal R channel analog non-reverse input terminal Zero input detection terminal L: P/S = H COMMON voltage output terminal Reference voltage input terminal Analog power supply terminal 4.5 5.5 V Analog ground terminal 0 V Zero input detection terminal L: P/S = H Master clock input terminal Parallel/serial select terminal L: Serial control mode H: Parallel control mode Audio data interface format 0 terminal (with parallel control mode) Chip select terminal (with 3-wire serial control mode) Audio data interface format 0 terminal (with parallel control mode) Control data clock terminal (with serial control mode) Loopback mode 0 terminal (with parallel control mode) Control data input terminal (with serial control mode) Loopback mode 1 terminal
1-26
TH-A10R/TH-A10 AK93C65AF-X (IC403) : EEPROM
1.Terminal layout
PE
1
8
NC
VCC
2
7
GND
CS
3
6
DO
SK
4 8 PIN SOP
5
DI
2.Block diagram
DO
DATA REGISTER 16 16
DI
INSTRUCTION REGISTER
R/W AMPS AND AUTO ERASE
INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION
EEPROM 4096bit 256 x 16
ADD. BUFFERS
DECODER
CS VPP SW SK
PE VREF
VPP GENERATOR
3.Pin function Pin no. 1 2 3 4 5 6 7 8 Symbol PE VCC CS SK DI DO GND NC Function Program enable (With built-in pull-up resistor) Power supply Chip selection Cereal clock input Cereal data input Cereal data output Ground No connection (VCC=5V)
NOTE : The pull-up resistor of the PE pin is about 2.5M
1-27
TH-A10R/TH-A10
AN8706FHQ (IC101) : Front end processor
1.Pin layout
CBDOSL CSAG DCAGC AGCG PEAK BOTTOM RFENV FC BOOST OFTR BDO JITOUT GND3 FUPDN ITDLI VCOIN PLFLT PLFLT2 FCPO PCPO VCC3 CAPA DTRD IDGT VCC5
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
CBDOFS RBCA TESTSG RFINP RFINN VCC2 GND2 VREF2 COFTFS COFTSL RFON RFOP TS DCRF FS VIN6 VIN5 VCC1 VIN1 VIN2 VIN3 VIN4 VREF4 DIFP DIFN
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
AN8706FHQ
RDCKP RDCKN RDTP RDTN GND5 GND4 VCC4 DTMONN DTMONP DSLFLT DSLO FLTOUT DCFLT VREF3 VPWBDO VPWOFT IDDLY DBAL GND1 VREF1 TKCNT TKCFLT TEOUT TEI RSCL
2.Block diagram
FE FBAL RFOUT FS/TS TBAL TKCNT TE TG FC/Boost AGC Cont RFIN RFENVDFLTOP/N
LDONB LDONA LPCOA LPC1 VHARF TGBAL POFLT PTH TBAL TG FGCTL FBAL FEOUT FEN VREFL VREFC VREFH PULIN SEN SCK STDI STNBY XTRON MTRON ROMRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TKCNT
Head Amp. SSD Signal
RF ENV
JITTER Det
FE(SSD) FE BAL AGC EQ DSL BDO Det
JITOUT CLK DATA
PLL SYNC
MU
DSLOUT BDO OFTR
Head Amp. DPD Signal
TE(DPD) TE BAL TG(DPD)
OFTR Det
I N T E R FA C E LPC(Amp) VREF reg
OPTICAL HEAD (650nm)
TGBAL
SERVO PROCESSOR Head Amp.
CPU
STNBY MTRON
1-28
TH-A10R/TH-A10
3.Pin function
AN8706FHQ (1/2)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Symbol LDONB LDONA LPCOA LPC1 VHARF TGBAL POFLT PTH TBAL TG FGCTL FBAL FEOUT FEN VREFL VREFC VREFH PULIN SEN SCK STDI STNBY XTRON MTRON ROMRAM RSCL TEI TEOUT TKCFLT TKCNT VREF1 GND1 DBAL IDDLY VPWOFT VPWBDO VREF3 DCFLT FLTOUT DSLO DSLFLT DTMONP DTMONN VCC4 GND4 GND5 RDTN RDTP RDCKN RDCKP
I/O I I O I O I O I I O I I O I O O O I I I I I I I I O I O O O O O I I I I O O O O O O O I O O O O O O
Functions Laser ON (CD Head) terminal Laser ON (DVD Head) terminal Laser drive output terminal Laser PIN input terminal VHALF voltage output terminal Tangential phase balance control terminal Track detection Threshold value level terminal Track detection Threshold value level terminal Tracking balance control terminal Tangential phase error signal output terminal Focus amplifier Gain control terminal Focus balance control terminal Focus error signal output terminal Focus error output amplifier reversing input terminal VREFL voltage output terminal VREFC voltage output terminal VREFH voltage output terminal DSL,PLL drawing mode switch terminal SEN(Cereal data input terminal) SCK(Cereal data input terminal) STDI(Cereal data input terminal) Standby mode control terminal Tracking OFF holding input terminal Monitor output ON/OFF switch terminal ROM . RAM switch terminal Standard current source terminal Tracking error output Amp reversing input terminal Tracking error signal output terminal Track count detection filter terminal Track count output terminal VREF1 voltage output terminal Earth terminal 1 Data slice offset adjustment terminal Data slice delay adjustment terminal OFTR detection level setting terminal BDO detection level setting terminal VREF3 voltage output terminal Capacity connection terminal for data slice input filter Filter amplifier output terminal Data slice single data output terminal Constant filter terminal when data is sliceddelly PLL differential motion 2 making to value edge signal moniter output (+) PLL differential motion 2 making to value edge signal moniter output (-) Power terminal 4 (5V) Earth terminal 4 Earth terminal 5 PLL differential motion making to synchronization RF signal reversing output PLL differential motion making to synchronization RF signal rotation output PLL differential motion making synchronization clock reversing output PLL differential motion making synchronization clock rotation output
1-29
TH-A10R/TH-A10
AN8706FHQ(2/2)
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol VCC5 IDGT DTRD CAPA VCC3 PCPO FCPO PLFLT2 PLFLT VCOIN ITDLI FUPDN GND3 JITOUT BDO OFTR BOOST FC RFENV BOTTOM PEAK AGCG DCAGC CSAG CBDOSL CBDOFS RBCA TESTSG RFINP RFINN VCC2 GND2 VREF2 COFTFS COFTFL RFON RFOP TS DCRF FS VIN6 VIN5 VCC1 VIN1 VIN2 VIN3 VIN4 VREF4 DIFP DIFN
I/O I I I I I O O O O I O I O O O O I I O O O O O O O O O I I I I O O O O O O O O O I I I I I I I O O O
Functions Power terminal 5 (3.3V) Data slice part address part gate signal input terminal (For RAM) Data slice data read signal input terminal(For RAM) Data slice CAPA(Address)signal input terminal (For RAM) Power terminal 3 (5V) PLL phase gain set terminal PLL frequency gain set terminal PLL low region filter terminal PLL high region filter terminal PLL VCO input terminal PLL jitter free current ripple removal filter terminal PLL frequency control input terminal Earth terminal 3 Detection signal output of jitter BDO output terminal OFTR output terminal Booth control terminal for filter FC control terminal for filter RF enve output terminal Bottom enve detection filter terminal Peak enve detection filter terminal AGC amplifier gain control terminal AGC amp filter terminal Sag cancellation circuit filter terminal BDO detection capacitor terminal BDO detection capacitor terminal BCA detection level setting terminal TEST signal input terminal RF signal positive moving input terminal RF signal reversing input terminal Power terminal 2 (5V) Earth terminal 2 VREF2 voltage output terminal OFTR detection capacitor terminal OFTR detection capacitor terminal RF signal output terminal P RF signal output terminal N All addition amplifier (DVD) output terminal All addition amplifier capacitor terminal All addition amplifier (CD) output terminal Focus input of external division into two terminal Focus input of external division into two terminal Power terminal 1 (5V) External division into four (DVD/CD) RF input terminal 1 External division into four (DVD/CD) RF input terminal 2 External division into four (DVD/CD) RF input terminal 3 External division into four (DVD/CD) RF input terminal 4 VREF4 voltage output terminal RF signal (RAM) output terminal P RF signal (RAM) output terminal N
1-30
TH-A10R/TH-A10
BA5983FM (IC271) : 4CH DRIVER
1.Block Diagram
28
27
26
25
24
23
22
21
20
19
Vcc
18
17
10k
16
10k
15
Vcc
STAND BY CH4
10k 10k 10k 10k 10k 10k
10k
20k Level Shift
10k
20k Level Shift
10k 10k 10k 10k 10k 10k STAND BY CH1/2/3 Vcc 10k 10k 10k 10k Level Shift
Level Shift
10k
10k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2.Pin Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol BLAS IN OPIN1(+) OPIN1(-) OPOUT1 OPIN2(+) OPIN2(-) OPOUT2 GND STBY1 PowVcc1 VO2(-) VO2(+) VO1(-) VO1(+) I/O I I I O I I O I O O O O Function Input for Bias-amplifier Non inverting input for CH1 OP-AMP Inverting input for CH1 OP-AMP Output for CH1 OP-AMP Non inverting input for CH2 OP-AMP Inverting input for CH2 OP-AMP Output for CH2 OP-AMP Substrate ground Input for CH1/2/3 stand by control Vcc for CH1/2 power block Inverted output of CH2 Non inverted outpur of CH2 Inverted output of CH1 Non inverted outpur of CH1 Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol VO4(+) VO4(-) VO3(+) VO3(-) PowVcc2 STBY2 GND OPOUT3 OPIN3(-) OPIN3(+) OPOUT4 OPIN4(-) OPIN4(+) PreVcc I/O O O O O I O I I O I I Function Non inverted output of CH4 Inverted output of CH4 Non inverted output of CH3 Inverted output of CH3 Vcc for CH3/4 power block Input for Ch4 stand by control Substrate ground Output for CH3 OP-AMP Inverting input for CH3 OP-AMP Non inverting input for CH3 OP-AMP Output for CH4 OP-AMP Inverting input for CH4 OP-AMP Non inverting input for CH4 OP-AMP Vcc for pre block
1-31
TH-A10R/TH-A10
JCE8011(IC551):GRAPHIC CONTROLLER
Pin No. 1~8 9 10 11 12 13 14 15 16~23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39~46 47 48 49 50 51 52 53 54~61 62 63~70 71 72 73~82 83 84~93 94 95 96 97 98 99 100 Symbol VD0~7 VCLKI HSYNCI VSYNCI VCC VCLKD HSYNCO VSYNCO DOUT0~7 TEST RESETB GND NTB DTSF0 DTSFI VIDEG DOSF0 DOSF1 XVRST F1 HBL VBL VOEDG VCC FRD7~0 GND FRCK FWCK FREB FWEB FRRSTB FWRSTB FWD7~0 VCC CHD7~0 GND CHOEB CHA19~10 VCC CHA9~0 GND ACK CS1B CS2B SCK RXD TXD I/O I I I I O O O O I I I I I I I O O O O I I O O O O O O O I O O O O I I I I O Function DVD Image signal input (Multi plex data Y,Cr,Cb) Dot clock signal input (27MHz) The horizontal synchronous signal input Vertical synchronous signal input Power supply Dot clock signal output (27MHz) 'H' blanking output 'V' blanking output Digital data output Test terminal (Uses as GND usually) System reset signal Connect to GND Mode switching NTSC(low) / PAL(high) Taking timing shift of VD input Taking timing shift of VD input Taking edge specification of VD input (0:up , 1:down) Timing shift input of output data Timing shift input of output data Non connect Field Identification signal output 'H' blanking output 'V' blanking output Output timing setting of DOUT (0:up , 1:down) Power supply Field memory read data input Connect to GND Field memory read clock Field memory write clock Field memory read enable Field memory write enable Field memory read address reset Field memory write address reset Field memory write data output Power supply Character ROM data Connect to GND Character ROM output enable Character ROM address output Power supply Character ROM address output Connect to GND Serial data chip select for graphic control Serial data chip select for encoder control Serial clock input Serial input data Serial output data
1-32
TH-A10R/TH-A10
MC44724AVFU(IC554):VIDEO ENCODER
EXT
1.Terminal Layout
64 ~ 1 49 48
2.Block Diagrams
ChipA DVdd DVdd DVss DVss DVIN[7:0] TP[8:1] TVIN TP[0]IN
H.V 0
Y cb
CVBS/Cb/B2Vdd
F/Vsync
Hsync
C/Cr/R2Vdd
Y/G2Vdd
Sync_ generator
CGMS, wss gen
Copy, protection
bus
CCwss gen
0
off_set
16 17 ~ 32
33
DEMAX
+
0
0 Modulator
0
RGB matrix Clock Reset PAL/NTSC
12C / SPI
TEST
BIAS
DAC
0
DAC
0
DAC
sub carrier gen
BIAS
cr
Output Selector
0
DAC
DAC
+
Y/G1Vdd CVBS/Cb/B1Vdd C/Cr/R1Vdd Y/G1 Y/G1 CVBS/Cb/B1 CVBS/Cb/B1 C/Cr/R1 C/Cr/R1 Vref1 iBIAS1 Y/G2 Y/G2 CVBS/Cb/B2 CVBS/Cb/B2 C/Cr/R2 C/Cr/R2 Vref2 Ibias DAVdd DAVss
0
DAC
~
SDA/SI
SCL/SCK
3.Pin function
No. Symbol
CVBS/Cb/B1 CVBS/Cb/B1 CVBS/Cb/B1Vdd Y/G1 Y/G1 Y/G1/Vdd C/Cr/R1 C/Cr/R1 C/Cr/R1Vdd
I/O
O O O O O O O O -
Function Analog composite drive signal (+) Analog composite drive signal (-) Power supply for CVBS/Cb/B DAC1 Analog brightness signal/G drive signal (+) Analog brightness signal/G drive signal (-) Power supply for Y/G DAC Analog chroma signal (+) Analog chroma signal (-) Power supply for C/Cr/RDAC Connect to ground for DAC Standard BIAS for DAC1 Standard voltage for DAC1 Power supply for DAC Standard voltage for DAC2 Standard BIAS for DAC2 Non connect Analog composite drive signal (+) Analog composite drive signal (-) Power supply for CVBS/Cb/B DAC2 Analog brightness signal/G drive signal (+) Analog brightness signal/G drive signal (-) Power supply for Y/G DAC Analog chroma signal (+) Analog chroma signal (-) Power supply for C/Cr/RDAC2 Chip address selection Connect to test pin Digital ground Clock signal input (27MHz) Power supply for digital circuit Reset signal input L:ON Selection NTSC/PAL NTSC:L PAL:H
No.
Symbol
SO SDA/SI SCL/SCK SEL DVdd DVss DVIN7 DVIN6 DVIN5 DVIN4 DVIN3 DVIN2 DVIN1 DVIN0 TVIN EXT F/Vsyac Chsyac DATST TP-8 TP7 TP6 TP5 DVss DVdd TP4 TP3 TP2 TP1 TP0 DLVdd DLVss
I/O
I I I --Non connect
DLVdd
DLVss
SO
SEL
TEST
~
Function SPI Mode : Serial data input Serial clock input
Power supply for serial data,chip select,digital
1 2 3 4 5 6 7 8 9
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Power supply for digital circuit Digital ground
I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I
VIDEO mote on Reset(0:nomal, 1:mute)
10 DAVss 11 TBIAS1 12 Vref1 13 DAVdd 14 Vref2 15 TBIAS2 16 NC 17 CVBS/Cb/B2
I/O Frame output / VBI information input I/O Frame / Vertical, synchronous I/O I/O The horizontal, synchronous I/O I
Data input
O 18 CVBS/Cb/B2 O 19 CVBS/Cb/B2Vdd 20 Y/G2 O 21 Y/G2 22 Y/GVdd 23 C/Cr/R2 24 C/Cr/R2 25 C/Cr/R2Vdd 26 ChipA 27 TEST 28 DVdd 29 CLOCK 30 DVss 31 Reset 32 PAL/NTSC O O O I I I I
I/O Multiplex data input I/O Multiplex data input I/O Multiplex data input I/O Multiplex data input Ground for digital circuit Power supply for digital circuit
I/O Data input / Test data I/O I/O Data input / Test data I/O I/O Data input / Test data I/O I/O Data input / Test data I/O I/O Data input / Test data I/O Power supply for D/A converter Ground for D/A converter
1-33
TH-A10R/TH-A10
MN101C12G (IC701): System micom
1.Terminal layout 100 ~ 76
1 25
75 51
2.Pin function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Symbol GND CS0 CS1 CS2 NTSEL POWER SW SHUT1 KEY1-5 KEY6-10 VREF VDD OSC2 OSC1 VSS MMOD OSDCS3 RSTE OSDDO S2UDT U2SDT SCLK BUSY CPURST REQ REMO CS3 TEST TEST TEST NC RESET NC NC VDD OSDCK NT I/O I I I I I I I I O I I O I O O O O I O O O I I I I I I I I O O O O Function GND A set bit0 (It is effective in the U.E version) A set bit1 (It is effective in the U.E version) A set bit2 (It is effective in the U.E version) NTSC/PAL switch SW input Power key input JOG shuttle inout (AD) 10 Key input (1~5) 10 Key input (6~10, +10) +B (Apply 5V) +B (Apply 5V) 10MHz OSC 10MHz OSC GND Unused, Connects with GND Unused Connects with GND VENCODER chip selection V.ENCOSER reset V.ENCODER communication DATA Communication between unit microcomputers DATA OUT Communication between unit microcomputers DATA IN Communication between unit microcomputers CLK Communication between unit microcomputers BUSY Unit microcomputer reset Communication between unit microcomputers REQ Remote control interruption Set password change judgment bit(H:Change, L:Usual) H:Checkers mode, L:Normal mode H:Running mode, L:Normal mode Un used Reset input Un uesd Un used Un used V.ENCODER communication CK
~
26 ~ 50
~
1-34
TH-A10R/TH-A10
MN101C12G (2/2)
Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66~76 77 78 79 80 81~85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol FS2 CHREQ CHST CHDATAIO NC CHCK FLDATAO FLDATAI FLCK FLCS FLRST EEDO EEDI EECK EECS VS1 VS3 DMUT1 DMUT2 PDB2 PDB2 DEMP2 DEMP1 DENA KARAOKE POWERON VS2 NC AVCI AVCO NC STANBYIND NC CS4 MA MB M1M3 MD MC GAIN2 GAIN1 HPMUT DAVSS LMUTE CMUTE SMUTE MUTE DAVDD
I/O O I O O O O I O O O O I O O O O O O O O I O O O O O O O O O O O O O O O -
Function 48kHz, 96kHz switch Changer communication REQUEST Changer communication STROBE Changer communication DATAI/O Changer communication CLOCK FL driver communication DATAO FL driver communication DATAI FL driver communication CLOCK FL driver communication CS FL reset output EEPROM communication DATAO EEPROM communication DATAI EEPROM communication CLOCK EEPROM communication CS S1 control S3 control(STBY:H, P.ON:L) Un used Un used Un used Un used Un used Un used Un used KARAOKE gain control(At KARAOKE : H) Power ON output S2 control Un used AV COMPULINK input AV COMPULINK output Un used Standby LED output Un used Un used DAC control MA DAC control MB DAC control M1M3 DAC control MD DAC control MC Un used Un used Un used Un used Un used Un used Un used Front mute output Apply 5V
1-35
TH-A10R/TH-A10
MN101C15FDD (IC401) : System controler
1. Terminal layout 80~61 1 20 21~40 2. Pin function Pin Symbol No 1 DVD-S/C 2 VCR-S/C 3 4 5 6 7 8 9 PROTECTOR IN VREF+ 10 VDD 11 OSC 2 12 OSC 1 13 VSS 14 X1 15 X0 16 MMOD 17 18 19 20 21 DSP-COMMAND DSP-STATUS 22 DSP-CLK 23 24 RESET-IN 25 TUNER-CE 26 TUNER-CLK 27 28 TUNER-DATA 29 RDS SCL 30 TUNER-IN 31 STEREO-IN 32 RDS-ST 33 M-BUSY 34 RDSCLOCKIN 35 36 37 38 VIDEO1 39 VIDEO2 40 60 41
Function
Ground connection DVD S/C selection terminal VCR S/C selection terminal Ground connection Ground connection Ground connection Ground connection Ground connection Protector input Ground connection Power supply terminal Quartz oscillation terminal (8 MHz) Quartz oscillation terminal (8 MHz) Ground connection Ground connection Terminal (unused) Ground connection Terminal (unused) Ground connection Ground connection DSP control signal terminal DSP control signal terminal DSP control signal terminal Ground connection Reset signal input terminal Tuner chip enable Tuner clock signal input Ground connection Tuner control terminal Clock signal (RDS) Tuner signal input terminal Stereo signal input terminal Terminal (unused) Busy signal from IC400 input Ground connection Terminal (unused) Terminal (unused) Terminal (unused) VIDEO 1 signal VIDEO 2 signal
Pin No
Symbol
S-MUTE T-MUTE
Function
System mute Terminal (unused) Tuner mute Terminal (unused) Terminal (unused) Terminal (unused)
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
RDS-DATA INHIBIT IN DSP-READY DSP-RESET M/CS M-RESET M-STATUS M-COMMAND M-CLK
RDS control signal terminal Terminal (unused) Inhibit signal input DSP control signal DSP reset signal Control signal from IC400 Reset signal from IC400 Status signal from IC400 Command signal from IC400 Clock signal from IC400 Terminal (unused) Terminal (unused) Terminal (unused) Terminal (unused) Data signal for source selector Clock signal for source selector Strop signal for controlling volume Data signal for controlling volume Clock signal for controlling volume Strop signal for source selector Terminal (unused) Sub woofer mute Terminal (unused) Front speaker relay control Center speaker relay control Rear speaker relay control Terminal (unused) Ground connection Ground connection Ground connection Ground connection Terminal (unused) Indicate control (DIGITAL AUTO) Indicate control (SURROUND)
SW-DATA SW-CLK VOL-STB VOL-DATA VOL-CLK SW-STB SWF MUTE SURR FR-RELAY CNTR-RELAY SUR-RELAY
LED D.AUT LED SURR LED
1-36
TH-A10R/TH-A10
MN102L25GCY(IC401):UNIT CPU
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Symbol WAIT RE MUTE WEM CS0 CS1 CS2 CS3 FGCONT /SPKICK LSIRST WORD A0 A1 A2 A3 VDD SYSCLK VSS XI XO VDD OSCI OSCO MODE A4 A5 A6 A7 A8 A9 A10 A11 VDD A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 TXSEL TMPSN ADPD TRVSW
I/O I O O O O O O O O O O O O O O O O I I O O O O O O O O O O O O O O O O O O O O I
Function Symbol Pin No. Micon wait signal input 51 FGIN Read enable 52 Driver mute 53 ADSCEN Write enable 54 VDD Non connect 55 FEPEN Chip select for ODC 56 SLEEP Chip select for ZIVA 57 BUSY Chip select for outer ROM 58 REQ Photo control 59 CIRCEN Spin kick 60 HSSEEK LSI reset 61 VSS Bus selection input 62 EPCS Address bus 0 for CPU 63 EPSK Address bus 1 for CPU 64 DPDI Address bus 2 for CPU 65 EPDO Address bus 3 for CPU 66 VDD Power supply 67 SCLK0 System clock signal output 68 S2UDT Power supply 69 U2SDT Non connect 70 CPSCK Non connect 71 SDIN Power supply 72 SDOUT Clock signal input(13.5MHz) 73 Non connect 74 CPU Mode selection input 75 NMI Address bus 4 for CPU 76 ADSCIRQ Address bus 5 for CPU 77 ODCIRQ Address bus 6 for CPU 78 DECIRQ Address bus 7 for CPU 79 WAKEUP Address bus 8 for CPU 80 ODCIRQ2 Address bus 9 for CPU 81 ADSEP Address bus 10 for CPU 82 RST Address bus 11 for CPU 83 VDD Power supply 84 TEST1 Address bus 12 for CPU 85 TEST2 Address bus 13 for CPU 86 TEST3 Address bus 14 for CPU 87 TEST4 Address bus 15 for CPU 88 TEST5 Address bus 16 for CPU 89 TEST6 Address bus 17 for CPU 90 TEST7 Address bus 18 for CPU 91 TEST8 Address bus 19 for CPU 92 VSS Power supply 93 D0 Address bus 20 for CPU 94 D1 TX Select 95 D2 Non connect 96 D3 Non connect 97 D4 AD Power down 98 D5 Non connect 99 D6 Detection switch of traverse 100 D7 inside
I/O I O O O I O O O O O I O I I O O I O I I I O I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O
Function Photo input Non connect Serial enable signal for ADSC Non connect Serial enable signal for FEP Standby signal for FEP Communication busy Communication Request CIRC command select Seek select Power supply EEPROM chip select EEPROM clock EEPROM data input EEPROM data output Power supply Communication clock Communication input data Communication output data Clock for ADSC serial ADSC serial data input ADSC serial data output Non connect Non connect Non connect Interrupt input of ADSC Interrupt input of ODC Interrupt input of ZIVA Non connect Non connect Address data selection input Reset input Power supply Test signal 1 input Test signal 2 input Test signal 3 input Test signal 4 input Test signal 5 input Test signal 6 input Test signal 7 input Test signal 8 input Power supply Data bus 0 of CPU Data bus 1 of CPU Data bus 2 of CPU Data bus 3 of CPU Data bus 4 of CPU Data bus 5 of CPU Data bus 6 of CPU Data bus 7 of CPU
1-37
TH-A10R/TH-A10 MN103007BGA (IC301) : Optical disc controller
1.Terminal layout
DMARQ NIOWR VSS NIORD IORDY NDMACK 5VDD INTRQ IOCS16 DA1 VSS NPDIAG DA0 DA2 VDD NCS1FX NCS3FX NDASP NTRYCL 5VDD NEJECT VSS MONI0 MONI1 MONI2 MONI3 SDATA SCLOCK VDD FAT0 DAT1 DAT2 DAT3 CHCK4 XCLDCK SUBC HDD15 HDD0 HDD14 5VDD HDD1 HDD13 HDD2 VSS HDD12 VDD HDD3 HDD11 HDD4 HDD10 5VDD HDD5 HDD9 VSS HDD6 HDD8 HDD7 5VDD NRESET MASTER NINT0 NINT1 WAITOOC NMRST DASPST VDD OSCO2 OSCI2 UATASEL VSS PVSSDRAM PVDDDAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MN103007BGA
SBCK VSS P0 P1 PVDD PVSS VDD OSC01 OSCI1 VSS LRCK BLKCK IPFLAG DACCLK DACLRCK DACDATA NTRON LG JMPINH IDDHOLD PLLOK CLKOUT2 VDD NRST MMOD VSS CPDET1 CPDET2 BDO IDGT DTRO TEHLD VDD CLKOUT1 CPUDT0 CPUDT1
2.Block diagram
DVD-ROM Formatter
CPUNDA17 CPUADR16 VSS CPUASR15 CPUADR14 CPUADR13 CPUADR12 VDD CPUADR11 CPUADR10 CPUADR9 CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 VSS CPUADR0 NCS NWR NRD VDD CPUDT17 CPUDT16 PVPODRAM PTESTORAM OVDDDRAM PVSSDRAM CPUDT15 CPUDT14 CPUDT13 VSS CPUDT2
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Formatter i /t CD-PRE
ECC
Host i / f MPEG i / t
High speed IO bus
ATAPI
CGEN
Instruction memory (40KB) DATA MEMORY (6KB)
DMA
32 bit CPU core BCU GCAL
DRAMC
MODE
4Mbit DRAM
General purpose IO bus
WDT
16 bit timer x 2
SYSTEM i/f
INTC
1-38
TH-A10R/TH-A10
3.Function
MN103007BGA(1/2)
Pin NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Symbol
HDD15 HDD0 HDD14 5VDD HDD1 HDD13 HDD2 VSS HDD12 VDD HDD3 HDD11 HDD4 HDD10 5VDD HDD5 HDD9 VSS HDD6 HDD8 HDD7 5VDD NRESET MASTER NINT0 NINT1 WAITODC NMRST DASPST VDD OSCO2 OSCI2 UATASEL VSS PVSSDRAM PVDODRAM CPUADR17 CPUADR18 VSS CPUADR15 CPUADR14 CPUADR13 CPUADR12 VDD CPUADR11 CPUADR10 CPUADR9
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O O O O I I,O I,O I
Function
ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI reset ATAPI master / slave selection System control interruption 0 System control interruption 1 System control weight control System control reset DASP signal initializing VSS connection,OPEN VSS connection, OPEN VSS connection
Pin NO. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol
CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 VSS CPUADR0 NCS NWR NRD VDD CPUDT7 CPUDT6 PVPPDRAM PTESTDRAM OVDDDRAM PVSSDRAM CPUDT5 CPUDT4 CPUDT3 VSS CPUDT2 CPUDT1 CPUDT0 CLKOUT1 VDD TEHLD DTRO IDGT BDO CPDET2 CPDET1 VSS MMOD NRST VDD CLKOUT2 PLLOK IDOHOLD JMPINH
I/O I I I I I I I I I I I I
Function
System control address System control address System control address System control address System control address System control address System control address System control address GND System control address System control chip selection System control wright System control lead Apply 3V System control data System control data
O I
C=10000PF is connected between VSS VSS connected
System control data System control data System control data GND System control data
I/O I/O O O O O I I I I I O O O O
System control data System control data 16.9/11.2/8.45MHz clock Apply 3V Mirror gate Data part frequency control switch Part CAPA switch RF dropout / BCA data of making to binary Outer side CAPA detection Side of surroundings on inside GND VSS connected System reset Apply 3V 16.9MHz clock Frame mark detection ID gate for tracking holding Jump prohibition
I I I I I I I I I
System control address System control address System control address System control address System control address System control address System control address System control address System control address System control address
81 82 83 84 85 86 87 88 89 90
1-39
TH-A10R/TH-A10
MN103007BGA(2/2)
Pin NO. Symbol 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 LG NTRON DACDATA DACCLK IPFLAG BLKCK LRCK VSS OSCI1 OSCO1 VDD PVSS PVDD P1 P0 VSS SBCK SUBC XCLDCK CHCK4 DAT3 DAT2 DAT1 DAT0 VDD
I/O
O I O I I I I
Function
Land / group switch Tracking ON Cereal output L and R identification output Clock for cereal output Interpolation flag input Sub-code,Block clock input L and R identification signal output
Pin NO. Symbol 133 134 135 136 137 138 139 140 141 142 143 144
I/O
Function
NPDIAG I/O ATAPI slave master diagnosis input VSS DA1 IOCS16 INTRQ 5VDD NDMACK IORDY NIORD VSS NIOWR DMARQ I/O ATAPI host writes O ATAPI host DMA demand I O I ATAPI host DMA response ATAPI host ready output ATAPI host read I/O ATAPI host address O O ATAPI output of selection of width of host data bus ATAPI host interruption output
DACLRCK O
I,O 16.9MHz oscillation I,O 16.9MHz oscillation
I/O Terminal MASTER polarity switch input I/O CIRC-RAM OVER/UNDER Interruption signal input O I I I I I I I
Sub-code, Clock output for serial input
Sub-code, Cereal input Sub-code, Frame clock input Read clock to DAT3~0(Output of dividing frequency four from ADSC) Read data from DISC (PAralle output from ADSC)
SCLOCK I/O Debugging cereal clock (270 SDATA (270 pull up) pull up) I/O Debugging cereal data O I Internal goods title monitor Eject detection
119~122 MONI3~0
123 124 125 126 127 128 129 130 131 132
VSS NEJECT 5VDD NTRYCL NDASP NCS3FX NCS1FX VDD DA2 DA0 I/O ATAPI host address I/O ATAPI host address I Tray close detection I/O ATAPI Drive active/ Sulave connection I/O I I ATAPI host chip selection ATAPI host chip selection
1-40
TH-A10R/TH-A10
MN103007BGA(3/4)
Pin NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
Symbol LG NTRON DACDATA DACLRCK DACCLK IPFLAG BLKCK LRCK VSS OSCI1 OSCO1 VDD PVSS PVDD P1 P0 VSS SBCK SUBC XCLDCK CHCK4 DAT3 DAT2 DAT1 DAT0 VDD SCLOCK SDATA MONI3 MONI2 MONI1 MONI0 VSS NEJECT 5VDD NTRYCL NDASP NCS3FX NCS1FX VDD DA2 DA0
I/O O I O O I I I I I,O I,O
Function Land / group switch Tracking ON Cereal output L and R identification output Clock for cereal output Interpolation flag input Sub-code,Block clock input L and R identification signal output 16.9MHz oscillation 16.9MHz oscillation
I/O I/O
Terminal MASTER polarity switch input CIRC-RAM OVER/UNDER Interruption signal input Sub-code, Clock output for serial input Sub-code, Cereal input Sub-code, Frame clock input Read clock to DAT3~0 (Output of dividing frequency four from ADSC) Read data from DISC (PAralle output from ADSC)
O I I I I I I
I/O I/O O O O O I I I/O I I I/O I/O
Debugging cereal clock (270 pull up) Debugging cereal data (270 pull up) Internal goods title monitor
Eject detection Tray close detection ATAPI Drive active/ Sulave connection I/O ATAPI host chip selection ATAPI host chip selection ATAPI host address ATAPI host address 1-41
TH-A10R/TH-A10
MN103007BGA(4/4)
Pin NO. 133 134 135 136 137 138 139 140 141 142 143 144
Symbol NPDIAG VSS DA1 IOCS16 INTRQ 5VDD NDMACK IORDY NIORD VSS NIOWR DMARQ
I/O I/O I/O O O I O I I/O O
Function ATAPI slave master diagnosis input ATAPI host address ATAPI output of selection of width of host data bus ATAPI host interruption output ATAPI host DMA response ATAPI host ready output ATAPI host read ATAPI host writes ATAPI host DMA demand
1-42
TH-A10R/TH-A10 MN173222DF (IC400): Operation Switches and Fluorescent Display Controller
1. Key matrix
KEY OUT 0 KEY IN 0 KEY IN 1 KEY IN 2 KEY IN 3 POWER ADJUST SETTING MEMORY KEY OUT1 DSP MODE SURROUND ANALOG/DIGITAL KEY OUT 2 DVD TV SOUND/DBS VCR ONE TOUCH OP. /INPUT ATT. KEY OUT 3 KEY OUT 4 CD PHONE TAPE/MD FM/AM
2. Pin function Pin No. 1-22 23 24-29 30,31 32,33 34-36 37-39 40,41 42 44 45 46 47 48 49 50 51 52 53 54 55 56,57 58 59 60-63 64-67 68 69 70 71 72,73 74 75-84 Symbol S22-S1 VPP KO0-5/G14-9 G8,G7 SW0,1/G6,5 G4-G2 G16,15,1 JOG1,2 MBUSY MCLK COMMAND STATUS M/CS RM VCRI DCSI DCSO VCRO TVO TVC POWER STANDBY KI3-KI0 S36-S33 RST X1 X2 VSS OSC2,1 VDD S32-S23 I/O O O O O O O I I I I O I I I I O O O O O I O I Functions Segment control signal output Power supply terminal Key matrix output/grid control signal output Grid control signal output Grid control signal output Grid control signal output Grid control signal output Ground connection JOG volume control input Busy signal from IC401 Clock signal from IC401 Command data input from IC401 Status signal output to IC401 Chip select signal input from IC401 Remote control signal input AV COMPULINK input (VCR) COMPULINK signal input COMPULINK signal output AV COMPULINK output (VCR) AV COMPULINK output (TV) AV COMPULINK control output Ground connection Power supply terminal Stand-by indicator control Key matrix input Segment control signal output Reset signal input Ground connection Terminal (unused) Ground connection Quartz oscillation terminal (6 MHz) Power supply terminal Segment control signal output
O
1-43
TH-A10R/TH-A10 MN67705EA (IC201) : Digital servo controller
1.Terminal layout
FEPNTRON N.C. N.C. CDDVD N.C. N.C. N.C. ECR(PWM3B) EC(PWM3A) DVSS SYSCLK VCOF1 DVSS IREF1 XRESET TEST MINTEST FG DSLO TKCRS2 TKCRS1 OFTR DVDD TRSDRVB(DA8) TRSDRVA(DA7) TRDRV(DA6) FODRV(DA5) DBAL(DA4) BOOST(DA3) FC(DA2) FBAL(DA1) AVDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
2.Block diagram
The signal of the error of the servo input from FEP.
CPSEN CPCEN CPUIRQ CPUCLK CPUDTIN CPUDTOUT CHK4I SCLK+ SCLKSDAT+ SDATBDO SBC