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FM7B Hepburn Intel UMA VER : D3B
A
*FM7B M/B PCB
A
Penryn POWER
SYSTEM RESET CIRCUIT BATT CHARGER RUN POWER SW
+3.3V_SUS/+5V_SUS +5V/+3.3V/+1.8V
FAN & THERMAL
SMSC1423 PG 39
POWER
REGULATOR
+1.5V_RUN/+1.05V_VCCP
(478 Micro-FCPGA) PG 44 PG 46 PG 3,4 1066 MHz FSB LVDS PG 53
CPU VR PG 48 DC/DC
+3.3V_ALW/+5V_ALW/+15V_ALW
CLOCK
SLG8SP513V (QFN-64) PG 17
PG 51
REGULATOR
+1.8V_SUS/+1.25V_RUN /+0.9V_DDR_VTT
AC/BATT CONNECTOR PG 54
PG 49
PG 52
Panel Connector PG 26
Cantiga
B
SDVO
DDR2-SODIMM1
PG 15,16
667/800 MHZ DDR II
1329 uFCBGA VGA PG 5,6,7,8,9,10 USB2.0 x 4
PI3VDP411LSZDE
PG 18
HDMI
HDMI CONN.
PG 26
B
DDR2-SODIMM2
PG 15,16
667/800 MHZ DDR II
CRT CONN.
PG 27 RJ45/Magnetics PG 43
SATA-ODD
PG 36 SATA-HDD PG 36 E-SATA Combo with USB CONN PG 35
C
SATA
USB conn x 4
DMI interface
PCIEx1 PCIEx1 USB2.0
PG 35
LAN BCM5784M
PG 42
SATA
EXPRESS-CARD
R5538 MINI-CARD WLAN MINI-CARD WWAN MINI-CARD WPAN PG 30
PI2EQX3211BHE
SATA
ICH9-M
676 BGA
PG 35 IHDA USB2.0
Cantiga
PCIEx2 USB2.0 PCIEx1 USB2.0 USB2.0 Biometric PG 38 CIR TSOP36136TR PG 37
PG 34
C
AUDIO/AMP
92HD73C PG 40 Audio SPK conn PG 40 Audio Jacks x3 PG 41 Camera + D-MIC PG 41 LPC
PG 11,12,13,14
PG 33
PG 33
KBC
ITE8512 PG 31 SPI PS/2 Touchpad PG 37 18X8
1394 33MHz PCI
Keyboard PG 37
8-in-1 Card Reader
R5C833 PG 28
1394 CONN. Card Reader CONN.
PG 29 PG 30
D
D
USER INTERFACE PG 38
FLASH 2Mbyts
PG 32
Title Size Date:
1 2 3 4 5 6
QUANTA COMPUTER
Schematic Block Diagram1 Document Number FM7B Monday, July 21, 2008
7
Rev 1A Sheet 1
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Table of Contents PAGE
1 2 3-4 5-10
A
Power States POWER PLANE
+PWR_SRC +RTC_CELL +3.3V_ALW +5V_ALW +15V_ALW +3.3V_LAN +5V_SUS +3.3V_SUS +1.8V_SUS +0.9V_DDR_VTT +5V_RUN +3.3V_RUN +1.8V_RUN +1.5V_RUN +1.25V_RUN +1.05V_VCCP +VCC_CORE +LCDVCC +5V_MOD +5V_HDD +PBATT +SBATT
DESCRIPTION
Schematic Block Diagram Front Page Merom Crestline ICH8M DDRII SO-DIMM(200P) Clock Generator HDMI LCD Conn. & SSP CRT Conn SATA Conn CARD READER/Conn & 1394 Express Card & Smart Card Mini Card SIO (ITE8512) FLASH/RTC USB TP / KEYBOARD SWITCH /LED FAN & Thermal Audio CODEC(ALC888)/Phone Jack LOM / Switch System Reset Circuit Battery Selector & Charger 1.05VCCP / 1.5VRUJN DDR2_1.8VSUS, 0.9V CPU_ISL6266(2phase) MAX8744 (+5.5V,+3,3V) RUN Power Switch DCIN,Batt PAD& SCREW EMI CAP SMBUS BLOCK Power Block Dianram
VOLTAGE
10V~+19V +3.0V~+3.3V +3.3V +5V +15V +3.3V +5V +3.3V +1.8V +0.9V +5V +3.3V +1.8V +1.5V +1.25V +1.05V +0.7V~+1.77V +3.3V +5V +5V +10V~+17V +10V~+17V
PAGE
4,26,32,34,46,48,49,51,52,56 11,14,31,32 3,31,32,34,36,37,38,44,46,49,52,53,54 35,36,46,48,49,52,53,54,56 26,36,37,52,53 42,43 14,38,51,53 3,11,12,13,14,26,30,37,38,43,48,49,51,53 6,8,9,15,48,49,53 16,49,53 14,18,27,36,37,38,39,40,41,53 14,18,27,36,37,38,39,40,41,53 18,38,53 4,9,14,30,33,34,48,53,56 6,9,14,49,53 3,4,5,6,8,9,11,14,48,56 4,51,56 26 36 36
DESCRIPTION
MAIN POWER RTC 8051 POWER LCD/CHARGE POWER LARGE POWER LAN POWER SLP_S5# CTRLD POWER SLP_S5# CTRLD POWER SODIMM POWER SODIMM POWER SLP_S3# CTRLD POWER SLP_S3# CTRLD POWER SDVO POWER CALISTOGA/ICH8 POWER CALISTOGA/ICH8 POWER
CONTROL SIGNAL
ACTIVE IN
S0~S5 S0~S5
11-14 15-16 17 18 23 24 25 26-27 28 29-30 31 32 33 35 36
ALWON ALWON +5V_ALW AUX_ON SUS_ON 3.3V_SUS_ON DDR_ON 0.9V_DDR_VTT_ON RUN_ON 3.3V_RUN_ON RUN_ON 1.5V_RUN_ON 1.25V_RUN_ON
S0~S5 S0~S5 S0~S5
A
B
37 38-39 40-41 44 46 48 49 51 52 53 54 55 56 57 58
B
CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON CPU CORE POWER LCD Power Module Power HDD Power MAIN BATTERY SECOND BATTERY IMVP_VR_ON LCDVCC_TST_EN & ENVDD MODC_EN# HDDC_EN# CHG_PBATT CHG_SBATT
C
C
GND PLANE
8731AGND AGND_0.9V AGND_DC/DC AGND_DC2 AGND_DDR AGND_ISL6260 GND
PAGE
46 49 52 48 49 51 ALL
DESCRIPTION
D
D
Title Size Date:
1 2 3 4 5 6
QUANTA COMPUTER
Index & Power Status Document Number FM6B Monday, June 30, 2008
7
Rev 1A Sheet 2
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H_A#[3..16]
H_A#[3..16] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#[0..4] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35] H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 F6 D3 N5 M4 B2 AE8 D8 F8 D22 T2 V3 AA8 AC8 AA7
U23A A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# R43 1 D21 A24 B25 C7 56 2 R45 1 R78 H_IERR# 1 56 2 H_ADS# H_BNR# H_BPRI# 5 5 5
5
H_D#[0..63]
H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
U23B D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
H_D#[0..63]
H_D#[0..63]
5
A
IERR# INIT# LOCK#
+1.05V_VCCP H_INIT# 11 H_LOCK# 5 2
1
ADDR GROUP 0
6/27-50
+1.05V_VCCP
H_DEFER# 5 H_DRDY# 5 H_DBSY# 5 H_BR0# 5
DATA GRP 0
DATA GRP 2
close R44 *51/F_NC CPU.
Layout Note: Place R44 to
CONTROL
A
5 5
H_ADSTB#0 H_REQ#[0..4]
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
2 0 0603 H_RESET# H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5 H_HIT# H_HITM# 5 5
H_RESET# 5 5 5 5 5 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[0..63] H_D#[0..63]
H_DSTBN#2 5 H_DSTBP#2 5 H_DINV#2 5 H_D#[0..63] H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#[0..63] 5
5
H_A#[17..35]
Layout Note: Place voltage divider within 0.5" of GTLREF pin
+1.05V_VCCP ITP_DBRESET# 13 +1.05V_VCCP 2
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
ADDR GROUP 1
THERMAL
PROCHOT# THERMDA THERMDC
XDP/ITP SIGNALS
DATA GRP 1
DATA GRP 3
4/23-38
1 1
R386 1K/F
B
5
H_ADSTB#1
H_PROCHOT# H_THERMDA H_THERMDC H_THERM R80 56 1 2
5 5 5
H_DSTBN#1 H_DSTBP#1 H_DINV#1 R53 R52 2 2 1 *1K/F_NC 1 *1K/F_NC T87 T85 T84 T86 T4
H_DSTBN#3 5 H_DSTBP#3 5 H_DINV#3 5 COMP0 COMP1 COMP2 COMP3
PAD T5 H_THERMDA 39 H_THERMDC 39
B
11 H_A20M# 11 H_FERR# 11 H_IGNNE# 11 11 11 11 H_STPCLK# H_INTR H_NMI H_SMI#
A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI#
THERMTRIP#
R387 2K/F +1.05V_VCCP 2
H CLK
BCLK[0] BCLK[1] RSVD[06] A22 A21 D2
PAD PAD PAD PAD PAD
CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17 PAD T3
Quard Core Only
TDI_1/RSV TDO_2/RSV
6,17 CPU_MCH_BSEL0 6,17 CPU_MCH_BSEL1 6,17 CPU_MCH_BSEL2
V_CPU_GTLREF AD26 CPU_TEST1 C23 CPU_TEST2 D25 CPU_TEST3 C24 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26 CPU_TEST7 C3 B22 B23 C21
MISC COMP[1]
Note: H_DPRTSTP need to daisy chain from ICH9 to IMVP6 to CPU.
H_DPRSTP# 6,11,51 H_DPSLP# 11 H_DPWR# 5 H_PWRGOOD 11 H_CPUSLP# 5 H_PSI# 51
BMP_1#[0]/RSV BMP_1#[1]/RSV BMP_1#[2]/RSV BMP_1#[3]/VSS DCLKPH_1/VSS ACLKPH_1/VSS GTLREF_2/RSV THRMDA_1/RSV THRMDC_1/RSV HFPLL_1/VSS SPARE_1[4]/VSS BR1#/VCC Penryn Ball-out Rev 1a
2
ICH
Penryn Ball-out Rev 1a
C450 *2200P_NC H_THERMDA H_THERMDC 1 2 50 +1.05V_VCCP +3.3V_ALW
Voltage Level shift
R38 *2.2K_NC
FSB 533 667
BCLK 133 166 200 266
BSEL2 0 0 0 0
BSEL1 0 1 1 0
BSEL0 1 1 0 0
C
C
2
Populate ITP700Flex for bringup
+1.05V_VCCP
2/18-5
Layout Note: Place couple 0.1uF Decoupling caps with in 0.1" ITP connector.
H_PROCHOT#
1
1
3
CPU_PROCHOT#
800 1066
Q11 *2N7002W-7-F_NC
+3.3V_RUN
H_THERMTRIP# 6,52
R24 54.9/F
R21 54.9/F
R25 54.9/F JITP1
COMP0 COMP1 COMP2 COMP3 2 2 2 2 R27 54.9/F 1 R30 27.4/F
+1.05V_VCCP C390 2 VTT0 VTT1 VTAP 27 28 26 C393 2 *0.1U_NC 1 *0.1U_NC 1
+3.3V_SUS 3 10 10 H_THERM 2 Q47 MMST3904-7-F 1 3 R391 10M 2 1 1 C442 0.1U 10 Q41 2N7002W-7-F 1 R29 54.9/F 1 R28 27.4/F 1
2
ITP_TDI ITP_TMS ITP_TCK ITP_TDO ITP_TRST# H_RESET# ITP_TCK 2
D
R367 1 R368 1
1 2 5 *0_NC 7 2 3 *150/F_NC 12 2 11 8 9 10 14 16 18 20 22
TDI TMS TCK TDO TRST# RESET# FBO BCLKN BCLKP GND0 GND1 GND2 GND3 GND4 GND5
Layout Note: Place R8 close ITP.
17 CLK_ITP_BCLK# 17 CLK_ITP_BCLK 1
DBR# DBA#
25 24
ITP_DBRESET#
R83 1
150 2 +1.05V_VCCP
ITP disable guidelines Signal
BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# NC0 NC1 GND_0 GND_1 *ITP700Flex_NC 23 21 19 17 15 13 4 6 29 30 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 R17 *54.9/F_NC
Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.
D
Resistor Value Connect To Resistor Placement 150 ohm +/- 5% 39 ohm +/- 5% 680 ohm +/- 5% 27 ohm +/- 5% Open R268 Depop VTT VTT GND GND VTT +3VRUN
5
C391 *100P_NC 50
TDI TMS TRST#
Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP
Size Title
R14 R15
54.9/F ITP_TCK 54.9/F ITP_TRST#
Layout Note: Place R74,R26, R19, R23, R16 , R17 close to CPU
3
TCK TDO ITP_EN
4
QUANTA COMPUTER
Merom Processor (HOST BUS) Document Number FM7B Wednesday, July 16, 2008
7
Close to CK410M Pin8
Date:
6
Rev 1A Sheet 3
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+VCC_CORE U23C +VCC_CORE A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE . AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26
+VCC_CORE A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 +1.5V_RUN F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
U23D VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE11 AE14 AE16 AE19 . AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
All use 10U 4V(+-20%,X6S,0805)Pb-Free.
1 1 1 1 C18 10U 0805 4 C19 10U 0805 4 2
1 C15 10U 0805 4
A
C16 *10U_NC 0805 4
C17 10U 0805 4
2
2
2
2
A
+VCC_CORE
1
1
1
1
C20 10U 0805 4
C21 *10U_NC 0805 4
C22 10U 0805 4
C23 10U 0805 4
1 C24 10U 0805 4 1 2
2
2
2
8 inside cavity, north side, secondary layer.
+VCC_CORE
1
1
1
1
2
5/7 +1.05V_VCCP
C48 10U 0805 4
C51 *10U_NC 0805 4
C46 *10U_NC 0805 4
C418 10U 0805 4
C37 10U 0805 4
2
2
2
2
2
+VCC_CORE
B
+ C30 220uF
B
1
1
1
1
C427 10U 0805 4
C426 *10U_NC 0805 4
C50 10U 0805 4
C429 10U 0805 4
1 C430 10U 0805 4 2
2
2
2
8 inside cavity, south side, secondary layer.
+VCC_CORE
2
1
C45 10U 0805 4
C428 10U 0805 4
C38 10U 0805 4
C47 10U 0805 4
C49 10U 0805 4
C431 *10U_NC 0805 4
AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7 VCCSENSE VSSSENSE
6 inside cavity, north side, primary layer.
+VCC_CORE
VID0 VID1 VID2 VID3 VID4 VID5 VID6
51 51 51 51 51 51 51
C444 0.01U 25
1 2
2
2
2
2
2
2
C443 10U 0805 4
1
1
1
1
1
1
VCCSENSE 51 VSSSENSE 51
1
1
1
1
1
C
1
2
Layout Note: Place C468 near PIN B26.
Penryn Ball-out Rev 1a C52 10U 0805 4 +VCC_CORE 1 R13 100/F 2
C
C413 10U 0805 4
C414 *10U_NC 0805 4
C415 10U 0805 4
C417 *10U_NC 0805 4
C416 10U 0805 4
2
2
2
2
2
6 inside cavity, south side, primary layer.
2
VCCSENSE VSSSENSE 1 +PWR_SRC +1.05V_VCCP + C409 *100U_NC 25 + C424 100U 25 + C412 100U 25 + C421 *100U_NC 25 R12 100/F 1 1 1 1 1 1 C25 0.1U 10 C27 0.1U 10 C26 0.1U 10 C39 0.1U 10 C36 0.1U 10 C40 0.1U 10 2
Penryn Ball-out Rev 1a
2
2
2
2
2
2
Layout out: Place these inside socket cavity on North side secondary.
D
Layout Note: Need to add 100uF cap on PWR_SRC for cap singing. Place on PWR_SRC near +VCC_CORE.
Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil. Place PU and PD within 2 inch of CPU.
D
Title Size Date:
1 2 3 4 5 6
QUANTA COMPUTER
Merom Processor (POWER) Document Number FM7B Wednesday, July 16, 2008
7
Rev 1A Sheet 4
8
of
60
1
2
3
4
5
6
7
8
U28A 3
A
H_A#[3..35] H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_D#[0..63]
H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING H_RCOMP F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 C5 E3 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP
H_A#[3..35]
3
A
+1.05V_VCCP
1
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
R98 221/F 2 H_SWING R99 100/F 2 2
2
2
2
1
1
1
1
10
10
10
1
C126 *0.1U_NC
C109 *0.1U_NC
C130 *0.1U_NC
2 C113 *0.1U_NC 10
1
B
C69 0.1U 10
B
+1.05V_VCCP H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3 H_BPRI# 3 H_BR0# 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 17 CLK_MCH_BCLK# 17 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3
+1.05V_VCCP
+1.05V_VCCP
2
2
2
HOST
R108 24.9/F
1
1
10
10
1
C119 *0.1U_NC
C124 *0.1U_NC
2 C98 *0.1U_NC 10
H_RCOMP
Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing.
1
Layout Note: C131 should be near AB1,AB2,AC2,Y3 C90 should be near AD2,AE2,AG3,AE3 C113 should be near AC5,AC6,AD7,AC7,AC9,AD9,AD11,AC11,AD12,AD13,AC14
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
3 3 3 3 3 3 3 3 3 3 3 3
C127 should be near E2,F3,H2,H3,G4,H5,G7,H7 C129 should be near M6,L7,K9,M7,N8,N9,M10,M11,N12,P13 C149 should be near H13,J13,L13,M14,L16,K16,J17,H17 C146 should be near E13,G17,F16,C15,B14,C11,B11,A11,B12
C
C
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 3 3 3 3 3 3 3 3
+1.05V_VCCP 2 R417 1K/F 1
3 3
H_RESET# H_CPUSLP#
C12 E11
H_CPURST# H_CPUSLP#
H_REF 1
A11 B11
H_AVREF H_DVREF CANTIGA_1p0
R416 2K/F 2
1 2
C457 0.1U 10
D
Layout Note: Place the 0.1 uF decoupling capacitor within 100 mils from GMCH pins.
D
Title Size Date:
1 2 3 4 5 6
QUANTA COMPUTER
Crestline (HOST) Document Number FM7B Wednesday, July 16, 2008
7
Rev 1A Sheet 5
8
of
60
5
4
3
2
1
U28C U28B +1.8V_SUS 2 M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 B31 AJ6 M1 R210 1K/F AY21 1 A47 BG23 BF23 BH18 BF18 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 R145 2 +VCC_PEG
CONTROL/COMPENSATION
R197 1K/F 1 SM_RCOMP_VOH 1 1 C185 0.01U 25 C190 2.2U 0805 10
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4
15 15 15 15 15 15 15 15 15,16 15,16 15,16 15,16 15,16 15,16 15,16 15,16
R425 +3.3V_RUN R89
26 BIA_PWM 31 PANEL_BKEN 10K/F_4 10K/F_4 26 LCD_DDCCLK 26 LCD_DDCDAT 26 ENVDD
L_CTRL_CLK L_CTRL_DATA LCD_DDCCLK LCD_DDCDAT
L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
VCC3G_PCIE_R
49.9/F 1
2/26-20
1
R208 3.01K/F 2
D
SM_RCOMP_VOL 1 1 C193 0.01U 25 C199 2.2U 0805 10 2
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE3_DIMMB DDR_CKE4_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT0 M_ODT1 M_ODT2 M_ODT3 SMRCOMPP SMRCOMPN SM_RCOMP_VOH SM_RCOMP_VOL 15,16 15,16 15,16 15,16
2
2
L_IBG T11
PAD
D
RSVD
LVDS
RSVD15 RSVD16 RSVD17 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25
L_IBG 2 R104 2.4K/F
26 26 26 26
LCD_ACLKLCD_ACLK+ LCD_BCLKLCD_BCLK+
2
2
GRAPHICS
+1.8V_SUS 1 2
26 LCD_A026 LCD_A126 LCD_A226 LCD_A0+ 26 LCD_A1+ 26 LCD_A2+ 26 LCD_B026 LCD_B126 LCD_B226 LCD_B0+ 26 LCD_B1+ 26 LCD_B2+
R207 *1K/F_NC 1 R206 1 R198 *1K/F_NC 1 0 2
UMA
+3.3V_RUN R129 1 R130 1 2 10K 2 10K PM_EXTTS#0 PM_EXTTS#1
V_DDR_MCH_REF_L R187 1 2 0 R199 1 2 499/F T33 PAD MCH_DREFCLK 17 MCH_DREFCLK# 17 DREF_SSCLK 17 DREF_SSCLK# 17 CLK_MCH_3GPLL 17 CLK_MCH_3GPLL# 17
V_DDR_MCH_REF
CLK
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
2/26-20
+1.8V_SUS 1 R68 R67 R65 75/F_4 75/F_4 75/F_4 F25 H25 K25 H24
PCI-EXPRESS
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
PCIE_MRX_GTX_P3
DDR
2
+1.05V_VCCP R137 1 56 2 THERMTRIP_MCH#
TVA_DAC TVB_DAC TVC_DAC TV_RTN
PCIE_MTX_GRX_C_N0 PCIE_MTX_GRX_C_N1 PCIE_MTX_GRX_C_N2 PCIE_MTX_GRX_C_N3
C82 C482 C490 C95
1 1 1 1
2 2 2 2
0.1U 0.1U 0.1U 0.1U
10 10 10 10
IN_D2IN_D1IN_D0IN_CLK-
18 18 18 18
TV
GRAPHICS VID
3,17 CPU_MCH_BSEL0 3,17 CPU_MCH_BSEL1 3,17 CPU_MCH_BSEL2 PAD T21 PAD T27 R106 2 PAD T19 PAD T15 PAD T8 R105 2 PAD T13 PAD T16 PAD T26 PAD T30 PAD T25 PAD T18 R119 2 +3.3V_RUN PAD T12 PAD T24 R135 2 R136 2
CFG3 CFG4 1 *4.02K/F_NC CFG5 CFG6 CFG7 CFG8 *4.02K/F_NC CFG9 1 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 1 *4.02K/F_NC CFG16 CFG17 CFG18 1 *4.02K/F_NC CFG19 1 *4.02K/F_NC CFG20
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43
DMI_MRX_ITX_P0 DMI_MRX_ITX_P1 DMI_MRX_ITX_P2 DMI_MRX_ITX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
12 12 12 12 12 12 12 12 12 12 12 12
SMRCOMPP SMRCOMPN
1
2
C
Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
AE41 AE37 AE47 AH39
DMI_MRX_ITX_N0 DMI_MRX_ITX_N1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N3
12 12 12 12
R200 80.6/F
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
C
R205 80.6/F 2
27 27 27
VGA_BLU VGA_GRN VGA_RED
VGA_BLU VGA_GRN VGA_RED
E28 G28 J28 G29
CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
DMI
PCIE_MTX_GRX_C_P0 PCIE_MTX_GRX_C_P1 PCIE_MTX_GRX_C_P2 PCIE_MTX_GRX_C_P3
C78 C478 C485 C89
1 1 1 1
2 0.1U 2 0.1U 2 0.1U 2 0.1U
10 10 10 10
IN_D2+ IN_D1+ IN_D0+ IN_CLK+
18 18 18 18
CFG
VGA
27 G_CLK_DDC2 27 G_DAT_DDC2 27 VGAHSYNC 27 VGAVSYNC
R107 1 R102 1 R109 1
2 30/F 2 1K/F 2 30/F
H32 J32 J29 E29 L29
13 PM_BMBUSY# 3,11,51 H_DPRSTP# 15 PM_EXTTS#0 15 PM_EXTTS#1 13,44 ICH_PWRGD 13,51 DPRSLPVR
PM_EXTTS#0 PM_EXTTS#1 PLTRST#_R THERMTRIP_MCH# 1 2 R147 0
R29 B7 N33 P32 AT40 AT11 T20 R32
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
T6 T7 T17 T14 T9
PAD PAD PAD PAD PAD
CANTIGA_1p0
+3.3V_RUN GFX_VR_EN C34 T10 PAD +1.05V_VCCP CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AH37 AH36 AN36 AJ35 AH34 CL_CLK0 13 CL_DATA0 13 ICH_CL_PWROK 13,31 ICH_CL_RST0# 13 MCH_CLVREF MCH_CLVREF DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN N28 M28 G36 E36 K36 H36 B12 R415 2 T22 PAD T23 PAD SDVO_CTRLCLK 18 SDVO_CTRLDATA 18 CLK_3GPLLREQ# 17 MCH_ICH_SYNC# 13 1 56 +1.05V_VCCP 2 C132 0.1U 2 10 R139 20K/F UMA_HDMI_HP# R166 1K/F 18 UMA_HDMI_HPD 1 2 2N7002W-7-F Q20 1 R141 7.5K/F 3 R140 1 0 2 PCIE_MRX_GTX_P3
B
B
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 CANTIGA_1p0
ME
1
2
PM NC
Non-iAMT
R142 100K R172 499/F
MISC
HDA
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
2
2
R101 150/F 1 1
R111 150/F 1
2
B28 B30 B29 C29 A28
ICH_AZ_HDMI_BITCLK 11 ICH_AZ_HDMI_RST# 11 ICH_AZ_HDMI_SDIN1 11 ICH_AZ_HDMI_SDOUT 11 ICH_AZ_HDMI_SYNC 11
1
VGA_BLU VGA_GRN VGA_RED R117 150/F
UMA
Layout Note: Place 150 ohm termination resistors close to GMCH.
+3.3V_RUN R121 R122 2 2 1 2.2K 1 2.2K LCD_DDCCLK LCD_DDCDAT
UMA
12 SB_NB_PCIE_RST# 12,30,31,33,34,42 PLTRST#
R470 R469 1
*0_NC 0 R466 2 100
2
1
PLTRST#_R
CFG5 CFG9
A
3,52 H_THERMTRIP#
R143
*0_NC THERMTRIP_MCH#
CFG16 CFG19
CFG20
Low=DMIx2 DMI X2 Select High=DMIx4(Default) Low= Reveise Lane PCI Express Graphic Lane High=Normal operation FSB Dynamic Low=Dynamic ODT Disable ODT High=Dynamic ODT Enable(default). DMI Lane Low=Normal(default). Reversal High=Lane Reversed Low=Only SDVO or PCIEx1 is SDVO/PCIE operational (defaults) Concurrent High=SDVO and PCIEx1 are operating Operation simultaneously via PEG port
Title Size Date:
A
Low=No SDVO Device Present (default) SDVO_CRTL_DATA SDVO Present. High=SDVO Device Present
QUANTA COMPUTER
Crestline (VGA,DMI) Document Number FM7B Wednesday, July 16, 2008
1
Rev 1A Sheet 6 of 60
5
4
3
2
1
2
3
4
5
6
7
8
15 DDR_A_D[0..63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
U28D SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 CANTIGA_1p0 SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 BB20 BD20 AY20 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
15 DDR_B_D[0..63] DDR_A_BS0 15,16 DDR_A_BS1 15,16 DDR_A_BS2 15,16 DDR_A_RAS# 15,16 DDR_A_CAS# 15,16 DDR_A_WE# 15,16 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
U28E SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 CANTIGA_1p0 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# BC16 BB17 BB33 AU17 BG16 BF14 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# DDR_B_BS0 15,16 DDR_B_BS1 15,16 DDR_B_BS2 15,16 DDR_B_RAS# 15,16 DDR_B_CAS# 15,16 DDR_B_WE# 15,16
A
A
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
B
SYSTEM
DDR
C
DDR
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_MA[0..14]
15,16
SYSTEM
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_DQS[0..7]
15
B
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DM[0..7]
15
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_DM[0..7]
15
A
DDR_B_DQS[0..7]
15
MEMORY
DDR_A_DQS#[0..7]
15
MEMORY
DDR_B_DQS#[0..7]
15
B
DDR_B_MA[0..14]
15,16
C
D
D
Title Size Date:
1 2 3 4 5 6
QUANTA COMPUTER
Crestline (DDR2) Document Number FM7B Wednesday, July 16, 2008
7
Rev 1A Sheet 7
8
of
60
5
4
3
2
1
+1.8V_SUS AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 BA36 BB24 BD16 BB21 AW16 AW13 AT13 +1.05V_VCCP Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
U28G
+3.3V_RUN VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 R88 1 10 2 D8 1
U28F
D
POWER
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC
+VCC_GMCH_L
2
SDMK0340L-7-F +1.05V_VCCP
1
1
1
+ C106 220U
POWER
10
Layout Note: Inside GMCH cavity. Layout Note: Inside GMCH cavity for VCC_AXG.
+VCC_AXG_NCTF 1 1 1 1 1 1 + C72 *330U_NC + C73 *330U_NC +1.05V_VCCP
2
2
2
2
2
10
10
2
C105 0.1U
C137 0.1U
C121 22U 0805 4
C162 10U 0603 6.3
C104 1U 0603 10
C149 0.47U 0603 10
Layout Note: 370 mils from edge.
VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35
VCC SM
VCC CORE
Layout Note: 370 mils from edge.
C479 22U 0805 4
C112 0.22U 0603 10
C160 0.22U 0603 10
1
5/7
2
2
2
2
C94 0.1U
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
D
+1.05V_VCCP VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
C
C
+1.8V_SUS 5/7
B
VCC SM LF
+1.05V_VCCP 2
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
VCC GFX NCTF
VCC_SM
1 1 C172 22U 0805 4 C183 22U 0805 4 2
1
C175 0.1U 10
+ C548 220U 2.5
2
Layout Note: Place C195 where LVDS and DDR2 taps.
Layout Note: Place on the edge.
2
VCC NCTF
B
VCC GFX
1
1
1
1
1
1
1
2
2
2
2
2
2
2
A
2
AJ14 AH14
VCC_AXG_SENSE VSS_AXG_SENSE
C184 0.1U 10
C157 0.1U 10
C181 0.22U 0603 10
C171 0.22U 0603 10
C158 0.47U 0603 10
C180 1U 0603 10
1 C174 1U 0603 10
R174 10
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
AV44 BA37 AM40 AV21 AY5 AM10 BB13
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
A
R173 10 1
CANTIGA_1p0
CANTIGA_1p0 Title Crestline (VCC,NCTF) Size Date: Document Number FM7B
QUANTA COMPUTER
Rev 1A Sheet
1
UMA: Places R721, R726 to 10 ohm. Dis: Please R721, R726 to 0 ohm.
5 4 3 2
Wednesday, July 16, 2008
8
of
60
5
4
3
2
1
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
L41 +3.3V_RUN 0603 C459 0.01U 25 R418 1
D
BLM18PG181SN1D +VCCA_CRTDAC 1 C460 0.1U 10 +VCCA_CRTDAC
U28H VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
+1.05V_VCCP
2
B27 A26 A25 B25
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 VCCA_DAC_BG VSSA_DAC_BG
1
1
1
1
1 C144 2.2U 0603 6.3 C156 4.7U 0603 6.3 2 2 2 2
0 2 1 +VCCA_DAC_BG C461 0.1U 10 C462 0.01U 25
+VCCA_DAC_BG
CRT
Place on the edge. Close to VTT
+1.05V_VCCP 2
2
C110 0.47U 6.3
C123 4.7U 0603 6.3
+ C474 220U 7343 5/7 2.5
D
2
+VCCA_DPLLA +VCCA_DPLLB +VCCA_HPLL
L48 AD1 AE1 J48 J47
VCCA_DPLLB VCCA_HPLL VCCA_MPLL VCCA_LVDS VSSA_LVDS
VTT
F47
VCCA_DPLLA
Non-iAMT
+1.05V_VCCP L11 BLM11A05S
45mA MAx.
+1.05V_VCCP L42 10uH 2 0805 1
40mA MAx.
10uH+-20%_100mA
+VCCA_DPLLA 1 1 + C468 220U 7343 2.5 C74 0.1U 10 5/7
+VCCA_MPLL C471 1000P 2 50 1 +VCC_TX_LVDS
PLL
VCC_HV
A LVDS
FB_120ohm+-25%_100mHz _200mA_0.2ohm DC
+VCCA_HPLL
D9 *SDMK0340L-7-F_NC 1 1 R92 *10_NC 2 +3.3V_RUN 1 L6 2 0 +1.05V_VCCP C67 1U 0603 10 C66 10U 0603 6.3 +VCC_HV_L
0603 1 C493 22U 1206 10 1 2 C120 0.1U 10 L14 BLM11A05S +VCCA_MPLL 0603 R180 0.5/F 1 2 0603
C
+1.5V_RUN AD48 1 C510 0.1U 10 +VCCA_PEG_PLL AA48 AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16 VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_PEG_BG
2
2
2
2
0.1Caps should be placed 200 mils with in its pins.
C150 0.1U 10 +1.05V_VCCP 1 R186
+ C487 220U 7343 2.5
1
5/7
1
0805
1
+VCCA_DPLLB C477 0.1U 10
2
L45 10uH
A PEG
POWER
A SM
Reserved L81 pad for inductor.
C
2
1
2
1
1
2
2
2
1
1
2
1
2
2
2
1
2/18-7 5/7
C159 4.7U 0603 6.3
C169 22U 0805 4
C168 22U 0805 4
1
C503 22U 1206 10
2
0 +VCCA_SM C173 1U 0603 10
2
1
0603 + C192 *100U_NC 7343 6.3
L22 805 1uH/300MA +1.8V_SUS
+1.05V_VCCP
1
1
1
A CK
C151 22U 0805 4
C143 1U 0603 10
C164 1U 0603 10
1
1uH/300mA
2
2
2
2
10
SM CK
+1.05V_VCCP L53 BLM21P221SGPT +VCCA_PEG_PLL 0805 1 R467 1/F 0603 C516 10U 0603 6.3 +1.5V_RUN 2
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
BF21 BH20 BG20 BF20
+VCC_SM_CK
2
C170 0.1U
2
2
1
+VCCA_SM_CK
1 2
L13
C472 1000P 50
1
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8
AXF
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
B22 B21 A21
+VCC_AXF
C188 0.1U 10
R211 1/F 0603 +VCC_SM_CK_L C198 10U 0603 6.3 L9 C475 + *220U_NC 7343 4 1uH/300MA 805 +1.8V_SUS
1 2
B
HV
1
FB_220ohm+-25%_100MHz _2A_0.1ohm DC
TV
R411 0 +VCCHDA
2
VCCA_TV_DAC_1 VCCA_TV_DAC_2
VCC_HV_1 VCC_HV_2 VCC_HV_3 VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
C35 B35 A35 V48 U48 V47 U47 U46 AH48 AF48 AH47 AG47
+3.3V_VCC_HV +VCC_PEG R438 1 1 1 5/7 2 1 + C502 220U 7343 2.5 C496 22U 1206 10 L55 2 91nH/1.5A 1 +1.05V_VCCP 2 2 C491 4.7U 0603 6.3 2 0 1206 +1.05V_VCCP
B
VCC_HDA
+VCCD_TVDAC +VCCD_QDAC C138 2 2 C509 C463 0.1U 10 0.1U 1 1 0.1U 10 +VCCA_MPLL +VCCD_PEG_PLL 10 +VCCD_LVDS 1 1 C88 1U 0603 10 C86 *10U_NC 0603 6.3
M25 L28 AF1 AA47 M38 L37
VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS_1 VCCD_LVDS_2
D TV/CRT
PEG
C456 0.1U 10
2
HDA
2
1
+VCCHDA
A32
+VCC_RXR_DMI
+3.3V_RUN
L40 BLM18PG181SN1D 0603
+VCC_TVDACA C464 0.01U 25 1
LVDS
DMI
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
+1.8V_SUS
2
1 R133 0
2
VTTLF
VTTLF1 VTTLF2 VTTLF3
2
2
CANTIGA_1p0
+1.05V_VCCP
+1.5V_RUN R409 1
A
0 2 1 C452 0.1U 10 +VCCD_TVDAC C80 0.01U 25 +VCCD_QDAC 1
5/29-51
D30 SDM10K45-7-F
A
+1.05V_VCCP L51 BLM21P221SGPT +VCCD_PEG_PLL 0805 1 R459 1/F 0603 C508 10U 0603 6.3 +VTTLF1 +VTTLF2 +VTTLF3 1 1 1 C122 0.47U 0603 10 C76 0.47U 0603 10 C70 0.47U 0603 10
L39 BLM18PG181SN1D 603
1 2
FB_220ohm+-25%_100MHz _2A_0.1ohm DC
2 1
2
2
2
A8 L1 AB2
+VTTLF1 +VTTLF2 +VTTLF3
1
C520 10U 0603 6.3
2
+VCC_TVDACA
B24 A24
VCC_TX_LVDS
K47
+VCC_TX_LVDS
1
1
+3.3V_VCC_HV R414 1 1 C465 0.1U/10V 2 0 1
R413 10 +3.3V_RUN Title Size Date:
2
C451 0.1U 10
QUANTA COMPUTER
Crestline (POWER) Document Number FM7B Wednesday, July 16, 2008 Sheet
1
2
2
2
C81 0.01U 25
2
2
Rev 1A 9 of 60
5
4
3
2
5
4
3
2
1
U28J U28I AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 CANTIGA_1p0 CANTIGA_1p0 Title Size Date:
5 4 3 2
D
VSS
C
B
A
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_235 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296
VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 B2 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
D
VSS
VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42
C
VSS NCTF
B
NC
VSS SCB
A
QUANTA COMPUTER
Crestline (VSS) Document Number FM7B Wednesday, July 16, 2008 Sheet
1
Rev 1A 10 of 60
1
2
3
4
5
6
7
8
32.768KHZ
1
W1 ICH_RTCX1 1 2
A
4 3 32.768KHZ
ICH_RTCX2 2
R525 332K/F
1 R524 332K/F 2 1 ICH_LAN100_SLP
A
R280 2
10M 1
+RTC_CELL
+RTC_CELL
C270 15P 50V
C271 15P 50V
4/3-27
ICH_INTVRMEN
1 R531 *0_NC 2
R530 *0_NC 2
+RTC_CELL
ICH9M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) ICH_INTVRMEN
R523 20K 1 ICH_RTCRST# ICH_SRTCRST# ICH_INTRUDER# ICH_RTCX1 ICH_RTCX2 ICH_RTCRST# ICH_SRTCRST# ICH_INTRUDER# C596 1U/10V ICH_INTVRMEN ICH_LAN100_SLP T54 PAD GLAN_CLK C23 C24 A25 F20 C22 B22 A22 E25 C13
ICH9M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05) ICH_LAN100_SLP Low = Internal VR Disabled High = Internal VR Enabled(Default)
+1.05V_VCCP
Low = Internal VR Disabled High = Internal VR Enabled(Default)
U31A RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GLAN_DOCK#/GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
1
2
R289 1M 2 1
R269 20K
2
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
K5 K4 L6 K2 K3 J3 J1 N7 AJ27 AJ25 AE23 AJ26 AD22 AF25 AE22 AG25 L3 AF23 AF24 AH27 AG26 AG27 THERMTRIP#_ICH PAD SIO_A20GATE H_DPRSTP# H_DPSLP# H_FERR#_L 2 R577 1 56
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
31,33 31,33 31,33 31,33
2
2
R579 *56_NC 1 1 H_DPRSTP# H_DPSLP# H_FERR#
R332 *56_NC 1
2 R578 56 +3.3V_RUN
B
1
1
RTC LPC
2
2
C267 1U/10V
FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M# DPRSTP# DPSLP#
LPC_LFRAME# 31,33 PAD PAD T68 T103
SIO_A20GATE 31 H_A20M# 3 H_DPRSTP# 3,6,51 H_DPSLP# 3 2 H_FERR# H_PWRGOOD 3 H_IGNNE# 3 1 H_INIT# 3 H_INTR 3 SIO_RCIN# 31 H_NMI H_SMI# 3 3 SIO_A20GATE SIO_RCIN# H_FERR# 3
B
6 ICH_AZ_HDMI_BITCLK 40 ICH_AZ_CODEC_BITCLK
R355 1 R348 1 2
2 33 2 33
ACZ_BIT_CLK
LAN / GLAN CPU
Reserved for Intel Nineveh T64 T66 design.
T51 T44 T55 T61
1
C373 *27P/50V_NC +3.3V_SUS
PAD PAD PAD PAD PAD PAD
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
2 R320 8.2K 1 +1.05V_VCCP 2 R334 56 1 R309 10K
F14 G13 D14 D13 D12 E13 B10 B28 B27 AF6 AH4 AE7 AF4 AG4 AH3 AE5
FERR# CPUPWRGD IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#
R287 *10K_NC 2 1 R291 24.9/F 1 2 GLAN_COMP ACZ_BIT_CLK ACZ_SYNC ACZ_RST#
6 40 6 31,40 6 40
ICH_AZ_HDMI_SYNC ICH_AZ_CODEC_SYNC ICH_AZ_HDMI_RST# ICH_AZ_CODEC_RST# ICH_AZ_HDMI_SDOUT ICH_AZ_CODEC_SDOUT
R357 R351 R354 R347 R349 R356
1 1 1 1 1 1
2 2 2 2 2 2
33 33 33 33 33 33
SIO_RCIN#
ACZ_SYNC ACZ_RST# ACZ_SDOUT
+1.5V_PCIE_ICH
H_STPCLK# 3
IHDA
Place all series terms close to ICH9 except for SDIN input lines,which should be close to source.Placement of R603, R600, R607 & R612 should equal distance to the T split trace point as R604, R599, R606 & R608 respective. Basically,keep the same distance from T for all series termination resistors.
40 ICH_AZ_CODEC_SDIN0 6 ICH_AZ_HDMI_SDIN1 PAD T80 PAD T78 ACZ_SDOUT +3.3V_SUS R333 2 R330 2
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT
TP9
T82 THERMTRIP#_ICH
AG5
1 *10K_NC AG7 1 *10K_NC AE8 AG8 AJ16 AH16 AF17 AG17 AH13 AJ13 AG14 AF14
C
36 36 36 36
SATA_TX0SATA_TX0+ SATA_TX1SATA_TX1+
C368 C367 C364 C363
0.01U/16V 0.01U/16V 0.01U/16V 0.01U/16V
SATA_TX0-_C SATA_TX0+_C SATA_TX1-_C SATA_TX1+_C
2/15-1
Master HDD
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED#
SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS
AH11 AJ11 AG12 AF12 AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7 24.9/F SATABIAS 1
PAD PAD
T83 T81 SATA_RX5- 35 SATA_RX5+ 35
38 36 36
SATA_ACT# SATA_RX0SATA_RX0+
E-SATA
SATA_TX0-_C SATA_TX0+_C
SATA
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP ICH9M REV 1.0
SATA_TX5-_C SATA_TX5+_C
2/15-1
C
CLK_PCIE_SATA# 17 CLK_PCIE_SATA 17 R585 2
SATA ODD
35 35 SATA_TX5SATA_TX5+ C382 C385 0.01U/16V 0.01U/16V SATA_TX5-_C SATA_TX5+_C
36 36
SATA_RX1SATA_RX1+
SATA_TX1-_C SATA_TX1+_C
Place within 500mils of ICH9 ball
+3.3V_RUN 2
XOR Chain Entrance Strap
ICH RSVD 0 0
D
R350 *1K_NC 1 ACZ_SDOUT ICH_RSVD 2 R532 *1K_NC 13
D
HDA SDOUT Description 0 1 0 1 RSVD Enter XOR Chain Normal Operation (Default) Set PCIE port config bit 1
1
1 1
Title Size Date:
1 2 3 4 5 6
QUANTA COMPUTER
ICH9-M (CPU,IDE,SATA,LPC,AC97,LAN) Document Number FM7B Wednesday, July 16, 2008
7
Rev 1A Sheet 11
8
of
60
1
2
3
4
5
6
7
8
U31D
Place TX DC blocking caps close ICH8.
33 33 34 34 33 33 30 30 PCIE_TX1PCIE_TX1+ PCIE_TX2PCIE_TX2+ PCIE_TX3PCIE_TX3+ PCIE_TX4PCIE_TX4+ C315 C323 C307 C305 C298 C289 C287 C284 C278 C276 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 10 10 10 10 10 10 10 10 10 10 PCIE_TXN1_C PCIE_TXP1_C PCIE_TXN2_C PCIE_TXP2_C PCIE_TXN3_C PCIE_TXP3_C PCIE_TXN4_C PCIE_TXP4_C GLAN_TXN_C GLAN_TXP_C
33 33
PCIE_RX1PCIE_RX1+
MiniWWAN
34 34 PCIE_RX2PCIE_RX2+
MiniWLAN
33 33 PCIE_RX3PCIE_RX3+
PCIE_TXN2_C PCIE_TXP2_C
L29 L28 M27 M26 J29 J28 K27 K26 G29 G28 H27 H26 E29 E28 F27 F26 C29 C28 D27 D26 D23 D24 F23 D25 E23 N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3 AG2 AG1
Direct Media Interface
PCIE_TXN1_C PCIE_TXP1_C
N29 N28 P27 P26
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP
V27 V26 U29 U28 Y27 Y26 W29 W28 AB27 AB26 AA29 AA28 AD27 AD26 AC29 AC28 T26 T25 AF29 AF28 AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2 DMI_COMP 1 R552
DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_MRX_ITX_N0 DMI_MRX_ITX_P0 DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_MRX_ITX_N1 DMI_MRX_ITX_P1 DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_MRX_ITX_N2 DMI_MRX_ITX_P2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_MRX_ITX_N3 DMI_MRX_ITX_P3
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
A
PCI-Express
MiniWPAN
30 30 PCIE_RX4PCIE_RX4+
PCIE_TXN3_C PCIE_TXP3_C
PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5
A
42 PCIE_TX6-/GLAN_TX42 PCIE_TX6+/GLAN_TX+
Express Card
T102 T101 T60 T56 PAD PAD PAD PAD
PCIE_TXN4_C PCIE_TXP4_C
CLK_PCIE_ICH# 17 CLK_PCIE_ICH 17 2 24.9/F ICH_USBP0- 35 ICH_USBP0+ 35 ICH_USBP1- 35 ICH_USBP1+ 35 ICH_USBP2- 35 ICH_USBP2+ 35 ICH_USBP3- 35 ICH_USBP3+ 35 ICH_USBP4- 34 ICH_USBP4+ 34 ICH_USBP5- 33 ICH_USBP5+ 33 ICH_USBP6- 33 ICH_USBP6+ 33 ICH_USBP7- 30 ICH_USBP7+ 30 PAD T73 PAD T75 PAD T74 PAD T72 ICH_USBP10- 38 ICH_USBP10+ 38 ICH_USBP11- 41 ICH_USBP11+ 41 +1.5V_PCIE_ICH
ICH_SPI_CS1#_R PCI_GNT0# 2 1
Boot BIOS Strap GNT0#
R305 *1K_NC 2
DMI_ZCOMP DMI_IRCOMP
Place within 500mils of ICH8
SPI_CS1# No stuff Stuff No stuff
42 PCIE_RX6-/GLAN_RX42 PCIE_RX6+/GLAN_RX+
R302 *1K_NC 1
LPC PCI SPI
11 10 01
No stuff No stuff Stuff
Giga Bit LOM
T48 T49 T53 T58 PAD PAD PAD PAD
GLAN_TXN_C GLAN_TXP_C SPI_CLK_R SPI_CS#0_R ICH_SPI_CS1#_R SPI_MOSI SPI_MISO USB_OC0_1# USB_OC2_3# OC4# OC5# OC6# OC7# USB_OC8# OC9# OC10# OC11# USBRBIAS
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
SPI_CLK_R +3.3V_RUN
B
2/20-12
+3.3V_RUN
35 USB_OC0_1# 35 USB_OC2_3#
R241 *10K/F_NC 1
C231 *0.1U_NC 10 8 VDD HOLD# VSS
C243 *0.1U_NC 10
U15 CE# SCK SI SO WP# 1 6 5 2 3 R239 R253 R256 R242 *22_NC SPI_CS#0_R *22_NC SPI_CLK_R *22_NC SPI_MOSI *22_NC SPI_MISO
R252 *10K/F_NC
USB_OC8#
SPI__HOLD#
7 4
R553 22.6/F 1 2
USBP0N USBP0P USBP1N USBP1P SPI_CLK USBP2N SPI_CS0# USBP2P SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3P SPI_MOSI USBP4N SPI_MISO USBP4P USBP5N OC0#/GPIO59 USBP5P OC1#/GPIO40 USBP6N OC2#/GPIO41 USBP6P OC3#/GPIO42 USBP7N OC4#/GPIO43 USBP7P OC5#/GPIO29 USBP8N OC6#/GPIO30 USBP8P OC7#/GPIO31 USBP9N OC8#/GPIO44 USBP9P OC9#/GPIIO45 USBP10N OC10#/GPIO46 USBP10P OC11#/GPIO47 USBP11N USBP11P
Side pair Top / left Side pair bottom / left Side pair top/right(DB) Side pair Bot right(DB) Mini Card (WLAN) Mini Card (WWAN) Mini Card (WPAN) Express Card
RP21 PCI_FRAME# PCI_TRDY# PCI_DEVSEL# PCI_REQ1# +3.3V_RUN 6 7 8 9 10 5 4 3 2 1 +3.3V_RUN PCI_PLOCK# PCI_STOP# PCI_PIRQD# PCI_IRDY# +3.3V_RUN 5 4 3 2 1
SPI
USB
2
PCI Pullups
B
2
1
2
1
2
Biometric Camera
1
SPI_WP#
*W25X40VSSIG_NC
Places within 500 mils of the ICH9
USBRBIAS USBRBIAS# ICH9M REV 1.0
2/25-18
RP27 PCI_PIRQA# PCI_REQ0# ICH_IRQH_GPIO5 PCI_SERR# +3.3V_RUN 6 7 8 9 10
PCI_PIRQB# PCI_PIRQC# PCI_PERR#
WWAN Noise - ICH improvements
OC6# OC4# OC5# OC7# USB_OC8# USB_OC2_3# USB_OC0_1# OC9#
C
+3.3V_SUS RP33 10 10 10 10 10 10 10 10 OC7# OC6# OC5# OC4# +3.3V_SUS OC10# OC11# 6 7 8 9 10 10KX8 R321 2 R323 2 5 4 3 2 1 1 10K 1 10K OC9# USB_OC2_3# USB_OC0_1# USB_OC8#
C308 C620 C623 C618 C622 C292 C321 C326
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
*0.1U_NC *0.1U_NC *0.1U_NC *0.1U_NC *0.1U_NC *0.1U_NC *0.1U_NC *0.1U_NC
+3.3V_SUS
SB_WPAN_PCIE_RST# SB_WWAN_PCIE_RST# SB_WLAN_PCIE_RST# SB_LOM_PCIE_RST# SB_NB_PCIE_RST#
R315 R307 R313 R288 R294
2 2 2 2 2
1 1 1 1 1
20K 20K 20K 20K 20K
C
28 PCI_AD[0..31]
U31B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3 J5 E1 J6 C4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD# ICH9M REV 1.0
BIOS should not enable the internal GPIO pull up resistor.
PCI
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME#
2 1
5
F1 G4 B6 A7 F13 F12 E6 F6 D8 B4 D6 A5 D3 E3 R1 C6 E4 C2 J4 A4 F5 D7
PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# SB_WWAN_PCIE_RST# PCI_GNT2# SB_LOM_PCIE_RST# PCI_GNT3#
PCI_REQ0# 28 PCI_GNT0# 28 PAD T34 PAD T99 SB_WWAN_PCIE_RST# 33 PAD T67 SB_LOM_PCIE_RST# 42 PAD T65 PCI_C_BE0# PCI_C_BE1# PCI_C_BE2# PCI_C_BE3# 28 28 28 28
CLK_PCI_ICH 2
Non-iAMT
R292 *10_NC C344 1 0.047U 10 1 PCI_RST#_G 2
+3.3V_SUS
Add Buffers as needed for Loading and fanout concerns.
U19 4 PCI_RST# 28
C275 *8.2P_NC
2 1 TC7SZ32FU(T5L,F,T) +3.3V_SUS
PCI_IRDY# PCI_RST#_G PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
PCI_IRDY# 28 PCI_PAR 28 PCI_DEVSEL# 28 PCI_PERR# 28 PCI_PLOCK# PCI_SERR# 28 PCI_STOP# 28 PCI_TRDY# 28 PCI_FRAME# 28 CLK_PCI_ICH 17 ICH_PME# 28,31
Reserved for 16 EMI.Place resister and cap close to ICH.
C250 1 2 5 2 4 1 TC7SZ32FU(T5L,F,T) PLTRST# 6,30,31,33,34,42 0.047U 10 U17
PCI_GNT3# 1 R304 *1K_NC
PCI_PLTRST#
D
C14 PCI_PLTRST# D4 CLK_PCI_ICH R2
D
Interrupt I/F
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
T50 PAD 28 PCI_PIRQB# 28 PCI_PIRQC# T38 PAD
H4 K6 F2 G2
SB_WPAN_PCIE_RST# SB_WLAN_PCIE_RST# SB_NB_PCIE_RST# ICH_IRQH_GPIO5
A16 away override strap.
SB_WPAN_PCIE_RST# 33 SB_WLAN_PCIE_RST# 34 SB_NB_PCIE_RST# 6 PAD T52
Title Size Date:
QUANTA COMPUTER
ICH9-M (USB,DMI,PCIE,PCI) Document Number FM7B Wednesday, July 16, 2008
7
SB_NB_PCIE_RST#
Low = A16 swap override enabled. High = Default.
2
PCI_IRDY#
Rev 1A Sheet 12
8
of
60
1
2
3
4
5
6
1
2
3
4
5
6
7
8
+3.3V_SUS RP19 1 3 2.2KX2 2 4
Non-iAMT
ICH_SMBDATA ICH_SMBCLK
Place these close to ICH8.
+3.3V_SUS
Non-iAMT
2 2 2 2 1 1 1 1 *10K_NC 10K 10K 1K RSV_ICH_CL_RST1# ICH_RI# SIO_EXT_SCI# PCIE_WAKE# +3.3V_RUN
CLK_ICH_48M 2
A
A
Non-iAMT
+3.3V_SUS RP20 1 3 2 4 *100KX2_NC ICH_SMLINK0 ICH_SMLINK1
ASF 2.0
U31C ICH_SMBCLK R271 1 ICH_SMBDATA R272 1 2 0 ICH_SMLINK0 2 0 ICH_SMLINK1 30,33,34 ICH_SMBCLK 30,33,34 ICH_SMBDATA T35 PAD T41 PAD T37 PAD ICH_SMBCLK ICH_SMBDATA RSV_ICH_CL_RST1# ICH_SMLINK0 ICH_SMLINK1 ICH_RI# T70 PAD 3 ITP_DBRESET# R300 8.2K 1 CLKRUN# 6 PM_BMBUSY# 34 USB_MCARD1_DET# 17 H_STP_PCI# 17 H_STP_CPU# R303 *10_NC 1 28,31 CLKRUN# 30,33,34,42 PCIE_WAKE# 28,31 IRQ_SERIRQ 39 THERM_ALERT# 31,44,51 IMVP_PWRGD T36 PAD 33 USB_MCARD2_DET# 33 USB_MCARD3_DET# 31 SIO_EXT_WAKE# 31 SIO_EXT_SMI# 31 SIO_EXT_SCI# T96 PAD USB_MCARD2_DET# USB_MCARD3_DET# SIO_EXT_SMI# SIO_EXT_SCI# CLKRUN# PCIE_WAKE# IRQ_SERIRQ THERM_ALERT# IMVP_PWRGD USB_MCARD1_DET# RSV_LPCPD# G16 A13 E17 C17 B18 F19 R4 G19 M6 A17 A14 E19 L4 E20 M5 AJ23 D21 A20 AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8 M7 AJ24 B21 AH20 AJ20 AJ21 SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1 RI# SUS_STAT#/LPCPD# SYS_RESET# PMSYNC#/GPIO0 SMBALERT#/GPIO11 S4_STATE#/GPIO26 STP_PCI#/GPIO15 STP_CPU#/GPIO25 PWROK SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# AH23 AF19 AE21 AD20 H1 AF3 P1 C16 E16 G17 C10 G20 M2 B13 R3 D20 D22 R5 R6 B16 F24 B19 F22 C19 C25 A19 F21 D18 A16 C18 C11 C20
1
50 CLK_ICH_14M CLK_ICH_14M CLK_ICH_48M ICH_SUSCLK 2 CLK_ICH_14M 17 CLK_ICH_48M 17 PAD T104 R539 *10_NC 1 1 50 ICH_PWRGD DPRSLPVR ICH_BATLOW# R529 2 ICH_PWRGD 6,44 DPRSLPVR 6,51 8.2K 1 +3.3V_SUS ICH_PWRGD DPRSLPVR ICH_RSMRST# R310 2 R542 1 R298 2 1 10K 2 100K 1 10K 1 10K 1 1M 2 C610 *4.7P_NC SIO_SLP_S3# 31 PAD T59 SIO_SLP_S5# 31
SMB
2
B
SYS GPIO Power MGT
Clocks
+3.3V_RUN 2
SATA GPIO
2
R346 8.2K
1 1 C357 *4.7P_NC
2
R273 R293 R275 R299
R337 *10_NC
CLKRUN#/GPIO32 WAKE# SERIRQ THRM# VRMPWRGD TP8 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LANPHYPC/GPIO12 ENGDET/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 SPKR MCH_SYNC# TP3 TP9 TP10 TP11 ICH9M REV 1.0
DPRSLPVR/GPIO16 BATLOW# PWRBTN# LAN_RST# RSMRST# CK_PWRGD CLPWROK SLP_M# CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# CL_RST1# MEM_LED/GPIO24 ALERT#/GPIO10 NETDETECT/GPIO14 WOL_EN/GPIO9
B
Option to " Disable " clkrun. Pulling it down will keep the clks running.
SIO_PWRBTN# 31 RSV_ICH_LAN_RST# ICH_RSMRST# PAD T46
ICH_RSMRST# 31 CLK_PWRGD 17
RSV_ICH_LAN_RST# 6,31
ICH_CL_PWROK
R290 2 R322 2
2/25-17 6/11-44
37 KB_LED_DET# 34 PCIE_MCARD1_DET# R155 1 2 0 PCIE_MCARD1_DET# R306 2
ICH_CL_PWROK PAD T40
Non-iAMT
ICH_CL_PWROK
PCIE_MCARD2_DET# PCIE_MCARD3_DET#
MISC GPIO Controller Link
1 4.7K 33 PCIE_MCARD2_DET# 33 PCIE_MCARD3_DET# 34 WLAN_RADIO_DIS# 41 CAMERA_CBL_DET# 17 SATA_CLKREQ# PLTRST_DELAY# 33 WPAN_RADIO_DIS_MINI# 33 WWAN_RADIO_DIS# T106 PAD T97 PAD 40 SPKR 6 MCH_ICH_SYNC# 11 ICH_RSVD T105 PAD T108 PAD T107 PAD
RSV_ICH_CL_CLK1 RSV_ICH_CL_DATA1 CL_VREF0 CL_VREF1 CL_RST1# RSV_GPIO24 RSV_GPIO10 RSV_GPIO14 RSV_WOL_EN R286 2
CL_CLK0 6 PAD T57 CL_DATA0 6 PAD T42 RSV_GPIO10 R270 2 +3.3V_SUS 1 10K
PLTRST_DELAY#
ICH_CL_RST0# 6 PAD T62 PAD PAD PAD PAD 8.2K 1 T43 T47 T45 T39 +3.3V_SUS
C
SPKR MCH_ICH_SYNC#_R TP9 TP10 TP11
DIS:ALW UMA:SUS (19)
Non-iAMT
+3.3V_RUN 2 +3.3V_ALW +3.3V_SUS 2 2
C
R331
2
1 10K
PLTRST_DELAY#
+3.3V_RUN 1
+3.3V_RUN
7/17-63
+3.3V_RUN R268 1 R344 R583 R257 R339 R255 1 1 1 1 1 1.91K/F 2 2 2 2 2 2 100K 100K 100K 100K 100K IMVP_PWRGD USB_MCARD2_DET# USB_MCARD3_DET# PCIE_MCARD1_DET# PCIE_MCARD2_DET# PCIE_MCARD3_DET#
SMbus address D2
R314 *1K_NC 2 4
Non-iAMT
1 CL_VREF0 1 RP13 2.2KX2
R285 3.24K/F 1
R527 R534 *3.24K/F_NC *3.24K/F_NC 1 1 R533 *453/F_NC 2
These are for backdrive issue.
2 Q29 1 1 3
CL_VREF1
2
1
C265 0.1U 2
R277 453/F
1 2
SPKR
C598 *0.1U_NC
No Reboot strap. SPKR Low = Default. High = No Reboot.
30,33,34 ICH_SMBDATA
2N7002W-7-F +3.3V_RUN
10
2
3
MEM_SDATA 15
10
+3.3V_RUN
D
R581 2 R316 2 R582 2
1 *10K_NC MCH_ICH_SYNC#_R IRQ_SERIRQ 1 10K THERM_ALERT# 1 10K
2
CL_VREF0/1 ~=0.405V
Q28 1
D
30,33,34 ICH_SMBCLK
3
MEM_SCLK 15
2N7002W-7-F +3.3V_SUS Title R278 2 R526 2 R528 1
1
QUANTA COMPUTER
ICH9-M (PM,GPIO,SMB,CL) Document Number FM7B Thursday, July 17, 2008
7
1 10K 1 10K 2 100K
RSV_WOL_EN SIO_EXT_SMI# USB_MCARD1_DET#
Size Date:
2 3 4 5 6
Rev 1A Sheet 13
8
of
60
1
2
3
4
5
6
7
8
U31F U31E AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[0