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INTEGRATED CIRCUITS
DATA SHEET
TDA4882 Advanced monitor video controller for OSD
Preliminary specification File under Integrated Circuits, IC02 December 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
FEATURES · 85 MHz video controller · Fully DC controllable · 3 separate video channels · Input black level clamping · White level adjustment for 2 channels only · Brightness control with correct grey scale tracking · Contrast control for all 3 channels simultaneously QUICK REFERENCE DATA SYMBOL VP IP VI(b-w) VO(b-w) IO(b-w) IOM B Gnom G Cc COSD Vbl PARAMETER positive supply voltage (pin 7) supply current input voltage (black-to-white; pins 2, 5 and 8) output voltage (black-to-white; pins 19, 16 and 13) output current (black-to-white; pins 20, 17 and 14) peak output current (pins 20, 17 and 14) bandwidth nominal gain (pins 2, 5 and 8 to pins 19, 16 and 13) gain control difference for 2 channels contrast control minimum contrast for OSD brightness control related to nominal output signal amplitude operating ambient temperature -3 dB nominal contrast; pins 3 and 11 open-circuit relative to Gnom V6 = 1 to 6 V V6 = 0.7 V nominal contrast; pins 3 and 11 open-circuit CONDITIONS - - - - - 70 - -5 -22 - -11 MIN. 7.2 TYP. 8.0 48 0.7 0.79 50 - 85 1 - - -40 - - · Cathode feedback to internal reference for cut-off control, which allows unstabilized video supply voltage · Current outputs for RGB signal currents · RGB voltage outputs to external peaking circuits · Blanking and switch-off input for screen protection · Sync on green operation possible · OSD application very easily.
TDA4882
GENERAL DESCRIPTION The TDA4882 is an RGB amplifier for colour monitor systems with super VGA performance, intended for DC or AC coupling of the colour signals to the cathodes of the CRT. With special advantages the circuit can be used in conjunction with the TDA485X monitor deflection IC family.
MAX. 8.8 1.0 - - 100 - - +2.6 +3.4 - +34 V
UNIT mA V V mA mA MHz dB dB dB dB %
Tamb
-20
-
+70
°C
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA4882 DIP20 DESCRIPTION plastic dual in-line package; 20 leads (300 mil) VERSION SOT146-1
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Preliminary specification
Advanced monitor video controller for OSD
BLOCK DIAGRAM
TDA4882
VP = 8 V
6.2 V
handbook, full pagewidth
VP 1 10 k brightness control signal input current output VOLTAGE CONVERTER
TDA4882
1.5 k
VCRT = 90 V
22 nF 2 10 M 19 CLAMP CLIPPING 20
BAV21 BFQ235
75
voltage output 33 33 220 68 k 8V
VP 3 10 k gain control
25 MHz
VOLTAGE CONVERTER
Channel 1
15 k 18 feedback 6.8 k
10 k cut-off control
1.5 k 4 BFQ236 signal input 17 5 10 M 16 voltage output 33 33 CLAMP CLIPPING current output BFQ235 10 1 k
VCRT = 90 V
BAV21
22 nF
40 MHz
220
CRT
75
10
68 k
8V 10 k cut-off control
REF GAIN VP 6 10 k contrast control VOLTAGE CONVERTER Channel 2 15
15 k BFQ256 feedback 860 VCRT = 65 V 6.8 k
VP signal input
7
+
14 current output BFQ235
BFQ236
BAV21
22 nF
8
CLAMP CLIPPING voltage output 18 18
10 1 k 47 nF 100 10
60 MHz
75
10 M 13
9 horizontal blanking switch off
VOLTAGE CONVERTER
VCRT Channel 3 BFQ256 12 feedback 10 k cut-off control 93 k
input clamping blanking PULSE DECODER
test mode ultra black output clamping
+
5.8 V VP 11 10 k
MED910
clamping pulse vertical blanking test mode
10
gain control
horizontal blanking
Fig.1 Block diagram and basic application circuit for DC and AC coupling.
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Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
PINNING SYMBOL BRC VI1 GC1 GND VI2 CC VP VI3 HBL CL GC3 FB3 VO3 IO3 FB2 VO2 IO2 FB1 VO1 IO1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION brightness control signal input Channel 1 gain control Channel 1 ground signal input Channel 2 contrast control, OSD switch supply voltage signal input Channel 3 horizontal blanking, switch-off input clamping, vertical blanking, test mode gain control Channel 3 feedback Channel 3 voltage output Channel 3 current output Channel 3 feedback Channel 2 voltage output Channel 2 current output Channel 2 feedback Channel 1 voltage output Channel 1 current output Channel 1 DC voltages are used for brightness, contrast and gain control. Brightness control yields a simultaneous signal black level shift of the three channels relative to a reference black level. For nominal brightness (pin 1 open-circuit) the signal black level is equal to the reference black level. Contrast control is achieved by a voltage at pin 6 and affects the three channels simultaneously. To provide the correct white point, an individual gain control (pins 3 and 11) adjusts the signals of Channels 1 and 3 compared to the reference Channel 2. Gain setting changes contrast as well as brightness to achieve correct grey scale tracking.
HBL 9 GND V I2 CC VP V I3 4 5 6 7 8 BR C V I1 GC1 1 2 3
TDA4882
20 I O1 19 V O1 18 FB 1 17 I O2 16 V O2
TDA4882
15 FB 2 14 I O3 13 V O3 12 FB 3 11 G C3
CL 10
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION The RGB input signals 0.7 V (p-p) are capacitively coupled into the TDA4882 (pins 2, 5 and 8) from a low ohmic source and are clamped to an internal DC voltage (artificial black level). Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below black level. Channels 1 and 3 have a maximum total voltage gain of 7 dB (maximum contrast and maximum individual channel gain), Channel 2 of 4.4 dB (maximum contrast and nominal gain). With the nominal channel gain of 1 dB and nominal contrast setting the nominal black-to-white output amplitude is 0.79 V (p-p).
Each output stage provides a current output (pins 20, 17 and 14) and a voltage output (pins 19, 16 and 13). External cascode transistors reduce power consumption of the IC and prevent breakdown of the output transistors. Signal output currents and peaking characteristics are determined by external components at the voltage outputs and the video supply. The channels have separate internal feedback loops which ensure large signal linearity and marginal signal distortion in spite of output transistor thermal VBE variation. The clamping pulse (pin 10) is used for input clamping only. The input signals have to be at black level during the clamping pulse and are
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Preliminary specification
Advanced monitor video controller for OSD
clamped to an internal artificial black level. The coupling capacitors are used in this way for black level storage. Because the threshold for the clamping pulse is higher than that for vertical blanking (pin 10) the rise and fall times of the clamping pulse have to be faster than 75 ns/V during transition from 1 V to 3.5 V. The vertical blanking pulse will be detected if the input voltage (pin 10) is higher than the threshold voltage for approximately 320 ns but does not exceed the threshold for the clamping pulse in the time between. During the vertical blanking pulse the input clamping is disabled in order to avoid misclamping in the event of composite input signals. The input signal is blanked and the artificial black level is inserted instead. Additionally the brightness is internally set to its nominal value, thus the output signal is at reference black level. The DC value of the reference black level will be adjusted by cut-off stabilization (see below). During horizontal blanking (pin 9) the output signal is set to reference black level as previously described and output clamping is activated. If the voltage at pin 9 exceeds the switch-off threshold the signal is blanked and switched to ultra black level for screen protection and spot suppression during V-flyback. Ultra black level is the lowest possible output voltage (at voltage outputs) and does not depend on cut-off stabilization. For cut-off stabilization (DC coupling to the CRT) respectively black level stabilization (AC coupling) the video signal at the cathode or the coupling capacitor is divided by an adjustable voltage divider and fed to the feedback inputs
TDA4882
(pins 18, 15 and 12). During horizontal blanking time this signal is compared with an internal DC voltage of approximately 5.8 V. Any difference will lead to a reference black level correction by charging or discharging the integrated capacitor which stores the reference black level information between the horizontal blanking pulses. For OSD fast switching of control pin 6 to less than 1 V (e.g. 0.7 V) blanks the input signals. The OSD signals can easily be inserted to the external cascode transistor (see Fig.3). During test mode (pins 9 and 10 connected to VP) the black levels at the voltage outputs (pins 19, 16 and 13) are internally set to typical 0.5 V nominal brightness, 3 V DC at signal inputs (pins 2, 5 and 8).
20
Channel 1
17 contrast
Channel 2
6 14 current output TDA4882
BFQ235
100 pF 1 k
Channel 3 PH2222 220
OSD fast blanking
OSD signal input
4.7 k PH2222 150
depending on channel gain 1 k to 10 k
Fig.3 OSD application.
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Preliminary specification
Advanced monitor video controller for OSD
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP VI Vext PARAMETER supply voltage (pin 7) input voltage (pins 2, 5 and 8) external DC voltage pins 20, 17 and 14 pins 19, 16 and 13 pins 1, 3, 6 and 11 pin 9 pin 10 IO(AV) IOM Ptot Tstg Tamb Tj VESD Notes average output current (pins 20, 17 and 14; note 1) peak output current (pins 20, 17 and 14) total power dissipation storage temperature operating ambient temperature junction temperature electrostatic handling for all pins (note 2) -0.1 -0.1 -0.1 -0.1 0 0 - -25 -20 -25 -500 VP VP VP + 0.7 VP + 0.7 50 100 1200 +150 +70 +150 +500 0 -0.1 MIN. 8.8 VP MAX.
TDA4882
UNIT V V V V V V mA mA mW °C °C °C V
no external voltages
1. Signal amplitude of 50 mA black-to-white is possible if the average current (including blanking times and signal variation against time) does not exceed 50 mA. The maximum power dissipation of 1200 mW has to be considered. 2. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rthj-a PARAMETER thermal resistance from junction to ambient in free air VALUE 65 UNIT K/W
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
CHARACTERISTICS VP = 8.0 V; Tamb = +25 °C; all voltages measured to GND (pin 4); note 1; see also Fig.4; unless otherwise specified. SYMBOL VP IP VI(b-w) PARAMETER supply voltage (pin 7) supply current (pin 7) CONDITIONS MIN. 7.2 36 - TYP. 8.0 48 MAX. 8.8 60 V mA UNIT
Video signal inputs (Channel 1: pin 2, Channel 2: pin 5 and Channel 3: pin 8) input voltage (black-to-white value; pins 2, 5 and 8) DC voltage during input clamping (artificial black + VBE) DC input current no clamping; VI2, 5, 8 = VI(cl)2, 5, 8; Tamb = -20 to +70 °C during clamping; VI2, 5, 8 = VI(cl)2, 5, 8 ± 0.7 V Brightness control (pin 1); note 2; see Fig.5 V1 R1 V1(nom) Vbl input voltage input resistance input voltage for nominal brightness pin 1 open-circuit 1.0 40 2.0 -13 30 - - 50 2.25 -11 34 - 6.0 60 2.5 -9.5 37 0.8 V k V % % % 0.7 1.0 V
VI(cl)2, 5, 8
2.8
3.1
3.4
V
II2, 5, 8
-0.05
+0.05
+0.250
µA
±50
±75
±120
µA
black level voltage change V1 = 1.0 V at voltage outputs referred V1 = 6.0 V to reference black level pin 1 open-circuit during output clamping (V9 > 1.6 V) related to output signal amplitude with nominal 0.7 V (p-p) input signal and nominal contrast (V6 = 4.3 V) for any gain setting difference of Vbl between any two channels
VBT
-
0
±1.2
%
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
SYMBOL
PARAMETER
CONDITIONS
MIN. - -
TYP.
MAX.
UNIT
Contrast control (pin 6); note 3; see Fig.6 V6 V6(max) V6(nom) I6 Cc input voltage maximum input voltage input voltage for nominal contrast input current contrast relative to nominal contrast note 4 V6 = 4.3 V V6 = 6.0 V; pins 3 and 11 open-circuit V6 = 1.0 V; pins 3 and 11 open-circuit V6(min) TRO tdfC input voltage for minimum contrast tracking of output signals of Channels 1, 2 and 3 delay between leading edges (falling) of step in contrast voltage and output signals at voltage outputs (pins 19, 16 and 13) delay between trailing edges (rising) of step in contrast voltage and output signals at voltage outputs (pins 19, 16 and 13) pins 3 and 11 open-circuit 1 V < V6 < 6 V; note 5 V6 = 4.3 V to 0.7 V; input fall time at pin 6: tfCC = 2 ns; Fig.7; note 6 1.0 - - -5 2.4 -26 - - - 6.0 VP - 1 - -0.1 - -19 - 0.5 20 V V V µA dB dB V dB ns
4.3 -1 3.4 -22 0.7 0 7
tdrC
V6 = 0.7 V to 4.3 V; input rise time at pin 6: trCC = 2 ns; Fig.7; note 6
-
15
25
ns
tfC
fall time of output signals at 90% to 10% amplitude; voltage outputs (pins 19, 16 input fall time at pin 6: and 13) tfCC = 2 ns; Fig.7; note 6 rise time of output signals at voltage outputs (pins 19, 16 and 13) 10% to 90% amplitude; input rise time at pin 6: trCC = 2 ns; Fig.7; note 6
-
6
15
ns
trC
-
6
15
ns
Gain control (pin 3 for Channel 1 and pin 11 for Channel 3); Fig.8; note 7 V3, 11 V3, 11(nom) R3, 11 G input voltage input voltage for nominal gain input resistance gain control difference relative to nominal gain (Channels 1 and 3 only) V6 = 4.3 V; V3, 11 = 6 V V6 = 4.3 V; V3, 11 = 1 V pins 3 and 11 open-circuit 1.0 3.6 44 2 -5.5 - 3.75 55 2.6 -5 6.0 3.95 66 3.3 -4.5 V V k dB dB
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Feedback input (Channel 1: pin 18, Channel 2: pin 15 and Channel 3: pin 12); Fig.9; note 8 Vref IO18, 15, 12(max) Vbl(CRT) Vref(T) Vref(VP) internal reference voltage maximum output current during output clamping; V18, 15, 12 = 3 V Tamb = -20 to +70 °C 7.2 V VP 8.8 V 5.6 -500 0 0 0 5.8 -100 40 20 60 6.1 -60 200 50 100 V nA mV mV mV
black level variation at CRT note 9 variation of Vref in the temperature range variation of Vref with supply voltage
Voltage outputs (Channel 1: pin 19, Channel 2: pin 16 and Channel 3: pin 13) VO(b-w) nominal signal output voltage (black-to-white value) maximum adjustable black level voltage black level voltage during switch-off, equal to minimum adjustable black level voltage black level voltage during test mode signal-to-noise ratio output thermal distortion black level variation between clamping pulses maximum offset during sync clipping variation of nominal output signal (black-to-white value) with temperature pins 3 and 11 open-circuit; V6 = 4.3 V; VI(b-w) = 0.7 V during output clamping; Tamb = -20 to +70 °C V9 = VP; RO = 33 ; Tamb = -20 to +70 °C 0.69 0.79 0.89 V
Vblx(max) Vbl(SO)
1 30
1.2 45
1.4 100
V mV
Vbl(TST)
V9 = VP; V10 = VP; pin 1 0.3 open-circuit; VI2, 5, 8 = VI(cl)2, 5, 8; note 10 note 11 IO(b-w) = 50 mA; note 12 line frequency 30 kHz VI2, 5, 8 < VI(cl)2, 5, 8; Fig.10; note 13 pins 3 and 11 open-circuit; V6 = 4.3 V; VI(b-w) = 0.7 V; Tamb = -20 to +70 °C - - - 0 0
0.7
1.2
V
S/N dO(th) Vbl(fl) Voff VO(b-w)(T)
50 0.6 0.5 7 2.5
44 1 4.5 15 10
dB % mV mV %
Current outputs (Channel 1: pin 20, Channel 2: pin 17 and Channel 3: pin 14); note 14 IO(b-w) V20-19; V17-16; V14-13 Ibl(SO) output current (black-to-white value) - with peaking - - - 0 50 - - - 20 - 100 2.0 2.2 900 mA mA V V µA
start of HF-saturation IO = 50 mA voltage of output transistors IO = 100 mA output current during switch-off V9 = VP; RO = 33
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
SYMBOL G(f)
PARAMETER
CONDITIONS -
MIN.
TYP.
MAX.
UNIT
Frequency response at voltage outputs (Figs 11, 12 and 13; note 15) gain decrease by frequency 70 MHz; single channel response at pins 19, 16 and 13 rise time at voltage output (pins 19, 16 and 13) overshoot of output signal pulse related to actual output pulse amplitude 10% to 90% amplitude; input rise time = 1 ns single channel; input rise time = 2.5 ns; VI(b-w) = 0.7 V; pins 3 and 11 open-circuit; V6 = 4.3 V 1.3 3 dB
tr(O) dVO
- -
4.1 4
5.0 8
ns %
Crosstalk at voltage outputs with speed up circuit (Figs 14, 15 and 16; note 16) cr(tr) V9 transient crosstalk - - 0.1 -
Threshold voltages for clamping, blanking and switch-off (pins 9 and 10); note 17 threshold for horizontal blanking (blanking, output clamping) threshold for switch-off (blanking, minimum black level, no output clamping) R9 td9 input resistance delay between horizontal blanking input and output signal blanking threshold for vertical blanking (blanking, no input clamping) threshold for clamping (input clamping, no blanking) threshold for test mode (no clamping, no blanking, for Vbl(TST) see above) I10 tr, f10 tw10 td10 current rise and fall time for clamping pulse width of clamping pulse delay between vertical blanking input and internal blanking Fig.18; note 19 against ground input rise time at pin 9 > 100 ns; Fig.17; note 18 Fig.18; note 19 1.2 1.4 1.6 V
5.8
6.5
6.8
V
50 -
80 40
110 60
k ns
V10
1.2
1.4
1.6
V
Fig.18; note 19
2.6
3.0
3.5
V
for test mode also V9 > 6.8 V (switch-off) V10 < VP - 1 V V10 VP - 1 V Fig.18; note 19
VP - 1
-
VP
V
-3 - - 0.6 260
-1 100 - - 320
- - 75 - 380
µA µA ns/V µs ns
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Preliminary specification
Advanced monitor video controller for OSD
Notes to the characteristics 1. Definition of levels:
TDA4882
a) Artificial black level: internal signal level behind input emitter follower during input clamping and signal clipping. This level is inserted instead of the input signal during blanking. b) Reference black level: DC voltage during output clamping at voltage outputs, not influenced by brightness, contrast or gain setting, adjustable by cut-off stabilization. c) Cut-off level: corresponding DC voltage at CRT cathode in closed feedback loop. d) Black level: actual signal black level at either voltage outputs or cathode, can be adjusted by (brightness × gain), refers to reference black level or cut-off level respectively. e) Ultra black level, switch-off level: lowest adjustable reference black level, lowest signal level at voltage outputs. f) The minimum guaranteed control range for reference black level is 0.1 to 1 V. The ultra black level is depending on the external resistor RO at voltage outputs (pins 13, 16 and 19) to ground. RO g) V bl ( SO ) ------------------------------- × 4.65 V 3.5 k + R O 2. Linear control range is 1 to 6 V for V1, independent from supply voltage. 3. Linear control range is 1 to 6 V for V6, independent from supply voltage. Open pin 6 leads to absolute maximum contrast setting. It is recommended to not exceed V6 = VP - 1 V in order to avoid saturation of internal circuitry. For V6 < V6(min) 0.7 V a small negative signal ( -40 dB) will appear. For frequency dependency of contrast control see note 15. 4. Definition for nominal output signals: input VI(b-w) = 0.7 V, gain pins 3 and 11 open-circuit, contrast control V6 = V6(nom). 5. A 1 A 20 A 1 A 30 A 2 A 30 Tr = 20 × maximum of log -------- × -------- ; log -------- × -------- ; log -------- × -------- [dB] A 10 A 2 A 10 A 3 A 20 A 3 Ax: signal output amplitude in Channel x at any contrast setting between 1 and 6 V. Ax0: signal output amplitude in Channel x at nominal contrast and same gain setting. 6. Typical step in contrast voltage and response at signal outputs for nominal input signal VI(b-w) = 0.7 V (OSD fast blanking input/output). 7. Linear control range is 1 to 6 V for V3 and V11, independent from supply voltage. 8. The internal reference voltage can be measured at pins 18, 15 and 12 during output clamping (V9 = 2 V) in closed feedback loop. 9. Slow variations of video supply voltage VCRT (see Fig.1) will be suppressed at CRT cathode by cut-off stabilization. Change of VCRT by 5 V leads to specified change of cut-off voltage. 10. The test mode allows testing without input and output clamping pulses. The signal inputs (pins 2, 5 and 8) have to be biased via resistors to the previously measured clamp voltages of approximately 3 V (artificial black level + VBE). Signal and brightness blanking is not possible during test mode. The output currents (pins 10, 17 and 14) should be adjusted by resistors >> R0 from voltage outputs to a positive voltage (e.g. VP). 11. The signal-to-noise ratio is calculated by the formula (frequency range 1 to 70 MHz): peak-to-peak value of the nominal signal output voltage S --- = 20 log -------------------------------------------------------------------------------------------------------------------------------------------------- [dB] RMS value of the noise output voltage N 12. Large output swing e.g. IO(b-w) = 50 mA leeds to signal depending power dissipation in output transistors. Thermal VBE variation is compensated. 13. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below black level.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
1 1 14. The output current approximately follows the equation I O = V O ------- + ----------------- 500 µA for VO > Vbl(SO) and with R O 2.2 k RO = external resistor at voltage output to ground. The external RC combination at pins 19, 16 and 13 (see Fig.1) enables peak currents during transients. 15. Frequency response, crosstalk and pulse response have been measured at voltage outputs in a special printed-circuit board with 50 line in/out connections and without peaking (see Chapter "Application information / test"). 16. Crosstalk between any two output pins. a) Input conditions: one channel (Channel A) with nominal input signal and minimum rise time. The inputs of the other channels capacitively coupled to ground (Channel B). Gain pins 3 and 11 open-circuit. b) Output conditions: output signal of Channel A controlled by contrast setting (pin 6) to VO(b-w) = VA = 0.7 V, the rise time should be 5 ns. Output signal of Channel B then is VO(b-w) = VB. VB c) Transient crosstalk: cr ( tr ) = -----VA d) Crosstalk as a function of frequency has been measured without peaking circuit, with nominal input signal and nominal settings. 17. The internal threshold voltages are derived from a stabilized voltage. The internal pulses are generated while the input pulses are higher than the thresholds. Voltages of less than -0.1 V at pins 9 and 10 can influence black level control and should be avoided. 18. The delay between horizontal blanking input at pin 9 (HBL pulse) and output signal blanking as well as brightness blanking (Vbl) at pins 19, 16 and 13 depends on the input rise time of the HBL pulse. The specified values for td9 are valid for HBL rise times greater than 100 ns only. 19. For 75 ns/V < trf10 < 240 ns/V generation of internal input clamping and blanking pulse is not defined. Any pulses not exceeding the threshold of input clamping (typical 3 V) will be detected as blanking pulse.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
input signals
input signal at pins 2, 5 and 8 with sync (on green) input clamping pulse at pin 10 horizontal blanking and output clamping pulse at pin 9 internal signal behind input stage sync clipping to artificial black level
video signal black level equal to artificial black level + VBE by input clamping (approximately 3 V)
video portion
horizontal flyback and output clamping black level equal to artificial black level by input clamping and storage by coupling capacitor inserted artificial black level max. nom. min. black level due to brightness setting reference black level brightness is set to nominal value during horizontal blanking max. nom.
output signals (pins 19, 16 and 13)
at nominal gain and contrast setting and maximum/nominal/minimum brightness setting
at nominal gain and maximum brightness setting and maximum/nominal/minimum contrast setting
min.
max. nom. at nominal contrast and maximum brightness setting and maximum/nominal/minimum gain setting min.
black level for maximum brightness reference black level
grey scale
reference black level ultra black level ground high tension supply voltage (e.g. 90 V) (raster) cut-off level black level
signal at CRT cathode
at nominal gain and contrast setting and maximum brightness setting
grey scale
Fig.4 Signal processing.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
50 Vbl (%) 40
400 (mV) 300
30 200 20
100 10
0
0
-10
-100
-20 -200 0 1 2 2.24 3 4 5 6 7 V1 (V) 8
Fig.5 Typical brightness characteristic.
signal amplitude (mV)
1400
(dB) 4
1200
3 2 1
1000
800
0 -1
600
-3 -5
400 -10 200 -20 0 -40
-200 0 0.7 1 2 3 4 4.3 5 6 7 V6 (V) 8
Fig.6 Typical contrast characteristic.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
OSD pulse at pin 6 (V) tfCC 4.3 trCC 90% 50% 0.7 output signal at pins 19, 16 and 13 (V) bl + VO(b-w) = 1.5 VO(b-w) 10% t tdfC tdrC 90% 50% 10% tfC trC t
bl = 0.7
Fig.7 Typical OSD fast blanking input/output waveforms.
1200 signal amplitude (mV) 1000 1 0 800 -1 -2 600 -3 -4 -5 400 -6 -8 3 (dB) 2
200 0 1 2 3 4 3.75 5 6 7 V3, V11 (V) 8
Fig.8 Typical gain characteristic.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
5.84 Vref (V) 5.83 VP = 8.8 V
5.82
5.81
VP = 8.0 V
5.8
5.79
5.78 VP = 7.2 V 5.77
5.76
5.75 -20 0 20 40 60 80 Tamb (°C) 100
Conditions: 0.5 V reference black level, no signal.
Fig.9 Typical variation of Vref with temperature and power supply voltage.
/user/v8860/v1/measurements/data/pic/feedback_100_p Re/Ko-Je/12.04.94
input signal
output signal
Voff e.g. with sync on green
Fig.10 Typical sync clipping.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
signal amplitude (dB) 0
-3
-6
-9
-12
-15 1 single channel 10 100 200
frequency (MHz)
white signal
Fig.11 Typical frequency response.
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Advanced monitor video controller for OSD
TDA4882
800 input pulse (mV) 600 90%
400 rise time 2.5 ns 200 10% 0 fall time 2.5 ns
1000 output pulse at voltage outputs 800 (mV) 90%
600
400 rise time 4.4 ns 200 10% 0 fall time 4.8 ns
-200 0 20 white pattern single channel 40 60 80 100 t (ns)
Fig.12 Typical pulse responses.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
10 signal amplitude (dB) 5
V6 =
7V 6V 5V
0 4V 3V -5 2V -10
-15 V6 = 0.7 V -20 1V -25 V6 = 0.7 V -30 1 single channel white signal 10 frequency (MHz)
70
100
120
Fig.13 Typical characteristic of contrast control as a function of frequency.
signal amplitude (dB)
5 0 channel -5 1
-10 -15 -20 2 -25 3 -30 -35 -40 -45 1 10 frequency (MHz) 100 200
Fig.14 Typical crosstalk: Channel 1 2 and 3.
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
signal amplitude (dB)
5 0 -5 channel 2
-10 -15 -20 -25 -30 -35 -40 -45 1 10 frequency (MHz) 100 200 3
1
Fig.15 Typical crosstalk: Channel 2 1 and 3.
signal amplitude (dB)
5 0 channel -5 3
-10 -15 -20 1 -25 2 -30 -35 -40 -45 1 10 frequency (MHz) 100 200
Fig.16 Typical crosstalk: Channel 3 1 and 2. December 1994 20
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Preliminary specification
Advanced monitor video controller for OSD
TDA4882
delay (ns)
80 70
HBL pulse (V) 1.45 0.2
60 50 40 30
delay1 at begin of brightness blanking
rise time output signal (V) (bl) 0.74 Vbl delay1 delay2
t
delay2 at end of brightness blanking
20 20 40 60 80 100 120 140 rise (fall) time for HBL from 0.2 V to 1.45 V (ns)
50% of Vbl t
(rbl) 0.5 bl = black level rbl = reference black level
Fig.17 Typical delay between HBL pulse and brightness blanking at voltage outputs.
/user/v8860/v1/measurements/data/pic/hbl2_p Ko-Je/13.04.94
3V V 10 tr,f10 75 ns/V tr,f10 > 240 ns/V 1.4 V
t
internal pulses input clamping no clamping
1/2td10
no clamping t
blanking
td10
t
Fig.18 Timing of pulses at pin 10.
December 1994
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Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
APPLICATION INFORMATION / TEST For high frequency measurements a special application and printed-circuit board with only a few external components is built. Figure 19 shows the application circuit and Fig.20 the layout of the double sided printed board. All components on the rear (below) are of SMD type as well as R13, R14 and R15 on the front. Short HF loops and minimum crosstalk between the channels as well as input and output are achieved by properly shaped ground areas star connected to the IC ground pin. The HF input signal can be fed to the subclick connectors X1, X2 and X3 by a 50 line. The line is then terminated by a 51 resistor on the board. With choice of jumper connections (JA1, JA2 and JA3) it is possible to connect channel inputs to its input connector, to connect all channels to one input connector (white pattern) and to ground each input via the coupling capacitor. For operation without input clamping (e.g. test mode) the DC bias can be provided by VIDC (connector X21) if a short-circuit at JA4, JA5 and JA6 is made (solder short or small SMD resistor). The output signal can be monitored via 50 terminated lines at the voltage outputs (subclick connectors X4, X5 and X6). With 100 in parallel to the 50 terminated line the effective load resistance at the voltage outputs is 33 .
TDA4882
The mismatch seen from the line towards the IC has no significant effect if the line is match terminated. A peaking circuit (C15, R16 Channel 1) can be added for realistic loading of the voltage outputs. Black level adjustment is done by VIOS, UFBX (connector X21) and resistors R19, R22 and R25 (Channel 1). If R19 is equal to the effective load resistor at the voltage output the reference black level is approximately: U REF = VIOS V ( IO1 ) and R22 V ( IO1 ) = V int + ( V int UFBX ) × ---------R25 Vint is the internal reference voltage at the feedback input (typical 5.8 V). By this it is possible to adjust the reference black level and the voltage at the current outputs independently. DC control for brightness, contrast and gain is prepared at connectors X21 and X22. Contrast control can also be set by the potentiometer P1 (jumper JA11). The series resistor R11 is necessary if fast OSD switching is activated via 50 line (X10), a line termination can be done at the connector X9. Clamping and blanking pulses are fed to the IC via connectors X7 and X8. Connector X23 is used for power supply. The capacitors C7 and C8 should be located as near as possible to the IC pins.
December 1994
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Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
TDA4882
subclick connector (50 ) solder points for short-circuiting or SMD 0 resistor connector pin jumper R7 110 C4 100 nF R19 33 C21 22 nF X4 C24 100 nF X21 E2 220 µF (25 V) C29 2.2 µF (multi layer) C28 100 nF C27 22 nF BRC/GC2 GC1 GND (sense) VIDC UFBX VIOS
1
C5 22 nF VI1 JA1
BRC /GC2
IO1
20
2
X1 R1 51 C1 22 nF JA4
VI1
VO1
19
C15 47 pF R13 100 R22 3 k R25 9.1 k C18 22 nF
R4 5.1 k C12 22 nF
3
C6 22 nF
GC1
FB1
18
R16 33
4
GND
IO2
17
R20 33 C22 22 nF C25 100 nF
TDA4882
VI2
JA2
X5
5
X2 R2 51 C2 22 nF JA5 R5 5.1 k C13 22 nF
VI2
VO2
16
C16 47 pF R14 100 R17 33 R23 3 k R26 9.1 k C19 22 nF
6
CC
FB2
15
7
C8 100 nF C7 1 nF
VP
IO3
14
R21 33 C23 22 nF X6 C26 100 nF
VI3
JA3
8
X3 R3 51 C3 22 nF JA6 R6 5.1 k C14 22 nF
VI3
VO3
13
C17 47 pF R15 100 R18 33 R24 3 k R27 9.1 k C20 22 nF
9
HBL
FB3
12
X22 GC3
10
CL
GC3
11
C11 22 nF
CC R10 1 k E1 10 µF C9 100 nF C10 100 nF R11 1 k JA10 JA11 P1 10 k X23 X9 OSD VP X10 GND (sense)
L1 R8 1 k R9 1 k 100 µH
R12 1 k VP (sense)
X7
X8
HBL
CL
GND (power)
Fig.19 Application circuit for test PCB.
v8860/pic/messplatine_p Re/07.03.94
December 1994
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Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
TDA4882
handbook, full pagewidth
E2
C29
X22 JA11 JA12 P1
X4
X5
X6 X10
R13 X21 R7
R14
R15 E1 X9 L1
IC1
X23
X8 JA1 JA2 JA3 X7 X1 X2 X3
R1
R2
R3
R8
R4 C12 C1 JA4 C5 R22 C4 C6 C2
R5 C14 R6 C3 C13 JA5 C8 R23 JA6 C7 R24 R9 C9 C11 C17 R18 R27 R11 R12 R18
R19 C15 R25 R20 C16 R26 R21 R16 C21 C24 C18 C22 C25 C19 R17 C23 C26
C20
C28
C27 C16
MLC783
Fig.20 Double sided test PCB layout.
December 1994
24
Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
RECOMMENDATIONS FOR BUILDING THE APPLICATION BOARD General · Double-sided board · Short HF loops by large ground plane on the rear. Voltage outputs · Capacitive loads as small as possible · Short interconnection via resistor to ground. Supply voltage
TDA4882
· Capacitors as near as possible to the pins · Use of high-frequency capacitors (low self inductance, e.g. SMD). Current outputs, emitter of cascode transistors · The external interconnection inductivity can build a resonance together with the internal substrate capacity, a damping resistor of 10 to 30 near to the IC pin can suppress such oscillations.
20
19 CL
18
17
16 CL
15
14
13 CL
12
11
TDA4882
CL CL CL
+ 1 2 3 4 5 6 7 8 9 10
MED911
+
diode protection on all pins except pins 4 and 7
zener diode protection at pin 7
Fig.21 Internal circuits.
December 1994
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full pagewidth
Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
PACKAGE OUTLINE
TDA4882
seating plane
26.92 26.54 3.2 max 4.2 max
8.25 7.80
3.60 3.05 2.0 max 0.53 max 1.73 max
0.51 min 2.54 (9x) 0.254 M 0.38 max 7.62 10.0 8.3
MSA258
20
11 6.40 6.22
1
10
Dimensions in mm.
Fig.22 Plastic dual in-line package; 20 leads (300 mil); DIP20; SOT146-1.
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s. December 1994 26
Philips Semiconductors
Preliminary specification
Advanced monitor video controller for OSD
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4882
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
December 1994
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