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TOSHIBA 27" TFT TV (17MB15) SERVICE MANUAL
TABLE OF CONTENTS
1. INTRODUCTION ...................................................................................................................................... 1 2. TUNER...................................................................................................................................................... 1 3. IF PART (TDA9886) ................................................................................................................................. 1 4. MULTI STANDARD SOUND PROCESSOR ............................................................................................ 2 5. VIDEO SWITCH TEA6415 ....................................................................................................................... 2 6. AUDIO AMPLIFIER STAGE WITH TPA3002D2 ...................................................................................... 2 7. POWER SUPPLY (SMPS) ....................................................................................................................... 3 8. MICROCONTROLLER ............................................................................................................................. 5 9. EEPROM 24LC32..................................................................................................................................... 5 10. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ......................................................................... 5 11. SAW FILTERS.......................................................................................................................................... 6 12. IC DESCRIPTIONS .................................................................................................................................. 7 12.1. TEA6415C ......................................................................................................................................... 8 12.2. 24LC02 .............................................................................................................................................. 9 12.3. 24LC32 ............................................................................................................................................ 10 12.4. 74LVC14A ....................................................................................................................................... 11 12.5. TEA6420.......................................................................................................................................... 12 12.6. CS4334............................................................................................................................................ 12 12.7. DS90C385 ....................................................................................................................................... 13 12.8. GAL16LV8 ....................................................................................................................................... 14 12.9. K6R4008V1D................................................................................................................................... 15 12.10. L6562............................................................................................................................................... 17 12.11. LM1086............................................................................................................................................ 17 12.12. LM1117............................................................................................................................................ 18 12.13. LM317.............................................................................................................................................. 19 12.14. LM809.............................................................................................................................................. 19 12.15. MSP34X0G (MSP3410G) ............................................................................................................... 20 12.16. M29W040B...................................................................................................................................... 23 12.17. MC33202 ......................................................................................................................................... 24 12.18. PCF8574 ......................................................................................................................................... 25 12.19. PI5V330........................................................................................................................................... 26 12.20. SDA55XX (SDA5550)...................................................................................................................... 26 12.21. SG3525A ......................................................................................................................................... 26 12.22. Sil 9993............................................................................................................................................ 27 12.23. NCP1014 ......................................................................................................................................... 28 12.24. SN74CB3Q3305.............................................................................................................................. 29 12.25. ST24LC21 ....................................................................................................................................... 30 12.26. LM2576............................................................................................................................................ 30 12.27. MC34063 ......................................................................................................................................... 31 12.28. TDA1308 ......................................................................................................................................... 32 12.29. TDA9886 ......................................................................................................................................... 32 12.30. TPA3002D2 ..................................................................................................................................... 34 12.31. µPA672T.......................................................................................................................................... 36 12.32. VPC3230D....................................................................................................................................... 36 13. SERVICE MENU SETTINGS ................................................................................................................. 39 14. BLOCK DIAGRAM.................................................................................................................................. 41 15. CIRCUIT DIAGRAMS ............................................................................................................................. 42
i 27" TFT TV Service Manual 10/10/2005
1. INTRODUCTION
27" TFT TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 1280*720 panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I', and L/L' including German and NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8 speakers. The chassis is equipped with many inputs and outputs allowing it to be used as a center of a media system. It supports following peripherals: 2 SCART sockets 1 AV input (CVBS + Stereo Audio) 1 SVHS input 1 Stereo Headphone input 1 Component input (YPbPr + Stereo Audio) 1 D-Sub 15 PC input 1 HDMI input 1 Stereo audio input for PC 1 Stereo audio output 1 Subwoofer output
2. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L', I/I', and D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on one of the Tuners in use. General description of UV1316: The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L', I and I'. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient. Features of UV1316: 1. Member of the UV1300 family small sized UHF/VHF tuners 2. Systems CCIR: B/G, H, L, L', I and I'; OIRT: D/K 3. Digitally controlled (PLL) tuning via I2C-bus 4. Off-air channels, S-cable channels and Hyperband 5. World standardised mechanical dimensions and world standard pinning 6. Compact size 7. Complies to "CENELEC EN55020" and "EN55013" Pinning: 1. Gain control voltage (AGC) 2. Tuning voltage 3. I˛C-bus address select 4. I˛C-bus serial clock 5. I˛C-bus serial data 6. Not connected 7. PLL supply voltage 8. ADC input 9. Tuner supply voltage 10. Symmetrical IF output 1 11. Symmetrical IF output 2 : : : : : : 4.0V, Max: 4.5V Max: 5.5V Min:-0.3V, Max: 5.5V Min:-0.3V, Max: 5.5V 5.0V, Min: 4.75V, Max: 5.5V 33V, Min: 30V, Max: 35V
3. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL. The following figure shows the simplified block diagram of the integrated circuit. The integrated circuit comprises the following functional blocks: VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and 1 27" TFT TV Service Manual 10/10/2005
acquisition help, Audio amplifier and mute time constant, I˛C-bus transceivers and MAD (module address), Internal voltage stabilizer.
4. MULTI STANDARD SOUND PROCESSOR
The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analogue TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analogue sound IF signal-in, down to processed analogue AF-out, is performed on a single chip. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
5. VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC TEA6415 is used. The main function of this device is to switch 8 video-input sources on the 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of sync. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible to have the same input connected to several outputs.
6. AUDIO AMPLIFIER STAGE WITH TPA3002D2
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 . The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music.
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7. POWER SUPPLY (SMPS)
The required DC voltages; at various parts of the chassis; are provided by an SMPS (switch mode power supply). Block diagram of SMPS as follows;
Connector layout as follows
SMPS can work between 160V 240 V AC and generate following voltages 24 V FOR INVERTER (BACK LIGHT) 12 V FOR AUDIO 5V AND 3.3 V FOR IMAGE NCP 1014 (IC 806) IC 806 generated 3.3V stby and 5 V stby. The features of the IC as follows, Current mode Fixed Frequency Operation 65 Khz Skip-Cycle operation at Low Peak Current .(Mainly at stand by operation Internal 1ms Soft Start Latched Overvoltage Protection with Auxiliary Winding Operation Auto-Recovery Internal Output Short-Circuit operation
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L6562 (IC 802) L6562 is ST PFC (Power Factor Controller) IC. That is keep voltage constant at 400VDC on BULK cap. If VDC is not 400V, No any voltage can not get from output at secondary side. The features of IC as follows,
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SG3525 (IC 807) Main SMPS control. SG 3525 is using as resonant mode power supply controller. System working as ZCS (Zero current switch) mode. The working frequency range of system is between 50-150 Khz. Main working (Resonant frequency) is 60-70 Khz.
8. MICROCONTROLLER
The Micronas SDA 55xx TV microcontroller is dedicated to 8 bit applications for TV control and provides dedicated graphic features designed for modern low class to mid range TV sets. The SDA 55xx provides also an integrated general purposefully 8051-compatible microcontroller with specific hardware features especially suitable in TV sets. The microcontroller core has been enhanced to provide powerful features such as memory banking, data pointers and additional interrupts, etc. The internal XRAM consists of up to 16 kBytes. The microcontroller provides an internal ROM of up to 128 kBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The 8-bit microcontroller runs at 33.33 MHz internal clock. SDA 55xx is realized in 0.25 micron technology with 2.5 V supply voltage for the core and 3.3 V for the I/O port pins to make them TTL compatible. Based on the SDA 55xx microcontroller the MINTS software package was developed and provides dedicated device drivers for many Micronas video & audio products and includes a full blown TV control SW for the PEPER application chassis. The SDA 55xx is also supported with powerful design tools like emulators from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler and TEDIpro OSD development SW by Tara Systems.
9. EEPROM 24LC32
The Microchip Technology Inc. 24AA32A/24LC32A(24XX32A*) is a 32 Kbit Electrically Erasable PROM. The device is organized as four blocks of 8K x 8-bitmemory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.8V, with standby and active currents of only 1µA and 1mA, respectively. It has been developed for advanced, low-power applications such as personal communications or data acquisition. The 24XX32A also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 256Kbits address space.
10. CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.
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11. SAW FILTERS
K9656M: Standard: · B/G · D/K ·I · L/L' Features · TV IF audio filter with two channels · Channel 1 (L') with one pass band for sound carriers at 40.40 MHz (L') and 39.75 MHz (L'- NICAM) · Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32.35 MHz and 33.40 MHz Terminals · Tinned CuFe alloy Pin configuration 1 Input 2 Switching input 3 Chip carrier - ground 4 Output 5 Output K3958M: Standard: · B/G · D/K ·I · L/L' Features · TV IF video filter with Nyquist slopes at 33.90 MHz and 38.90 MHz · Constant group delay Terminals Tinned CuFe alloy Pin configuration 1 Input 2 Input - ground 3 Chip carrier - ground 4 Output 5 Output
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12. IC DESCRIPTIONS
IC List: TEA6415C 24LC02 24LC32 74LVC14A TEA6420D CS4334 DS90C385 GAL16LV8 K6R4008V1 L6562D LM1086 LM1117 LM317T LM809 MSP3411G M29W040B MC33202 PCF8574 PI5V330 SDA5550 SG3525 SII9993 NCP1014 SN74CB3Q3305 ST24LC21 LM2576 MC34063 TDA1308 TDA9886T TPA3002D2 µPA672T VPC3230D
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12.1.
TEA6415C
12.1.1. General Description The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75 load needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration. 12.1.2. Features · 20MHz Bandwidth · Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage) · 8 Inputs (CVBS, RGB, MAC, CHROMA,...) · 6 Outputs · Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge · Bus controlled · 6.5dB gain between any input and output · 55dB crosstalk at 5mHz · Fully ESD protected 12.1.3. Pinning Input : Data : Input Clock Input Input Prog Input Vcc Input Input Ground Output Output Output Output Output Output Ground Input : : : : : : : : : : : : : : :
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
Max Low level High level Max Low level High level Max Max Max 12V Max Max 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp, 5.5Vpp,
: 2Vpp, Input Current: 1mA, Max : 3mA : -0.3V Max: 1.5V, : 3.0V Max : Vcc+0.5V : 2Vpp, Input Current: 1mA, Max : 3mA : -0.3V Max: 1.5V, : 3.0V Max : Vcc+0.5V : 2Vpp, Input Current: 1mA, Max : 3mA : 2Vpp, Input Current: 1mA, Max : 3mA
: 2Vpp, Input Current: 1mA, Max: 3mA : 2Vpp, Input Current: 1mA, Max : 3mA : 2Vpp, Input Current: 1mA, Max : 3mA Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp Min : 4.5Vpp Max : 2Vpp, Input Current : 1mA, Max : 3mA
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12.2.
24LC02
12.2.1. Description The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.8V, with standby and active currents of only 1µA and 1mA, respectively. The 24XX02 also has a page write capability for up to 8 bytes of data. 12.2.2. Features · Single supply with operation down to 1.8V · Low-power CMOS technology -1mA active current typical -1µA standby current typical (I-temp) · Organized as 1 block of 256 bytes (1 x 256 x 8) · 2-wire serial interface bus, I2CTM compatible · Schmitt Trigger inputs for noise suppression · Output slope control to eliminate ground bounce · 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility · Self-timed write cycle (including auto-erase) · Page write buffer for up to 8 bytes · 2ms typical write cycle time for page write · Hardware write-protect for entire memory · Can be operated as a serial ROM · Factory programming (QTP) available · ESD protection > 4,000V · 1,000,000 erase/write cycles · Data retention > 200 years · 8-lead PDIP, SOIC, TSSOP and MSOP packages · 5-lead SOT-23 package · Pb-free finish available · Available for extended temperature ranges: -Industrial (I): -40°C to +85°C -Automotive (E): -40°C to +125°C 12.2.3. Pinning
9 27" TFT TV Service Manual 10/10/2005
12.3.
24LC32
12.3.1. General Description The Microchip Technology Inc. 24AA32A/24LC32A(24XX32A*) is a 32 Kbit Electrically Erasable PROM. The device is organized as four blocks of 8K x 8-bitmemory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.8V, with standby and active currents of only 1µA and 1mA, respectively. It has been developed for advanced, low-power applications such as personal communications or data acquisition. The 24XX32A also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 256Kbits address space. 12.3.2. Features · Single supply with operation down to 1.8V · Low-power CMOS technology -1mA active current typical -1µA standby current typical (I-temp) · Organized as 4 block of 8K bits (32K bit) · 2-wire serial interface bus, I2CTM compatible · Schmitt Trigger inputs for noise suppression · Output slope control to eliminate ground bounce · 100 kHz (<2.5V) and 400 kHz (2.5V) compatibility · Self-timed write cycle (including auto-erase) · Page write buffer for up to 8 bytes · 2ms typical write cycle time for page write · Hardware write-protect for entire memory · Can be operated as a serial ROM · Factory programming (QTP) available · ESD protection > 4,000V · 1,000,000 erase/write cycles · Data retention > 200 years · 8-lead PDIP, SOIC, TSSOP and MSOP packages · 5-lead SOT-23 package · Standard and Pb-free finishes available · Available for extended temperature ranges: -Industrial (I): -40°C to +85°C -Automotive (E): -40°C to +125°C 12.3.3. Pinning
10 27" TFT TV Service Manual 10/10/2005
12.4.
74LVC14A
12.4.1. Description The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5V environment. The 74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 12.4.2. Features · Wide supply voltage range from 1.2 to 3.6 V · CMOS low power consumption · Direct interface with TTL levels · Inputs accept voltages up to 5.5 V · Complies with JEDEC standard no.8-1A · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V. · Specified from -40 to +85C and -40 to +125C. 12.4.3. Pinning
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12.5.
TEA6420
12.5.1. Features · 5 Stereo Inputs · 4 Stereo Outputs · Gain Control 0/2/4/6dB/Mute for each Output · Cascadable (2 different addresses) · Serial Bus Controlled · Very low Noise · Very low Distortion 12.5.2. Description The TEA6420 switches 5 stereo audio inputs on4stereo outputs. All the switching possibilities are changed through the I2C bus. 12.5.3. Pin Connections
12.6.
CS4334
12.6.1. Features · Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering · 24-Bit Conversion · 96 dB Dynamic Range · -88 dB THD+N · Low Clock Jitter Sensitivity · Single +5V Power Supply · Filtered Line Level Outputs · On-Chip Digital De-emphasis · Popgaurd® Technology · Functionally Compatible with CS4330/31/33 12.6.2. General Description The CS4334 family members are complete, stereo digital-to-analog output systems including interpolation, 1-bitD/A conversion and output analog filtering in an 8-pinpackage. The CS4334/5/6/7/8/9 support all major audio data interface formats, and the individual devices differ only in the supported interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers.
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12.6.3. Pin Descriptions
12.7.
DS90C385
12.7.1. General Description The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) without any translation logic. The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. 12.7.2. Features · 20 to 85 MHz shift clock support · BestinClass Set & Hold Times on TxINPUTs · Tx power consumption <130 mW (typ) @85MHz Grayscale · Tx Power-down mode <200µW (max) · Supports VGA, SVGA, XGA and Dual Pixel SXGA. · Narrow bus reduces cable size and cost · Up to 2.38 Gbps throughput · Up to 297.5 Megabytes/sec bandwidth · 345 mV (typ) swing LVDS devices for low EMI · PLL requires no external components · Compatible with TIA/EIA-644 LVDS standard · Low profile 56-lead or 48-lead TSSOP package · DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
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12.7.3. Pin Description DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter Pin Name
TxIN TxOUT+ TxOUTTxCLKIN R_FB TxCLK OUT+ TxCLK OUTPWR DOWN Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND
I/O I O O I I O O I I I I I I I
No. 28 4 4 1 1 1 1 1 3 4 1 2 1 3
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines --FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differentiaI data output. Negative LVDS differential data output. TTL Ievel clock input. Pin name TxCLK IN. Programmable strobe select Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. Power supply pins for TTL inputs. Ground pins for TTL inputs. Power supply pin for PLL. Ground pins for PLL. Power supply pin for LVDS outputs. Ground pins for LVDS outputs.
DS90C385SLC SLC64A Package Pin Description-FPD Link Transmitter Pin Name
TxIN TxOUT+ TxOUTTxCLKIN R_FB TxCLK OUT+ TxCLK OUTPWR DOWN Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND NC
I/O I O O I I O O I I I I I I I
No. 28 4 4 1 1 1 1 1 3 5 1 2 2 4 6
Description
TTL level input. Positive LVDS differentiaI data output. Negative LVDS differential data output. TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN. Programmable strobe select. HIGH = rising edge, LOW = falling edge. Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. Power supply pins for TTL inputs. Ground pins for TTL inputs. Power supply pin for PLL. Ground pins for PLL. Power supply pin for LVDS outputs. Ground pins for LVDS outputs. Pins not connected.
12.8.
GAL16LV8
12.8.1. Description The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
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12.8.2. Features · HIGH PERFORMANCE E2CMOS® TECHNOLOGY - 3.5 ns Maximum Propagation Delay - Fmax = 250 MHz - 2.5 ns Maximum from Clock Input to Data Output - UltraMOS® Advanced CMOS Technology · 3.3V LOW VOLTAGE 16V8 ARCHITECTURE - JEDEC-Compatible 3.3V Interface Standard - 5V Compatible Inputs - I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C) · ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only) · E2 CELL TECHNOLOGY - Reconfigurable Logic - Reprogrammable Cells - 100% Tested/100% Yields - High Speed Electrical Erasure (<100ms) - 20 Year Data Retention · EIGHT OUTPUT LOGIC MACROCELLS - Maximum Flexibility for Complex Logic Designs - Programmable Output Polarity · PRELOAD AND POWER-ON RESET OF ALL REGISTERS - 100% Functional Testability · APPLICATIONS INCLUDE: - Glue Logic for 3.3V Systems - DMA Control - State Machine Control - High Speed Graphics Processing - Standard Logic Speed Upgrade · ELECTRONIC SIGNATURE FOR IDENTIFICATION · LEAD-FREE PACKAGE OPTIONS 12.8.3. Pin connections
12.9.
K6R4008V1D
12.9.1. Description The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. TheK6R4008V1D uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4008V1D is packaged in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.
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12.9.2. Features · Fast Access Time 8, 10ns(Max.) · Low Power Dissipation - Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) - Operating K6R4008V1D-08 : 80mA(Max.) K6R4008V1D-10 : 65mA(Max.) · Single 3.3 ±0.3V Power Supply · TTL Compatible Inputs and Outputs · Fully Static Operation - No Clock or Refresh required · Three State Outputs · Center Power/Ground Pin Configuration · Standard Pin Configuration K6R4008V1D-J : 36-SOJ-400 K6R4008V1D-K : 36-SOJ-400(Lead-Free) K6R4008V1D-T : 44-TSOP2-400BF K6R4008V1D-U : 44-TSOP2-400BF(Lead-Free) · Operating in Commercial and Industrial Temperature range. 12.9.3. Pin Description
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12.10. L6562 12.10.1. Features · TRANSITION-MODE CONTROL OF PFC PRE-REGULATORS · PROPRIETARY MULTIPLIER DESIGN FOR MINIMUM THD OF AC INPUT CURRENT · VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION · ULTRA-LOW (70µA) START-UP CURRENT · LOW (4 mA) QUIESCENT CURRENT · EXTENDED IC SUPPLY VOLTAGE RANGE · ON-CHIP FILTER ON CURRENT SENSE · DISABLE FUNCTION · 1% (@ Tj = 25 °C) INTERNAL REFERENCE VOLTAGE 12.10.2. Description The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible with the predecessor L6561, it offers improved performance. The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. 12.10.3. Pin Connections and Descriptions
12.11. LM1086 12.11.1. Description The LM1086 is a series of low dropout positive voltage regulators with a maximum dropout of 1.5V at 1.5A of load current. It has the same pin-out as National Semiconductor's industry standard LM317. The LM1086 is available in an adjustable version, which can set the output voltage with only two external resistors. It is also available in five fixed voltages: 2.5V, 2.85V, 3.3V, 3.45V and 5.0V. The fixed versions integrate the adjust resistors. The LM1086 circuit includes a zener trimmed band-gap reference, current limiting and thermal shutdown. 12.11.2. Features · Available in 2.5V, 2.85V, 3.3V, 3.45V, 5V and Adjustable Versions 17 27" TFT TV Service Manual 10/10/2005
· Current Limiting and Thermal Protection · Output Current 1.5A · Line Regulation 0.015% (typical) · Load Regulation 0.1% (typical) 12.11.3. Applications · SCSI-2 Active Terminator · High Efficiency Linear Regulators · Battery Charger · Post Regulation for Switching Supplies · Constant Current Regulator · Microprocessor Supply 12.11.4. Connection Diagrams
12.12. LM1117 12.12.1. General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor's industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability. 12.12.2. Features · Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions · Space Saving SOT-223 Package · Current Limiting and Thermal Protection · Output Current 800mA · Line Regulation 0.2% (Max) · Load Regulation 0.4% (Max) · Temperature Range -- LM1117 0°C to 125°C -- LM1117I -40°C to 125°C 12.12.3. Applications · 2.85V Model for SCSI-2 Active Termination · Post Regulator for Switching DC/DC Converter · High Efficiency Linear Regulators · Battery Charger · Battery Powered Instrumentation
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12.12.4. Connection Diagrams
12.13. LM317 12.13.1. General Description This monolithic integrated circuit is an adjustable 3-terminal positive voltage regulator designed to supply more than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V. It employs internal current limiting, thermal shut-down and safe area compensation. 12.13.2. Features · Output Current In Excess of 1.5A · Output Adjustable Between 1.2V and 37V · Internal Thermal Overload Protection · Internal Short Circuit Current Limiting · Output Transistor Safe Operating Area Compensation · TO-220 Package 12.13.3. Pin Description
12.14. LM809 12.14.1. General Description The LM809/810 microprocessor supervisory circuits can be used to monitor the power supplies in microprocessor and digital systems. They provide a reset to the microprocessor during power-up, power-down and brown-out conditions. The function of the LM809/810 is to monitor the VCC supply voltage, and assert a reset signal whenever this voltage declines below the factory-programmed reset threshold. The reset signal remains asserted for 240 ms after VCC rises above the threshold. The LM809 has an active-low RESET output, while the LM810 has an active-high RESET output. Seven standard reset voltage options are available, suitable for monitoring 5V, 3.3V, and 3V supply voltages. With a low supply current of only 15µA, the LM809/810 are ideal for use in portable equipment. 12.14.2. Features · Precise monitoring of 3V, 3.3V, and 5V supply voltages · Superior upgrade to MAX809/810 · Fully specified overtemperature · 140 ms min. Power-On Reset pulse width, 240 ms typical Active-low RESET Output(LM809) Active-high RESET Output(LM810) 19 27" TFT TV Service Manual 10/10/2005
· Guaranteed RESET Output valid for VCC1V · Low Supply Current, 15µAtyp · Power supply transient immunity 12.14.3. Pinning
12.15. MSP34X0G (MSP3410G) Multistandard Sound Processor Family 12.15.1. Introduction The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure shows a simplified functional block diagram of the MSP 34x0G. This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments. All MSP 34x0G versions are pin and software downward compatible to the MSP 34x0D. The MSP 34x0G further simplifies controlling software. Standard selection requires a single I˛C transmission only. The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I˛C interaction is necessary (Automatic Sound Selection).
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Source Select I2S bus interface consists of five pins: 1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32 kHz) are transmitted. 2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz). 4. I2S_WS: The I2S_WS word strobe line defines the left and right sample. 12.15.2. Features · Standard Selection with single I2C transmission · Automatic Standard Detection of terrestrial TV standards · Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS · Two selectable sound IF (SIF) inputs · Automatic Carrier Mute function · Interrupt output programmable (indicating status change) · Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness · AVC: Automatic Volume Correction · Subwoofer output with programmable low-pass and complementary high-pass filter · 5-band graphic equalizer for loudspeaker channel · Spatial effect for loudspeaker channel · Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs · Complete SCART in/out switching matrix · Two I2S inputs; one I2S output · Dolby Pro Logic with DPL 351xA coprocessor · All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard · Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM · Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) · ASTRA Digital Radio (ADR) together with DRP 3510A · All NICAM standards · Korean FM-Stereo A2 standard 12.15.3. Pin connections NC = not connected; leave vacant LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS
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Pin No. PLCC 68-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 PSDIP 64-pin 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PSDIP 52-pin 14 13 12 11 10 9 8 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PQFP 80-pin 9 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 PLQFP 64-pin 8 7 6 5 4 3 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Pin Name
Type
Connection (if not used) LV LV LV LV LV LV LV OBL OBL LV OBL OBL LV LV LV LV LV LV LV OBL OBL OBL AVSS via 56 pF/LV AVSS via 56 pF/LV LV OBL OBL LV LV OBL OBL LV LV OBL LV LV AHVSS LV LV AHVSS LV LV AHVSS LV LV LV or AHVSS OBL OBL OBL LV LV OBL OBL OBL LV LV OBL LV LV LV LV LV
Short Description
ADR_WS NC ADR_DA I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL NC STANDBYQ ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1 NC NC NC AUD_CL_OUT TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_INANA_IN1+ AVSUP AVSUP NC NC AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC DACM_SUB
OUT OUT IN OUT IN/OUT IN/OUT IN/OUT IN/OUT IN IN IN/OUT IN/OUT
OUT OUT IN IN IN IN IN
ADR word strobe Not connected ADR Data Output 2 I S1 data input 2 I S data output 2 I S word strobe 2 I S clock 2 I C data 2 I C clock Not connected Stand-by (low-active) 2 I C bus address select D_CTR_I/O_0 D_CTR_I/O_1 Not connected Not connected Not connected Audio clock output (18.432 MHz) Test pin Crystal oscillator Crystal oscillator Test pin IF Input 2 (can be left vacant, only if IF input 1 is also not in use) IF common (can be left vacant, only if IF input 1 is also not in use) IF input 1 Analog power supply 5V Analog power supply 5V Not connected Not connected Analog ground Analog ground Mono input Not connected Reference voltage IF A/D converter SCART 1 input, right SCART 1 input, left Analog Shield Ground 1 SCART 2 input, right SCART 2 input, left Analog Shield Ground 2 SCART 3 input, right SCART 3 input, left Analog Shield Ground 4 SCART 4 input, right SCART 4 input, left Not connected Analog reference voltage Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply 8V Volume capacitor AUX SCART output 1, left SCART output 1, right Reference ground 1 SCART output 2, left SCART output 2, right Not connected Not connected Subwoofer output
IN
IN IN IN IN IN IN IN IN
OUT OUT OUT OUT
OUT
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55 56 57 58 59 60 61 62 63 64 65 66 67 68
30 29 28 27 26 25 24 23 22 21 20 19 18 17
25 24 23 22 21 20 19 18 17 16 15
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
22 21 20 19 18 17 16 15 14 13 12 11 10 9
NC DACM_L DACM_R VREF2 DACA_L DACA_R NC NC RESETQ NC NC NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP DVSUP DVSUP ADR_CL
OUT OUT OUT OUT
IN
IN
OUT
LV LV LV OBL LV LV LV LV OBL LV LV LV LV OBL OBL OBL OBL OBL OBL LV
Not connected Loudspeaker out, left Loudspeaker out, right Reference ground 2 Headphone out, left Headphone out, right Not connected Not connected Power-on-reset Not connected Not connected Not connected 2 I S2-data input Digital ground Digital ground Digital ground Digital power supply 5V Digital power supply 5V Digital power supply 5V ADR clock
12.16. M29W040B 12.16.1. Description The M29W040B is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W040B is fully backward compatible with the M29W040.The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are writ-ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.
12.16.2. Features · SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS · ACCESS TIME: 55ns · PROGRAMMING TIME - 10µs per Byte typical8 · UNIFORM 64 Kbytes MEMORY BLOCKS · PROGRAM/ERASE CONTROLLER - Embedded Byte Program algorithm - Embedded Multi-Block/Chip Erase algorithm - Status Register Polling and Toggle Bits · ERASE SUSPEND and RESUME MODES - Read and Program another Block during Erase Suspend · UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming · LOW POWER CONSUMPTION - Standby and Automatic Standby · 100,000 PROGRAM/ERASE CYCLES per BLOCK · 20 YEARS DATA RETENTION - Defectivity below 1 ppm/year · ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: E3h 23 27" TFT TV Service Manual 10/10/2005
12.16.3. Pin Descriptions
12.17. MC33202 12.17.1. General Description The MC33201/2/4 family of operational amplifiers provide rail-to-rail operation on both the input and output. The inputs can be driven as high as 200mV beyond the supply rails without phase reversal on the outputs, and the output can swing within 50 mV of each rail. This rail-to-rail operation enables the user to make full use of the supply voltage range available. It is designed to work at very low supply voltages (±0.9 V) yet can operate with a supply of up to +12V and ground. Output current boosting techniques provide a high output current capability while keeping the drain current of the amplifier to a minimum. Also, the combination of low noise and distortion with a high slew rate and drive capability make this an ideal amplifier for audio applications. 12.17.2. Features · Low Voltage, Single Supply Operation (+1.8 V and Ground to +12 V and Ground) · Input Voltage Range Includes both Supply Rails · Output Voltage Swings within 50 mV of both Rails · No Phase Reversal on the Output for Over-driven Input Signals · High Output Current (ISC = 80 mA, Typ) · Low Supply Current (ID = 0.9 mA, Typ) · 600 Output Drive Capability · Extended Operating Temperature Ranges (-40° to +105°C and -55° to +125°C) · Typical Gain Bandwidth Product = 2.2 MHz · Pb-Free Packages are Available 12.17.3. Pin Connections
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12.18. PCF8574 12.18.1. General Description The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C).The device consists of an 8-bit quasibidirectional port and an I2C-bus interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device. 12.18.2. Features · Operating supply voltage 2.5 to 6V · Low standby current consumption of 10 µA maximum · I2C to parallel port expander · Open-drain interrupt output · 8-bit remote I/O port for the I2C-bus · Compatible with most microcontrollers · Latched outputs with high current drive capability for directly driving LEDs · Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A) · DIP16, or space-saving SO16 or SSOP20 packages. 12.18.3. Pinning
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12.19. PI5V330 12.19.1. General Description The PI5V330 is well suited for video applications when switching composite or RGB analogue. A picture-in-picture application will be described in this brief. The pixel-rate creates video overlays so two or more pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by superimposing the output of a character generator on a standard composite video background.
12.20. SDA55XX (SDA5550) 12.20.1. General description The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking, data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can also be used for customer defined on screen displays. Internal XRAM consists of up to16 Kbytes. Device has an internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS, PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5 TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented characters (DRCS). The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does most of the internal TTX acquisition processing, transfers data to/from external memory interface and receives/ transmits data via I2C-firmware user-interface. The slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition tasks (hamming and parity-checks, page search and evaluation of header control bits) once per field. Additionally, the firmware can provide high-end Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology with 2.5 V supply voltage and 3.3 V I/O (TTL compatible). The software and hardware development environment (TEAM) is available to simplify and speed up the development of the software and On Screen Display. TEAM stands for TVT Expert Application Maker. It improves the TV controller software quality in following aspects: Shorter time to market Re-usability Target independent development Verification and validation before targeting General test concept Graphical interface design requiring minimum programming and controller know how. Modular and open tool chain, configurable by customer.
12.21. SG3525A 12.21.1. General Description The SG3525A pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on-chip +5.1 V reference is trimmed to ±1% and the error amplifier has an input common-mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of dead time can be programmed by a single resistor connected between the CT and Discharge pins. This device also features built-in soft-start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft-start capacitor when VCC is below nominal. The output stages are totem-pole 26 27" TFT TV Service Manual 10/10/2005
design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525Afeatures NOR logic resulting in a low output for an off-state. 12.21.2. Features · 8.0 V to 35 V Operation · 5.1 V ± 1.0% Trimmed Reference · 100 Hz to 400 kHz Oscillator Range · Separate Oscillator Sync Pin · Adjustable Deadtime Control · Input Undervoltage Lockout · Latching PWM to Prevent Multiple Pulses · Pulse-by-Pulse Shutdown · Dual Source/Sink Outputs: ±400 mA Peak 12.21.3. Pin Connections
12.22. Sil 9993 12.22.1. General Description The SiI 9993 is the first generation of PanelLink receivers that are designed for the HDMI 1.0 (High Definition Multimedia Interface) specification. DTVs, plasma displays, LCD TVs and projectors can now provide the purest level of protected digital audio/video over a simple, low cost cable. Backwards compatibility with DVI 1.0 allows HDMI systems to connect to any DVI 1.0 host (DVD players, HD set top boxes, D-VHS players and receivers, PC). The SiI 9993 incorporates a flexible audio and video interface. The receiver can connect to RGB input and output YCbCr using an integrated color space converter. This allows full backward compatibility to DVI, and interfaces to all major video processors. A S/PDIF port can output PCM encoded data as well as Dolby Digital, DTS and all other formats capable of being sent over S/PDIF. A 2-channel I2S port outputs data converted from S/PDIF. The SiI 9993 comes pre-programmed with HDCP keys, greatly simplifying the manufacturing process, lowering costs, all the while providing the highest level of HDCP key security. Silicon Image's PanelLink receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores pass all HDMI compliancy tests. 12.22.2. Features · HDMI 1.0 and DVI 1.0 compliant receiver · Integrated PanelLink core supports DTV resolutions (480i/576i/480p/576p/720p/1080i) · Digital video interface supports video processors: o 24-bit RGB 4:4:4 o 24-bit YCbCr 4:4:4 o 16/20/24-bit YCbCr 4:2:2 o 8/10/12-bit YCbCr 4:2:2 embedded syncs · Analog RGB and YPbPr output: o 10-bit DAC o Separate or Composite Syncs (Sync on G) · S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-48kHz Fs) using IEC 60958 and IEC 61937. 27 27" TFT TV Service Manual 10/10/2005
· Programmable I2S interface for connection to low-cost audio DACs. · Integrated HDCP decryption engine for receiving protected audio and video content · Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing · Programmable registers via slave I2C interface · 3.3V operation in 100-pin TQFP package · Flexible power management
12.23. NCP1014 12.23.1. General Description The NCP101X series integrates a fixed-frequency current-modecontroller and a 700 V MOSFET. Housed in a PDIP-7 or SOT-223package, the NCP101X offers everything needed to build a rugged and low-cost power supply, including soft-start, frequency jittering, short-circuit protection, skip-cycle, a maximum peak current setpoint and a Dynamic Self-Supply (no need for an auxiliary winding). Unlike other monolithic solutions, the NCP101X is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (65-100-130 kHz). When the current setpoint falls below a given value, e.g. the output power demand diminishes, the IC automatically enters the so-called skip cycle mode and provides excellent efficiency at light loads. Because this occurs at typically 1/4 of the maximum peak value, no acoustic noise takes place. As a result, standby power is reduced to the minimum without acoustic noise generation. Short-circuit detection takes place when the feedback signal fades away, e.g. in true short-circuit conditions or in broken Optocoupler cases. External disabling is easily done either simply by pulling the feedback pin down or latching it to ground through an inexpensive SCR for complete latched-off. Finally soft-start and frequency jittering further ease the designer task to quickly develop low-cost and robust offline power supplies. For improved standby performance, the connection of an auxiliary winding stops the DSS operation and helps to consume less than100 mW at high line. In this mode, a built-in latched overvoltage protection prevents from lethal voltage runaways in case the Optocoupler would brake. 12.23.2. Features · Built-in 700 V MOSFET with Typical RDSon of 11 and 22 · Large Creepage Distance Between High-Voltage Pins · Current-Mode Fixed Frequency Operation: 65 kHz100 kHz-130 kHz · Skip-Cycle Operation at Low Peak Currents Only: No Acoustic Noise! · Dynamic Self-Supply, No Need for an Auxiliary Winding · Internal 1.0 ms Soft-Start · Latched Overvoltage Protection with Auxiliary Winding Operation · Frequency Jittering for Better EMI Signature · Auto-Recovery Internal Output Short-Circuit Protection · Below 100 mW Standby Power if Auxiliary Winding is Used · Internal Temperature Shutdown · Direct Optocoupler Connection · SPICE Models Available for TRANsient Analysis 12.23.3. Pin Connections and Descriptions
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12.24. SN74CB3Q3305 12.24.1. General Description The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ONstate resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. 12.24.2. Features · High-Bandwidth Data Path (Up To 500 MHz) · 5-V Tolerant I/Os with Device Powered-Up or Powered-Down · Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Typical) · Rail-to-Rail Switching on Data I/O Ports - 0- to 5-V Switching With 3.3-V VCC - 0- to 3.3-V Switching With 2.5-V VCC · Bidirectional Data Flow, With Near-Zero Propagation Delay · Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) · Fast Switching Frequency (fOE = 20 MHz Max) · Data and Control Inputs Provide Undershoot Clamp Diodes · Low Power Consumption (ICC = 0.25 mA Typical) · VCC Operating Range From 2.3 V to 3.6 V · Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) · Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs · Ioff Supports Partial-Power-Down Mode Operation · Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II · ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101) · Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating 12.24.3. Pin Connections
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12.25. ST24LC21 12.25.1. Description The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. 12.25.2. Features · 1 million Erase/Write cycles · 40 years data retention · 2.5V to 5.5V single supply voltage · 400k Hz compatibility over the full range of supply voltage · Two wire serial interface I2C bus compatible · Page Write (Up To 8 Bytes) · Byte, random and sequential read modes · Self timed programming cycle · Automatic address incrementing · Enhanced ESD/Latch up · Performances 12.25.3. Pin connections
DIP Pin connections NC: Not connected Signal names
SDA SCL Vcc Vss VCLK Serial data Address Input/Output Serial Clock (I2C mode) Supply voltage Ground Clock transmit only mode
CO Pin connections
12.26. LM2576 12.26.1. General Description The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a stepdown switching regulator (buck converter). All circuits of this series are capable of driving a 3.0 A load with excellent line and load regulation. These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output version. These regulators were designed to minimize the number of external components to simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different inductor manufacturers. Since the LM2576 converter is a switchmode power supply, its efficiency is significantly higher in comparison with popular threeterminal linear regulators, especially with higher input voltages. In many 30 27" TFT TV Service Manual 10/10/2005
cases, the power dissipated is so low that no heatsink is required or its size could be reduced dramatically. A standard series of inductors optimized for use with the LM2576 are available from several different manufacturers. This feature greatly simplifies the design of switchmode power supplies. The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input voltages and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is included, featuring 80 mA (typical) standby current. The output switch includes cyclebycycle current limiting, as well as thermal shutdown for full protection under fault conditions. 12.26.2. Features · 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions · Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load Conditions · Guaranteed 3.0 A Output Current · Wide Input Voltage Range · Requires Only 4 External Components · 52 kHz Fixed Frequency Internal Oscillator · TTL Shutdown Capability, Low Power Standby Mode · High Efficiency · Uses Readily Available Standard Inductors · Thermal Shutdown and Current Limit Protection · Moisture Sensitivity Level (MSL) Equals 1 12.26.3. Pin description
12.27. MC34063 12.27.1. Description The MC34063A Series is a monolithic control circuit containing the primary functions required for DC toDC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in StepDown and StepUp and VoltageInverting applications with a minimum number of external components. 12.27.2. Features · Operation from 3.0 V to 40 V Input · Low Standby Current · Current Limiting · Output Switch Current to 1.5 A · Output Voltage Adjustable · Frequency Operation to 100 kHz · Precision 2% Reference
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12.27.3. Pin connections
12.28. TDA1308 12.28.1. General Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications. 12.28.2. Features · Wide temperature range · No switch ON/OFF clicks · Excellent power supply ripple rejection · Low power consumption · Short-circuit resistant · High performance · high signal-to-noise ratio · High slew rate · Low distortion · Large output voltage swing. 12.28.3. Pinning
SYMBOL OUTA INA(neg) INA(pos) VSS INB(pos) INB(neg) OUTB VDD PIN 1 2 3 4 5 6 7 8 DESCRIPTION Output A (Voltage swing) Inverting input A Non-inverting input A Negative supply Non-inverting input B Inverting input B Output B (Voltage swing) Positive supply PIN VALUE Min : 0.75V, Max : 4.25V Vo(clip) : Min : 1400mVrms 2.5V 0V 2.5V Vo(clip) : Min : 1400mVrms Min : 0.75V, Max : 4.25V