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Perugia 10M
MP Build(A03)
2009.05.05
EE DRAWER DESIGN CHECK RESPONSIBLE SIZE = 3 FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX
DATE
POWER
DATE
INVENTEC
TITLE
Perugia10M
DOC. NUMBER REV
VER :
SIZE CODE
A3
CS
SHEET
1310A2250501
1 OF 63
x01
DATE
CHANGE NO.
REV
TABLE OF CONTENTS
PAGE 1.COVER PAGE 2.INDEX 3.BLOCK DIAGRAM 4.POWER SEQUENCE BLOCK 5-12.SYSTEM POWER 13.CLOCK GENERATOR 14.PENRYN-1 15.PENRYN-2 16.PENRYN-3 17.PENRYN-4 18.FAN & THERMAL CONTROLLER 19.CANTIGA-1 20.CANTIGA-2 21.CANTIGA-3 22.CANTIGA-4 23.CANTIGA-5 24.CANTIGA-6 25.CANTIGA-7 26.DDR2 DIMM0 27.DDR2 DIMM1 28.DDR DAMPING 29.CRT CONN 30.LCM CONN
PAGE 31.ICH9-1 32.ICH9-2 33.ICH9-3 34.ICH9-4 35.ICH9-5 36.SATA HDD CONN 37.ODD CONN 38.USB CONN 39.ESATA CONN 40.Camera 41.BLUE TOOTH CONN 42.KBC 43.K/B & TP/B CONN 44.Audio Codec 45.Audio AMP/MIC/Speaker 46.LAN CONTROLLER 47.RJ45 & TRANSFORMER 48.HDMI & CEC 49.HDMI CONN 50.USB Card Reader 51.Card Bus-1 52.Card Bus-2 53.Express Card
PAGE 54.WLAN /Debug 55.MDC 1.5 CONN 56.LED(M/B) & HOTKEY/B CONN 57.KILL SWITCH& HALL SENSOR 58.Screw 59.EMI 60.3D sensor 61. Hotkey board 62. Touch pad board 63. power board
INVENTEC
TITLE
Perugia10M
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 24-Mar-2009
CS
SHEET
1310A2250501
2 OF 63
x01
Penryn
XDP HDMI CONN PTN3360A Level shifter
FSB 677/800/1067
(uFCPGA)
Socket P
Clock generator SLG8SP510T
DDR II _SODIMM0
667 MHz/ 800 MHz
DDR II _SODIMM1
667 MHz/ 800 MHz
LCM CRT USB1 + eSATA
Cantiga
SATA_1 SATA_4 DMI
DDR2 Interface DDR2 Interface
CONN
HDD ODD
NEW Card Bluetooth
SATA_5 3.3V, PCI_Interface,33MHz
RESERVE
RESERVE
CAMERA
USB0
CONN
WLAN
CONN
CONN
USB2
USB4
USB5
USB8
USB3
USB6
USB7
USB9
ICH9-M
Realtek RTL8103E 3.3V, LPC_Interface,33MHz EXPRESS CARD
MINI CARD Wireless LAN
CARD BUS RICOH_R5C804
3.3V, AZALIA
RJ45 ANT ANT PCMCIA
MDC / Modem Module 56K BATTERY RJ11 System Charger & DC/DC System power (IMVP-6 VR)
Realtek ALC 272 MIC JACK
WINBOND NPCE781LA0DX
SPEAKER BIOS SPI EEROM HP JACK
INVENTEC
TITLE
Perugia10M
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 15-Apr-2009
CS
SHEET
1310A2250501
3 OF 63
x01
1
2
3
4
5
6
7
8
Adaptor
A FUSE GM 8A 6036A0003401 PM 12A 6036A0006001 BQ24721C Charger Charge current 3A/1.5A/512mA Charge voltage 12.6V EC_SMB2 CHG_EN BATT_IN ACPRES Battery Pack P.5
+VBAT
P.5
+V5A_+-5%
P.7 TPS51125_ 5V Power budget 10.164A F 300K OCP 7.42A R=120K Peak 6.10A Avg 4.31A 330uF_25m // 108.5uF_0.8m L/S AM3423
Power budget 3.802A Peak 2.67A 145.1uF_1.7m
+V5S
P.12
Inrush 1.28A
A
+V3LA_+-5%
P.6 P.7 TPS51125_ V3.3LA Power budget 11.487A F 375K OCP 7.85A R=130K Peak 6.89A Avg 1.77A 330uF_25m // 21.9uF_3.1m L/S AM3423
Power budget 0.598A Peak 0.42A 0.7uF_14.9m
+V3A
P.7
Inrush 0.51A
+V3A_LAN
L/S AM3423
Power budget0. 399A
P.8
Inrush 0.53A
B
+V3
P.12
Inrush 0.336A
Peak 0.24A 10.4uF_6.7m
B
L/S AM3423
Power budget0.35A Peak 0.25A 131.1uF_2.7m
+V3S
P.12
L/S AM3423
Power budget 10.229A Inrush 1.3A Peak 7.16A 293.9uF_0.3m
C
C
V1.8_+-5%
+VCORE_+-1.5% +VCORE1_+-1.5% TI_51620 Power budget 57A F 280K OCP 60.87A R=10K peak 57A Avg 30.629A 900uF_1.5m P.12 P.9 TSP51117_ 1.8V Power budget 10.688A F 300K OCP 9.53A R=13K Peak 7.48A Avg7.27A 330uF_14m // 542uF_0.8m APL5930
Power budget 3.384A Peak 2.37A 432.9uF_0.5m
+V1.5S
P.9
+V0.9
G2997 F6U
Power budget 0.9A Peak 0.63A 3.4uF_3.1m
D
P.9
D
E
E
+VCCP_+-5%
P.11 TSP51117_VCC_NB Power budget 17.324A F 300K OCP 13.76A R=10K Peak 12.13A Avg 8.64A 330uF_14m // 1230.2uF_0.5m
Changing Points~~All PWM as same Minneapolis 10 F
F
TITLE Power budget ~~IC Spec (max current ) G Peak current ~~Ratio of Internal prediction Avg current ~~test result(max current) Inrush ~~L/S turn no 1 2
Perugia10M Power Sequence Block
CODE CS DOC.NUMBER 1310A2250501 REV A
SIAE A3
F
CHANGE by 3 4 5
Loren Huang 6
14-Feb-2009 7
SHEET
4
OF 8
70
+VBAT +VADPTR CN6000 1 2 G1 G 3 G2 G 4 FUSE6000 1 2 8A_125V 1 C6004 2 10pF_50V 1 2
55-,6-,7-,8-,9-,11-,30-,591
1 2 3 4
R6024 174K_1%
C6003 0.1uF_50V HW_V_ADC
421 R6005 2
2
ACES_91302_0047L_1_4P
33_5% C6032 1 0.1uF_10V 2 1 D6005 For ESD
1
R6026 13.3K_1%
2 RLZ3.0B_OPEN
2
+VADPTR
5-
+VBAT
5-,6-,7-,8-,9-,11-,30-,59-
+VPACK
6-
L6000 1 NFM60R30T222 4 3 2
1 2
D6000 3 PDS1040S C6002 1 C6006 1 0.01uF_50v 2
Q6001 AM4825P_AP 1 S D 8 2 7 3 6 4 5 G
Q6000 1
3
R6001 0.01_1%
2
4
C6014 C6013 1 0.1uF_25V 2 1 2 0.1uF_25V NEAR IC 1 C6012 2 0.1uF_25V
1 C6028
1 C6009
C6005 1 1 C6008 2 4.7uF_25V 1 C6010 2 4.7uF_25V 1 C6029 0.01uF_50v 2
1 2 3 4
S
D
G
8 7 6 5
AM4825P_AP
2 4.7uF_25V 2 0.1uF_25V
47uF_35v 2
2 68uF_25V
1 C6025
1 R6015 2
0_5%
12 1 R6002 2
U803
ACDRV# VCC SYS 2 23
2 4.7uF_25v 5 6 7 8
D 24 32 G S
1 D6001 ROHM_RLZ24 1 2 R6009 432K_1% 2
4.7K_5% 1 R6008 2 4.7K_5%
2 3 +V5LA
5-,6-,7-,12-,18-,39-,49-
3 4 6
ACN ACP BYPASS#
BATDRV# PVCC
Q6003
FDMC8884
4 3 2 1
HIDRV 30
D6004 BAT54S_30V_0.2A 1
1
PLC0755P_10uH_3.9A 1 L6001 2 Q6002
D FDMC8884
1
3
R6000 0.01_1%
2
4
5 6 7 8
29 31 28 27 26 22 21 20 19 18 7 8 9 16 33 1 R6004 2
5 11 10
ACDET VREF5 AGND TS
PH BTST REGN LODRV PGND SYNP SYNN SRP SRN BAT EAO
1 R6003 4.7_5% 2 1 1 C6000 1 C6027
C6011 1 D6003 2 3 BAT54AW 1 2
R6013 1K_5%
2
0.1uF_25V
G
1 C6001
1 C6026
4.7_5%
3 1
B C E
1
R6010 33K_1%
1 1 2 C6015 0402_OPEN 2 C6018 R6021 47K_5% 1
1
EMI
R6018 8.06K_1%
2 61
15
1 C6020 2 1uF_10v
2 2 4.7uF_25V 4.7uF_25V C6007 4 3 2 1 D6002 2 2200pF_50V SBR3U40P1
S
1
2
2 2 4.7uF_25V 4.7uF_25V C6021 1 2 0.1uF_25V NEAR IC
1 R6016 10K_5% 2
Q6004 2 MMBT3904
2
THRM1
1 CHGEN#
1uF_10v 2 1 R6022 100K_5% 2
R6019 39.2K_1%
2 421
1 C6022 2 0.1uF_25V 1 R6014 18K_5% 1 R6017 56K_5% 2 2 1 2 R6012 200K_5% 1 C6019 2 100pF_50v 1 C6016 2 56pF_50v 1 C6017 2 0.0015uF_50V 2 1 R6011 10K_5%
1 C6023 2 0.22uF_25v
BATT_IN
R6020 22.6K_1%
2
14 SCL 13 SDA 25 ALARM# 17 IOUT
EAI FBO ISYNSET TML
TI_BQ24721C_QFN_32P ACPRES
4242-
HW_I_ADC
1 2 CHG_EN +V5LA
5-,6-,7-,12-,18-,39-,491 R6006 42-
C6033 0.1uF_10V
1 2
C6035 0.1uF_10V
2 1 R6007 200K_5% 2
100K_5%
TP27
TP28
INVENTEC
EC_SMB2_CLK EC_SMB2_DATA
18-,4218-,42-
TITLE
Perugia10M
SIZE CODE DOC. NUMBER REV
A3
CHANGE by Loren 15-Oct-2008
CS
SHEET
1310A2250501
5 OF 63
x01
+VPACK
5-
CN800 1 THRM1 EC_SMB1_DATA EC_SMB1_CLK
542-,6042-,601 2
FUSE800 2
LITTLEFUSE_R451015_15A_65V R25021 R25031
2 2
33_5% 33_5% 1 D2500
R804
1K_5%
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
1 D2501 2 EZJZ0V500AA D7410 1 D7411 1 D7412 1
G G G G
G1 G2 G3 G4
1 C803 2 1000pF_50v
SYN_200045MR009G151ZR_9P
EZJZ0V500AA 2
PHP_PESD5V0S1BB_SOD523_2P_OPEN PHP_PESD5V0S1BB_SOD523_2P_OPEN 2 2
PHP_PESD5V0S1BB_SOD523_2P_OPEN
2
+VBAT +V5LA
5-,7-,8-,9-,11-,30-,59-
+V5LA
5-,6-,7-,12-,18-,39-,49-
5-,6-,7-,12-,18-,39-,49-
1
R6960 10K_5%
1 R6961
D9068 1 3
510K_1%
2 2
BAT54_30V_0.2A_OPEN U6960 +V5AUXON
7-,421 2 3 5 RESET MR GND 4 VSEN VCC 18-
THRM_SHUTDWN#
GMT_G686LT11U_SOT23_5P C4388 1 0.1uF_10V 2
1 R6962
100K_1%
2
INVENTEC
TITLE
SELECT & BATTERY CONN
SIZE CODE DOC. NUMBER REV
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
6 OF 63
x01
+V3LA +V5LA
5-,6-,7-,12-,18-,39-,491 7-,12-,18-,31-,38-,39-,42-,48-,56-,57-
+V3A 4 3 Q6101
S D
1 C8402 2 0402_OPEN
G
1 2 5 6
8-,31-,32-,33-,34-,39-,42-,46-,53-,54-,56-
2
R6101 10K_5% BAT54_30V_0.2A
AM3423P
D6100 1 3 C6117
1
EC_PW_ON
42-
R6103 2 1 10K_5%
Q6106 3 D 1G
S
1 R6100 2
100K_5%
0.033uF_16V
R6102 200_5%
2
1
SSM3K7002FU 2
Q6103 3 D 1G
S
SSM3K7002FU 2
Q6107 3 D 1G
S
1
R6112 120K_1%
2
SSM3K7002FU 2
1 +V5AUXON
6-,42-
3
D6101 BAT54C_30V_0.2A 2 +VBAT +VBAT
1 5-,6-,7-,8-,9-,11-,30-,595-,6-,7-,8-,9-,11-,30-,59-
R6111 130K_1%
2
2
PAD6013 POWERPAD_2_0610
PAD6102 POWERPAD_2_0610
4.7uF_25v C6109 1 8 7 6 5 +V3LA
7-,12-,18-,31-,38-,39-,42-,48-,56-,57D
4.7uF_25V C6108 1 C6115 1 2
25
2 0.22uF_6.3V 5 6 7 8
D G 24 23 22 21 20 19 6 5 4 3 2 1
1 C6107 1 C6101 1 C6113 2 2 2 4.7uF_25V 4.7uF_25V 4.7uF_25V +V5A
8-,9-,11-,12-,30-,34-,38-,39-,44-,45-
2
Q6105 FDMC8884
S
G 7 8 9 10 11 12
ENTRIP2 VFB2 TONSEL VREF VFB1 ENTRIP1
TML
PAD6101 2 1 POWERPAD_2_0610 C6103 1 R6109 0402_OPEN 2 6.8K_1%
1
2 L6101 1 MPLC0730_3R3_5.7A
D
1 2 3 4 8 7 6 5
G S
C6105 2 1 0.1uF_25V
EN0 SKIPSEL GND VIN VREG5 VCLK
VO2 VREG3 VBST2 DRVH2 LL2 DRVL2
VO1 PGOOD VBST1 DRVH1 LL1 DRVL1
0.1uF_25V C6106 1 2 4 3 2 1
Q6102 FDMC8884
S
L6100 1 2 MPLC0730_3R3_5.7A
D 1
PAD6100 POWERPAD_2_0610 1 C6102 R6107 15.4K_1% 2 0402_OPEN
5 6 7 8
G S
Q6104 FDS6690AS 1 2 C6104 330uF_6.3V
U6100 TI_TPS51125_QFN_24P
13 14 15 16 17 18
+V5LA
5-,6-,7-,12-,18-,39-,49-
Q6100 FDS6690AS
2
1 2 3 4 +V3LDO
1
C6100 1 2 330uF_6.3V
2
4 3 2 1 PAD6843
POWERPAD2x2m
1
1
R6110 10K_1%
C6110 1 2 1uF_6.3V
2
R6104 820K_5% 2 4.7uF_6.3V 1 C6116
1 C6112 2 2.2uF_25v 1 C6111 2 10uF_6.3V
R6108 10K_1%
2
>>VRE3 OR VRE5=OOA SKIPSEL >>VREF=ASKIP >>GND=PWM >>VRE5=365/460 >>VRE3=300/375 TONSEL >>VREF=245/305 >>GND=200/250
2
INVENTEC
TITLE
SYSTEM POWER(3V/5V/12V)
SIZE CODE DOC. NUMBER REV
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
7 OF 63
x01
+VBAT
5-,6-,7-,9-,11-,30-,59-
PAD6200 POWERPAD_2_0610 +V5A
7-,8-,9-,11-,12-,30-,34-,38-,39-,44-,45-
1 R6207 10_5% 2 SLP_S5#_3R
8-,12-,32-,421 R6204 2 2
56 78 R6203
1
1 C6210 D Q6201
FDMC8884
1 C6203 2 4.7uF_25V +V1.8
8-,19-,23-,24-,26-,27-,59-
G C6201 2.2_5% 0.1uF_25V
2 2 1 2
2 4.7uF_25v
274K_1% U6200
1 2 3 4 5 6 7 EN_PSV TON VOUT V5FILT VFB PGOOD GND VBST DRVH LL TRIP V5DRV DRVL PGND TML 14 13 12 11 10 9 8 15 1 1
S 4 3 2 1 1 L6200 2 MPLC0730_2R2_7.3A D Q6200 G S 4 3 2 1
1 1
R6201
PAD6201
POWERPAD_2_0610
0_5%
C6204 1 0402_OPEN 2 C6207 1 2.2uF_6.3v 2 C6205 1 0402_OPEN 2
R6202 13K_1%
56 7 8
FDS6690AS
R6205 14.3K_1%
2
1 C6206 2 0402_OPEN 1 2 330uF_2.5V C6208
TI_TPS51117_QFN_14P
1 C6202 2 2.2uF_6.3v
R6206 10K_1%
2
+V5A
7-,8-,9-,11-,12-,30-,34-,38-,39-,44-,45-
+V1.8
8-,19-,23-,24-,26-,27-,59-
+V0.9S
28-,59-
SLP_S5#_3R SLP_S3#_3R +V5S
8-,12-,18-,29-,32-,34-,36-,37-,40-,42-,43-,44-,51-,59-,60-
8-,12-,32-,428-,12-,32-,4211 10 9 8 7 6
U6840
TML VDDQSNS VIN VLDOIN S5 VTT GND PGND S3 VTTSNS VTTREF 1 2 3 4 5
PAD6840
POWERPAD_2_0610
+V1.5S
M_VREF
19-,26-,27-
+V1.8 +V5S
8-,19-,23-,24-,26-,27-,598-,12-,18-,29-,32-,34-,36-,37-,40-,42-,43-,44-,51-,59-,60-
1
R6823 0402_OPEN U9
5 VIN VCNTL VOUT VOUT FB GND 4 POWERPAD_2_0610 3 2 1
16-,24-,34-,44-,53-,54-,59-
GMT_G2997F6U_MSOP10_10P 1 C6843 1 2 0.1uF_10V 2 C6841 1uF_6.3V 1 C6840 1 C6842
2
PAD6
2 22uF_6.3v 2 22uF_6.3v
1 1 C190
C162
6
2 22uF_6.3v
2 2.2uF_6.3v
POK 7 EN 8 VIN 9
1
C189
1
2 39pF_50V
2
R168 9.1K_1% 1 C197
1 C198
1
ANPEC_APL5930KAI_TRG_SOP_8P
1 1
2 22uF_6.3v 2 2.2uF_6.3V R167 0603_OPEN
2
R163 0402_OPEN
2
1 2
C163 0402_OPEN
R169 10K_1%
2
+V3A +V1.5A
7-,31-,32-,33-,34-,39-,42-,46-,53-,54-,5612-,34-
SLP_S3#_3R
8-,12-,32-,42-
SLP_S3_5R
12-,49-
1G
Q22 3 D
1
S
U3
IN OUT 5 1 3 SET SHDN# GND 2 2 4
SSM3K7002FU_OPEN 2
R27 2.1K_1% 1 2 C69 4.7uF_6.3V
1 2
C68
GMT_G916T1Uf_SOT23_5_5P
1
R28 10K_1%
1uF_10V
2
INVENTEC
TITLE
Perugia10M
DOC. NUMBER REV
SYSTEM POWER(+V1.8/+V1.25S)
SIZE CODE
A3
CHANGE by Loren 22-Oct-2008
CS
SHEET
1310A2250501
8 OF 63
x01
+VBAT
5-,6-,7-,8-,11-,30-,59-
PAD9 POWERPAD_2_0610 +V5A
7-,8-,11-,12-,30-,34-,38-,39-,44-,45-
+V3S 1
11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59R240 2 R242 1
1
5 6 7 8
D G
1 C252 Q28
SI7230DN
1 C4390 +VCCP
11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
R186 10K_5% SLP_S3#_5R
11-,12-,601
10_5% 2 U18
1 2 3 4 5 6 7
274K_1% R233
1 1 2 2
2 4.7uF_25V 2 4.7uF_25V
R232
2
2
100K_5%
VCCP_PG
11-
EN_PSV TON VOUT V5FILT VFB PGOOD GND
C250 0.1uF_10V
1 2
C275
1
C276
1
VBST DRVH LL TRIP V5DRV DRVL PGND TML
14 13 12 11 10 9 8 15
C278 2.2_5% 0.1uF_25V
1 2
S
4 3 2 1 1 L18 2 MPLC0730_1R0_10.6A 5 6 7 8
D G 1
PAD7
POWERPAD_2_0610
R243 13K_1%
R241 4.12K_1%
S 2
1 0402_OPEN 2 C274 1
1
2.2uF_6.3v 2
0402_OPEN 2
TI_TPS51117_QFN_14P
1 C277 2 2.2uF_6.3v
4 3 2 1 Q31 FDS8672S R262 10K_1%
2
C251
2 330uF_2.5V
INVENTEC
TITLE
GRAPHIC POWER (+VGFX_CORE)
SIZE CODE DOC. NUMBER REV
Perugia10M
CS
SHEET 9
A3
CHANGE by Loren 10-Oct-2008
1310A2250501
OF 63
x01
BLANK
INVENTEC
TITLE
Perugia10M
DOC. NUMBER REV
SYSTEM POWER(+VCCP/+V1.5S)
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
10 OF 63
x01
+V3S
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
5 VCCP_PG
91
R185
2
2 C201 1uF_6.3v 3
PHP_74LVC1G17_SOT753_5P U13 4 11-,42-
VCORE_EN
+VBAT
5-,6-,7-,8-,9-,30-,59-
+VBAT_CPU
11-
180K_1% 1 1 SLP_S3#_5R
9-,12-,601
L3312 2 4 3
1 2
2 D24 BAT54C 2 1 C192 0.1uF_10V 5 U12 4
R6071 10K_5%
2
1 NFM60R30T222
4.7uF_25V C4156 1 C4157 1 C4160
4.7uF_25V 1 C4161 1 C4162 1 C4163 2 2 2 4.7uF_25V
4.7uF_25V 1 C4391 2 1 C4392 2 4.7uF_25V
3
2 2 0.01uF_50v 0.01uF_50v
4.7uF_25V
2 VR_PWRGD
11-,14-,18-,32-
1 R184 2 180K_1% 1 2
2 C200 1uF_6.3v 3
19-,32-
PM_PWROK
PHP_74LVC1G17_SOT753_5P
+V3S
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
+V5A
7-,8-,9-,12-,30-,34-,38-,39-,44-,45-
R6981 VR_PWRGD PM_DPRSLPVR IMVP_CKEN# VCORE_EN
11-,4211-,14-,18-,3219-,321 2
1
R6980
2 2
10K_5% R6982
1
CSN1
11-
1 R6994 2
499_1%
0_5% C4164 1 2 0.01uF_16V
1 R6991 2
10K_5% +VBAT_CPU
TP1002 11-
CSP1
11-
5 6 7 8
1 1
R6977 2 124K_1% 2.2uF_6.3v 1
G
R6973 0402_OPEN
2
C4152 2
5 Q1406 7 8 TPCA8030_H 6
S
D
2
R6987 1
1 R6989 2
200K_1% 1 R6995 2 63.4K_1%
42.2K_1%
220K_5% L3313
+VCC_CORE
16-,59-
4 3 2 1 1 43 2 1 0.1uF_25v 1 2 D G C4153
1 1
2 ETQP4LR36WFC_PANASONIC
Q1407 S
TPCA8A04_H 2 R6985
CSP1 C4141 1 47pF_50v 2
PwPd V5FILT ISLEW OSRSEL TONSEL TRIPSEL PWRMON VR_ON CLK_EN# DPRSLPVR PGOOD
11-
1 R6967 2
0.22uF_6.3v 2
330_5% 2 47pF_50v 1 C4145
1 11- R6968 112
R6974 470pF_50V 2 0_5% 2 1 C4151
41 40 39 38 37 36 35 34 33 32 31
C4150 1
1 1
R6975 4.75K_1%
2 1 2 3 4 5 6 7 8 9 10
R6983 2.2_5%
1 2 1
0603_OPEN
C4142 47pF_50v 1 2 CSN1 C4143 47pF_50v CSN2 1 2 C4144 1 47pF_50v 2 CSP2
1
2
VR_TT# DPRSTP# PSI# VID6 VID5 VID4 VID3 VID2 VID1 VID0
330_5% R6969 330_5% 2
1
DROOP DRVH1 VBST1 VREF LL1 GND CSP1 DRVL1 CSN1 U6961 V5IN TI_TPS51620RHAR_QFN_40P CSN2 PGND CSP2 DRVL2 LL2 GNDSNS VBST2 VSNS DRVH2 THERM
30 29 28 27 26 25 24 23 22 21
2
C4158 0603_OPEN
C4155 2 2.2uF_6.3v
1
R6976 20K_1%
R6984 2.2_5% 43 2 1 S G D 567 8 4 3 2 1
TPCA8A04_H
2 1 0603_OPEN C4159
2
1 2 0.1uF_25v
47pF_50v 1 C4146
9-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
11 12 13 14 15 16 17 18 19 20
2
2
C4154
+VCCP
Q1409 0603_OPEN R6986
1
11-
R6970 330_5% 2
1 1
L3314 1 2 ETQP4LR36WFC_PANASONIC
C4147 1 0402_OPEN 2 VSSSENSE
161 R6971 2
R6979 1 56_5% R6978 0402_OPEN
2
2 G
S TPCA8030_H 2
R6988
1
1
R6990 2
1
R6996 2
Q1408
D
0_5% VCCSENSE
161 R6972 2
1
C4148 2 0402_OPEN
0_5% C4149 1 0402_OPEN2
H_DPRSTP# PSI# H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0
15-,19-,311516161616161616-
42.2K_1%
220K_5% 63.4K_1% 1 R6992 2 200K_1% C4165 1 2 0.01uF_16V
5 6 7 8
1111-
+VBAT_CPU
CSP2
CSN2
1 R6993 2 11-
0_5%
INVENTEC
TITLE
Perugia10M
CPU POWER(VCC_CORE)
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
11 OF 63
x01
+V3S +V3 +V3LA
9-,11-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
+V1.5A
8-,34-
+V1.5 Q6 8 D 7 6 5 S 1 2 3 4
55-
7-,18-,31-,38-,39-,42-,48-,56-,57-
G
AO4406
1 2 5 6 1
C377 22uF_6.3v
D
S
S
D
680pF_50v
2
G
3
C8403 1 2
C8404 1
2 1
Q42
4
4 3
Q40
G
1 2 5 6 1 C356 47uF_6.3V
C8
1
AM3423P 0402_OPEN
2 0402_OPEN
AM3423P
R376 200_5%
1
SLP_S5#_5R
12-
1
R1
2
220K_5%
R6 200_5%
2
2 1 2 C365
2 1 C378
1
3D
S
2 680pF_50v
G 1 Q38 SSM3K7002FU
SLP_S5_5R
12-
1G
Q1 3 D
S
2 680pF_50v
SSM3K7002FU 2
R420 200_5%
2
3 1
D42
1
R421 220K_5%
2 2
BAT54_30V_0.2A
2 R418 +V5LA 220K_5%
5-,6-,7-,12-,18-,39-,491
D43
BAT54_30V_0.2A 1 D44 5-,6-,7-,12-,18-,39-,493 +V5LA
3
1
R417 1 BAT54A_30V_0.2A 200_5%
2
+V5LA
5-,6-,7-,12-,18-,39-,49-
SLP_S5#_5R
12-
U29-B 4 74ACT14MTC
14 3 7
8-,32-,42-
14 9
SLP_S3#_3R
U29-D 8
7 74ACT14MTC
2
U29-A 2 74ACT14MTC
14 1 7
R419 220K_5%
1
8-,49-
SLP_S3_5R
12-
SLP_S5_5R +V5A +V5S
+V5LA
5-,6-,7-,12-,18-,39-,49-
7-,8-,9-,11-,30-,34-,38-,39-,44-,45- 8-,12-,18-,29-,32-,34-,36-,37-,40-,42-,43-,44-,51-,59-,60-
4 3
Q25
S D
+V5S
8-,12-,18-,29-,32-,34-,36-,37-,40-,42-,43-,44-,51-,59-,60-
G
1 2 5 6
AM3423P
2 1
C366
1
R202 200_5%
2
U29-C 6 0.1uF_10V 74ACT14MTC
14 5 7 4 C8406 1 0402_OPEN 2 3
S 8-,32-,42-
SLP_S5#_3R Q26
D
BAT54_30V_0.2A 1 D26 3
5-,6-,7-,12-,18-,39-,49-
G
1 2 5 6
+V5LA
AM3423P C213
SLP_S3#_5R
9-,11-,60-
U29-F 12 74ACT14MTC
14 13 7
1 2 680pF_50v
INVENTEC
TITLE
Perugia10M
POWER(SLEEP)
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
12 OF 63
x01
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
+VCCP
+VCCP_CLKGEN Layout note: All decoupling 0.1uF disperse closed to pin
+V3S
+V3S_CLKGEN
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
L2501 BLM11A121S 1 2
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
1
C4027
1
C4028
1
C4029
1
C4030
1
C4032
1
C4034
1
C4035
1
C4036 L2502 BLM11A121S 1 2
Layout note: All decoupling 0.1uF disperse closed to pin 9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,591 C4037 1 C4038 1 C4039 1 C4040 1 C4041 +V3S +V3S
2 10uF_10v
2 10uF_10v
2 0.1uF_10v
2 0.1uF_10v
2 0.1uF_10v
2 0.1uF_10v
2 0.1uF_10v
2 0.1uF_10v
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,591
2 10uF_10v 2
2 2 2 0.1uF_10v 0.1uF_10v 0.1uF_10v 0.1uF_10v
R6031 1K_5%
2
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,591 R6032 2
1 R7130
1 R7129
CPU_BSEL0
15-,19-
+V3S U4001 OPEN OPEN 33_5%
26 45 36 12 39 61 20 49 VDD_SRC_IO VDD_SRC_IO VDD_SRC_IO VDD_IO VDD_SRC VDD_REF VDD_PLL3_IO VDD_CPU_IO NC PCI_STOP# CPU_STOP# CPU_1_MCH CPU_1_MCH# CPU_0 CPU_0# 2 1 10K_5% 10K_5% 10K_5% 2 9 2 55 16 VDD_48 VDD_PCI VDD_CPU VDD_PLL3 SRC_8_CPU_ITP SRC_8#_CPU_ITP# SRC_11_CLKREQ_H# SRC_11#_CLKREQ_G# SRC_10 SRC_10# 48 38 37 51 50 54 53 47 46 33 32 34 35 30 31 44 43 41 40 6 7 27 28 24 25 21 22 17 18 13 14 CLK_PCIE_SB CLK_PCIE_SB# CLK_3S_MINICARD2 CLK_3S_ICHPCI CLK_PEG_MCH CLK_PEG_MCH# CLK_PCIE_LAN CLK_PCIE_LAN# CLK_SATA CLK_SATA# CLKSS1_DREF CLKSS1_DREF# CLK_DREF CLK_DREF# CLKREQ_NEWCARD# CLKREQ_WLAN# CLK_PCIE_NCARD CLK_PCIE_NCARD# CLK_PCIE_WLAN CLK_PCIE_WLAN# CLK_NBCLK CLK_NBCLK# CLK_CPUBCLK CLK_CPUBCLK#
10K_5%_OPEN
2 2
10K_5%_OPEN
R7115 10K_5%
1
1 R7116 10K_5%
2.2K_5%
2
2 323221211414-
Card reader R967 R6029
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
Stuff 22._1% 22_1%
5032-
PCISTOP#_3 CPUSTOP#_3 CLK_NBCLK CLK_NBCLK# CLK_CPUBCLK CLK_CPUBCLK#
CLK_R_CARD48 CLK_R_SB48
1 R7128 2
R967 R6029
1 1
2 22_1% 2 22_1%
1
+VCCP
R7132
R71082 R7122 1
0402_OPEN
2 1
1K_5% R7107 CPU_BSEL0_USB48
CLK_SB14 10 57 62 1 3 4 5 56 64 63 2 60
475_1% 1 475_1% 1
2 2
R7111 R7112
535453535454-
CLKREQ_R_NEWCARD# CLKREQ_R_WLAN# CLK_PCIE_NCARD CLK_PCIE_NCARD# CLK_PCIE_WLAN CLK_PCIE_WLAN#
CPU_BSEL1 CPU_BSEL2 CLK_R_SB14
15-,1915-,1932-
10K_5% 1 R7120 1
2 R7127 2 33_5%
USB_FS_A FS_B_TEST_MODE REF_FS_C_TEST_SEL
2
CLKREQ_R_SATA# CLKREQ_R_MCH# 42CLK_R_KBPCI 51CLK_R_CBPCI
1 2
3219-
R7118 2 R7109 1 R7119 1 R7125 1
1 475_1% 2 475_1% 2 33_5% 2 33_5%
CLKREQ_SATA# CLKREQ_MCH# CLK_KBPCI CLK_CBPCI
1K_5% R7124
1
1
SRC_9 SRC_9# PCI_0_CLKREQ_A# PCI_1_CLKREQ_B# SRC_7_CLKREQ_F# SRC_7#_CLKREQ_E# PCI_2 PCI_3 SRC_6 SRC_6# CKPWRGD_PD# SCL SDA XTAL_IN XTAL_OUT VSS_PCI VSS_48 VSS_IO VSS_PLL3 VSS_SRC VSS_SRC VSS_SRC VSS_REF VSS_CPU SRC_3_CLKREQ_C# SRC_3#_CLKREQ_D# SRC_2 SRC_2# LCDCLK_27M LCDCLK#_27M_SS SRC_0_DOT_96 SRC_0#_DOT_96# PCI_4_SEL_LCDCLK# PCIF_5_ITP_EN SRC_4 SRC_4#
323233_5% 1 33_5% 1 2 2 R6042 R6043 5433-
CLK_PCIE_SB CLK_PCIE_SB#
R7131
0402_OPEN
R7126 0402_OPEN
CLK_R_PCI_DEBUG CLK_R_ICHPCI
19194646313119191919-
CLK_PWRGD
3259
CLK_PEG_MCH CLK_PEG_MCH# CLK_PCIE_LAN CLK_PCIE_LAN# CLK_SATA CLK_SATA# CLKSS1_DREF CLKSS1_DREF# CLK_DREF CLK_DREF#
ICH_3S_SMCLK ICH_3S_SMDATA
26-,27-,3226-,27-,32-
X401 14.31818MHZ FSA FSB FSC FSB CLOCK FREQUENCY HOST CLOCK FREQUENCY
1 2
8 11 15 19 23 29 42 58 52
1 0 0
1 1 0
0 0 0
667 800 1066
166 200 266
1 C4031 27pF_50V 2
1 30PPM 2
C4033 27pF_50V
SLG_SLG8SP510T_TSSOP_64P
Please place close to CLKGEN within 500mils
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
+V3S
1 R6045 2
*CLKREQ# pin controls SRC Table.
Byte5: bit6 =0(PWD) Byte5: bit6 =1 Byte5: bit4 =0(PWD) Byte5: bit4 =1
Byte6: bit7=0, disable CR#_E; 1,enable CR#_E
R6050 10K_5%
1
0402_OPEN
1
CR#_E
SRC6
2
R6044 2 10K_5%
CR#_A
SRC0
SRC2
CR#_B
SRC1
SRC4
Byte6: bit6=0, disable CR#_F; 1,enable CR#_F
27_Select=0
LCD_SST 100MHz
CR#_F
Byte5: bit5=0, disable CR#_B; 1,enable CR#_B SRC8 Byte6: bit5=0, disable CR#_G; 1,enable CR#_G
27_Select=1
27MHz NON-SPREAD CLOCK
Byte5: bit7=0, disable CR#_A; 1,enable CR#_A
CR#_G
Byte5: bit2 =0(PWD) SRC0 Byte5: bit2 =1 SRC2 Byte5: bit0 =0(PWD) SRC1 Byte5: bit0 =1 SRC4 SRC9 Byte6: bit4=0, disable CR#_H; 1,enable CR#_H
CR#_C
INVENTEC
TITLE
CR#_D
CR#_H
Byte5: bit1=0, disable CR#_D; 1,enable CR#_D SRC10 CHANGE by Loren 10-Oct-2008
Perugia10M
CLOCK_GENERATOR
DOC. NUMBER REV
Byte5: bit3=0, disable CR#_C; 1,enable CR#_C
SIZE CODE
A3
CS
SHEET
1310A2250501
13 OF 63
x01
H_A#(35:3)
21-
CN807-1
H_A#(3) H_A#(4) H_A#(5) H_A#(6) H_A#(7) H_A#(8) H_A#(9) H_A#(10) H_A#(11) H_A#(12) H_A#(13) H_A#(14) H_A#(15) H_A#(16)
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD01 RSVD02 RSVD03 RSVD04 RSVD05 RSVD06 RSVD07 RSVD08 RSVD09 RSVD010 ADS# BNR# BPRI# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 1 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 2121212121212121-
H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BREQ#0 H_INIT# H_LOCK# R59
2
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,591 R153
ADDR GROUP 0
DEFER# DRDY# DBSY#
56_5%
2
CLOSED TO CPU
CONTROL
BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM# BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
3121-
+VCCP
H_REQ#(4:0)
21-
H_ADSTB#0
H_REQ#(0) H_REQ#(1) H_REQ#(2) H_REQ#(3) H_REQ#(4)
21-
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,5921-
51 ohm +/-1% pull-up to +VCCP (VCCP) if ITP is implemented
H_CPURST# 0402_OPEN
H_RS#(0) H_RS#(1) H_RS#(2)
H_RS#(2:0)
212121-
H_TRDY# H_HIT# H_HITM#
H_A#(17) H_A#(18) H_A#(19) H_A#(20) H_A#(21) H_A#(22) H_A#(23) H_A#(24) H_A#(25) H_A#(26) H_A#(27) H_A#(28) H_A#(29) H_A#(30) H_A#(31) H_A#(32) H_A#(33) H_A#(34) H_A#(35)
ADDR GROUP 1
XDP/ITP SIGNALS
1414141432-
H_BPM5_PREQ# H_TCK TDI_FLEX H_TMS XDP_DBRESET#
1 R128
THERMAL
PROCHOT# THERMDA THERMDC D21 A24 B25 C7
14R152 1
PROCHOT#
2 68_5%
+VCCP
54.9_1% 10mils/10mils
2 181818-,19-,31-
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#
2131313131313131-
VR_PWRGD
11-,18-,321
H_THERMDA THERM_MINUS PM_THRMTRIP#
ICH_PROCHOT# 33-
ICH
THERMTRIP#
R7404 2M_5%
2
H CLK
BCLK0 BCLK1 A22 A21 1313-
CLK_CPUBCLK CLK_CPUBCLK# Q72063 2B C
Q7207 3 D 1G
S
SSM3K7002FU 2
141 R7305 2
RESERVED +VCCP
PROCHOT#
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,591
1
C7402
E 2.2K_5% 2SC2411K 1
2 0402_OPEN
R65
2
14-
54.9_1% 1 R142 2
1
H_BPM5_PREQ# TDI_FLEX H_TMS H_TCK
14-
FOX_PZ4782K_274M_41_478P
54.9_1% R63 2
14-
54.9_1% 1 R64 2 GMCH CPU ICH9 +VCCP 54.9_1%
14-
INVENTEC
PM_THRMTRIP# should be T at CPU
CHANGE by Loren 10-Oct-2008 TITLE
Perugia10M
PENRYN-1
DOC. NUMBER REV
SIZE CODE
A3
CS
SHEET
1310A2250501
14 OF 63
x01
H_D#(63:0)
15-,21-
CN807-2
H_D#(0) H_D#(1) H_D#(2) H_D#(3) H_D#(4) H_D#(5) H_D#(6) H_D#(7) H_D#(8) H_D#(9) H_D#(10) H_D#(11) H_D#(12) H_D#(13) H_D#(14) H_D#(15)
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
15-,21-
H_D#(32) H_D#(33) H_D#(34) H_D#(35) H_D#(36) H_D#(37) H_D#(38) H_D#(39) H_D#(40) H_D#(41) H_D#(42) H_D#(43) H_D#(44) H_D#(45) H_D#(46) H_D#(47)
21212115-,21-
H_D#(63:0)
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#(63:0)
21212115-,21-
DATA GRP 0
DATA GRP 2
H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#(63:0)
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,591 R911
H_D#(16) H_D#(17) H_D#(18) H_D#(19) H_D#(20) H_D#(21) H_D#(22) H_D#(23) H_D#(24) H_D#(25) H_D#(26) H_D#(27) H_D#(28) H_D#(29) H_D#(30) H_D#(31)
212121-
1K_1%
2 1 R912
H_DSTBN#1 H_DSTBP#1 H_DINV#1 GTLREF
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26
D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 1 R60
H_D#(48) H_D#(49) H_D#(50) H_D#(51) H_D#(52) H_D#(53) H_D#(54) H_D#(55) H_D#(56) H_D#(57) H_D#(58) H_D#(59) H_D#(60) H_D#(61) H_D#(62) H_D#(63)
212121-
DATA GRP 1
DATA GRP 3
H_DSTBN#3 H_DSTBP#3 H_DINV#3 Note: COMP1 & COMP3 5-mil wide COMP0 & COMP2 18-mil wide
2K_1%
2
Layout note: Zo=55 ohm, 0.5" max for GTLREF.
R901 R900 R62 R61
11-,19-,31-
1 1 1 1
2 2 2 2
27.4_1% 54.9_1% 27.4_1% 54.9_1%
MISC
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
H_DPRSTP#
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
13-,1913-,1913-,19-
B22 BSEL0 B23 BSEL1 C21 BSEL2
CLOSED TO CPU 31H_DPSLP# 21H_DPWR# 31H_PWRGD 21H_CPUSLP# 11PSI#
FOX_PZ4782K_274M_41_478P
0402_OPEN
2
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
INVENTEC
TITLE
Perugia10M
PENRYN-2
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
15 OF 63
x01
+VCC_CORE
11-,16-,59-
+VCC_CORE
11-,16-,59-
CN807-3
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC001 VCC002 VCC003 VCC004 VCC005 VCC006 VCC007 VCC008 VCC009 VCC010 VCC011 VCC012 VCC013 VCC014 VCC015 VCC016 VCC017 VCC018 VCC019 VCC020 VCC021 VCC022 VCC023 VCC024 VCC025 VCC026 VCC027 VCC028 VCC029 VCC030 VCC031 VCC032 VCC033 VCC034 VCC035 VCC036 VCC037 VCC038 VCC039 VCC040 VCC041 VCC042 VCC043 VCC044 VCC045 VCC046 VCC047 VCC048 VCC049 VCC050 VCC051 VCC052 VCC053 VCC054 VCC055 VCC056 VCC057 VCC058 VCC059 VCC060 VCC061 VCC062 VCC063 VCC064 VCC065 VCC066 VCC067 VCC068 VCC069 VCC070 VCC071 VCC072 VCC073 VCC074 VCC075 VCC076 VCC077 VCC078 VCC079 VCC080 VCC081 VCC082 VCC083 VCC084 VCC085 VCC086 VCC087 VCC088 VCC089 VCC090 VCC091 VCC092 VCC093 VCC094 VCC095 VCC096 VCC097 VCC098 VCC099 VCC0100 VCCP01 VCCP02 VCCP03 VCCP04 VCCP05 VCCP06 VCCP07 VCCP08 VCCP09 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
1 3
2
C142 900uF_2.5V
+VCCP
PLACE THESE INSIDE SOCKET CAVITY ON L8 (NORTH SIDE
SECONDARY) 9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
1 1 C930 2
C153
1
C154
1
C155
1
C120
1
C121
1
C119
2 220uF_2v_15mR_Panasonic
2 2 2 2 2 0.1uF_10V 0.1uF_10V 0.1uF_10V 0.1uF_10V 0.1uF_10V 0.1uF_10V
+V1.5S
8-,24-,34-,44-,53-,54-,59-
B26 VCCA01 C26 VCCA02 VID0 VID1 VID2 VID3 VID4 VID5 VID6 AD6 AF5 AE5 AF4 AE3 AF3 AE2 11111111111111-
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
+VCC_CORE
11-,16-,591
C957 0.01uF_16v
1 2
1
R114 100_1%
2 11-
C956 2 10uF_6.3V
VCCSENSE
AF7
VCCSENSE VSSSENSE
LAYOUT NOTE: PLACE C2461 NEAR PIN B26
VSSSENSE
AE7
11-
FOX_PZ4782K_274M_41_478P
1
R127 100_1%
2
LAYOUT NOTE: ROUTE VCCSENSE AND VSSSENSE TRACE AT 24.7 OHM WITH 50 MIL SPACEING PLACE PU AND PD WITHIN I INCH OF CPU
INVENTEC
TITLE
Perugia10M
PENRYN-3
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
16 OF 63
x01
CN807-4
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS001 VSS002 VSS003 VSS004 VSS005 VSS006 VSS007 VSS008 VSS009 VSS010 VSS011 VSS012 VSS013 VSS014 VSS015 VSS016 VSS017 VSS018 VSS019 VSS020 VSS021 VSS022 VSS023 VSS024 VSS025 VSS026 VSS027 VSS028 VSS029 VSS030 VSS031 VSS032 VSS033 VSS034 VSS035 VSS036 VSS037 VSS038 VSS039 VSS040 VSS041 VSS042 VSS043 VSS044 VSS045 VSS046 VSS047 VSS048 VSS049 VSS050 VSS051 VSS052 VSS053 VSS054 VSS055 VSS056 VSS057 VSS058 VSS059 VSS060 VSS061 VSS062 VSS063 VSS064 VSS065 VSS066 VSS067 VSS068 VSS069 VSS070 VSS071 VSS072 VSS073 VSS074 VSS075 VSS076 VSS077 VSS078 VSS079 VSS080 VSS081 VSS082 VSS083 VSS084 VSS085 VSS086 VSS087 VSS088 VSS089 VSS090 VSS091 VSS092 VSS093 VSS094 VSS095 VSS096 VSS097 VSS098 VSS099 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
FOX_PZ4782K_274M_41_478P
INVENTEC
TITLE
Perugia10M
PENRYN-4
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
17 OF 63
x01
+V5S
8-,12-,29-,32-,34-,36-,37-,40-,42-,43-,44-,51-,59-,60-
U1
1 2 FON VIN VO VSET GND GND GND GND 8 7 6 5
C810
FAN1_DAC0_3 42-
1
3 4
2.2uF_6.3v 2
GMT_G995P1U_SOP8_8P +V5S_FAN
9-,11-,12-,13-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
+V3S 1 2 C3 2.2uF_6.3v CN802 1 1 2 2 G G1 3 3 G G2 ACES_85205_0300N_3P
1
R2 10K_5%
2 42-
FAN_TACH1
1 C1
1 2
C2 680pF_50V
VR_PWRGD 11-,14-,321
FAN CN
2 220pF_25V
close to KBC
+V5LA
5-,6-,7-,12-,39-,49-
R187 2M_5%
2
6-,18-
THRM_SHUTDWN#
1G
1
Q23 3 D
S
R66
U4
2 5 VCC SET GND 1 2 3 1
R36
2
SSM3K7002FU 2
14-,19-,31- 1 R188 2
150_5% 1
4 HYST OT
24.9K_1%
6-,18-
PM_THRMTRIP#
C76 0.1uF_10V 2
THRM_SHUTDWN#
Q24 3 2B C E 330_5% 2SC2411K 1
1 2
C202 0402_OPEN
GMT_G708T1U_SOT23_5P
+V3LA
7-,12-,31-,38-,39-,42-,48-,56-,57-
Thermal shoutdown at 86.1C +/-3C from 60C to 100C RSET=0.0012*T - 0.9308*T+96.147 Hysteresis is 30C
C193 100pF_50v 1 2
1
2
1 C165 2 0.1uF_10V
U14
VDD D+ DSCL SDA ALERT 8 7 6 5 2 3 4
5-,425-,42-
EC_SMB2_CLK EC_SMB2_DATA
H_THERMDA THERM_MINUS THRM_SHUTDWN#
14146-,18-
T_CRIT_A GND
WINB_W83L771AWG_TSSOP_8P
Thermal Sensor For CPU
LAYOUT NOTES: PUT THE THERMAL SENSOR CLOSE TO CPU
INVENTEC
TITLE
Perugia10M
THERMAL&FAN CONTROLLER
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
18 OF 63
x01
LOW=DMIx2 MCH_CFG(5) HIGH=DMIx4
MCH_CFG(7) (CPU Strap)
LOW=RSVD HIGH=Mobile CPU
MCH_CFG(9) LOW=Reverse Lane PCIE Graphics HIGH=Normal operation Lane
NOTE : USE 4K-OHM RESISTOR WHEN INSTALLING PULL-UP/PULL-DOWN RESISTOR ON ANY MCH-CFG CONNECTION/PINS.
LOW=TPM Enable HIGH=TPM Disable
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 B31 AJ6 M1
MCH_CFG(13:12) XOR/ALLZ
00=PARTIAL CLOCK GATING DISABLE 01=XOR MODE ENABLE 10=ALL-Z MODE ENABLE 11=NORMAL OPERATION
MCH_CFG(16) (FSB Dynamic ODT)
LOW=Dynamic ODT Disable HIGH=Dynamic ODT Enable
MCH_CFG(6)
U7-2
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 SM_VREF SM_PWROK SM_REXT SM_DRAMRST# DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK# DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43 AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43 B33 B32 G33 F33 E33 262627272626272726-,2826-,2827-,2827-,2826-,2826-,2827-,2827-,2826-,2826-,2827-,2827-,2819191919-
NOTE: CFG[2:0] STRP : 010b : 800 MT/S 011b : 667 MT/S MCH_CFG(5) MCH_CFG(6) MCH_CFG(7) MCH_CFG(9)
191919191
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
+V3S
MA_CLK_DDR1 MA_CLK_DDR2 MB_CLK_DDR1 MB_CLK_DDR2 MA_CLK_DDR1# MA_CLK_DDR2# MB_CLK_DDR1# MB_CLK_DDR2# MA_CKE0 MA_CKE1 MB_CKE0 MB_CKE1 MA_CS0# MA_CS1# MB_CS0# MB_CS1# MA_ODT0 MA_ODT1 MB_ODT0 MB_ODT1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL
8-,26-,271
+V1.8
8-,19-,23-,24-,26-,27-,59-
R889 2.2K_1%
1 R875
1
0402_OPEN
2 2
1 R877 R874 0402_OPEN 0402_OPEN 2
1
1 R870 R871 0402_OPEN 0402_OPEN 2
2
2
2
1
R130 80.6_1%
1919-
MCH_CFG(19) MCH_CFG(10) MCH_CFG(12) MCH_CFG(13) MCH_CFG(16)
191919191
1919-
SM_RCOMP SM_RCOMP#
MCH_CFG(20)
AY21
RSVD20
R888 0402_OPEN
1 R886
1
0402_OPEN
2 2
1 R876 R887 CPU_BSEL0 0402_OPEN 0402_OPEN
13-,1513-,1513-,15-
R879 R878 R880
1 1 1
2 2 2
1K_5% 1K_5% 1K_5%
CPU_BSEL1
2 2
A47 BG23 BF23 BH18 BF18
RSVD21 RSVD22 RSVD23 RSVD24 RSVD25
R143 80.6_1%
2
CPU_BSEL2
MCH_CFG(17:3) +V3S
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
19-
M_VREF
1
2
19-,26-
R868
1 2
10K_5%
19-,27-
PM_EXTTS#0 PM_EXTTS#1
R869
10K_5%
MCH_CFG(3) MCH_CFG(4) MCH_CFG(5) MCH_CFG(6) MCH_CFG(7) MCH_CFG(8) MCH_CFG(9) MCH_CFG(10) MCH_CFG(11) MCH_CFG(12) MCH_CFG(13) MCH_CFG(14) MCH_CFG(15) MCH_CFG(16)
TP3 TP2
R885 1 TP1
2 499_1%
1
13131313131332-
C889 0.1uF_10V
CLK_DREF CLK_DREF# CLKSS1_DREF CLKSS1_DREF# CLK_PEG_MCH CLK_PEG_MCH# DMI_TXN(3:0)
2
DMI_TXN(0) DMI_TXN(1) DMI_TXN(2) DMI_TXN(3)
32-
MCH_CFG(19) MCH_CFG(20)
1919-
DMI_TXP(0) DMI_TXP(1) DMI_TXP(2) DMI_TXP(3)
32-
DMI_TXP(3:0)
R842 0_5%_OPEN VR_PWRGD_CK505 +V1.8
8-,19-,23-,24-,26-,27-,591 R131 3211-,19-,322 1
PM_SYNC# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PLT_RST# PM_THRMTRIP# PM_DPRSLPVR
3211-,15-,3119-,2619-,2733-,4214-,18-,3111-,32-
PM_EXTTS#0 PM_EXTTS#1
R165
1
2
100_5%
PM_PWROK
R29 B7 N33 P32 AT40 AT11 T20 R32
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
DMI_RXN(0) DMI_RXN(1) DMI_RXN(2) DMI_RXN(3)
32-
DMI_RXN(3:0) +VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
DMI_RXP(0) DMI_RXP(1) DMI_RXP(2) DMI_RXP(3)
DMI_RXP(3:0)
1 R7038
1K_1%
2
1K_1%
2 191 R133
SM_RCOMP_VOH
3K_1% 1 2
2
C136 0.01uF_16v
1 2
C138 2.2uF_6.3v
191 R132
SM_RCOMP_VOL
1K_1% 1
2
C135 0.01uF_16v
1 2
C137 2.2uF_6.3v
2
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1
1 2 C1020 0.1uF_10V
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25
1
R7039 499_1%
2
GFX_VR_EN
C34
4 mils/ 7mils
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# AH37 AH36 AN36 AJ35 AH34 N28 M28 G36 E36 K36 H36 323211-,19-,3232-
CL_CLK0 CL_DATA0 PM_PWROK CL_RST#0
2 2
+V3S
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
iHDMI enable : stuff iHDMI disnable : no stuff
R7036 1 2 2.2K_5% 4848-
DDPC_CTRLCLK DDPC_CTRLDATA TMDS_SCLK TMDS_SDATA
1332-
R7032 1 R7033 1
0402_OPEN 0402_OPEN
TMDS_SCLK TMDS_SDATA
R7037 1
2 2.2K_5%
CLKREQ_R_MCH# R7031 MCH_ICH_SYNC# 2 1 9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59- +VCCP 0402_OPEN 56_5% R7030
TSATN B12 2 1 HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 3131313131-
iHDMI enable : no stuff iHDMI disnable : stuff
LOW=ONLY DIGITAL DISPLAY PORT MCH_CFG(20) (SDVO/DP/iHDMI)OR PCIEIS OPERATIONAL DIGITAL DISPLAY HIGH= DIGITAL DISPLAY PORT PORT(SDVO/DP/iHDMI) (SDVO/DP/iHDMI)AND PCIE ARE OPERATING CONCURRENT WITH PCIE VIA THE PEG PORT
MCH_CFG(19) (DMI LANE REVERSAL)
LOW=NORMAL HIGH=LANES REVERSED
1 R7090 2
33_5%
HDA_BCLK HDA_RST# HDA_SDIN3 HDA_SDOUT HDA_SYNC Loren 10-Oct-2008
INVENTEC
TITLE
Perugia10M
CANTIGA-1
DOC. NUMBER REV
SIZE CODE
ITL_CANTIGA_GM_FCBGA_1329P CHANGE by
A3
CS
SHEET
1310A2250501
19 OF 63
x01
+V3S
9-,11-,12-,13-,18-,19-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
1
R7050 10K_5%
2
2
1
R7054 10K_5% +VCCP U7-3
L32 G32 M32 M33 K33 J33 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA PEG_COMPI PEG_COMPO T37 T36 1 R7055 2 9-,11-,13-,14-,15-,16-,19-,21-,23-,24-,31-,34-,59-
INV_PWM_3 LCM_BKLTEN
30-,4230-,421
R7046 1
0402_OPEN 2
49.9_1%
R7040 100K_1%
2
LCM_DDCPCLK LCM_DDCPDATA LCM_3S_VDDEN
30-
3030-
1
1
R7044 100K_1%
2
R7045 2.4K_1%
2
LVDS_TXCLN LVDS_TXCLP LVDS_TXCUN LVDS_TXCUP LVDS_TXDL0N LVDS_TXDL1N LVDS_TXDL2N LVDS_TXDL0P LVDS_TXDL1P LVDS_TXDL2P LVDS_TXDU0N LVDS_TXDU1N LVDS_TXDU2N LVDS_TXDU0P LVDS_TXDU1P LVDS_TXDU2P
30303030303030-
M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37
L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40
303030-
303030-
303030-
48-
TMDS_HPD_IC#
R7051 1 R7052 1 R7053 1
2 75_1% 2 75_1% 2 75_1%
F25 H25 K25 H24
TVA_DAC TVB_DAC TVC_DAC TV_RTN
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
2 R7041 1
J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 HDMI_NB_TXCN C1021 0.1uF_10V C1022 0.1uF_10V AA40 HDMI_NB_TX0N 1 2 C1023 AD43 HDMI_NB_TX1N 1 2 AC46 HDMI_NB_TX2N 1 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 HDMI_NB_TXCP C1025 AA39 HDMI_NB_TX0P 1 AD42 HDMI_NB_TX1P AD46 HDMI_NB_TX2P
2
0.1uF_10V C1024 1 2
0.1uF_10V
48484848-
20-,29-
HDMI_NBC_TXCN HDMI_NBC_TX0N HDMI_NBC_TX1N HDMI_NBC_TX2N
CRT_R Trace Wd: 11mil(to R) CRT_G Trace Wd: 4mil(to Conn) CRT_B CRT_DDCCLK CRT_DDCDATA CRT_HSYNC CRT_VSYNC
1
150_1%
2 R7042 1 20-,29-
CRT_B CRT_G CRT_R
20-,2920-,2920-,29-
E28 G28 J28 G29
CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
150_1% 2 R7043 1 150_1%
20-,29-
CLOSE TO CALISTOGA
29292929-
1 R7048 2 30_5% 1 R7049 2 30_5%
CRT_H CRT_V
H32 J32 J29 E29 L29
0.1uF_10V C1026 2 1
2
0.1uF_10V C1027 1 2
0.1uF_10V C1028 1 2
0.1uF_10V
R7047 1.02K_0.5% Close GMCH and away form any signal (spacing>30mil)
2
484848-
HDMI_NBC_TXCP HDMI_NBC_TX0P HDMI_NBC_TX1P HDMI_NBC_TX2P
ITL_CANTIGA_GM_FCBGA_1329P
INVENTEC
TITLE
Perugia10M
CANTIGA-2
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
20 OF 63
x01
H_D#(63:0)
15-
14-
H_A#(35:3)
U7-1
H_D#(0) H_D#(1) H_D#(2) H_D#(3) H_D#(4) H_D#(5) H_D#(6) H_D#(7) H_D#(8) H_D#(9) H_D#(10) H_D#(11) H_D#(12) H_D#(13) H_D#(14) H_D#(15) H_D#(16) H_D#(17) H_D#(18) H_D#(19) H_D#(20) H_D#(21) H_D#(22) H_D#(23) H_D#(24) H_D#(25) H_D#(26) H_D#(27) H_D#(28) H_D#(29) H_D#(30) H_D#(31) H_D#(32) H_D#(33) H_D#(34) H_D#(35) H_D#(36) H_D#(37) H_D#(38) H_D#(39) H_D#(40) H_D#(41) H_D#(42) H_D#(43) H_D#(44) H_D#(45) H_D#(46) H_D#(47) H_D#(48) H_D#(49) H_D#(50) H_D#(51) H_D#(52) H_D#(53) H_D#(54) H_D#(55) H_D#(56) H_D#(57) H_D#(58) H_D#(59) H_D#(60) H_D#(61) H_D#(62) H_D#(63)
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,591
H_A#(3) H_A#(4) H_A#(5) H_A#(6) H_A#(7) H_A#(8) H_A#(9) H_A#(10) H_A#(11) H_A#(12) H_A#(13) H_A#(14) H_A#(15) H_A#(16) H_A#(17) H_A#(18) H_A#(19) H_A#(20) H_A#(21) H_A#(22) H_A#(23) H_A#(24) H_A#(25) H_A#(26) H_A#(27) H_A#(28) H_A#(29) H_A#(30) H_A#(31) H_A#(32) H_A#(33) H_A#(34) H_A#(35)
14141414141414141313151414141414-
R154 221_1%
2
MCH_HSWING
211
R155 100_1%
1
2
C156 0.1uF_10V
2
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_DEFER# H_DBSY# CLK_NBCLK CLK_NBCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
MCH_HRCOMP
21-
R893
1
2
24.9_1%
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
151515151515151515151515-
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#(0) H_REQ#(1) H_REQ#(2) H_REQ#(3) H_REQ#(4) H_RS#(0) H_RS#(1) H_RS#(2)
Layout notes: Trace need be 10 mils wide with 20 mils MCH_HSWING MCH_HRCOMP
2121-
14-
C5 E3
H_REQ#(4:0)
H_SWING H_RCOMP
14-
H_CPURST# H_CPUSLP#
1415-
C12 E11
H_RS#(2:0)
H_CPURST# H_CPUSLP#
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,591 R148
A11 B11
H_AVREF H_DVREF
ITL_CANTIGA_GM_FCBGA_1329P
1K_1%
2 1 R149
2K_1%
2
1 2
C145 0.1uF_10V
INVENTEC
TITLE
Perugia10M
CANTIGA-3-HOST
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
21 OF 63
x01
MB_DATA(63:0) MA_DATA(63:0)
27-
U7-5 U7-4
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 BB20 BD20 AY20 26-,2826-,2826-,2826-,2826-,2826-,28-
MA_BA0 MA_BA1 MA_BA2 MA_RAS# MA_CAS# MA_WE#
26SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
MA_DM(0) MA_DM(1) MA_DM(2) MA_DM(3) MA_DM(4) MA_DM(5) MA_DM(6) MA_DM(7)
26-
MA_DM(7:0)
MA_DQS(0) MA_DQS(1) MA_DQS(2) MA_DQS(3) MA_DQS(4) MA_DQS(5) MA_DQS(6) MA_DQS(7) MA_DQS#(0) MA_DQS#(1) MA_DQS#(2) MA_DQS#(3) MA_DQS#(4) MA_DQS#(5) MA_DQS#(6) MA_DQS#(7) MA_A(0) MA_A(1) MA_A(2) MA_A(3) MA_A(4) MA_A(5) MA_A(6) MA_A(7) MA_A(8) MA_A(9) MA_A(10) MA_A(11) MA_A(12) MA_A(13) MA_A(14)
MA_DQS(7:0)
26-
MA_DQS#(7:0)
26-,28-
MA_A(14:0)
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2
BC16 BB17 BB33
27-,2827-,2827-,28-
MB_BA0 MB_BA1 MB_BA2 MB_RAS# MB_CAS# MB_WE#
SB_RAS# SB_CAS# SB_WE#
AU17 BG16 BF14
27-,2827-,2827-,28-
27SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 27AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
MB_DM(7:0)
MB_DQS(7:0)
27-
MB_DQS#(7:0)
27-,28-
MB_A(0) MB_A(1) MB_A(2) MB_A(3) MB_A(4) MB_A(5) MB_A(6) MB_A(7) MB_A(8) MB_A(9) MB_A(10) MB_A(11) MB_A(12) MB_A(13) MB_A(14)
MB_A(14:0)
ITL_CANTIGA_GM_FCBGA_1329P
ITL_CANTIGA_GM_FCBGA_1329P
INVENTEC
TITLE
Perugia10M
CANTIGA-4-DDR2
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 11-Oct-2008
CS
SHEET
1310A2250501
22 OF 63
x01
+V1.8
8-,19-,23-,24-,26-,27-,59AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 BA36 BB24 BD16 BB21 AW16 AW13 AT13
+VCCP U7-7
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36_NC VCC_SM_37_NC VCC_SM_38_NC VCC_SM_39_NC VCC_SM_40_NC VCC_SM_41_NC VCC_SM_42_NC VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 1
U7-6
2 1
C168 220uF_2.5V
1 2
C915 10uF_6.3v
1 2
C917 0.22uF_6.3v
1 2
C918 0.22uF_6.3v
1 2
C908 0.1uF_10V
308 mils from the Edge
Cavity Capacitors
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
+VCCP
R866 0_5%
2
T32
+VCCP
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
+V1.8 C122 220uF_2.5V
8-,19-,23-,24-,26-,27-,59-
2
2 1
1
C925 0.1uF_10V
1 2
C124 22uF_6.3v
1 2
C102 22uF_6.3v
ITL_CANTIGA_GM_FCBGA_1329P
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
AV44 BA37 AM40 AV21 AY5 AM10 BB13
AJ14 AH14
1
VCC_AXG_SENSE VSS_AXG_SENSE
C932 0.1uF_10V
1 2
C934 0.1uF_10V
1 2
C939
1
C927
1
C904
1
C903 1uF_6.3V
1 2
C894 1uF_6.3V
2
2 2 2 0.47uF_6.3v 0.22uF_6.3v 0.22uF_6.3v
ITL_CANTIGA_GM_FCBGA_1329P
INVENTEC
TITLE
Perugia10M
CANTIGA-5-POWER
DOC. NUMBER REV
SIZE CODE
A3
CHANGE by Loren 10-Oct-2008
CS
SHEET
1310A2250501
23 OF 63
x01
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
+V3S
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59+V3S +NB_VCCA_CRT_DAC
2 1
1 2
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
C43 0.1uF_10V
C44 0.01uF_16v
L3 1 2 BLM11A121S 1 C45 0.1uF_10V 2 C47 0.01uF_16v 2 1 U7-8
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
+VCCP
+VCCP L2 1 2 1 2 C40 220uF_2.5V 1 2 C41 1 2 0.1uF_10V C42 0.1uF_10V BLM11A121S
B27 A26
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
1 2
C895 4.7uF_6.3v
1 2
C906 2.2uF_6.3v
1 2
C907 0.47uF_6.3v
1 2
C232 100uF_6.3v
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
+VCCP L813 1 2 1 C953 2 4.7uF_6.3v 1 C952 2
+NB_VCCA_DPLL
A25 B25
VCCA_DAC_BG VSSA_DAC_BG
BLM11A121S
F47 L48 AD1 AE1
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL
Place on the Edge
0.1uF_10V
+V1.8
8-,19-,23-,24-,26-,27-,59-
+NB_VCCA_HPLL +NB_VCCA_MPLL
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
L812 1 2 1 2 C950 22uF_6.3v 1 2 C951 +V1.5S 0.1uF_10V +V1.05_PEGPLL
24-
+VCCP
BLM11A121S
1 C46 1000pF_50v 2
J48 J47
VCCA_LVDS VSSA_LVDS
8-,16-,24-,34-,44-,53-,54-,59-
1 2
C929 1uF_6.3V +V1.8
1 L806 2 BLM11A121S
1 2
C896
AD48
1 2
C890 0.1uF_10V
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
0.1uF_10V
VCCA_PEG_BG 8-,19-,23-,24-,26-,27-,59-
+VCCP
AA48
2 1
VCCA_PEG_PLL
1 C926 2 0.1uF_10V
C933 10uF_6.3v +V1.8
8-,19-,23-,24-,26-,27-,59-
2 1
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
C167 100uF_6.3v
1 2
C171 4.7uF_6.3v
1 2
C170 22uF_6.3v
1 2
C936 1uF_6.3V
+VCCP
2 1 C954 1 C916 0.1uF_10V
AP28 AN28 AP25 AN25 AN24 9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59AM28 AM26 AM25 AL25 AM24 AL24 C1030 C1029 1 1 C7505 1 AM23 AL23 2.2uF_6.3V 2 2 2
1000pF_50v
2 22uF_6.3v 2
+V3S
+V1.5S
8-,16-,24-,34-,44-,53-,54-,591 R7056 2
0.1uF_10V
0.01uF_16V
1
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
BF21 BH20 BG20 BF20
D814 BAT54_30V_0.2A
VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
B22 B21 A21
+V3S
9-,11-,12-,13-,18-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,591 R850
C909 1 0.1uF_10V 2
10_5%
2
+VCCP
3
2 1
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9
1
C66
C67 22uF_6.3v
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
VCC_TX_LVDS
K47 C35 B35 A35
+V1.5S
8-,16-,24-,34-,44-,53-,54-,59-
B24 A24
VCCA_TV_DAC_1 VCCA_TV_DAC_2
C1031 1 0.1uF_10V 2 1 C49 0.1uF_10V C50 0.01uF_16v 2
0_5%
1
1 2 BLM11A121S 1 2
L4
R7057 0_5%_OPEN
VCC_HV_1 VCC_HV_2 VCC_HV_3
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
+VCCP
+NB_VCC_HDA
A32
VCC_HDA VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 V48 U48 V47 U47 U46
2
2 1
+NB_VCCD_TVDAC M25 1 L5 2 C51 BLM11A121S 1 2 0.1uF_10V 1 2 BLM11A121S 1 +V1.05_PEGPLL
24-
VCCD_TVDAC VCCD_QDAC
C962 4.7uF_6.3v
2 1
C935 22uF_6.3v
1 2
C955 220uF_2.5V
+NB_VCCD_QDAC L28
9-,11-,13-,14-,15-,16-,19-,20-,21-,23-,24-,31-,34-,59-
AA47
VCCD_PEG_PLL
L7
8-,19-,23-,24-,26-,27-,59-
C63 0.1uF_10V
+V1.8
M38 L37
VCCD_LVDS_1 VCCD_LVDS_2
2
VTTLF1 VTTLF2 VTTLF3
A8 L1 AB2
2 1
1 2
C48 0.1uF_10V
C64 1uF_6.3v
ITL_CANTIGA_GM_FCBGA_1329P
1 C169 1 2 2
C166
1 2
C146
2 1
+VCCP
+NB_VCCD_HPLL AF1
VCCD_HPLL
VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
AH48 AF48 AH47 AG47
C928 0.1uF_10V
INVENTEC
TITLE
Perugia10M
CANTIGA-6
DOC. NUMBER REV
0.47uF_6.3v
0.47uF_6.3v
0.47uF_6.3v Loren 10-Oct-2008
SIZE CODE
A3
CHANGE by
CS
SHEET
1310A2250501
24 OF 63
x01
U7-9
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13
U7-10
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_235 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29
AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42
AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 B2 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
INVENTEC
TITLE
ITL_CANTIGA_GM_FCBGA_1329P
Perugia10M
CANTIGA-7
DOC. NUMBER REV
ITL_CANTIGA_GM_FCBGA_1329P CHANGE by Loren 10-Oct-2008
SIZE CODE
A3
CS
SHEET
1310A2250501
25 OF 63
x01
MA_A(14:0)
22-,28-
22-
MA_DATA(63:0)
CN804-1
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10_AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
+V1.8
8-,19-,23-,24-,27-,59-
Layout notes: Place these Caps closed So-Dimm0
112 111 117 96 95 118 81 82 87 103 88 104 199 83 120 50 69 163 1 G1 G2
CN804-2
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDDSPD NC1 NC2 NC3 NC4 NCTEST VREF GND GND VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
MA_BA2 MA_BA0 MA_BA1 MA_CS0# MA_CS1# MA_CLK_DDR1 MA_CLK_DDR1# MA_CLK_DDR2 MA_CLK_DDR2# MA_CKE0 MA_CKE1 MA_CAS# MA_RAS# MA_WE#
22-,2822-,2822-,2819-,2819-,281919191919-,2819-,2822-,2822-,2822-,28-
1 2
C59
1
C91
1 2
C93
0.1uF_10V
1 2
C92
1
C116
1
C95
1
C60
1
C94
1
C61
2.2uF_6.3v
1 2
C117 100uF_6.3v
0.1uF_10V 2 0.1uF_10V
0.1uF_10V 2 2.2uF_6.3v 2 2.2uF_6.3v 2 2.2uF_6.3v 2 2.2uF_6.3v 2
+V3S
9-,11-,12-,13-,18-,19-,20-,24-,27-,29-,30-,31-,32-,33-,34-,39-,41-,42-,43-,44-,45-,46-,48-,49-,50-,51-,53-,54-,56-,59-
ICH_3S_SMCLK ICH_3S_SMDATA
1 1 R158
13-,27-,3