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24C32
32K 5.0V I2CTM Smart Serial EEPROM
FEATURES
· Voltage operating range: 4.5V to 5.5V - Peak write current 3 mA at 5.5V - Maximum read current 150 µA at 5.5V - Standby current 1 µA typical · Industry standard two-wire bus protocol, I2CTM compatible - Including 100 kHz and 400 kHz modes · Self-timed write cycle (including auto-erase) · Power on/off data protection circuitry · Endurance: - 10,000,000 Erase/Write cycles guaranteed for High Endurance Block - 1,000,000 E/W cycles guaranteed for Standard Endurance Block · 8 byte page, or byte modes available · 1 page x 8 line input cache (64 bytes) for fast write loads · Schmitt trigger, filtered inputs for noise suppression · Output slope control to eliminate ground bounce · 2 ms typical write cycle time, byte or page · Up to 8 chips may be connected to the same bus for up to 256K bits total memory · Electrostatic discharge protection > 4000V · Data retention > 200 years · 8-pin PDIP/SOIC packages · Temperature ranges - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C
PACKAGE TYPES
PDIP A0 A1 A2 VSS 1 2 3 4 24C32 8 7 6 5 VCC NC SCL SDA
SOIC 1 2 3 4
24C32
A0 A1 A2 VSS
8 7 6 5
VCC NC SCL SDA
BLOCK DIAGRAM
A0..A2 HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. This device has been developed for advanced, low power applications such as personal communications or data acquisition. The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K-bit block of ultra-high endurance memory for data that changes frequently. The 24C32 is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to 8 - 24C32 devices on the same bus, for up to 256K bits address space. Advanced CMOS technology makes this device ideal for low-power non-volatile code and data applications. The 24C32 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY
PAGE LATCHES I/O SCL Cache
SDA YDEC
VCC VSS SENSE AMP R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
DS21061F-page 1
This document was created with FrameMaker 4 0 4
24C32
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name A0..A2 VSS SDA SCL VCC NC
PIN FUNCTION TABLE
Function User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock +4.5V to 5.5V Power Supply No Internal Connection
VCC ..................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65°C to +150°C Ambient temp. with power applied ................ -65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD protection on all pins .................................................. 4 kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +4.5V to +5.5V Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Parameter Symbol Min .7 Vcc -- .05 Vcc -- -10 -10 -- -- -- -- Max -- .3 Vcc -- .40 10 10 10 3 150 5 Units V V V V µA µA pF mA µA µA Conditions
A0, A1, A2, SCL and SDA pins: High level input voltage VIH Low level input voltage VIL Hysteresis of Schmitt Trigger inputs VHYS Low level output voltage VOL Input leakage current ILI Output leakage current ILO Pin capacitance CIN, COUT (all inputs/outputs) Operating current ICC WRITE ICC Read Standby current ICCS
Note:
(Note) IOL = 3.0 mA VIN = .1V TO VCC VOUT = .1V to VCC VCC = 5.0V (Note 1) Tamb = 25°C, Fclk = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SCL = SDA = VCC (Note)
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL TSU:STA SDA THD:STA TSU:STO
START
STOP
DS21061F-page 2
© 1996 Microchip Technology Inc.
24C32
TABLE 1-3: AC CHARACTERISTICS
STD. MODE Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Symbol Min FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns FAST MODE Units Remarks
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition
Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance High Endurance Block Rest of Array
TOF TSP TWR -- --
-- -- -- 10M 1M
250 50 5 -- --
20 + 0.1 CB -- -- 10M 1M
250 50 5 -- --
ns ns
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3)
ms/page (Note 4) cycles 25°C, Vcc = 5.0V, Block Mode (Note 5)
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time. 5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW TR
SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT TAA THD:DAT TSU:DAT TSU:STO
TBUF
© 1996 Microchip Technology Inc.
DS21061F-page 3
24C32
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24C32 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C32 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24C32 does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24C32) will leave the data line HIGH to enable the master to generate the STOP condition.
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) SCL
(B)
(D)
(D)
(C)
(A)
SDA
START CONDITION
ADDRESS DATA ALLOWED OR TO CHANGE ACKNOWLEDGE VALID
STOP CONDITION
DS21061F-page 4
© 1996 Microchip Technology Inc.
24C32
3.6 Device Addressing
A control byte is the first byte received following the start condition from the master device. The control byte consists of a four bit control code; for the 24C32 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte (R/W) defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 3-3). Because only A11..A0 are used, the upper four address bits must be zeros. The most significant bit of the most significant byte of the address is transferred first. Following the start condition, the 24C32 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24C32 will select a read or write operation. Operation Read Write Control Code 1010 1010 Device Select Device Address Device Address R/W 1 0
FIGURE 3-2:
START
CONTROL BYTE ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
A 2 A 1 A 0 R/W
ADDRESS BYTE 1
A 11 A 10 A 9 A 8 A 7
ADDRESS BYTE 0
· · · · · · A 0
1
0
1
0
0
0
0
0
SLAVE ADDRESS
DEVICE SELECT BUS
© 1996 Microchip Technology Inc.
DS21061F-page 5
24C32
4.0
4.1
WRITE OPERATION
Split Endurance
4.3
Page Write
The 24C32 is organized as a continuous 32K block of memory. However, the first 4K, starting at address 000, is rated at 10,000,000 E/W cycles guaranteed. The remainder of the array, 28K bits, is rated at 100K E/W cycles guaranteed. This feature is helpful in applications in which some data change frequently, while a majority of the data change infrequently. One example would be a cellular telephone in which last-number redial and microcontroller scratch pad require a highendurance block, while speed dials and lookup tables change infrequently and so require only a standard endurance rating.
4.2
Byte Write
Following the start condition from the master, the control code (four bits), the device select (three bits), and the R/W bit which is a logic low are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24C32. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24C32 the master device will transmit the data word to be written into the addressed memory location. The 24C32 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C32 will not generate acknowledge signals (Figure 4-1).
The write control byte, word address and the first data byte are transmitted to the 24C32 in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to eight pages of eight data bytes each (64 bytes total) which are temporarily stored in the on-chip page cache of the 24C32. They will be written from cache into the EEPROM array after the master has transmitted a stop condition. After the receipt of each word, the six lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remain constant. If the master should transmit more than eight bytes prior to generating the stop condition (writing across a page boundary), the address counter (lower three bits) will roll over and the pointer will be incremented to point to the next line in the cache. This can continue to occur up to eight times or until the cache is full, at which time a stop condition should be generated by the master. If a stop condition is not received, the cache pointer will roll over to the first line (byte 0) of the cache, and any further data received will overwrite previously captured data. The stop condition can be sent at any time during the transfer. As with the byte write operation, once a stop condition is received, an internal write cycle will begin. The 64-byte cache will continue to capture data until a stop condition occurs or the operation is aborted (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
S t o p
S t Bus Activity: a Master r t SDA Line Bus Activity
Control Byte
Word Address (1) 0000 A C K A C K
Word Address (0)
Data
A C K
A C K
FIGURE 4-2:
BUS ACTIVITY MASTER SDA LINE S T A R T
PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 6-3)
CONTROL BYTE WORD ADDRESS (1) WORD ADDRESS (0) S T O P
DATA n
DATA n + 7
0 0 0 0 A C K A C K A C K A C K A C K
BUS ACTIVITY
DS21061F-page 6
© 1996 Microchip Technology Inc.
24C32
5.0 ACKNOWLEDGE POLLING 6.0 READ OPERATION
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.
6.1
Current Address Read
FIGURE 5-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The 24C32 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C32 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C32 discontinues transmission (Figure 6-1).
6.2
Send Stop Condition to Initiate Write Cycle
Random Read
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C32 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C32 will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24C32 to discontinue transmission (Figure 6-2).
FIGURE 6-1:
CURRENT ADDRESS READ
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY A C K N O A C K S T A R T CONTROL BYTE S T O P
DATA n
© 1996 Microchip Technology Inc.
DS21061F-page 7
24C32
6.3 Contiguous Addressing Across Multiple Devices
To provide sequential reads the 24C32 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The address pointer, however, will not roll over from address 07FF to address 0000. It will roll from 07FF to unused memory space.
The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 256K bits by adding up to eight 24C32's on the same bus. In this case, software can use A0 of the control byte as address bit A12, A1 as address bit A13, and A2 as address bit A14.
6.5
Noise Protection
6.4
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the 24C32 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24C32 to transmit the next sequentially addressed 8 bit word. (Figure 6-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a stop condition.
The SCL and SDA inputs have filter circuits which suppress noise spikes to ensure proper device operation even on a noisy bus. All I/O lines incorporate Schmitt triggers for 400 kHz (Fast Mode) compatibility.
FIGURE 6-2:
S T A R T SDA LINE
RANDOM READ
S T A R T
CONTROL BYTE
WORD ADDRESS (1)
WORD ADDRESS (0)
CONTROL BYTE
DATA n
S T O P
0 0 0 0 A C K A C K A C K A C K N O A C K
BUS ACTIVITY:
FIGURE 6-3:
SEQUENTIAL READ
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
CONTROL BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
S T O P
P
A C K A C K A C K A C K N O A C K
DS21061F-page 8
© 1996 Microchip Technology Inc.
24C32
7.0 PAGE CACHE AND ARRAY MAPPING
will'roll over' and be loaded into the first two bytes of page 0 (of the cache). When the stop bit is sent, page 0 of the cache is written to page 3 of the array. The remaining pages in the cache are then loaded sequentially to the array. A write cycle is executed after each page is written. If a partially loaded page in the cache remains when the STOP bit is sent, only the bytes that have been loaded will be written to the array.
The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer. The cache allows the loading of up to 64 bytes of data before the write cycle is actually begun, effectively providing a 64-byte burst write at the maximum bus rate. Whenever a write command is initiated, the cache starts loading and will continue to load until a stop bit is received to start the internal write cycle. The total length of the write cycle will depend on how many pages are loaded into the cache before the stop bit is given. Maximum cycle time for each page is 5 ms. Even if a page is only partially loaded, it will still require the same cycle time as a full page. If more than 64 bytes of data are loaded before the stop bit is given, the address pointer will'wrap around' to the beginning of cache page 0 and existing bytes in the cache will be overwritten. The device will not respond to any commands while the write cycle is in progress.
7.3
Power Management
7.1
Cache Write Starting at a Page Boundary
This design incorporates a power standby mode when the device is not in use and automatically powers off after the normal termination of any operation when a stop bit is received and all internal functions are complete. This includes any error conditions, ie. not receiving an acknowledge or stop condition per the two-wire bus specification. The device also incorporates VDD monitor circuitry to prevent inadvertent writes (data corruption) during low-voltage conditions. The VDD monitor circuitry is powered off when the device is in standby mode in order to further reduce power consumption.
8.0
8.1
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
If a write command begins at a page boundary (address bits A2, A1 and A0 are zero), then all data loaded into the cache will be written to the array in sequential addresses. This includes writing across a 4K block boundary. In the example shown below, (Figure 8-1) a write command is initiated starting at byte 0 of page 3 with a fully loaded cache (64 bytes). The first byte in the cache is written to byte 0 of page 3 (of the array), with the remaining pages in the cache written to sequential pages in the array. A write cycle is executed after each page is written. Since the write begins at page 3 and 8 pages are loaded into the cache, the last 3 pages of the cache are written to the next row in the array.
The A0..A2 inputs are used by the 24C32 for multiple device operation and conform to the two-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-3).
8.2
SDA Serial Address/Data Input/Output
7.2
Cache Write Starting at a Non-Page Boundary
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10K for 100 kHz, 1K for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
When a write command is initiated that does not begin at a page boundary (i.e., address bits A2, A1 and A0 are not all zero), it is important to note how the data is loaded into the cache, and how the data in the cache is written to the array. When a write command begins, the first byte loaded into the cache is always loaded into page 0. The byte within page 0 of the cache where the load begins is determined by the three least significant address bits (A2, A1, A0) that were sent as part of the write command. If the write command does not start at byte 0 of a page and the cache is fully loaded, then the last byte(s) loaded into the cache will roll around to page 0 of the cache and fill the remaining empty bytes. If more than 64 bytes of data are loaded into the cache, data already loaded will be overwritten. In the example shown in Figure 8-2, a write command has been initiated starting at byte 2 of page 3 in the array with a fully loaded cache of 64 bytes. Since the cache started loading at byte 2, the last two bytes loaded into the cache
8.3
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
© 1996 Microchip Technology Inc.
DS21061F-page 9
24C32
FIGURE 8-1: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
1 Write command initiated at byte 0 of page 3 in the array; First data byte is loaded into the cache byte 0. cache page 0 cache byte 0 cache byte 1 · · · cache byte 7 cache page 1 cache page 2 bytes 8-15 bytes 16-23 · · · cache page 7 bytes 56-63
2 64 bytes of data are loaded into cache.
3 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. page 0 page 1 page 2 page 0 page 1 page 2 byte 0 byte 1 · · ·
4 Remaining pages in cache are written to sequential pages in array. byte 7 page 4 page 4 · · · · · · page 7 array row n page 7 array row n + 1
page 3
5 Last page in cache written to page 2 in next row.
FIGURE 8-2:
CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
1 Write command initiated; 64 bytes of data loaded into cache starting at byte 2 of page 0. cache byte 1 cache byte 2 cache byte 7 2 Last 2 bytes loaded 'roll over' to beginning. cache page 7 bytes 56-63
Last 2 bytes loaded into page 0 of cache.
3 cache byte 0
· · ·
cache page 1 cache page 2 bytes 8-15 bytes 16-23
· · ·
4 Write from cache into array initiated by STOP bit. 5 Remaining bytes in cache are Page 0 of cache written to page 3 of array. written sequentially to array. Write cycle is executed after every page is written. page 7 array row n page 7 array row n+1
page 0 page 1 page 2 page 0 page 1 page 2
byte 0
byte 1
byte 2
byte 3 page 3
byte 4
· · ·
byte 7
page 4 page 4
· · · · · ·
6 Last 3 pages in cache written to next row in array.
DS21061F-page 10
© 1996 Microchip Technology Inc.
24C32
24C32 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
24C32
-
/P Package: Temperature Range: Device: P = Plastic DIP (300 mil Body), 8-lead SM = Plastic SOIC (207 mil Body, EIAJ standard) Blank = 0°C to +70°C I = -40°C to +85°C 24C32 24C32T 32K I2C Serial EEPROM (100 kHz/400 kHz) 32K I2C Serial EEPROM (Tape and Reel)
© 1996 Microchip Technology Inc.
DS21061F-page 11
WORLDWIDE SALES & SERVICE
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9/3/96
All rights reserved. © 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
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DS21061F-page 12
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