Text preview for : cop88cl.pdf part of 8-Bit Microcontroller The COP888 family of microcontrollers uses an 8-bit single chip core architecture fabricated with National Semiconduc- tor’s M 2 CMOS™ process technology. The COP888CL is a member of this expandable 8-bit core processor family of microcontrollers.



Back to : cop88cl.pdf | Home

COP888CL 8-Bit Microcontroller

September 2000

COP888CL 8-Bit Microcontroller
General Description
The following part numbers are pin count and temperature variations of the COP888CL: COP688CL, COP684CL, COP884CL, COP988CL, COP984CL. The COP888 family of microcontrollers uses an 8-bit single chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CL is a member of this expandable 8-bit core processor family of microcontrollers. It is a fully static part, fabricated using double-metal silicon gate microCMOS technology. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUS serial I/O, two 16-bit timer/counters supporting three modes (Processor Independent PWM generation, External Event counter, and Input Capture mode capabilities), and two power savings modes (HALT and IDLE), both with a multisourced wakeup/interrupt capability. This multi-sourced interrupt capability may also be used independent of the HALT or IDLE modes. Each I/O pin has software selectable configurations. The device operates over a voltage range of 2.5V to 6V. High throughput is achieved with an efficient, regular instruction set operating at a maximum of 1 µs per instruction rate.

I/O Features
n Memory mapped I/O n Software selectable I/O options ( TRI-STATE Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) n High current outputs n Schmitt trigger inputs on port G n Packages: -- 44 PLCC with 40 I/O pins -- 40 DIP with 36 I/O pins -- 28 DIP with 24 I/O pins -- 28 SO with 24 I/O pins

CPU/Instruction Set Feature
n 1 µs instruction cycle time n Ten multi-source vectored interrupts servicing -- External Interrupt with selectable edge -- Idle Timer T0 -- Timers (Each with 2 interrupts) -- MICROWIRE/PLUS -- Multi-Input Wake Up -- Software Trap -- Default VIS (default interrupt) n Versatile and easy to use instruction set n 8-bit Stack Pointer (SP) -- stack in RAM n Two 8-bit Register Indirect Data Memory Pointers (B, X)

Key Features
n Two 16-bit timers, each with two 16-bit registers supporting: -- Processor Independent PWM mode -- External Event counter mode -- Input Capture mode n 4 kbytes of on-chip ROM n 128 bytes of on-chip RAM

Fully Static CMOS
n Low current drain (typically < 1 µA) n Single supply operation: 2.5V to 6.0V n Temperature ranges: 0°C to +70°C, -40°C to +85°C, -55°C to +125°C

Additional Peripheral Features
n n n n Idle Timer Multi-input Wake Up (MIWU) with optional interrupts (8) WATCHDOG and Clock Monitor logic MICROWIRE/PLUSTM serial I/O

Development Support
n Emulation and OTP devices n Real time emulation and full program debug offered by MetaLink Development System

MICROWIRE/PLUSTM, M2CMOSTM, COPSTM microcontrollers, and MICROWIRETM are trademarks of National Semiconductor Corporation. iceMASTERTM is a trademark of MetaLink Corporation.

© 2001 National Semiconductor Corporation

DS009766

www.national.com

COP888CL

Block Diagram

DS009766-1

FIGURE 1. Block Diagram

www.national.com

2

COP888CL

Connection Diagrams
Plastic Chip Carrier Dual-In-Line Package

DS009766-2

Top View Order Number COP688CL-XXX/V, COP888CL-XXX/V, COP988CL-XXX/V or COP988CLH-XXX/V See NS Plastic Chip Package Number V44A

DS009766-4

Top View Order Number COP688CL-XXX/N, COP888CL-XXX/N, COP988CL-XXX/N or COP988CLH-XXX/N See NS Molded Package Number N40A Dual-In-Line Package

DS009766-5

Top View Order Number COP688CL-XXX/N, COP884CL-XXX/N, COP984CL-XXX/N or COP984CLH-XXX/N See NS Molded Package Number N28B Order Number COP684CL-XXX/WM, COP884CL-XXX/WM, COP984CL-XXX/WM, or COP984CLHXXX/WM See NS Surface Mount Package Number M28B FIGURE 2. Connection Diagrams

3

www.national.com

COP888CL

Connection Diagrams
Port L0 L1 L2 L3 L4 L5 L6 L7 G0 G1 G2 G3 G4 G5 G6 G7 D0 D1 D2 D3 I0 I1 I2 I3 I4 I5 I6 I7 D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7 Unused (Note 1) Unused (Note 1) VCC GND CKI RESET

(Continued)

Pinouts for 28-, 40- and 44-Pin Packages Type I/O I/O I/O I/O I/O I/O I/O I/O I/O WDOUT I/O I/O I/O I/O I I/CKO O O O O I I I I I I I I O O O O I/O I/O I/O I/O I/O I/O I/O I/O 16 15 6 23 5 24 8 33 7 34 8 37 7 38 29 30 31 32 39 40 1 2 9 10 T1B T1A SO SK SI HALT RESTART 19 20 21 22 7 8 25 26 27 28 9 10 11 12 13 14 29 30 31 32 9 10 11 12 13 14 15 16 33 34 35 36 43 44 1 2 21 22 23 24 Alt. Fun MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU INT T2A T2B Alt. Fun 28-Pin 11 12 13 14 15 16 17 18 25 26 27 28 1 2 3 4 40-Pin 17 18 19 20 21 22 23 24 35 36 37 38 3 4 5 6 44-Pin 17 18 19 20 25 26 27 28 39 40 41 42 3 4 5 6

Note 1: On the 40-pin package Pins 15 and 16 must be connected to GND.

www.national.com

4

COP888CL

Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 7V -0.3V to VCC + 0.3V

Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range

100 mA 110 mA -65°C to +140°C

Note 2: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics
COP98XCL: 0°C TA + 70°C unless otherwise specified. Parameter Operating Voltage COP98XCL COP98XCLH Power Supply Ripple (Note 3) Supply Current (Note 4) CKI = 10 MHz CKI = 4 MHz HALT Current (Note 5) IDLE Current CKI = 10 MHz Input Levels RESET Logic High Logic Low CKI (External and Crystal Osc. Modes) Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current per Pin D Outputs (Sink) All others
5

Conditions

Min 2.5 4.0

Typ

Max 4.0 6.0 0.1 VCC 12.5 2.5

Units V V V mA mA µA µA mA

Peak-to-Peak VCC = 6V, tc = 1 µs VCC = 4V, tc = 2.5 µs VCC = 6V, CKI = 0 MHz VCC = 4V, CKI = 0 MHz VCC = 6V, tc = 1 µs

< 0.7 < 0.4

8 5 3.5

0.8 VCC 0.2 VCC 0.7 VCC 0.2 VCC 0.7 VCC 0.2 VCC VCC = 6V VCC = 6V, VIN = 0V -1 -40 +1 -250 0.35 VCC

V V V V V V µA µA V

VCC = 4V, VOH = 3.3V VCC = 2.5V, VOH = 1.8V VCC = 4V, VOL = 1V VCC = 2.5V, VOL = 0.4V VCC = 4V, VOH = 2.7V VCC = 2.5V, VOH = 1.8V VCC = 4V, VOH = 3.3V VCC = 2.5V, VOH = 1.8V VCC = 4V, VOL = 0.4V VCC = 2.5V, VOL = 0.4V VCC = 6.0V

-0.4 -0.2 10 2.0 -10 -2.5 -0.4 -0.2 1.6 0.7 -1 +1 -100 -33

mA mA mA mA µA µA mA mA mA mA µA

15 3

mA mA
www.national.com

COP888CL

DC Electrical Characteristics
Parameter Maximum Input Current without Latchup (Note 6) RAM Retention Voltage, Vr Input Capacitance Load Capacitance on D2
Note 3: Rate of voltage change must be less then 0.5 V/ms.

(Continued)

COP98XCL: 0°C TA + 70°C unless otherwise specified. Conditions TA = 25°C 500 ns Rise and Fall Time (Min) 7 1000 pF pF 2 Min Typ Max Units mA V

± 100

Note 4: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0­G5 configured as outputs and set high. The D port set to zero. The clock monitor is disabled.

AC Electrical Characteristics
0°C TA + 70°C unless otherwise specified. Parameter Instruction Cycle Time (tc) Crystal or Resonator R/C Oscillator Inputs tSETUP tHOLD Output Propagation Delay (Note 7) tPD1, tPD0 SO, SK All Others MICROWIRETM Setup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time Reset Pulse Width 1 1 1 1 1 tc tc tc tc µs 4V VCC 6V 2.5V VCC < 4V 4V VCC 6V 2.5V VCC < 4V 20 56 220 0.7 1.75 1 2.5 µs µs µs µs ns ns ns 4V VCC 6V 2.5V VCC < 4V 4V VCC 6V 2.5V VCC < 4V RL = 2.2k, CL = 100 pF 200 500 60 150 ns ns ns ns 4V VCC 6V 2.5V VCC < 4V 4V VCC 6V 2.5V VCC < 4V 1 2.5 3 7.5 DC DC DC DC µs µs µs µs Conditions Min Typ Max Units

Note 6: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCCwhen biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

www.national.com

6

COP888CL

Absolute Maximum Ratings (Note 8)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 7V -0.3V to VCC + 0.3V

Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range

100 mA 110 mA -65°C to +140°C

Note 8: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics
COP88XCL: -40°C TA +85°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note 9) Supply Current (Note 10) CKI = 10 MHz CKI = 4 MHz HALT Current (Note 11) IDLE Current CKI = 10 MHz Input Levels RESET Logic High Logic Low CKI (External and Crystal Osc. Modes) Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 12) TA = 25°C 15 3 mA mA mA VCC = 4V, VOH = 2.7V VCC = 2.5V, VOH = 1.8V VCC = 4V, VOH = 3.3V VCC = 2.5V, VOH = 1.8V VCC = 4V, VOL = 0.4V VCC = 2.5V, VOL = 0.4V VCC = 6.0V -10 -2.5 -0.4 -0.2 1.6 0.7 -2 +2 -100 -33 µA µA mA mA mA mA µA VCC = 4V, VOH = 3.3V VCC = 2.5V, VOH = 1.8V VCC = 4V, VOL = 1V VCC = 2.5V, VOL = 0.4V -0.4 -0.2 10 2.0 mA mA mA mA VCC = 6V VCC = 6V, VIN = 0V -1 -40 0.7 VCC 0.2 VCC +1 -250 0.35 VCC V V µA µA V 0.7 VCC 0.2 VCC V V 0.8 VCC 0.2 VCC V V VCC = 6V, tc = 1 µs 3.5 mA VCC = 6V, tc = 1 µs VCC = 4V, tc = 2.5 µs VCC = 6V, CKI = 0 MHz 12.5 2.5 mA mA µA Peak-to-Peak Conditions Min 2.5 Typ Max 6 0.1 VCC Units V V

<1

10

± 100

7

www.national.com

COP888CL

DC Electrical Characteristics
Parameter RAM Retention Voltage, Vr Input Capacitance Load Capacitance on D2
Note 9: Rate of voltage change must be less then 0.5 V/ms.

(Continued)

COP88XCL: -40°C TA +85°C unless otherwise specified Conditions 500 ns Rise and Fall Time (Min) 7 1000 pF pF Min 2 Typ Max Units V

Note 10: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 11: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0­G5 configured as outputs and set high. The D port set to zero. The clock monitor is disabled.

AC Electrical Characteristics
-40°C TA +85°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal or Resonator R/C Oscillator Inputs tSETUP tHOLD Output Propagation Delay (Note 13) tPD1, tPD0 SO, SK All Others MICROWIRE Setup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time Reset Pulse Width 1 1 1 1 1 tc tc tc tc µs 4V VCC 6V 2.5V VCC 0.7 1.75 1 2.5 20 56 220 µs µs µs µs ns ns ns 4V VCC 6V 2.5V VCC < 4V 4V VCC 6V 2.5V VCC < 4V RL = 2.2k, CL = 100 pF 200 500 60 150 ns ns ns ns 4V VCC 6V 2.5V VCC < 4V 4V VCC 6V 2.5V VCC < 4V 1 2.5 3 7.5 DC DC DC DC µs µs µs µs Conditions Min Typ Max Units

< 4V

4V VCC 6V 2.5V VCC < 4V

Note 12: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 13: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

www.national.com

8

COP888CL

Electrical Specifications
DC ELECTRICAL SPECIFICATIONS
Note 14: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

COP688CL Absolute Specifications
Supply Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range 100 mA -65°C to +150°C 90 mA 7V -0.3V to VCC + 0.3V

DC Electrical Characteristics
COP68XCL: -55°C TA +125°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note 15) Supply Current (Note 16) CKI = 10 MHz CKI = 4 MHz HALT Current (Note 17) IDLE Current CKI = 10 MHz CKI = 4 MHz Input Levels RESET Logic High Logic Low CKI (External and Crystal Osc. Modes) Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage VCC = 4.5V, VOH = 3.8V VCC = 4.5V, VOH = 3.8V VCC = 4.5V, VOL = 0.4V VCC = 5.5V -9.0 -0.4 1.4 -5.0 +5.0 -140 µA mA mA µA VCC = 4.5V, VOH = 3.8V VCC = 4.5V, VOL = 1.0V -0.4 9 mA mA VCC = 5.5V VCC = 5.5V, VIN = 0V -5 -35 0.7 VCC 0.2 VCC +5 -400 0.35 VCC V V µA µA V 0.7 VCC 0.2 VCC V V 0.8 VCC 0.2 VCC V V VCC = 5.5V, tc = 1 µs VCC = 5.5V, tc = 2.5 µs 3.5 2.5 mA mA VCC = 5.5V, tc = 1 µs VCC = 5.5V, tc = 2.5 µs VCC = 5.5V, CKI = 0 MHz 12.5 5.5 mA mA µA Peak-to-Peak Conditions Min 4.5 Typ Max 5.5 0.1 VCC Units V V

< 10

30

Note 15: Rate of voltage change must be less then 0.5 V/ms. Note 16: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 17: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0­G5 configured as outputs and set high. The D port set to zero. The clock monitor is disabled.

9

www.national.com

COP888CL

DC Electrical Characteristics
-55°C TA +25°C unless otherwise specified Parameter Allowable Sink/Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 21) RAM Retention Voltage, Vr Input Capacitance Load Capacitance on D2
Note 18: Rate of voltage change must be less then 0.5 V/ms. Note 19: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 20: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G ports in the TRI-STATE mode and tied to ground, all outputs low and tied to ground. The Clock Monitor and the comparators are disabled.

Conditions

Min

Typ

Max

Units

12 2.5 150 500 ns Rise and Fall Time (Min) 7 1000 2.0

mA mA mA V pF pF

AC Specifications for COP688CL AC Electrical Characteristics
-55°C TA +125°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal, Resonator, or External Oscillator R/C Oscillator (div-by 10) Inputs tSETUP tHOLD Output Propagation Delay (Note 22) tPD1, tPD0 SO, SK All Others MICROWIRE Setup Time (tUWS) MICROWIRE Hold Time(tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time Reset Pulse Width 1 1 1 1 1 tc tc tc tc µs VCC 4.5V VCC 4.5V 20 56 220 0.7 1 µs µs ns ns ns VCC 4.5V VCC 4.5V RL = 2.2k, CL = 100 pF 200 60 ns ns VCC 4.5V 3 DC µs VCC 4.5V 1 DC µs Conditions Min Typ Max Units

Note 21: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCCwhen biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 22: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

www.national.com

10

COP888CL

AC Electrical Characteristics

(Continued)

DS009766-26

FIGURE 3. MICROWIRE/PLUS Timing

Typical Performance Characteristics
Halt -- IDD

-40°C TA +85°C unless otherwise specified Idle -- IDD(Crystal Clock Option)

DS009766-27

DS009766-28

Dynamic -- IDD vs VCC (Crystal Clock Option)

Port L/C/G Weak Pull-Up Source Current

DS009766-29

DS009766-30

11

www.national.com

COP888CL

Typical Performance Characteristics
Port L/C/G Push-Pull Source Current

-40°C TA +85°C unless otherwise specified (Continued) Port L/C/G Push-Pull Sink Current

DS009766-31

DS009766-32

Port D Source Current

Port D Sink Current

DS009766-33

DS009766-34

Pin Descriptions
VCC and GND are the power supply pins. CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See Reset Description section. The device contains three bidirectional 8-bit I/O ports (C, G and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports G and L), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 4 shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:

CONFIGURATION Register 0 0 1 1

DATA Register 0 1 0 1

Port Set-Up

Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull One Output

DS009766-6

FIGURE 4. I/O Port Configurations

www.national.com

12

COP888CL

Pin Descriptions

(Continued)

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs. Port L supports Multi-Input Wakeup (MIWU) on all eight pins. L4 and L5 are used for the timer input functions T2A and T2B. Port L has the following alternate features: L0 MIWU L1 MIWU L2 MIWU L3 MIWU L4 MIWU or T2A L5 MIWU or T2B L6 MIWU L7 MIWU Port G is an 8-bit port with 5 I/O pins (G0, G2­G5), an input pin (G6), and two dedicated output pins (G1 and G7). Pins G0 and G2­G6 all have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output, while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the single-pin R/C oscillator mask option selected, G7 serves as a general purpose input pin, but is also used to bring the device out of HALT mode with a low to high transition. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 5 I/O bits (G0, G2­G5) can be individually configured under software control. Since G6 is an input only pin and G7 is the dedicated CKO clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeros. Note that the chip will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writing a "1" to bit 6 of the Port G Data Register. Writing a "1" to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used. Config Reg. G7 G6 CLKDLY Alternate SK Data Reg. HALT IDLE

Port C is an 8-bit I/O port. The 40-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation for these unterminated pins will return unpredictable values. Port I is an 8-bit Hi-Z input port. The 40-pin device does not have a full complement of Port I pins. Pins 15 and 16 on this package must be connected to GND. The 28-pin device has four I pins (I0, I1, I4, I5). The user should pay attention when reading port I to the fact that I4 and I5 are in bit positions 4 and 5 rather than 2 and 3. The unavailable pins (I4­I7) are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes into account by either masking or restricting the accesses to bit operations. The unterminated port I pins will draw power only when addressed. Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.8 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to less than 1000 pF.

Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits transfer of data from ROM to RAM. CPU REGISTERS The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tc) cycle time. There are five CPU registers: A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented. X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented. SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset. All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC). PROGRAM MEMORY Program memory consists of 4096 bytes of ROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts vector to program memory location 0FF Hex.

Port G has the following alternate features: G0 INTR (External Interrupt Input) G2 T1B (Timer T1 Capture Input) G3 T1A (Timer T1 I/O) G4 SO (MICROWIRE Serial Data Output) G5 SK (MICROWIRE Serial Clock) G6 SI (MICROWIRE Serial Data Input) Port G has the following dedicated functions: G1 WDOUT WATCHDOG and/or Clock Monitor dedicated output G7 CKO Oscillator dedicated output or general purpose input
13

www.national.com

COP888CL

Functional Description
DATA MEMORY

(Continued)

The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers. The device has 128 bytes of RAM. Sixteen bytes of RAM are mapped as "registers" at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers (other than reserved register 0FF) being available for general usage. The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.

DS009766-7

RC

> 5 x Power Supply Rise Time

FIGURE 5. Recommended Reset Circuit

Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction cycle clock (1/tc).

Figure 6 shows the Crystal and R/C diagrams.
CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.

Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is pulled low. Upon initialization, the data and configuration registers for Ports L, G, and C are cleared, resulting in these Ports being initialized to the TRI-STATE mode. Pin G1 of the G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and/or Clock Monitor error output pin. Port D is initialized high with RESET . The PC, PSW, CNTRL, ICNTRL, and T2CNTRL control registers are cleared. The Multi-Input Wakeup registers WKEN, WKEDG, and WKPND are cleared. The Stack Pointer, SP, is initialized to 06F Hex. The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, and with both the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor detector circuits are inhibited during reset. The WATCHDOG service window bits are initialized to the maximum WATCHDOG service window of 64k tc clock cycles. The Clock Monitor bit is initialized high, and will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will continue until 16­32 tc clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE mode. The external RC network shown in should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes.

Table 1 shows the component values required for various standard crystal values.
R/C OSCILLATOR By selecting CKI as a single pin oscillator input, a single pin R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart pin.

Table 2 shows the variation in the oscillator frequencies as functions of the component (R and C) values.

DS009766-8

DS009766-9

FIGURE 6. Crystal and R/C Oscillator Diagrams

www.national.com

14

COP888CL

Oscillator Circuits
R1 (k) 0 0 0 R2 (M) 1 1 1 C1 (pF) 30 30 200 C2 (pF)

(Continued)

TABLE 2. RC Oscillator Configuration, TA = 25°C R (k) 3.3 5.6 VCC = 5V VCC = 5.0V VCC = 5V 6.8 C (pF) 82 100 100 CKI Freq (MHz) 2.2 to 2.7 1.1 to 1.3 0.9 to 1.1 Instr. Cycle (µs) 3.7 to 4.6 7.4 to 9.0 8.8 to 10.8 VCC = 5V VCC = 5V VCC = 5V Conditions

TABLE 1. Crystal Oscillator Configuration, TA = 25°C CKI Freq (MHz) 10 4 0.455 Conditions

30­36 30­36 100­150

Note 23: 3k R 200k, 50 pF C 200 pF

Control Registers
CNTRL Register (Address X'00EE) The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8) IEDG External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge) MSEL Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively T1C0 Timer T1 Start/Stop control in timer modes 1 and 2 Timer T1 Underflow Interrupt Pending Flag in timer mode 3 T1C1 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C3 Timer T1 mode control bit T1C3 T1C2 T1C1 T1C0 MSEL IEDG Bit 7 SL1 SL0 Bit 0 ICNTRL Register (Address X'00E8) The ICNTRL register contains the following bits: T1ENB Timer T1 Interrupt Enable for T1B Input capture edge T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge µWEN Enable MICROWIRE/PLUS interrupt µWPND MICROWIRE/PLUS interrupt pending T0EN T0PND LPEN Timer T0 Interrupt Enable (Bit 12 toggle) Timer T0 Interrupt pending L Port Interrupt Enable (Multi-Input Wakeup/ Interrupt) Bit 7 could be used as a flag

Unused LPENT0PND T0EN µWPND µWENT1PNDB T1ENB Bit 7 Bit 0

PSW Register (Address X'00EF) The PSW register contains the following select bits: GIE Global interrupt enable (enables interrupts) EXEN Enable external interrupt BUSY MICROWIRE/PLUS busy shifting flag EXPND External interrupt pending T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3) C Carry Flag HC Half Carry Flag HC Bit 7 C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 0

T2CNTRL Register (Address X'00C6) The T2CNTRL register contains the following bits: T2ENB Timer T2 Interrupt Enable for T2B Input capture edge T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge T2ENA Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3) T2C0 Timer T2 Start/Stop control in timer modes 1 and 2 Timer T2 Underflow Interrupt Pending Flag in timer mode 3 Timer T2 mode control bit Timer T2 mode control bit Timer T2 mode control bit

T2C1 T2C2 T2C3

T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB Bit 7 Bit 0

The Half-Carry bit is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and RC (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC, SUBC, RRC and RLC instructions affect the carry and Half Carry flags.

15

www.national.com

COP888CL

Timers
The device contains a very versatile set of timers (T0, T1, T2). All timers and associated autoreload/capture registers power up containing random data.

Figure 7 shows a block diagram for the timers.

DS009766-11

FIGURE 7. Timers TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0, which is a 16-bit timer. The Timer T0 runs continuously at the fixed rate of the instruction cycle clock, tc. The user cannot read or write to the IDLE Timer T0, which is a count down timer. The Timer T0 supports the following functions: Exit out of the Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start up delay out of the HALT mode The IDLE Timer T0 can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the T0PND pending flag, and will occur every 4 ms at the maximum clock frequency (tc = 1 µs). A control flag T0EN allows the interrupt from the thirteenth bit of Timer T0 to be enabled or disabled. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt. TIMER T1 AND TIMER T2 The device has a set of two powerful timer/counter blocks, T1 and T2. The associated features and functioning of a timer block are described by referring to the timer block Tx. Since the two timer blocks, T1 and T2, are identical, all comments are equally applicable to either timer block. Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers, RxA and RxB. Each timer block has two pins associated with it, TxA
www.national.com 16

and TxB. The pin TxA supports I/O required by the timer block, while the pin TxB is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode. The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation. Mode 1. Processor Independent PWM Mode As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The user only has to define the parameters of the PWM signal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely independent of the microcontroller. The user software services the timer block only when the PWM parameters require updating. In this mode the timer Tx counts down at a fixed rate of tc. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB. The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the timer for PWM mode operation.

COP888CL

Timers

(Continued)

Figure 8 shows a block diagram of the timer in PWM mode.

DS009766-13

FIGURE 8. Timer in PWM Mode The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts. Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user must reset these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts. Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output. Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer, Tx, is clocked by the input signal from the TxA pin. The Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer are latched into the TxPNDA pending flag. Setting the TxENA control flag will cause an interrupt when the timer underflows. In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag.

Figure 9 shows a block diagram of the timer in External Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being used as the counter input clock.

DS009766-14

FIGURE 9. Timer in External Event Counter Mode Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, Tx, in the input capture mode.
17

In this mode, the timer Tx is constantly running at the fixed tc rate. The two registers, RxA and RxB, act as capture regis-

www.national.com

COP888CL

Timers

(Continued)

ters. Each register acts in conjunction with a pin. The register RxA acts in conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin. The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently. The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition on the TxA and TxB pins will be respectively latched into the pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin. Similarly, the flag TxENB controls the interrupts from the TxB pin. Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture mode, the user must check both

the TxPNDA and TxC0 pending flags in order to determine whether a TxA input capture or a timer underflow (or both) caused the interrupt.

Figure 10 shows a block diagram of the timer in Input Capture mode.
TIMER CONTROL FLAGS The timers T1 and T2 have indentical control structures. The control bits and their functions are summarized below. TxC0 Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) TxPNDA Timer Interrupt Pending Flag TxPNDB Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag TxENB Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control

DS009766-15

FIGURE 10. Timer in Input Capture Mode

www.national.com

18

COP888CL

Timers
TxC3 0 0 1 1 0

(Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below: TxC2 0 0 0 0 1 TxC1 0 1 1 0 0 Timer Mode MODE 2 (External Event Counter) MODE 2 (External Event Counter) MODE 1 (PWM) TxA Toggle MODE 1 (PWM) No TxA Toggle MODE 3 (Capture) Captures: TxA Pos. Edge TxB Pos. Edge 1 1 0 MODE 3 (Capture) Captures: TxA Pos. Edge TxB Neg. Edge 0 1 1 MODE 3 (Capture) Captures: TxA Neg. Edge TxB Pos. Edge 1 1 1 MODE 3 (Capture) Captures: TxA Neg. Edge TxB Neg. Edge Interrupt A Source Timer Underflow Timer Underflow Autoreload RA Autoreload RA Pos. TxA Edge or Timer Underflow Pos. TxA Edge or Timer Underflow Neg. TxB Edge or Timer Underflow Neg. TxA Edge or Timer Underflow Neg. TxB Edge tc Pos. TxB Edge tc Neg. TxB Edge tc Edge Pos. TxB Edge Autoreload RB Autoreload RB Pos. TxB Edge tc tc Interrupt B Source Pos. TxB TxA Pos. Edge TxA Neg. Edge tc Timer Counts On

Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped. In either mode, all on-board RAM, registers, I/O states, and timers (with the exception of T0) are unaltered. HALT MODE The device is placed in the HALT mode by writing a "1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock, timers, are stopped. The WATCHDOG logic is disabled during the HALT mode. However, the clock monitor circuitry, if enabled, remains active and will cause the WATCHDOG output pin (WDOUT) to go low. If the HALT mode is used and the user does not want to activate the WDOUT pin, the Clock Monitor should be disabled after the device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register). In the HALT mode, the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr (Vr = 2.0V) without altering the state of the machine. The device supports three different ways of exiting the HALT mode. The first method of exiting the HALT mode is with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may be used with an RC clock configuration. The third method of exiting the HALT mode is by pulling the RESET pin low. Since a crystal or ceramic resonator may be selected as the oscillator, the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the tc instruction cycle clock. The tc clock is derived by dividing the oscillator clock down by a factor of 10. The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip. If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be

19

www.national.com

COP888CL

Power Save Modes

(Continued)

introduced or not. The delay is included if CLKDLY is set, and excluded if CLKDLY is reset. The CLKDLY bit is cleared on reset. The device has two mask options associated with the HALT mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT mode. With the HALT mode enable mask option, the device will enter and exit the HALT mode as described above. With the HALT disable mask option, the device cannot be placed in the HALT mode (writing a "1" to the HALT flag will have no effect). The WATCHDOG detector circuit is inhibited during the HALT mode. However, the clock monitor circuit, if enabled, remains active during HALT mode in order to ensure a clock monitor error if the device inadvertently enters the HALT mode as a result of a runaway program or power glitch. IDLE MODE The device is placed in the IDLE mode by writing a "1" to the IDLE flag (G6 data bit). In this mode, all activity, except the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer T0, is stopped. As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wake-up from the L Port. Alternately, the microcontroller resumes normal operation from the IDLE mode when the thirteenth bit (representing 4.096 ms at internal clock frequency of 1 MHz, tc = 1 µs) of the IDLE Timer toggles. This toggle condition of the thirteenth bit of the IDLE Timer T0 is latched into the T0PND pending flag. The user has the option of being interrupted with a transition on the thirteenth bit of the IDLE Timer T0. The interrupt can be enabled or disabled via the T0EN control bit. Setting the T0EN flag enables the interrupt and vice versa. The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the device will first execute the Timer T0 interrupt service routine and then return to the instruction following the "Enter Idle Mode" instruction. Alternatively, the user can enter the IDLE mode with the IDLE Timer T0 interrupt disabled. In this case, the device will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.
Note: It is necessary to program two NOP instructions following both the set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes.

Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate up to 8 edge selectable external interrupts.

Figure 11 shows the Multi-Input Wakeup logic. The Multi-Input Wakeup feature utilizes the L Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the Reg: WKEN. The Reg: WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit enables a Wakeup from the associated L port pin. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). This selection is made via the Reg: WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a pseudo Wakeup condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows: RBIT 5, WKEN SBIT 5, WKEDG RBIT 5, WKPND SBIT 5, WKEN If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited pseudo wakeup conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared. This same procedure should be used following reset, since the L port inputs are left floating as a result of reset. The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wakeup conditions, the device will not enter the HALT mode if any Wakeup bit is both enabled and pending. Consequently, the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode. The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.

www.national.com

20

COP888CL

Multi-Input Wakeup

(Continued)

DS009766-16

FIGURE 11. Multi-Input Wake Up Logic PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions. The GIE (Global Interrupt Enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate. Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation. The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (T0) generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case, upon detecting a valid Wakeup signal, only the oscillator circuitry and the IDLE Timer T0 are enabled. The IDLE Timer is loaded with a value of 256 and is clocked from the tc instruction cycle clock. The tc clock is derived by dividing down the oscillator clock by a factor of 10. A Schmitt trigger following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop.
21

The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip. If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay to be inserted and resetting it will exclude the clock start up delay. The CLKDLY flag is cleared during reset, so the clock start up delay is not present following reset with the RC clock options.

Interrupts
The device supports a vectored interrupt scheme. It supports a total of ten interrupt sources. The following table lists all the possible interrupt sources, their arbitration ranking and the memory locations reserved for the interrupt vector for each source. Two bytes of program memory space are reserved for each interrupt source. All interrupt sources except the software interrupt are maskable. Each of the maskable interrupts have an Enable bit and a Pending bit. A maskable interrupt is active if its associated enable and pending bits are set. If GIE = 1 and an interrupt is active, then the processor will be interrupted as soon as it is ready to start executing an instruction except if the above conditions happen during the Software Trap service routine. This exception is described in the Software Trap sub-section. The interruption process is accomplished with the INTR instruction (opcode 00), which is jammed inside the Instruction Register and replaces the opcode about to be executed. The following steps are performed for every interrupt: 1. The GIE (Global Interrupt Enable) bit is reset. 2. The address of the instruction about to be executed is pushed into the stack. 3. The PC (Program Counter) branches to address 00FF. This procedure takes 7 tc cycles to execute.

www.national.com

COP888CL

Interrupts

(Continued) Arbitration Ranking (1) Highest (2) (3) (4) (5) (6) Source Software Reserved External Timer T0 Timer T1 Timer T1 MICROWIRE/PLUS Reserved Reserved Reserved (7) (8) Timer T2 Timer T2 Reserved Reserved (9) (10) Lowest
y is VIS page, y 0.

Vector Description INTR Instruction for Future Use Pin G0 Edge Underflow T1A/Underflow T1B BUSY Goes Low for Future Use for UART for UART T2A/Underflow T2B for Future Use for Future Use Port L Edge VIS Instr. Execution without Any Interrupts Address Hi-Low Byte 0yFE­0yFF 0yFC­0yFD 0yFA­0yFB 0yF8­0yF9 0yF6­0yF7 0yF4­0yF5 0yF2­0yF3 0yF0­0yF1 0yEE­0yEF 0yEC­0yED 0yEA­0yEB 0yE8­0yE9 0yE6­0yE7 0yE4­0yE5 0yE2­0yE3 0yE0­0yE1

Port L/Wakeup Default

At this time, since GIE = 0, other maskable interrupts are disabled. The user is now free to do whatever context switching is required by saving the context of the machine in the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to branch to the interrupt service routine of the highest priority interrupt enabled and pending at the time of the VIS. Note that this is not necessarily the interrupt that caused the branch to address location 00FF Hex prior to the context switching. Thus, if an interrupt with a higher rank than the one which caused the interruption becomes active before the decision of which interrupt to service is made by the VIS, then the interrupt with the higher rank will override any lower ones and will be acknowledged. The lower priority interrupt(s) are still pending, however, and will cause another interrupt immediately following the completion of the interrupt service routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the end of the interrupt service routine just completed. Inside the interrupt service routine, the associated pending bit has to be cleared by software. The RETI (Return from Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing the processor to be interrupted again if another interrupt is active and pending. The VIS instruction looks at all the active interrupts at the time it is executed and performs an indirect jump to the beginning of the service routine of the one with the highest rank. The addresses of the different interrupt service routines, called vectors, are chosen by the user and stored in ROM in a table starting at 01E0 (assuming that VIS is located between 00FF and 01DF). The vectors are 15-bit wide and therefore occupy 2 ROM locations.
www.national.com 22

VIS and the vector table must be located in the same 256-byte block (0y00 to 0yFF) except if VIS is located at the last address of a block. In this case, the table must be in the next block. The vector table cannot be inserted in the first 256-byte block. The vector of the maskable interrupt with the lowest rank is located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte) and so forth in increasing rank number. The vector of the maskable interrupt with the highest rank is located at 0yFA (Hi-Order byte) and 0yFB (Lo-Order byte). The Software Trap has the highest rank and its vector is located at 0yFE and 0yFF. If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector located at 0yE0­0yE1. WARNING A Default VIS interrupt handle routine must be present. As a minimum, this handler should confirm that the GIE bit is cleared (this indicates that the interrupt sequence has been taken), take care of any required housekeeping, restore context and return. Some sort of Warm Restart procedure should be implemented. These events can occur without any error on the part of the system designer or programmer.
Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits.

Figure 12 shows the Interrupt block diagram.

COP888CL

Interrupts

(Continued)

DS009766-18

FIGURE 12. Interrupt Block Diagram SOFTWARE TRAP The Software Trap (ST) is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from ROM and placed inside the instruction register. This may happen when the PC is pointing beyond the available ROM address space or when the stack is over-popped. When an ST occurs, the user can re-initialize the stack pointer and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization procedures) before restarting. The occurrence of an ST is latched into the ST pending bit. The GIE bit is not affected and the ST pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction. The RPND instruction is used to clear the software interrupt pending bit. This pending bit is also cleared on reset. The ST has the highest rank among all interrupts. Nothing (except another ST) can interrupt an ST being serviced. The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window. Table 4 shows the four possible combinations of lower and upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software. Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit. TABLE 3. WATCHDOG Service Register (WDSVR) Window Select X 7 X 6 0 5 1 4 1 3 0 2 0 1 Key Data Clock Monitor Y 0

TABLE 4. WATCHDOG Service Window Select WDSVR Bit 7 0 0 1 1 WDSVR Bit 6 0 1 0 1 Service Window (Lower-Upper Limits) 2k-8k tc Cycles 2k-16k tc Cycles 2k-32k tc Cycles 2k-64k tc Cycles

WATCHDOG
The device contains a WATCHDOG and clock monitor. The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or "runaway" programs. The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin. The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window. Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 3 shows the WDSVR register.

Clock Monitor
The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock (1/tc) is greater or equal to 10 kHz. This equates to a clock input rate on CKI of greater or equal to 100 kHz.

WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the WATCHDOG armed, the WATCHDOG Window Select bits (bits 6, 7 of the WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
23 www.national.com

COP888CL

WATCHDOG Operation

(Continued)

WDSVR Register) enabled. Thus, a Clock Monitor error will occur after coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value, including the case where the oscillator fails to start. The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR Register) must match to be a valid write. This write to the WDSVR register involves two irrevocable choices: (i) the selection of the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor. Hence, the first write to WDSVR Register involves selecting or deselecting the Clock Monitor, select the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service window value and the key data (bits 7 through 1) in the WDSVR Register. Table 5 shows the sequence of events that can occur. The user must service the WATCHDOG at least once before the upper limit of the serivce window expires. The WATCHDOG may not be serviced more than once in every lower

limit of the service window. The user may service the WATCHDOG as many times as wished in the time period between the lower and upper limits of the service window. The first write to the WDSVR Register is also counted as a WATCHDOG service. The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G. WDOUT is active low. The WDOUT pin is in the high impedance state in the inactive state. Upon triggering the WATCHDOG, the logic will pull the WDOUT (G1) pin low for an additional 16 tc­32 tc cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold. After this delay, the device will stop forcing the WDOUT output low. The WATCHDOG service window will restart when the WDOUT pin goes high It is recommended that the user tie the WDOUT pin back to VCC through a resistor in order to pull WDOUT high. A WATCHDOG service while the WDOUT signal is active will be ignored. The state of the WDOUT pin is not guaranteed on reset, but if it powers up low then the WATCHDOG will time out and WDOUT will enter high impedance state.

TABLE 5. WATCHDOG Service Actions Key Data Match Don't Care Mismatch Don't Care Window Data Match Mismatch Don't Care Don't Care Clock Monitor Match Don't Care Don't Care Mismatch Valid Service: Restart Service Window Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Action

TABLE 6. MICROWIRE/PLUS Master Mode Clock Select SL1 0 0 1 SL0 0 1 x SK 2 x tc 4 x tc 8 x tc

Where tc is the instruction cycle clock

The Clock Monitor forces the G1 pin low upon detecting a clock frequency error. The Clock Monitor error will continue until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc­32 tc clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the minimum specified frequency. The specification for the Clock Monitor is as follows: 1/tc > 10 kHz -- No clock rejection. 1/tc < 10 Hz -- Guaranteed clock rejection. WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and Clock Monitor should be noted:

·

The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error. Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors. The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0's. The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes. The Clock Monitor detector circuit is active during both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a Clock Monitor error (provided that the Clock Monitor enable option has been selected by the program). With the single-pin R/C oscillator mask option selected and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left off before entering the HALT mode.

·

·

· ·

· ·

Both WATCHDOG and Clock Monitor detector circuits are inhibited during reset. Following reset, the WATCHDOG and Clock Monitor are both enabled, with the WATCHDOG having the maximum service window selected. The WATCHDOG service window and Clock Monitor enable/disable option can only be changed once, during the initial WATCHDOG service following reset.
24

·

·

www.national.com

COP888CL

WATCHDOG Operation
·

(Continued)

With the crystal oscillator mask option selected, or with the single-pin R/C oscillator mask option selected and the CLKDLY bit set, the WATCHDOG service window will be set to its selected value from WDSVR following HALT. Conse