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SERVICE MANUAL
8M29B CHASSIS
Design and specifications are subject to change without prior notice.
(Only Referrence)
Description:
SERVICE MANUAL 8M29B
MODEL. Brand Name: SKYWORTH
JOB NO.
Engineering Dept:
Artwork By: Date: 2011-5-23
SIZE:A5 Checked By:
Approved By:
Date:
Date:
Content-------------------------------------------------------------------------------2
Technical Specification-----------------------------------------------------------3-14
8M29 Block Diagram -------------------------------------------------------------15
List of key parts---------------------------------------------------------------------16
IC BLOCK Diagram----------------------------------------------------------------17-31
MAIN PCB-TOP--------------------------------------------------------------------32
MAIN PCB-BOT--------------------------------------------------------------------33
Circuit Diagrams--------------------------------------------------------------------34-42
-2-
LCD 8M29B chassis.
-3-
4.
105 For 32LED
140 For 42LED
Base on different order
5.
93 95 97
93 95 97
400 FOR 32LED
450 FOR 42LED
-4-
For 42LED
For 42LED
9800 12500 12500(266, 276)
9800(280, 290)
6500(313, 329)
-5-
40
40
3
2
1
4.2
50
0.5
80 12000
40
-6-
1080
1920
40 uv
NO
YES
8
6
46 uv
46
NO
Standard
Standard
20
English
Middle
-7-
-8-
DTV-PRODUCTOINS SPECIFICATION
Model # 32" 46"
Country( West Eu./East Eu./Russia/AP/US/S.A./Japan/
Brazil & Argentina
...)
Brand Skyworth/ODM
Category (Monitor/TV/Combo/Portable TV...) TV
Panel technology (LCD / PDP) LCD/LED
Market Position (High/Mid/Access,,,) Class
Cabinet Design (Example: 01,23 series ) K06/E60
Product Nb -
Chassis solution MSD309
Chassis name 8M29B
Chassis PCB Standard Skyworth RGB New Standard
Predecessor (replace) -
MP date requested (ETD) 2011.1
MP date confirmed by supplier (ETD/ETA) -
Status( Pre./Finish ) -
Regional requirement
Homologation (Gostandard/CE/MPTT/CB/...) CB
RoHS Yes
Power supply(100-240V AC +/-10%/...) 100-240V AC (-20%,+10%)
Power consumption working / Annual -
Power consumption standby <1W
Power plug(VDE/UL/BS/...) UCIEE/2pins
Picture display
Screen size : diagonale (inch) 32",42", 46"
Aspect ratio (16/9 // 4/3 // 15/9) 16:9
1st panel supplier : panel suppliers LG
1st panel supplier : panel reference
Panel Display Type(MVA/PVA/IPS/...) TFT LCD
1st panel supplier : resolution 32:1366x768 42/46:1920x1080
Dynamic contrast ratio >10000 1
Video signal process
Comb Filter (2D/3D) 3D
Noise Reduction (adaptative/3D/...) 3D
Picture improvement ( LTI/CTI,BLE,WLE,...) LTI/CTI
Color process (Gama correction/Skin correction /... ) Follow main IC
-9-
Colour preset (Cool/Normal/Warm/Personal) Medium, Cool, Warm and Personal in PC mode
Picture control ( Bright/Con./Sharpness/Color/Tint/...) Yes
Picture presets : Standard / Bright / Soft / User Standard / Mild / Film / Dynamic / Personal
Picture freeze Yes
Multi picture : PIP ( AV )/POP AV No
Dynamic Backlight Control No
LED Backlight Yes
Deinterlacer (No/linerar/motion adaptive/motion
3D motion adaptive
compensative)
Film mode / reverse 3:2/2:2 pull down Yes / Yes
Full HD support ( 1080P ) Yes
Single scan / Dual scan ( 120HZ ) 32:Single scan,42/46:Dual scan(only for LED)
Zoom type : 4/3 format Yes
Zoom type : 14/9 Zoom Yes
Zoom type : 16/9 Zoom 16/9 ZOOM 1
Zoom type : 16/9 Zoom up/down 16/9 ZOOM 2
Zoom type : Cinerama Yes
Zoom type : 16/9 Format Yes
Zoom type : Auto ( by SCART Pin8 and WSS ) Yes
Picture Auto adjustment (PC mode) Yes
3D Panel Type(PR / SG)
3D Mode
3D To 2D (Y/N)
2D To 3D (Y/N)
Left / Right Swap (For PR Panel)
Sound
Sound type ( Mono/AV stereo/Stereo ) stereo
Music Power (Watt)/RMS Power (Watt) 2 x 8W
Tone control ( Bass&Treble / Graphic Equalizer ) Bass&Treble
Special sound effect ( AVL / WIDE / Pseudo /... ) AVL
Suround system ( Dolby / VD / SRS / BBE / ... ) Built-in Surround
Sound control ( Volume , Balance , Mute ) Volume, Balance, Mute
Sound presets (User/Speech/News/Standard) Standard / Music / Movie / Sport / Personal
Headphone volume control ( Separated / linked ) Yes(Linked)
Sound quality ( High / Mid / Low ) Mid
Reception and Decoding capability
RF range ATV 54MHz 864MHz
RF range DTV VHF 177-213 MHZ, UHF 473-803 MHZ
Color System (PAL/SECAM/NTSC/PAL M,N ) PAL M,PAL N,NTSC M
Audio Standard ( B/G/H/D/K/K'/I/L/L' ) M,N
Stereo audio system ( Nicam,MTS,A2,....) BTSC,SAP
Video standard NTSC 3.58 / 4.43 (AV)/PAL 60 NTSC 3.58/4.43 , PAL
-10-
DTV SD support (DVB-T/S/C , ATSC , QAM , ... ) ISDB-T
DTV HD Support MPEG2,MPEG4,H.264
MHEG5 No
HD capability with YPbPr Yes (720p; 1080i; 1080p@24/50/60Hz; 480i/p; 576i/p)
PC capability (up to maximum format) Up to 1280X1024 60Hz
HDMI capability AV/PC Format) Up to 1080P 24/50/60HZ
Compatible video format if DVD/USB:
JPEG/MPEG2/MPEG4/H.264/DivX (depending on license)
DviX/VCD/SVCD/JPEG/AVI/MPEG2/WMV- HD/SD
Compatible audio format if DVD/USB:
MP3/WMA(depending on license)
MP3/WMA/AAC/MPEG1/...
Playable Discs (CD/CD-R(RW)/CD-ROM/DVD+R/+RW/-
No
R/-RW)
Card reader format compatibility No
Macrovision Yes
PVR Yes FOR USB
Network No
User convenience
OSD Language* English/Spanish/Portuguese/French
OSD Positioning No
OSD Transparency Adjust No
OSD Timeout Adjust No
Customer Brand name(LOGO) Yes
IB languages English
ATV Program Numbers (example: 99+3AV input ) 99+7AV
DTV Program Numbers 600
Program edit ( naming , sorting , skip , swap .... ) Naming / Skip / Swap
Auto Naming/Auto Sorting No
TV Guide(DTV EPG) EPG(next Seven-day)
Favorite program Yes
Number of buttons on cabinet (Power; Vol+/-; Pr+/-,
Vol+/-; Pr+/-, Menu ,Source,Power(optional)
Menu )
Main switch button (yes/No) Yes
CCD Closed Caption)/V-CHIP Yes/No
Text Standard: (Top, FLOF,,,) No
Teletext Level: 2.5 / 1.5 -
Pages for teletext -
Teletext character sets **** -
DVB-T teletext -
Real clock From DTV
Sleep timer 10-240 Min.
Timer Turn On / Off, Program Switch
Parent Control -Source and Channel lock (Input code for
Yes
certain channel)
Parent Control - Child lock (set the lock of the keyboard,
No
only the RCU can control the TV)
-11-
Parent Control - Kid pass (preset the ontime, channel for
No
each day of the week)
Parent Control - Channel lock (For digital transmission
Yes
and DVD program, to filter some programms)
Calendar / Games No
No program auto switch off 15 mins.
Hotel mode (Y/N) T.B.D
DVD player (No/slot/tray) No
Tuner FM (yes/No) No
software download(RS232/CI/USB/OAD) USB
Factory reset Yes in factory menu,reset the setting to shipment state )
Screen saver Yes
Blue Back No
LED indicator(Power on/Standby) Blue / Red
Connectors -Rear
RF Input (Antenna): Air/ Cable/ 2in1 Air+Cable
Scart : CVBS in&out / RGB / S-VIDEO No
CINCH video in / out AV1 No
CINCH audio in / out (No volumpe control on Audio
No
out/can be jack 3,5mm)
S-video in No
Component Video Input (YCrCb/YPrPb) No
Component Audio Input (YCrCb/YPrPb) No
VGA in / Audio L/R in / Jack audio in 3.5mm VGA + dia. 3.5mm for audio in
HDMI 2
DVI No
Audio input for DVI No
CINCH subwoofer out / Coaxial out (S/PDIF) No
Headphone output connector (mm) No
RS232 ( Y/N , VGA or DB9 port ...) No
Card Readers No
1 (Software update, JPEG, MP3, WMA, RMVB, DivX) Multimedia
USB slot (No/1.1/2)
depends on license
DVB-CI (common interface) No
External power converter input No
Connectors -Side
HDMI 1
AV-IN 1
AV-OUT No
-12-
Component Video Input (YCrCb/YPrPb) 1
Component Audio Input (YCrCb/YPrPb) 1 with cable adapter
Headphone output connector (dia.mm) 1 3.5mm)
CINCH subwoofer out / Coaxial out (S/PDIF) S/PDIF out ( optical
1 (Software update, JPEG, MP3, WMA, RMVB, DivX) Multimedia
USB slot (No/1.1/2)
depends on license
DVB-CI (common interface) No
DLNA No
UI/RC
UI design (font/pixel, 2D/3D graphic engine..) SOD Standard
RC Model YK76B3 ( Toshiba )
RC system RGB Standard
RC # of keys
Accessories included
Carton (English/French/Spanish) English
IB English
Circuit diagram No
Batteries Yes
Product registration Card Yes English)
AC Cable Length 1.8m
Audio Cord (Jack 3.5mm) Yes(For component audio in)
VGA Cord No
Wallmount frame Optional
Antenna Cable No
6 in 1( YPbPr & CVBS) cable adapter No
3D Glasses No
General Data
Size (W x H x D, with stand) in mm -
Size (W x H x D, without stand) in mm -
Package Size (W x H x D, without stand) in mm -
Net Weight in kg -
Gross Weight in Kg -
Design / Mechanical
Wallmount VESA compatible (standard reference) Yes
Adaptor for VESA wallmount compatibility (accessory
Yes
ref)
Desktop Stand (included/optionnal + ref/No) included
Panel Tilt (Fowards/Backwards/Rotation) No
Swivel function desktop stand (yes/No) + motorized? No
Docking station (yes/No) No
Floor Stand (included/optionnal + ref/No) No
Glass shield (yes/No) No
Finish on Front -
Finish on side -
Finish on back -
-13-
Finish on stand -
number of colors on carton box 2
Brand logo Customer Inlet
Other logo No
External AC/DC Power with DC power cord (yes/No) No
Handle (yes/No) No
Detachable speaker (yes/No) No
Rating Label langages English
-14-
SYSTEM
POWER SUPPLY
Uplayer1 KEY PAD, IR Receiver ,Ambient Sensor
Optional
PIXELWORKS 3D Processor FLASH
Motion Engine
PA131DG
HDMI1
DDRII
DVB-T&ATV MSD309PX-LF-SB
Demo d
PR DVB-T & IF Demo. Build in
MPEG1/2/4 /H.264 Decoder
PB JPEG MP3 Decoder R/L TPA3121
3D Comb filter Video Decoder
10W + 10W
Y
R
L DTV Toshiba TC90517
ATV
ISDB-T Demod
Video SAW P/S
IF (ATV) IF+/-
Rear Terminals
PC PC Audio S/PDIF
Uplayer2 HDMI2 HDMI3
Tuner
Side Terminals -15-
List of key parts
No. Name Position Type P/N
1 IR U29 HS0038B4 5300-140038-0010
Bass SL-R3018H-3E 5600-106154-0060
2 Speaker
Treble YDG3040-2 5600-708254-00
Y2 49U3H 4900-125453-R000
3 Crystal
Y1 HC-49U/S 4900-124053-R000
4 Tuner U10 VA1P1BF8405 5202-45733D-7H10
5 Saw U30 F4401 4900-744015-0X00
U3 MP1482DS 476A-M14820-0080
U5 MP1482DS 476A-M14820-0080
MP1482DS 476A-M14820-0080
MP1482DS 476A-M14820-0080
U9 W9751G6JB-25 4737-W97511-0840
U15 W9751G6JB-25 4737-W97511-0840
6
IC U24 EN25F32-100HIP 471R-N25321-0080
U55 TC90517FG 4701-T90510-0640
U37 AS1117L-3.3 47B6-A11170-03
U38 AS1117L-3.3 47B6-A11170-03
N1 AS1117L-3.3 47B6-A11170-03
N2 AS1117L-1.2 47B6-A11175-0300
U54 TPA3121D2PWPR 4722-T31210-0240
U2 MSD309PX-LF-Z1-SB 475C-M30900-5230
-16-
IC Block Diagram
Pin Configurations---AS1117L-3.3
L Package U Package
(SOT-223) (SOT-89)
3 INPUT INPUT
3
V OUT
2 OUTPUT V OUT
2 OUTPUT
1 ADJ/GND 1 ADJ/GND
T Package R Package
(TO-220) (TO-252)
3 INPUT
3 INPUT 2 OUTPUT
V OUT
V OUT 2 OUTPUT
1 ADJ/GND 1 ADJ/GND
S Package
(TO-263)
3 INPUT
V OUT 2 OUTPUT
1 ADJ/GND
-17-
IC Block Diagram
Pin Configurations---AS1117L-ADJ
L Package
(SOT-223)
3 INPUT
V OUT
2 OUTPUT
1 ADJ/GND
PIN ASSIGNMENT
The package of AX3113 is SOP-8L; the pin assignment is given by:
Name Description
FB Feedback pin
( Top View ) Power-off pin
H normal operation(Step-down)
FB 1 8 Vss EN
L Step-down operation stopped
EN 2 7 Vss (All circuits deactivated)
AX3113
Ocset 3 6 SW Add an external resistor to set max
OCSET
Vcc 4 5 SW switch output current.
VCC IC power supply pin
SOP8L
Switch pin. Connect external
SW
inductor & diode here.
VSS GND pin
-18-
IC Block Diagram
LM4558
MP1482DS
TOP VIEW
BS 1 8 SS
IN 2 7 EN
SW 3 6 COMP
GND 4 5 FB
-19-
IC Block Diagram
MST6M20S-LF
-20-
IC Block Diagram
.
W25X40BVSNIG
PWP (TSSOP) PACKAGE
(TOP VIEW)
PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR
PIN CONFIGURATION PAD CONFIGURATION
SOIC 150-MIL / 208-MIL WSON 6X5-MM
PIN CONFIGURATION
PDIP 300-MIL
-21-
IC Block Diagram
EN25F32
Figure.1 CONNECTION DIAGRAMS
8 - LEAD SOP / DIP 8 - CONTACT VDFN
16 - LEAD SOP
-22-
IC Block Diagram
EN25F32
Figure 2. BLOCK DIAGRAM
-23-
IC Block Diagram
EN25F32
SIGNAL DESCRIPTION
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially
written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle
is in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, CS#
must transition from high to low before a new instruction will be accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don't care). The hold function can be useful when multiple devices are sharing the same SPI
signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register's Block Protect (BP0, BP1and BP2) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol Pin Name
CLK Serial Clock Input
DI Serial Data Input
DO Serial Data Output
CS# Chip Enable
WP# Write Protect
HOLD# Hold Input
Vcc Supply Voltage (2.7-3.6V)
Vss Ground
-24-
IC Block Diagram
CONFIDENTIAL TC90517FG Toshiba products specification [Tentative]
2. Configuration
All functions required for ISDB-T demodulation and error correction are built into the TC90517.
The input signals to be supported are a low IF (intermediate frequency) signal and direct IF signal.
Baseband IQ signals can also be input.
The output signal is an MPEG-2 transport stream (TS) in serial format. Note that a TS in parallel format
can be output by setting registers.
IF input ADC Quadrature Interpolation ISIC (unguarded Frequency Pilot Adaptive
detection Filter phase interpolation
or IQ input AGC
preecho/postecho
suppression)
FFT CPE extraction
ADC AFC correction filter
AGC control output Tuner Synchroni FFT window CVI CSI Equalization
SW AGC Control (CW interference (reliability
zation control detection)
control detection)
External AGC input
AGC distortion signal
2 2
Tuner I C IC Layer TMCC
2
Host I C control isolation demodulation
Frequency Demapping Viterbi Energy RS Error Synchroni-
Modulation division
Crystal Clock PLL CSI
Byte deinterleaving
despreading decoding detection zation flag
Bit deinterleaving
(reference clock) deinterleaving processing decoding
TS multiplex
Demapping Energy
Time CSI despreading Output
Memory processing control TS output
deinterleaving
Demapping Energy
CSI despreading
processing
Fig. 2.1 TC90517FG Block Diagram
-25-
IC Block Diagram
CONFIDENTIAL TC90517FG Toshiba products specification [Tentative]
3. Pin Assignment (Top view)
-26-
IC Block Diagram
4. Pin Functions
This specification indicates pins and their signals in upper case letters and registers and their signals in lower case
letters.
(Note4) (Note5,7) (Note 3)
Pin Pin name Function Remarks(Note 2 and 6)
I/O PU/PD
1 TSMD0 I - Shut down 0: Normal operation 1: Shut down
2 XSEL1 I - Crystal frequency division ratio 1 Set according to crystal frequency.
3 XSEL0 I - Crystal frequency division ratio 0 Set according to crystal frequency.
4 VSS - - Digital GND Connects to DGND.
5 SLADRS1 I/O - Slave address 1 Set according to slave address.
6 SLADRS0 I/O - Slave address 0 Set according to slave address.
7 AGCI I - External AGC input Connects to DGND when not used.
8 S_INFO I - Pin for pre-shipment test Connects to DGND.
9 AGCCNTI I/O PD IF_AGC control output Connects to tuner IF_AGC control input pin.
Connects to tuner RF_AGC control input pin.
10 AGCCNTR I/O PD RF_AGC control output
Open, fixed to L when not used.
11 CKI I - Pin for pre-shipment test Connects to DGND.
Connects to tuner I2C clock pin.
12 TNSCL I/O OD I2C clock output
(Pull-up performed outside IC.)
13 VDDS - - I/O power supply Connects to digital +3.3 V typ.
Connects to tuner I2C data pin.
14 TNSDA I/O OD I2C data I/O
(Pull-up performed outside IC.)
15 VSS - - Digital GND Connects to DGND.
16 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
17 PLLVSS - - Clock PLL GND Connects to AGND.
Connects to crystal.
18 XO O - Crystal output ixosl="1" and open when an external reference clock
is input.
Connects to crystal.
19 XI I - Crystal or reference clock input amplitude (p-p) is 0.5 V to PLLVDD when an
The
external reference clock is input.
20 PLLVDD - - Clock PLL power supply Connects to analog +2.5 V typ.
21 FIL O - PLL filter output Connects to AGND via 1500 pF.
22 AD_AVDD - - ADC analog power supply Connects to analog +2.5 V typ.
23 AD_AVSS - - ADC analog GND Connects to AGND.
24 AD_VREFP - - ADC reference voltage output +1.75 V typ. Connects to AGND via PC.
25 AD_VREFN - - ADC reference voltage output +0.75 V typ. Connects to AGND via PC.
26 AD_VREF - - ADC reference voltage output +1.25 V typ. Connects to AGND via PC.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to AGND via PC.
Q signal (differential negative side)
27 ADQ_AIN I - Single-ended IQ: Connects to AGND via PC.
input
Differential IQ: Connects to tuner Q (-) output after
the DC component was cut.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to AGND via PC.
Q signal (differential positive side) Single-ended IQ: Connects to tuner Q output after
28 ADQ_AIP I -
input the DC component was cut.
Differential IQ: Connects to tuner Q (+) output after
the DC component was cut.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to tuner IF (-) output after
IF signal (differential negative side)
the DC component was cut.
29 ADI_AIN I - input or I signal (differential
Single-ended IQ: Connects to AGND via PC.
negative side) input
Differential IQ: Connects to tuner I (-) output after the
DC component was cut.
Single-ended IF: Connects to tuner IF output after
the DC component was cut.
IF signal (differential positive side) Differential IF: Connects to tuner IF (+) output after
30 ADI_AIP I - input or I signal (differential the DC component was cut.
positive side) input Single-ended IQ: Connects to tuner I output after the
DC component was cut.
Differential IQ: Connects to tuner I (+) output after the
-27-
IC Block Diagram
CONFIDENTIAL TC90517FG Toshiba products specification [Tentative]
DC component was cut.
31 AD_DVSS - - ADC digital GND Connects to DGND.
32 AD_ DVDD - - ADC digital power supply Connects to digital +2.5 V typ.
33 VSS - - Digital GND Connects to DGND.
34 DR1VDD - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
35 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
36 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
37 VSS - - Digital GND Connects to DGND.
38 STSFLG1 O PD Status flag 1 output Open, fixed to L when not used.
39 DTCLK I PD Pin for pre-shipment test Open or connects to DGND.
40 DTMB I PU Pin for pre-shipment test Open or connects to digital +3.3 V typ.
41 TSMD1 I - Pin for pre-shipment test Connects to DGND.
42 SYRSTN I/O OD System reset input Inputat specified timing at power ON.
43 DR2VDD - - Digital +2.5 V power supply Connects to digital +2.5 V typ.
44 VSS - - Digital GND Connects to DGND.
Connects to I2C clock bus.
45 SCL I/O OD I2C clock input for host CPU
(Pull-up performed outside IC.)
Connects to I2C data bus.
46 SDA I/O OD I2C data I/O for host CPU
(Pull-up performed outside IC.)
47 VSS - - Digital GND Connects to DGND.
48 DR1VDD - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
49 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
50 VSS - - Digital GND Connects to DGND.
51 STSFLG0 I/O PD Status flag 0 output Open, fixed to L when not used.
Synchronization completion Open, fixed to L when not used.
52 SLOCK O
(sequence 8 or higher) flag
53 RERR O - RS decoding error flag output Open, fixed to L when not used.
54 RLOCK O - RS decoding error free flag output Open, fixed to L when not used.
55 RSEORF O - TS error flag output Open, fixed to L when not used.
56 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
57 VSS - - Digital GND Connects to DGND.
58 PBVAL O - TS valid flag output Open, fixed to L when not used.
59 SBYTE O - TS synchronization byte flag output Open, fixed to L when not used.
60 SRDT O - Serial TS data output -
61 SRCK O - TS serial clock output -
62 VSS - - Digital GND Connects to DGND.
63 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
64 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
Note 2 AGND is the abbreviation for analog GND, and DGND is the abbreviation for digital GND.
Note 3 The test dedicated pin is used for the pre-shipment test only. Make sure that processing is performed as
indicated in the "Remarks" column. Any other method will lead to malfunction or failure.
Note 4 I/O indicates the type of the cell used. It may be different from the pin function because a test is conducted
concurrently.
Note 5 PU indicates an I/O with a pull-up resistor (50 k typ.) and PD indicates an I/O with a pull-down resistor (50
k typ.). Pulling down the PU pin or pulling up the PD pin outside the IC sometimes changes the electric
potential to the midpoint, resulting in instability. Caution is required.
Note 6 The unused output pins must be open and fixed to L by setting the output enable control register of each pin
for noise reduction or to the output OFF state.
set
Note 7 OD indicates an open drain I/O. To use the pin for output, pull up the resistance outside the IC.
* The following pins are added with the upgrade from TC90507 to TC90517 (except the changes of power
supply and GND pins):
Pin
Pin Name Description
Number
21 FIL Added to the PLL loop filter.
27 ADQ_AIN Added for IQ input (differential).
28 ADQ_AIP Added for IQ input.
7 AGCI Added to passthrough the AGC control signal of other ICs.
52 SLOCK Changed from conventional FLOCK.
-28-
IC Block Diagram
PRELIMINARY W9751G6JB
4. B A L L C O N FIG U R A TIO N
1 2 3 4 5 6 7 8 9
VD D NC VSS A VSSQ U D Q S VD D Q
D Q 14 V S S Q UDM B U D Q S VSSQ D Q 15
VD D Q DQ9 VD D Q C VD D Q DQ8 VD D Q
D Q 12 V S S Q D Q 11 D D Q 10 V S S Q D Q 13
VD D NC VSS E V S S Q LD Q S V D D Q
DQ6 VSSQ LD M F LD Q S V S S Q DQ7
VD D Q DQ1 VD D Q G VD D Q DQ0 VD D Q
DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5
VD D L VR EF VSS J VSSDL C LK VD D
C KE W E K RAS C LK ODT
NC BA0 BA1 L CAS CS
A 10/ P
A A1 M A2 A0 VD D
VSS A3 A5 N A6 A4
A7 A9 P A 11 A8 VSS
VD D A 12 NC R NC NC
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IC Block Diagram
PRELIMINARY W9751G6JB
5. BALL DESCRIPTION
BALL NUMBER SYMBOL FUNCTION DESCRIPTION
Provide the row address for active commands, and the column
M8,M3,M7,N2,N8,N3 address and Auto-precharge bit for Read/Write commands to select
,N7,P2,P8,P3,M2,P7 A0-A12 Address one location out of the memory array in the respective bank.
,R2 Row address: A0-A12.
Column address: A0-A9. (A10 is used for Auto-precharge)
BA0-BA1 define to which bank an ACTIVE, READ, WRITE or
L2,L3 BA0-BA1 Bank Select
PRECHARGE command is being applied.
G8,G2,H7,H3,H1,H9 Data Input
,F1,F9,C8,C2,D7,D3, DQ0-DQ15 Bi-directional data bus.
D1,D9,B1,B9 / Output
On Die Termination ODT (registered HIGH) enables termination resistance internal to the
K9 ODT
Control DDR2 SDRAM.
Data Strobe for Lower Byte: Output with read data, input with write
LDQS, data for source synchronous operation. Edge-aligned with read data,
F7,E8 LOW Data Strobe center-aligned with write data. LDQS corresponds to the data on
LDQS DQ0-DQ7. LDQS is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
Data Strobe for Upper Byte: Output with read data, input with write
UDQS, data for source synchronous operation. Edge-aligned with read data,
B7,A8 UP Data Strobe center-aligned with write data. UDQS corresponds to the data on
DQ8-DQ15. is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
All commands are masked when is registered
L8 Chip Select HIGH. provides for external bank selection on systems with
multiple ranks. is considered part of the command code.
RAS , CAS RAS , CAS and (along with ) define the command being
K7,L7,K3 Command Inputs
entered.
DM is an input mask signal for write data. Input data is masked when
UDM DM is sampled high coincident with that input data during a Write
Input Data Mask
B3,F3 LDM access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
CLK and CLK are differential clock inputs. All address and control
CLK, Differential Clock input signals are sampled on the crossing of the positive edge of CLK
J8,K8
CLK Inputs and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
K2 CKE Clock Enable
deactivates clocking circuitry on the DDR2 SDRAM.
J2 VREF Reference Voltage VREF is reference voltage for inputs.
A1,E1,J9,M9,R1 VDD Power Supply Power Supply: 1.8V ± 0.1V.
A3,E3,J3,N1,P9 VSS Ground Ground.
A9,C1,C3,C7,C9,E9,
VDDQ DQ Power Supply DQ Power Supply: 1.8V ± 0.1V.
G1,G3,G7,G9
A7,B2,B8,D2,D8,E7,
VSSQ DQ Ground DQ Ground. Isolated on the device for improved noise immunity.
F2,F8,H2,H8
A2,E2,L1,R3,R7,R8 NC No Connection No connection.
J7 VSSDL DLL Ground DLL Ground.
J1 VDDL DLL Power Supply DLL Power Supply: 1.8V ± 0.1V.
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IC Block Diagram
PRELIMINARY W9751G6JB
6. BLOCK DIAGRAM
CLK DLL
CLK CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
GENERATOR
RAS COMMAND
CAS
DECODER
COLUMN DECODER COLUMN DECODER
WE
CELL ARRAY CELL ARRAY
A10 BANK #0 BANK #1
MODE
A0
REGISTER
SENSE AMPLIFIER SENSE AMPLIFIER
ADDRESS
A9
BUFFER
A11
A12
BA0
BA1 ODT
DQ0
PREFETCH REGISTER
DQ |
DQ15
DATA CONTROL BUFFER ODT
LDQS
CIRCUIT CONTROL LDQS
REFRESH COLUMN UDQS
UDQS
COUNTER COUNTER
LDM
UDM
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #2 BANK #3
SENSE AMPLIFIER SENSE AMPLIFIER
NOTE: The cell array configuration is 8192 * 1024 * 16
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MAIN PCB-TOP
-32-
MAIN PCB-BOT
-33-
5 4 3 2 1
Power Input 1.32V DC-DC DC-DC Module
1.32V
3.3VU