Text preview for : js28f640j3d75.pdf part of Dreambox DM500 js28f640j3d75
Back to : js28f640j3d75.pdf | Home
NumonyxTM Embedded Flash Memory (J3 v. D)
32, 64, 128, and 256 Mbit
Datasheet
Product Features
Architecture -- High-density symmetrical 128-Kbyte blocks -- 256 Mbit (256 blocks) -- 128 Mbit (128 blocks) -- 64 Mbit (64 blocks) -- 32 Mbit (32 blocks) Performance -- 75 ns Initial Access Speed (128/64/32 -Mbit densities) -- 95 ns Initial Access Speed (256 Mbit only) -- 25 ns 8-word and 4-word Asynchronous page-mode reads -- 32-Byte Write buffer -- 4 µs per Byte Effective programming time System Voltage and Power -- VCC = 2.7 V to 3.6 V -- VCCQ = 2.7 V to 3.6 V Packaging -- 56-Lead TSOP package (32, 64, 128 Mbit only) -- 64-Ball Numonyx Easy BGA package (32, 42, 128 and 256 Mbit) Security -- Enhanced security options for code protection -- 128-bit Protection Register -- 64-bit Unique device identifier -- 64-bit User-programmable OTP cells -- Absolute protection with VPEN = GND -- Individual block locking -- Block erase/program lockout during power transitions Software -- Program and erase suspend support -- Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Quality and Reliability -- Operating temperature: -40 °C to +85 °C -- 100K Minimum erase cycles per block -- 0.13 µm ETOXTM VIII Process
308551-05 November 2007
Downloaded from Elcodis.com electronic components distributor
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Numonyx B.V., All Rights Reserved.
Datasheet 2
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Contents
1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 6 1.3 Conventions ....................................................................................................... 7 Functional Overview .................................................................................................. 8 2.1 Block Diagram .................................................................................................. 10 2.2 Memory Map..................................................................................................... 11 Package Information ............................................................................................... 12 3.1 56-Lead TSOP Package (32, 64, 128 Mbit) ............................................................ 12 3.2 Easy BGA Package (32, 64, 128 and 256 Mbit) ...................................................... 13 Ballouts and Signal Descriptions.............................................................................. 15 4.1 Easy BGA Ballout (32/64/128 Mbit) ..................................................................... 15 4.2 56-Lead TSOP Package Pinout (32/64/128 Mbit).................................................... 17 4.3 Signal Descriptions ............................................................................................ 17 Maximum Ratings and Operating Conditions............................................................ 19 5.1 Absolute Maximum Ratings................................................................................. 19 5.2 Operating Conditions ......................................................................................... 19 5.3 Power Up/Down ................................................................................................ 19 5.3.1 Power-Up/Down Characteristics................................................................ 20 5.3.2 Power Supply Decoupling ........................................................................ 20 5.4 Reset............................................................................................................... 20 Electrical Characteristics ......................................................................................... 21 6.1 DC Current Specifications ................................................................................... 21 6.2 DC Voltage specifications.................................................................................... 22 6.3 Capacitance...................................................................................................... 22 AC Characteristics ................................................................................................... 23 7.1 Read Specifications............................................................................................ 23 7.2 Write Specifications ........................................................................................... 27 7.3 Program, Erase, Block-Lock Specifications ............................................................ 29 7.4 Reset Specifications........................................................................................... 29 7.5 AC Test Conditions ............................................................................................ 30 Bus Interface........................................................................................................... 31 8.1 Bus Reads ........................................................................................................ 32 8.1.1 Asynchronous Page Mode Read ................................................................ 32 8.1.2 Output Disable ....................................................................................... 33 8.2 Bus Writes........................................................................................................ 33 8.3 Standby ........................................................................................................... 34 8.3.1 Reset/Power-Down ................................................................................. 34 8.4 Device Commands............................................................................................. 34 Flash Operations ..................................................................................................... 36 9.1 Status Register ................................................................................................. 36 9.1.1 Clearing the Status Register .................................................................... 37 9.2 Read Operations ............................................................................................... 37 9.2.1 Read Array ............................................................................................ 37 9.2.2 Read Status Register .............................................................................. 38 9.2.3 Read Device Information ......................................................................... 38 9.2.4 CFI Query ............................................................................................. 38
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
November 2007 308551-05
Datasheet 3
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
9.3 9.4 9.5 9.6 9.7
Programming Operations ....................................................................................38 9.3.1 Single-Word/Byte Programming................................................................39 9.3.2 Buffered Programming ............................................................................39 Block Erase Operations .......................................................................................40 Suspend and Resume .........................................................................................41 Status Signal (STS)............................................................................................42 Security and Protection.......................................................................................43 9.7.1 Normal Block Locking ..............................................................................43 9.7.2 Configurable Block Locking.......................................................................44 9.7.3 OTP Protection Registers..........................................................................44 9.7.4 Reading the OTP Protection Register..........................................................44 9.7.5 Programming the OTP Protection Register ..................................................44 9.7.6 Locking the OTP Protection Register ..........................................................45 9.7.7 VPP/ VPEN Protection ..............................................................................46
10.0 Device Command Codes ...........................................................................................47 11.0 Device ID Codes.......................................................................................................48 12.0 Flow Charts..............................................................................................................49 13.0 Common Flash Interface ..........................................................................................58 13.1 Query Structure Output ......................................................................................58 13.2 Query Structure Overview...................................................................................59 13.3 Block Status Register .........................................................................................60 13.4 CFI Query Identification String ............................................................................60 13.5 System Interface Information ..............................................................................61 13.6 Device Geometry Definition .................................................................................61 13.7 Primary-Vendor Specific Extended Query Table ......................................................62 A B Additional Information.............................................................................................66 Ordering Information ...............................................................................................67
Datasheet 4
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Revision History
Date July 2005
Revision 001
Description Initial release Changed Marketing name from 28FxxxJ3 to J3 v. D. Updated the following: · Table 18, "Command Bus Operations" on page 35 · Section 9.2.2, "Read Status Register" on page 38 · Section 9.3.2, "Buffered Programming" on page 39 · Table 24, "Valid Commands During Suspend" on page 41 Added Table 25, "STS Configuration Register" on page 42.
Section 5.3.1, "Power-Up/Down Characteristics" on page 20 was modified. Notes on Table 8, "DC Voltage Characteristics" on page 22 were updated Table 10, "Read Operations" on page 23 was updated with R16 value Table 12, "Configuration Performance" on page 29 was updated Note 1 of Table 26, "STS Configuration Coding Definitions" on page 43 was updated.
September 2005
002
February 2006
003
February 2007 November 2007
004 05
Added 256-Mbit; Updated format. Applied Numonyx branding.
November 2007 308551-05
Datasheet 5
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
1.0
Introduction
This document contains information pertaining to the NumonyxTM Embedded Flash Memory (J3 v. D) device features, operation, and specifications. The NumonyxTM Embedded Flash Memory J3 Version D (J3 v. D) provides improved mainstream performance with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Intel* 0.13 µm ETOXTM VIII process technology. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the NumonyxTM Embedded Flash Memory (J3 v. D) device brings reliable, low-voltage capability (3 V read, program, and erase) with high speed, low-power operation. The NumonyxTM Embedded Flash Memory (J3 v. D) device takes advantage of the proven manufacturing experience and is ideal for code and data applications where high density and low cost are required, such as in networking, telecommunications, digital set top boxes, audio recording, and digital imaging. Numonyx Flash Memory components also deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Numonyx Flash Memory devices.
1.1
Nomenclature
AMIN:
All Densities All Densities 32 Mbit
AMIN = A0 for x8 AMIN = A1 for x16 AMAX = A21 AMAX = A22 AMAX = A23
AMAX:
64 Mbit 128 Mbit
Block: Clear: Program: Set: VPEN: VPEN :
A group of flash cells that share common erase circuitry and erase simultaneously Indicates a logic zero (0) To write data to the flash array Indicates a logic one (1) Refers to a signal or package connection name Refers to timing or voltage levels
1.2
Acronyms
CUI: OTP: PLR: PR: PRD: RFU:
Command User Interface One Time Programmable Protection Lock Register Protection Register Protection Register Data Reserved for Future Use
Datasheet 6
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
SR: SRD: WSM: ECR:
Status Register Status Register Data Write State Machine Enhanced Configuration Register
1.3
Conventions
h: k (noun): M (noun): Nibble Byte: Word: Kword: Kb: KB: Mb: MB: Brackets: Hexadecimal Affix 1,000 1,000,000 4 bits 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e. A[21:1], SR[4,1] and D[15:0]). Denotes 16-bit hexadecimal numbers Denotes 32-bit hexadecimal numbers Data I/O signals
00FFh: 00FF 00FFh: DQ[15:0]:
November 2007 308551-05
Datasheet 7
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
2.0
Functional Overview
The NumonyxTM Embedded Flash Memory (J3 v. D) family contains high-density memory organized in any of the following configurations: · 32 Mbytes or 16 Mword (256-Mbit), organized as two-hundred-fifty-six 128-Kbyte (131,072 bytes) erase blocks- Users should be aware that this density is not offered in a monolithic part and the device is made up of 2x128-Mb devices. · 16 Mbytes or 8 Mword (128-Mbit), organized as one-hundred-twenty-eight 128Kbyte erase blocks · 8 Mbytes or 4 Mword (64-Mbit), organized as sixty-four 128-Kbyte erase blocks · 4 Mbytes or 2 Mword (32-Mbit), organized as thirty-two 128-Kbyte erase blocks These devices can be accessed as 8- or 16-bit words. See Figure 1, "Memory Block Diagram (32, 64 and 128 Mbit)" on page 10 for further details. A 128-bit Protection Register has multiple uses, including unique flash device identification. The NumonyxTM Embedded Flash Memory (J3 v. D) device includes new security features that were not available on the (previous) 0.25µm and 0.18µm versions of the J3 family. These new security features prevent altering of code through different protection schemes that can be implemented, based on user requirements. The NumonyxTM Embedded Flash Memory (J3 v. D) device optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device's 128-Kbyte blocks typically within one second, independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments.
Datasheet 8
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Blocks are selectively and individually lockable in-system. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (using the Set Block Lock-Bit and Clear Block Lock-Bits commands). The Status Register indicates when the WSM's block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), program is suspended, or the device is in reset/power-down mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device: · BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high byte. · BYTE#-high enables16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don't care). Figure 1, "Memory Block Diagram (32, 64 and 128 Mbit)" on page 10 shows a device block diagram. When the device is disabled, with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared. (see Table 15, "Chip Enable Truth Table" on page 31).
November 2007 308551-05
Datasheet 9
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
2.1
Figure 1:
Block Diagram
Memory Block Diagram (32, 64 and 128 Mbit)
DQ0 - DQ15
VCCQ
Output Buffer
Input Buffer
Output Latch/Multi pl exer
Query Write Buffer Data Registe r Identifier Register Status Register
I/O Logic CE Logic
VCC BYTE# CE0 CE1 CE2 WE# OE# RP#
Command User Interface
A0 - A2
Data Comparator
Multiplexer
32-Mbit: A0 - A21 64-Mbit: A0 - A22 128-Mbit: A0 - A23
Input Buffer
Y-Decoder
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty -eight Write State Machine Program/Erase Voltage Switch
STS V PEN VCC GND
Address Latch Address Counter
X-Decoder
128-Kbyte Blocks
Figure 2:
NumonyxTM Embedded Flash Memory (J3 v. D) Memory Block Diagram (256 Mbit)
Vcc 28F128J3 CE1 CE# Upper Address CE0 Device D[15-0] A[23-A0] A[23-A0] CE2
A24
D[15-0]
28F128J3 CE1 Lower Address CE0 Device D[15-0] A[23-A0] CE2
Datasheet 10
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
2.2
Figure 3:
Memory Map
NumonyxTM Embedded Flash Memory (J3 v. D) Memory Map
A[24-1]: 256 Mbit A [23-1]: 128 Mbit A [22-1]: 64 Mbit A [21-1]: 32 Mbit
FFFFFF 255 FF0000
A[24-0]: 256 Mbit A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit
1FFFFFF 1FE0000
128-Kbyte Block
64-Kword Block
255
0FFFFFF 0FE0000
128-Kbyte Block
7FFFFF 127 7F0000
64-Kword Block
127
07FFFFF 07E0000
128-Kbyte Block
3FFFFF 63 3F0000
64-Kword Block
63
03E0000
128-Kbyte Block
31
1F0000
64-Kword Block
31
003FFFF 0020000 001FFFF 0000000
128-Kbyte Block 128-Kbyte Block
1 0
01FFFF 010000 00FFFF 000000
64-Kword Block 64-Kword Block
1 0
Byte-Wide (x8) Mode
Word Wide (x16) Mode
November 2007 308551-05
32-Mbit
64-Mbit
03FFFFF
1FFFFF
1 28-Mbit
256-Mbit
Datasheet 11
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
3.0
3.1
Figure 4:
Package Information
56-Lead TSOP Package (32, 64, 128 Mbit)
56-Lead TSOP Package Mechanical
Z
See Notes 1 and 3
Pin 1
See Note 2
A2 e
E
See Detail B
Y
D1 D
A1 Seating Plane
See Detail A
A
Detail A Detail B
C
0
b
L
Notes: 1. One dimple on package denotes Pin 1. 2. If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Table 1:
56-Lead TSOP Dimension Table
Millimeters Inches Max 1.200 0.050 0.965 0.100 0.100 18.200 13.800 0.995 0.150 0.150 18.400 14.000 0.500 19.800 0.500 20.00 0.600 20.200 0.700 0.780 0.020 1.025 0.200 0.200 18.600 14.200 0.002 0.038 0.004 0.004 0.717 0.543 0.039 0.006 0.006 0.724 0.551 0.0197 0.787 0.024 0.795 0.028 0.040 0.008 0.008 0.732 0.559 Min Nom Max 0.047 Symbol Min Nom A A1 A2 b c D1 E e D L
Parameter Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length
Datasheet 12
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Table 1:
56-Lead TSOP Dimension Table
Millimeters Inches Max Min Nom 56 5° 0.100 0.150 0.250 0.350 0.006 0.010 0° 3° 5° 0.004 0.014 Max Symbol Min Nom 56 0° 3° N q Y Z
Parameter Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset
3.2
Figure 5:
Easy BGA Package (32, 64, 128 and 256 Mbit)
Easy BGA Mechanical Specifications
Ball A1 Corner D S1
Ball A1 Corner
1 A B C D E F G H
2
3
4
5
6
7
8 A B C E D E F G H
8
7
6
5
4
3
2
1
S2
e
b
Top View - Plastic Backside
Complete Ink Mark Not Shown A1 A2 A
Bottom View - Ball Side Up
Seating Plane
Y
Table 2:
Easy BGA Package Dimensions Table (Sheet 1 of 2)
Millimeters Parameter Symb ol A A A1 A2 0.250 0.780 Min Nom Max 1.200 1.300 0.0098 0.0307 Note s Min Inches Nom Max 0.0472 0.0512
Package Height (32, 64, 128- Mbit) Package Height (256- Mbit) Ball Height Package Body Thickness (32, 64, 128- Mbit)
November 2007 308551-05
Datasheet 13
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Table 2:
Easy BGA Package Dimensions Table (Sheet 2 of 2)
Millimeters Parameter Symb ol A2 b D E [e] N Y S1 S2 1.400 2.900 1.500 3.000 0.330 9.900 12.900 Min Nom 0.910 0.430 10.000 13.000 1.000 64 0.100 1.600 3.100 1 1 0.0551 0.1142 0.0591 0.1181 0.530 10.100 13.100 1 1 0.0130 0.3898 0.5079 Max Note s Min Inches Nom 0.0358 0.0169 0.3937 0.5118 0.0394 64 0.0039 0.0630 0.1220 0.0209 0.3976 0.5157 Max
Package Body Thickness (256- Mbit) Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D (32/64/128 Mb) Corner to Ball A1 Distance Along E (32/64/128 Mb)
Notes: 1. For Daisy Chain Evaluation Unit information refer to the Numonyx Flash Memory Packaging Technology Web page at: www.Numonyx.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Numonyx Flash Memory Packaging Technology Web page at: www.Numonyx.com/design/packtech/index.htm
Datasheet 14
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
4.0
Ballouts and Signal Descriptions
NumonyxTM Embedded Flash Memory (J3 v. D) is available in two package types. All densities of the NumonyxTM Embedded Flash Memory (J3 v. D) are supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages, except the 256 Mbit density that is available only in Easy BGA. Figure 6, Figure 7 and Figure 8 show the ballouts.
4.1
Figure 6:
Easy BGA Ballout (32/64/128 Mbit)
Easy BGA Ballout (32/64/128 Mbit)
1 A
A1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1 A
A6
A8
VPEN
A13
VCC
A18
A22
A22
A18
VCC
A13
VPEN
A8
A6
A1
B
A2 VSS A9 CE0# A14 RFU A19 CE1# CE1# A19 RFU A14 CE0# A9 VSS A2
B C
A3 A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3
C D
A4 A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4
D E
D8 D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8
E F
BYTE# D0 D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE#
F G
A23 A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23
G H
CE2# RFU VCC VSS D13 VSS D7 RFU RFU D7 VSS D13 VSS VCC RFU CE2# Intel® Embedded Flash Memory (J3 v. D) Easy BGA Top View- Ball side down 32/64/128 Mbit Intel® Embedded Flash Memory (J3 v. D) Easy BGA Bottom View- Ball side up 32/64/128 Mbit
H
Notes: 1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC). 2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC).
November 2007 308551-05
Datasheet 15
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Figure 7:
Easy BGA Ballout (256 Mbit)
1 A
A1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1 A
A6
A8
VPEN
A13
VCC
A18
A22
A22
A18
VCC
A13
VPEN
A8
A6
A1
B
A2 VSS A9 CE# A14 RFU A19 NC NC A19 RFU A14 CE# A9 VSS A2
B C
A3 A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3
C D
A4 A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4
D E
D8 D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8
E F
BYTE# D0 D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE#
F G
A23 A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23
G H
NC RFU VCC VSS D13 VSS D7 A24 A24 D7 VSS D13 VSS VCC RFU NC Intel® Embedded Flash Memory (J3 v. D) Easy BGA Top View- Ball side down 256 Mbit Intel® Embedded Flash Memory (J3 v. D) Easy BGA Bottom View- Ball side up 256 Mbit
H
Datasheet 16
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
4.2
Figure 8:
3V 3V 3V
56-Lead TSOP Package Pinout (32/64/128 Mbit)
56-Lead TSOP Package Pinout (32/64/128 Mbit)
RFU 3V WE# 3V OE# 3V STS 3V DQ15 3V DQ 3V 7 DQ14 3V DQ 3V 6 GND DQ13 3V 3V DQ 5 DQ12 3V DQ 3V 4 VCCQ 3V GND DQ11 3V DQ 3V 3 DQ10 3V DQ 3V 2 VCC 3V DQ 3V 9 DQ 3V 1 DQ 3V 8 DQ 0 A0 GND BYTE# 3V A23 3V CE2 GND
3V
3V
3V A22 GND CE1 3V A21 3V A20 3V A19 3V A18 3V A17 3V A16 3V VCC 3V A15 3V A14 3V A13 3V A12 3V CE0 3V VPEN 3V RP# 3V A11 3V A10 3V A9 3V A8 GND 3V A7 3V A6 3V A5 3V A4 3V A3 3V A2 3V A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Intel® Embedded Flash Memory (28FXXXJ3D) JS28F640J3D75 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View
32/64/128 Mbit
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Notes: 1. A22 exists on 64- and 128- densities. On 32-Mbit density this signal is a no-connect (NC). 2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC)
4.3
Signal Descriptions
Table 3 lists the active signals used on NumonyxTM Embedded Flash Memory (J3 v. D) and provides a description of each.
Table 3:
Symbol A0
Signal Descriptions for NumonyxTM Embedded Flash Memory (J3 v. D) (Sheet 1 of 2)
Type Input Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle: 32-Mbit -- A[21:1] 64-Mbit-- A[22:1] 128-Mbit -- A[23:1] 256-Mbit -- A[24:1] A24 acts as a virtual CE for the two devices. A24 at VIL selects the lower die and A24 at VIH selects the upper die. LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data is internally latched during write operations.
A[MAX:1]
Input
D[7:0]
Input/ Output
November 2007 308551-05
Datasheet 17
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Table 3:
Symbol D[15:8]
Signal Descriptions for NumonyxTM Embedded Flash Memory (J3 v. D) (Sheet 2 of 2)
Type Input/ Output Name and Function HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode CHIP ENABLE: Activate the 32-, 64- and 128 Mbit devices' control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected, power reduces to standby levels. All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of CE0, CE1, or CE2 that disables the device. CHIP ENABLE: Activates the 256Mbit devices' control logic, input buffers, decoders, and sense amplifiers. Device selection occurs with the first edge of CE# that enables the device. Device deselection occurs with the first edge of CE# that disables the device.s RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of WE#. STATUS: Indicates the status of the internal state machine. When configured in level mode (default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. STS is to be tied to VCCQ with a pull-up resistor. BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order address bit. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With VPEN VPENLK, memory contents cannot be altered. CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC VLKO . Caution: Device operation at invalid Vcc voltages should not be attempted. I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC . Ground: Ground reference for device logic voltages. Connect to system ground. No Connect: Lead is not internally connected; it may be driven or floated. Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device functionality and enhancement.
CE[2:0]
Input
CE#
Input
RP#
Input
OE# WE#
Input Input Open Drain Output
STS
BYTE#
Input
VPEN
Input
VCC VCCQ GND NC RFU
Power Power Supply -- --
Datasheet 18
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
5.0
5.1
Warning:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design.
Table 4:
Absolute Maximum Ratings
Parameter Min 40 65 2.0 2.0 2.0 -- Max +85 +125 +5.6 +5.6 VCCQ (max) + 2.0 100 Unit °C °C V V V mA Notes -- -- 2 2 1 3
Temperature under Bias Expanded (TA, Ambient) Storage Temperature VCC Voltage VCCQ Voltage on any input/output signal (except VCC, VCCQ) ISH Output Short Circuit Current
Notes: 1. Voltage is referenced to VSS. During infrequent non-periodic transitions, the voltage potential between VSS and input/ output pins may undershoot to 2.0 V for periods < 20 ns or overshoot to VCCQ (max) + 2.0 V for periods < 20 ns. 2. During infrequent non-periodic transitions, the voltage potential between VCC and the supplies may undershoot to 2.0 V for periods < 20 ns or VSUPPLY (max) + 2.0 V for periods < 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time
5.2
Warning:
Operating Conditions
Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability
Table 5:
Symbol TA VCC VCCQ
Temperature and VCC Operating Condition of NumonyxTM Embedded Flash Memory (J3 v. D)
Parameter Min -40.0 VCC Supply Voltage VCCQ Supply Voltage 2.70 2.70 +85 3.6 3.6 Max °C V V Unit Test Condition Ambient Temperature -- --
5.3
Power Up/Down
This section provides an overview of system level considerations with regards to the flash device. It includes a brief description of power-up, power-down and decoupling design considerations.
November 2007 308551-05
Datasheet 19
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
5.3.1
Power-Up/Down Characteristics
To prevent conditions that could result in spurious program or erase operations, the power-up/power-down sequence shown in here is recommended. Note that each power supply must reach its minimum voltage range before applying/removing the next supply voltage.
Table 6:
Power-Up/Down Sequence
Power-UpSequence 1st 2nd 3rd 1st 2nd 3rd Sequencing not required 2nd 1st Power-Down Sequence 2nd 1st
Power Supply Voltage VCC(min) VCCQ(min) VPEN(min)
1st 2nd
2nd 1st
Sequencing not required
Note:
Power supplies connected or sequenced together. Device inputs must not be driven until all supply voltages reach their minimum range. RP# should be low during power transitions.
5.3.2
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized, charge pumps are switched on, and internal voltage nodes are ramped. All of this internal activities produce transient signals. The magnitude of the transient signals depends on the device and system loading. To minimize the effect of these transient signals, a 0.1 µF ceramic capacitor is required across each VCC/VSS and VCCQ signal. Capacitors should be placed as close as possible to device connections. Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor should help overcome voltage slumps caused by PCB (printed circuit board) trace inductance.
5.4
Reset
By holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset, internal flash circuitry is disabled and outputs are placed in a highimpedance state. After return from reset, a certain amount of time is required before the flash device is able to perform normal operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Figure 16, "AC Waveform for Reset Operation" on page 29 for detailed information regarding reset timings.
Datasheet 20
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
6.0
6.1
Table 7:
Electrical Characteristics
DC Current Specifications
DC Current Characteristics
VCCQ V CC 2.7 - 3.6V 2.7 - 3.6V Typ Max ±1 ±10 50 100 0.71 1.42 50 15 4-Word Page 24 29 mA 120 240 2 4 120 20 mA A mA Unit A A A VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or VSS VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or VSS CMOS Inputs, VCC = VCC Max; Vccq = VccqMax Device is disabled RP# = VCCQ ± 0.2 V TTL Inputs, VCC = VCC Max, Vccq = VccqMax Device is disabled, RP# = VIH RP# = GND ± 0.2 V, IOUT (STS) = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max Device is enabled f = 5 MHz, IOUT = 0 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max Device is enabled f = 33 MHz, IOUT = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads. Device is enabled f = 5 MHz, IOUT = 0 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads. Device is enabled f = 33 MHz, IOUT = 0 mA CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC 1,4 1,3 1 1 Test Conditions Notes
Symbol ILI ILO
Parameter Input and VPEN Load Current Output Leakage Current 32, 64, 128 Mbit 256 Mbit
ICCS
VCC Standby Current
32, 64, 128 Mbit 256 Mbit
1,2,3
ICCD
VCC Power-Down Current
ICCR VCC Page Mode Read Current
10 8-Word Page 30
15
mA
54
mA
ICCW
VCC Program or Set Lock-Bit Current VCC Block Erase or Clear Block Lock-Bits Current VCC Program Suspend or Block Erase Suspend Current
35 40 35 40
60 70 70 80
mA mA mA mA
ICCE
1,4
ICCWS ICCES
10
mA
Device is enabled
1,5
Notes: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Numonyx's Application Support Hotline or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH. 4. Sampled, not 100% tested. 5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend mode, the device's current draw is ICCR and ICCWS.
November 2007 308551-05
Datasheet 21
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
6.2
Table 8:
DC Voltage specifications
DC Voltage Characteristics
VCCQ V CC 2.7 - 3.6 V 2.7 - 3.6 V Min 0.5 2.0 Max 0.8 VCCQ + 0.5V 0.4 Unit V V V VCC = VCC Min VCCQ = VCCQ Min IOL = 2 mA VCC = VCC Min VCCQ = VCCQ Min IOL = 100 µA VCC = VCCMIN VCCQ = VCCQ Min IOH = 2.5 mA VCC = VCCMIN VCCQ = VCCQ Min IOH = 100 µA 2, 5, 6 2, 5, 6 Test Conditions Notes
Symbol VIL VIH
Parameter Input Low Voltage Input High Voltage
VOL
Output Low Voltage 0.2 V
1, 2
0.85 × VCCQ VOH Output High Voltage VCCQ 0.2 VPEN Lockout during Program, Erase and Lock-Bit Operations VPEN during Block Erase, Program, or Lock-Bit Operations VCC Lockout Voltage 2.7 2.0
V
1, 2
V
VPENLK VPENH VLKO
2.2 3.6
V V V
2, 3 3 4
Notes: 1. Includes STS. 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 4. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). 5. Includes all operational modes of the device including standby and power-up sequences 6. Input/Output signals can undershoot to -1.0v referenced to VSS and can overshoot to VCCQ = 1.0v for duration of 2ns or less, the VCCQ valid range is referenced to VSS.
6.3
Table 9:
Symbol CIN
Capacitance
NumonyxTM Embedded Flash Memory (J3 v. D) Capacitance
Parameter1 Input Capacitance 32, 64, 128 Mb 256 Mb 32, 64, 128 Mb 256 Mb Type Max Unit Condition2 VIN = 0.0 V
6 12 8 16
8 16 12 24
pF
COUT
Output Capacitance
pF
VOUT = 0.0 V
Notes: 1. sampled. not 100% tested. 2. TA = +25 °C, f = 1 MHZ
Datasheet 22
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
7.0
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the following convention:
Figure 9:
Timing Signal Naming Convention
t
Source Signal Source State
E L Q V
Target State Target Signal
Figure 10: Timing Signal Name Decoder
Signal Address Data - Read Data - Write Chip Enable (CE#) Output Enable (OE#) Write Enable (WE#) Address Valid (ADV#) Reset (RST#) Clock (CLK) WAIT A Q D E G W V P C T Code High Low High-Z Low-Z Valid Invalid State H L Z X V I Code
Note:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash device's data sheet, and is the address-to-data delay for subsequent page-mode reads.
7.1
Read Specifications
Table 10: Read Operations (Sheet 1 of 2)
Asynchronous Specifications VCC = 2.7 V3.6 V (3) and VCCQ = 2.7 V3.6 V(3) # Sym Parameter Density 32 Mbit R1 tAVAV Read/Write Cycle Time 64 Mbit 128 Mbit 256 Mbit Min 75 75 75 95 ns Max Unit Notes 1,2 1,2 1,2 1,2
November 2007 308551-05
Datasheet 23
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Table 10: Read Operations (Sheet 2 of 2)
Asynchronous Specifications VCC = 2.7 V3.6 V (3) and VCCQ = 2.7 V3.6 V(3) # Sym Parameter Density 32 Mbit R2 tAVQV Address to Output Delay 64 Mbit 128 Mbit 256 Mbit 32 Mbit R3 tELQV CEX to Output Delay 64 Mbit 128 Mbit 256 Mbit R4 tGLQV OE# to Non-Array Output Delay 32 Mbit R5 tPHQV RP# High to Output Delay 64 Mbit 128 Mbit 256 Mbit R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 tELQX tGLQX tEHQZ tGHQZ tOH tELFL/tELFH tFLQV/tFHQV tFLQZ tEHEL tAPA tGLQV CEX to Output in Low Z OE# to Output in Low Z CEX High to Output in High Z OE# High to Output in High Z Output Hold from Address, CEX, or OE# Change, Whichever Occurs First CEX Low to BYTE# High or Low BYTE# to Output Delay BYTE# to Output in High Z CEx High to CEx Low Page Address Access Time OE# to Array Output Delay 0 0 25 15 Min Max 75 75 75 95 75 75 75 95 25 150 180 210 210 ns ns ns ns ns 10 1 1 ns µs µs ns 25 25 ns ns ns ns ns ns Unit Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,4 1,2 1,2 1,2 1,2 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2 1,2,5 1,2,5 5, 6 1,2,4
All
0
All All
0
Notes: 1. CEX low is defined as the first edge of CE0, CE1, CE2 or CE# that enables the device. CEX high is defined at the first edge of CE0, CE1, CE2 or CE# that disables the device. 2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate. 3. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, CE2 or CE# that enables the device without impact on tELQV. 4. See Figure 17, "AC Input/Output Reference Waveform" on page 30 and Figure 18, "Transient Equivalent Testing Load Circuit" on page 30 for testing characteristics. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Datasheet 24
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Figure 11: Single Word Asynchronous Read Waveform
R1 R2 Address [A] R3 CEx [E] R9 OE# [G] WE# [W] R4 R16 R7 R6 Data [D/Q] R11 BYTE#[F] R5 RP# [P]
Notes: 1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device. 2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads, query reads, or device identifier reads).
R8
R10
R12 R13
Figure 12: 4-Word Asynchronous Page Mode Read Waveform
R1 R2 A[MAX:3] [A] A[2:1] [A] R3 CEx [E] R4 OE# [G] WE# [W] R6 R7 D[15:0] [Q] R5 RP# [P]
Note: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device.
00
01
10
11
R10 R15 1 2 3 4
R8 R10 R9
November 2007 308551-05
Datasheet 25
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Figure 13: 8-Word Asynchronous Page Mode Read
R1 R2 A[MAX:4] [A] A[3:1] [A] R3 CEx [E] R4 OE# [G] WE# [W] R6 R7 D[15:0] [Q] R5 RP# [P] BYTE#
Notes: 1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device. 2. In this diagram, BYTE# is asserted high
R10 1 R15 2 7 8
R10 R8 R9
Datasheet 26
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
7.2
Write Specifications
Table 11: Write Operations
# Symbol Parameter Density Valid for All Speeds Min 32 Mbit W1 tPHWL (tPHEL) RP# High Recovery to WE# (CE X) Going Low 64 Mbit 128 Mbit W2 W3 W4 W5 W6 W7 W8 W9 W11 W12 W13 W15 tELWL (tWLEL) tWP tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL CEX (WE#) Low to WE# (CEX) Going Low Write Pulse Width Data Setup to WE# (CE X) Going High Address Setup to WE# (CE X) Going High CEX (WE#) Hold from WE# (CE X) High Data Hold from WE# (CEX) High Address Hold from WE# (CEX) High Write Pulse Width High VPEN Setup to WE# (CEX) Going High Write Recovery before Read WE# (CEX) High to STS Going Low VPEN Hold from Valid SRD, STS Going High 0 All 150 180 210 0 60 50 55 0 0 0 30 0 35 500 ns 1,2,4 1,2,4 1,2,5 1,2,5 1,2, 1,2, 1,2, 1,2,6 1,2,3 1,2,7 1,2,8 1,2,3,8,9 Max 1,2,3 Unit Notes
Notes: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE X high is defined at the first edge of CE0, CE1, or CE2 that disables the device. 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC CharacteristicsRead-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 5. Refer to Table 16, "Enhanced Configuration Register" on page 33 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CE X or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[1,3,4,5] = 0).
November 2007 308551-05
Datasheet 27
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Figure 14: Asynchronous Write Waveform
W5 ADDRESS [A] W6 CEx (WE#) [E (W)] W2 WE# (CEx) [W (E)] OE# [G] W4 DATA [D/Q] D W13 STS[R] W1 RP# [P] W11 VPEN [V] W7 W3 W9 W8
Figure 15: Asynchronous Write to Read Waveform
W5 Address [A] W6 CE# [E] W2 WE# [W] W12 OE# [G] W4 Data [D/Q] W1 RST #/ RP# [P] W11 VPEN [V] D W7 W3 W8
Datasheet 28
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
7.3
Program, Erase, Block-Lock Specifications
Table 12: Configuration Performance
# W16 W16 tWHQV3 tEHQV3 Symbol Parameter Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write to Buffer Command) W16 W16 W16 W16 W16 WY tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH tSTS Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time to Read Erase Suspend Latency Time to Read STS Pulse Width Low Time Typ 128 40 0.53 1.0 50 0.5 15 15 500 Max (8) 654 175 2.4 4.0 60 0.70 20 20 Unit µs µs sec sec µs sec µs µs ns Notes 1,2,3,4,5,6,7 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4,9 1,2,3,4,9 1,2,3,9 1,2,3,9 1
Notes: 1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. These performance numbers are valid for all speed versions. 3. Sampled but not 100% tested. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (tWHQV1, tEHQV1) is 4µs/byte (typical). 7. Effective per-word program time (tWHQV2, tEHQV2) is 8µs/word (typical). 8. Max values are measured at worst case temperature, data pattern and VCC corner after 100k cycles (except as noted). 9. Max values are expressed at 25 °C/-40 °C.
7.4
Reset Specifications
Figure 16: AC Waveform for Reset Operation
STS (R) P1 RP# (P) P3 Vcc
Note: STS is shown in its default mode (RY/BY#)
P2
November 2007 308551-05
Datasheet 29
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Table 13: Reset Specifications
# P1 P2 P3 Symbol tPLPH tPHRH tVCCPH Parameter RP# Pulse Low Time (If RP# is tied to VCC , this specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration Vcc Power Valid to RP# de-assertion (high) 60 Min 25 100 Max Unit µs ns µs Notes 1,2 1,3
Notes: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
7.5
AC Test Conditions
Figure 17: AC Input/Output Reference Waveform
VCCQ Input VCCQ/2 0.0
Note: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Test Points
VCCQ/2
Output
Figure 18: Transient Equivalent Testing Load Circuit
Device Under Test
CL
Out
Note:
CL Includes Jig Capacitance
Figure 19: Test Configuration
Test Configuration VCCQ = VCCQMIN CL (pF)
30
Datasheet 30
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
8.0
Bus Interface
This section provides an overview of Bus operations. Basically, there are three operations you can do with flash memory: Read, Program (Write), and Erase.The on-chip Write State Machine (WSM) manages all erase and program algorithms. The system CPU provides control of all in-system read, write, and erase operations through the system bus. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Table 14 summarizes the necessary states of each control signal for different modes of operations.
Table 14: Bus Operations
Mode Async., Status, Query and Identifier Reads Output Disable Standby Reset/Power-down Command Writes Array Writes(8) Notes: 1. 2. 3. 4. 5. 6. 7. 8. RP# CEx(1) OE#(2) WE#(2) V PEN DQ15:0(
3)
STS (Default Mode) High Z High Z High Z High Z High Z VIL
Notes
VIH VIH VIH VIL VIH VIH
Enabled Enabled Disable d X Enabled Enabled
VIL VIH X X VIH VIH
VIH VIH X X VIL VIL
X X X X X VPENH
DOUT High Z High Z High Z DIN X
4,6
6,7 8,5
See Table 15 for valid CEx Configurations. OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#. DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high. VPENLK, memory contents can be read but not altered. Refer to DC characteristics. When VPEN X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or VOH. In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit configuration algorithm. It is VOH (pulled up by an external pull up resistance ~= 10k) when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset power-down mode. See Table 18, "Command Bus Operations" on page 35 for valid DIN (user commands) during a Write operation Array writes are either program or erase operations. /
Table 15: Chip Enable Truth Table
CE2 VIL VIL VIL VIL VIH VIH VIH VIH Note: CE1 VIL VIL VIH VIH VIL VIL VIH VIH
GND.
CE0 VIL VIH VIL VIH VIL VIH VIL VIH
DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
For single-chip applications, CE2 and CE1 can be connected to
The next few sections detail each of the basic flash operations and some of the advanced features available on flash memory.
November 2007 308551-05
Datasheet 31
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
8.1
Bus Reads
Reading from flash memory outputs stored information to the processor or chipset, and does not change any contents. Reading can be performed an unlimited number of times. Besides array data, other types of data such as device information and device status is available from the flash. To perform a bus read operation, CEx and OE# must be asserted. CEx is the deviceselect control; when active, it enables the flash memory device. OE# is the data-output control; when active, the addressed flash memory data is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted.
8.1.1
Asynchronous Page Mode Read
There are two Asynchronous Page mode configurations available on NumonyxTM Embedded Flash Memory (J3 v. D), depending on the system design requirements: · Four-Word Page mode: This is the default mode on power-up or reset. Array data can be sensed up to four words (8 Bytes) at a time. · Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a time. This mode must be enabled on power-up or reset by using the command sequence described in Table 18, "Command Bus Operations" on page 35. Address bits A[3:1] determine which word is output during a read operation, and A[3:0] determine which byte is output for a x8 bus width. After the initial access delay, the first word out of the page buffer corresponds to the initial address. In Four-Word Page mode, address bits A[2:1] determine which word is output from the page buffer for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus width. Subsequent reads from the device come from the page buffer. These reads are output on D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0] (Four-Word Page mode) or A[3:0] (Eight-Word Page mode). Data can be read from the page buffer multiple times, and in any order. In Four-Word Page mode, if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is toggled, the device will sense and load new data into the page buffer. Asynchronous Page mode is the default read mode on power-up or reset. To perform a Page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous Page mode reads are permitted in all blocks and are used to access register information. During register access, only one word is loaded into the page buffer.
8.1.1.1
Enhanced Configuration Register (ECR)
The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed by the Set Enhanced Configuration Register command can select between Four-Word Page mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set Enhanced Configuration Register command. The Set Enhanced Configuration Register command is written along with the configuration register value, which is placed on the lower 16 bits of the address bus A[15:0]. This is followed by a second write that confirms the operation and again presents the Enhanced Configuration Register data on the address bus. After executing this command, the device returns to Read Array mode. The ECR is shown in Table 16. 8-word page mode Command Bus-Cycle is captured in Table 17.
Datasheet 32
November 2007 308551-05
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
Note:
For forward compatibility reasons, if the 8-word Asynchronous Page mode is used on NumonyxTM Embedded Flash Memory (J3 v. D), a Clear Status Register command must be executed after issuing the Set Enhanced Configuration Register command. See Table 17 for further details.
Table 16: Enhanced Configuration Register
Reserved ECR 15 ECR 14 Page Length ECR 13 ECR 12 ECR 11 ECR 10 ECR 9 ECR 8 ECR 7 Reserved ECR 6 ECR 5 ECR 4 ECR 3 ECR 2 ECR 1 ECR 0
BITS ECR[15:14] ECR[13] ECR[12:0] RFU · · RFU
DESCRIPTION
NOTES All bits should be set to 0.
"1" = 8 Word Page mode "0" = 4 Word Page mode All bits should be set to 0.
Table 17: Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command Set Enhanced Configuration Register (Set ECR) Bus Cycles Required 2 First Bus Cycle Oper Write Addr(1) ECD Data 0060h Oper Write Second Bus Cycle Addr(1) ECD Data 0004h
1. X = Any valid address within the device. ECD = Enhanced Configuration Register Data
8.1.2
Output Disable
With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled. Output signals D[15:0] are placed in a high-impedance state.
8.2
Bus Writes
Writing or Programming to the device, is where the host writes information or data into the flash device for non-volatile storage. When the flash device is programmed, `ones' are changed to `zeros'. `Zeros' cannot be programed back to `ones'. To do so, an erase operation must be performed. Writing commands to the Command User Interface (CUI) enables various modes of operation, including the following: · Reading of array data · Common Flash Interface (CFI) data · Identifier codes, inspection, and clearing of the Status Register · Block Erasure, Program, and Lock-bit Configuration (when VPEN = VPENH) Erasing is performed on a block basis all flash cells within a block are erased together. Any information or data previously stored in the block will be lost. Erasing is typically done prior to programming. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command requires the command and address within the device to be cleared.
November 2007 308551-05
Datasheet 33
Downloaded from Elcodis.com electronic components distributor
NumonyxTM Embedded Flash Memory (J3 v. D)
The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 15 on page 31). Standard microprocessor write timings are used.
8.3
Standby
CE0, CE1, and CE2 can disable the device (see Table 15 on page 31) and place it in standby mode. This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.
8.3.1
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a highimpedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is set to 0080h. During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during Block Erase, Program, or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Numonyx Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESE