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AN578
INITIATING AND TERMINATING DATA TRANSFER
During times of no data transfer (idle time), both the SCL and SDA lines are pulled high. A Master device which wishes to take control of the bus must first generate a START condition. A START is defined as a high to low transition of SDA when SCL is high. When the Master has completed all data transmissions and wishes to relinquish the bus, it generates a STOP condition. A STOP is defined as a low to high transition of SDA while SCL is high. Because the START and STOP conditions are defined as transitions of the SDA when the SCL line is high, the SDA line can only change when SCL is low during the actual data transmission. Figure 1 shows the relationship between SCL and SDA for the various conditions.

Use of the SSP Module in the I2CTM Multi-Master Environment
Scott Fink Microchip Technology Inc.

INTRODUCTION
The Inter-IC (I2C) bus is a two-wire serial interface developed by Philips/Signetics. The specification supports data transmission up to 400 Kbps. The I2C interface employs a comprehensive protocol to ensure reliable transmission and reception of data. When the bus is active, one device is the Master (generates the clock and the handshaking signals), while all the other devices are Slaves. The current bus Master can both read-from and write-to any of the Slave units by addressing them individually. On a Multi-Master bus the Masters follow an arbitration scheme to ensure that the bus is not corrupted. Each device attached to the I2C bus is assigned a unique address. When a Master wishes to initiate a data transfer, it first transmits the address of the device that it wishes to "talk" to. All devices "listen" to see if this is their address. Within this address, a bit specifies whether the Master wishes to read-from or write-to the Slave device. The output stages of each device on the bus, attached to the clock (SCL) and data (SDA) lines, must have an open-drain or open-collector in order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high level when no device is pulling the line down. The only limitation on the number of devices that may be attached to the bus is the maximum bus loading specification. For complete bus specifications, refer to Philips/Signetics document "The I2C-bus and How to Use It" (www.semiconductors.philips.com).

FIGURE 1:

START AND STOP CONDITIONS

SDA

SCL

S Start Condition Change of Data Allowed Change of Data Allowed

P Stop Condition

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ADDRESSING I2C DEVICES
There are two address formats. The simplest of these is the 7-bit address format with a R/W bit (Figure 2). The more complex is the 10-bit address with a R/W bit (Figure 3). For 10-bit addressing, two bytes must be transmitted with the first five bits specifying this to be a 10-bit address. Only 7-bit addressing is used in this application note.

TRANSFER ACKNOWLEDGE
Slave as Receiver
All data is transmitted as bytes, with no limit to the number of bytes transmitted per data transfer. After each byte, the slave-receiver generates an acknowledge bit (ACK) by pulling the SDA line low. When a slave-receiver doesn't acknowledge the slave address or received data, the master aborts the transfer. Whether the ACK bit is generated or not, the SDA line must be released by the slave so that the master can generate the STOP condition.

FIGURE 2:
MSb S

7-BIT ADDRESS FORMAT
LSb R/W ACK

Master as Receiver
If the master is receiving the data, it generates an acknowledge signal for each received byte of data except for the last byte. To signal the end of data to the slave-transmitter, the master does not generate an acknowledge. The slave then releases the SDA line so the master can generate the STOP condition. The master can also generate the STOP condition during the acknowledge pulse for valid termination of data transfer. If the slave needs to delay the transmission of the next byte, holding the SCL line low will force the master into a wait state. Data transfer continues when the slave releases the SCL line. This allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. This wait state technique can also be implemented at the bit level.

Slave Address

Sent by Slave

S R/W ACK -

Start Condition Read/Write bit Acknowledge

FIGURE 3:

10-BIT ADDRESS FORMAT
1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

S 1

Sent by Slave = 0 for write S R/W ACK Start Condition Read/Write bit Acknowledge

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MULTI-MASTER
The I2C protocol allows a system to have more than one master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur.

Clock Synchronization
Clock synchronization occurs after the devices have started arbitration. This is performed using a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the concerned devices to start counting off their low period. Once a device clock has gone low, it will hold the SCL line low until its SCL high state is reached. The low to high transition of this clock may not change the state of the SCL line, if another device clock is still within its low period. The SCL line is held low by the device with the longest low period. Devices with shorter low periods enter a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start counting off their high periods. The first device to complete its high period will pull the SCL line low. The SCL line high time is determined by the device with the shortest high period (Figure 5).

Arbitration
Arbitration takes place on the SDA line while the SCL line is high. The master which transmits a high when the other master transmits a low loses arbitration (Figure 4) and turns off its data output stage. A master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. When the master devices are addressing the same device, arbitration continues into the data.

FIGURE 4:

MULTI-MASTER ARBITRATION
Transmitter 1 Loses Arbitration Data 1 = SDA

DATA 1

DATA 2

SDA

SDL S

FIGURE 5:

CLOCK SYNCHRONIZATION
Wait State Start Counting High Period

CLK1 Counter Reset

CLK2

SCL

© 1997 Microchip Technology Inc.

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IMPLEMENTATION IN THE PIC16CXXX
This Application Note uses the PIC16CXXX in a Multi-Master I2C environment. The PIC16CXXX acts as both a Master and a Slave on the bus. The transmit routine scans the keypad, debounces the keypresses, and transmits their encoded value in Master mode over the I2C bus to slave address A6. Before transmitting, the status of the Synchronous Serial Port (SSP) is checked. No data is sent until the SSP status register indicates that a Stop bit was received. If the transmission causes any errors, the error code will be displayed on the LEDs, and transmission will again be attempted. Data received in Slave mode at address A2 from the bus is displayed on the LEDs. Slave reception is interrupt driven. When a complete word is received with the proper address, the processor is interrupted, and the program verifies that an SSP interrupt was received. Once it has been verified that the interrupt was caused by the SSP module, and that the buffer is full, the data word is read and output to the LEDs.

Hardware
The demonstration hardware consists of a keypad multiplexed with eight LEDs on PORTB and connections to the I2C bus through the RC3/SCL and RC4/SDA pins (Figure 6).

Software
The software transmits in Master mode and receives data in Slave mode.

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FIGURE 6: HARDWARE
+5V

C9 8.1

11 32 1 13 14 2 3 4 5 6 7 8 9 10 15 16 17

MCLR 4 MHz

I2C

BUS

SCL SDA

18 23 24

VDD VSS MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RA0 RA1 RA2 RA3 RA4 RA4 RE0 RE1 RE2 RC0 RC1 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO

U1

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RC7 RC6 VSS VSS

40 39 38 37 36 35 34 33 30 29 28 23 22 21 20 19 26 25 12 31

PIC16CXXX

C D E F

3 6 9 B

2 5 8 0

3 4 7 A

8x470

© 1997 Microchip Technology Inc.

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Please check the Microchip BBS for the latest version of the source code. Microchip's Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required).

APPENDIX A: IICMULT.ASM
MPASM 01.40 Released IICMULT.ASM 1-16-1997 17:01:20 PAGE 1

LOC OBJECT CODE VALUE

LINE SOURCE TEXT

00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028 00000029 0000002A 0000002B 0000002C 0000002D 0000002E 0000002F 00000030 00000031

00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00001 00002 00238 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051

TITLE " Demonstration of I2C MultiMaster mode" ; LIST P=16C64 ERRORLEVEL -302 ; ;************************************************************************ ;** Two wire/I2C Bus MultiMaster sample routines for Microchip's ;** PIC16C64 8-bit CMOS single chip microcomputer ;** Revised Version (3/06/94). ; Program: IICMULT.ASM ; Revision Date: ; 1-15-97 Compatibility with MPASMWIN 1.40 ; ;** ;** Part used = PIC16C64 ;**Note: 1)All timings are based on a reference crystal frequency of ;** 4MHz which is equivalent to an instruction cycle time of 1 usec. ;** 2) Address and literal values are read in decimal unless ;** otherwise specified. ;************************************************************************ ; ;-----------------------------------------------------------------------; File Register Assignment ;-----------------------------------------------------------------------; include LIST ;P16C64.INC Standard Header File, Version 1.01 Microchip Technology LIST ; FLAG EQU 20h ; Common flag bits register EEPROM EQU 21h ; Bit buffer ERCODE EQU 22h ; Error code (to indicate bus status) ADDR EQU 23h ; Address register DATAI EQU 24h ; Stored data input register DATAO EQU 25h ; Stored data output register SLAVE EQU 26h ; Device address (1010xxx0) TXBUF EQU 27h ; TX buffer RXBUF EQU 28h ; RX buffer COUNT EQU 29h ; Bit counter TEMP EQU 2Ah ; Temporary storage ROW EQU 2Bh ; Keypad row NEW_KEY EQU 2Ch ; Storage for latest key OLD_KEY EQU 2Dh ; Storage for last key pressed DISPVAL EQU 2Eh ; Value displayed on LEDs TEMP1 EQU 2Fh ; Scratchpad register TEMP_W EQU 30h ; Storage for W register TEMP_STAT EQU 31h ; Storage for STATUS register ; ;-----------------------------------------------------------------------; Bit Assignments ;-----------------------------------------------------------------------; FLAG Bits

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00000000 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 ERR_1 EQU 0 ; Error flag

; EEPROM Bits DI DO EQU EQU 7 6 ; EEPROM input ; EEPROM output

00000007 00000006

; I2C Device Bits SDA SCL EQU EQU 4 3 ; RB7, data in/out ; RB6, serial clock

00000004 00000003

;End of files/bits equate ORG goto ORG goto ORG starting clrf clrf clrf movlw movwf movlw movwf bsf clrf movlw movwf movlw movwf bsf bsf bcf bcf movlw movwf KbdWait clrf call call bcf movf andlw btfsc goto movwf movlw movwf bsf CheckAgain btfsc goto btfsc goto Goxmit bcf bcf call btfss TEMP SetupDelay ScanKbd STATUS,RP0 NEW_KEY,W 0FFh STATUS,Z KbdWait DATAO B'10100110' SLAVE STATUS,RP0 SSPSTAT,4 Goxmit SSPSTAT,3 CheckAgain STATUS,RP0 INTCON,7 WRBYTE FLAG,ERR_1 DISPVAL FLAG PORTC 08h ROW B'00111110' SSPCON STATUS,RP0 TRISB B'00001000' PIE1 b'10100010' SSPADD TRISC, 3 TRISC, 4 STATUS,RP0 PIR1,3 B'11000000' INTCON ; Blank out LEDs ; Clear error register ; Set SDA, SCL low when not tri-stated ; ; ; ; ; ; Set initial row to be strobed I2C 7 bit slave mode with master mode enabled Select Bank1 Set PORT_B to all outputs Enable SSP interrupt 00h starting 04h service_int 10h ; Reset Vector

0000 0000 2810 0004 0004 28EB 0010 0010 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 002F 0030 0031 0032 0033 0033 0034 0035 0036

; Interrupt Vector

; Begining of Program space

01AE 01A0 0187 3008 00AB 303E 0094 1683 0186 3008 008C 30A2 0093 1587 1607 1283 118C 30C0 008B

; Slave address ; ; ; ; ; Set SCL high Set SDA high Select Bank0 Clear SSP interrupt flag Enable interrupts

01AA 216B 2102 1283 082C 39FF 1903 2823 00A5 30A6 00A6 1683 1A14 2833 1994 282F 1283 138B 203F 1C20

; Check for key pressed ; Get latest key ; Key pressed? ; No, go check again ; Yes, output it on I2C bus ; Address of device being addressed

;If STOP bit received last... ; OK to transmit ;If START bit recieved last... ; wait for STOP bit

; Disable interrupts ; Output byte ; Check for error

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0037 0038 0039 003A 003B 003C 003D 003D 003E 283D 0822 0086 00AE 1020 282F 178B 2823 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 goto movf movwf movwf bcf goto Checkout bsf goto INTCON,7 KbdWait ; Enable interrupts Checkout ERCODE,W PORTB DISPVAL FLAG,ERR_1 CheckAgain ; No error, go on ; Get error code ; Put error code on LEDs ; Clear error flag

003F 003F 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049

1283 0826 00A7 20BF 2071 1283 0825 00A7 2071 20CD 0008

;-----------------------------------------------------------------------; BYTE-WRITE, write one byte to I2C (Master Mode) ;-----------------------------------------------------------------------; Input : DATAO = data to be written ; ADDR = destination address ; SLAVE = device address (1010xxx0) ; Output : Data written to EEPROM device ;-----------------------------------------------------------------------; WRBYTE bcf STATUS,RP0 movf SLAVE,W ; Send SLAVE address movwf TXBUF ; to TX buffer call BSTART ; Generate START bit call TX ; Output SLAVE data address bcf STATUS,RP0 movf DATAO,W ; Move DATA movwf TXBUF ; into transmit buffer call TX ; Output DATA and detect acknowledgement call BSTOP ; Generate STOP bit return ;-----------------------------------------------------------------------; BYTE-READ, read one byte from I2C (Master Mode) ;-----------------------------------------------------------------------; Input : ADDR = source address ; SLAVE = device address (1010xxx0) ; Output : DATAI = data read from serial EEPROM ;-----------------------------------------------------------------------RDBYTE bcf movf movwf call call bcf movf movwf call call bcf movf movwf bsf call call call bcf movf movwf return STATUS,RP0 SLAVE,W TXBUF BSTART TX STATUS,RP0 ADDR,W TXBUF TX BSTART STATUS,RP0 SLAVE,W TXBUF TXBUF,0 TX RX BSTOP STATUS,RP0 RXBUF,W DATAI ; Move SLAVE address ; into buffer (R/W = 0) ; Generate START bit ; Output SLAVE address. Check ACK. ; Put slave data address into ; Xmit buffer ; Output WORD address. Check ACK. ; START READ ; ; ; ; ; Specify READ mode (R/W = 1) Output SLAVE address READ in data and acknowledge Generate STOP bit

004A 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 005A 005B 005C 005D 005E

1283 0826 00A7 20BF 2071 1283 0823 00A7 2071 20BF 1283 0826 00A7 1427 2071 205F 20CD 1283 0828 00A4 0008

; Save data from buffer ; to DATAI file.

;-----------------------------------------------------------------------; RECEIVE eight data bits subroutine ;------------------------------------------------------------------------

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00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 ; Input : None ; Output : RXBUF = 8-bit data received ;-----------------------------------------------------------------------RX bcf movlw movwf clrf ; RXLP rlf btfss bcf btfsc bsf call bcf btfsc bsf decfsz goto bsf call retlw RXBUF, F 3,0 RXBUF,0 3,0 RXBUF,0 BITIN STATUS,RP0 EEPROM,DI RXBUF,0 COUNT, F RXLP EEPROM,DO BITOUT 0 ; Shift data to buffer ; carry ---> f(0) STATUS,RP0 .8 COUNT RXBUF ; 8 bits of data

005F 005F 0060 0061 0062 0063 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070

1283 3008 00A9 01A8

0DA8 1C03 1028 1803 1428 2087 1283 1BA1 1428 0BA9 2863 1721 209E 3400

; Input bit =1 ; 8 bits? ; Set acknowledge bit = 1 ; to STOP further input

;-----------------------------------------------------------------------; TRANSMIT 8 data bits subroutine ;-----------------------------------------------------------------------; Input : TXBUF ; Output : Data X'mitted to EEPROM device ;-----------------------------------------------------------------------TX bcf movlw movwf ; TXLP bcf btfsc bsf call bcf rlf btfss bcf btfsc bsf decfsz goto call bcf movlw btfsc call bcf retlw EEPROM,DO TXBUF,7 EEPROM,DO BITOUT STATUS,RP0 TXBUF, F 3,0 TXBUF,0 3,0 TXBUF,0 COUNT, F TXLP BITIN STATUS,RP0 3 EEPROM,DI ERR STATUS,RP0 0 ; ; ; ; ; ; ; ; Shift data bit out. If shifted bit = 0, data bit = 0 Otherwise data bit = 1 Serial data out Rotate TXBUF left f(6) ---> f(7) f(7) ---> carry carry ---> f(0) STATUS,RP0 .8 COUNT

0071 0071 1283 0072 3008 0073 00A9 0074 0074 0075 0076 0077 0078 0079 007A 007B 007C 007D 007E 007F 0080 0081 0082 0083 0084 0085 0086

1321 1BA7 1721 209E 1283 0DA7 1C03 1027 1803 1427 0BA9 2874 2087 1283 3003 1BA1 20DE 1283 3400

; 8 bits done? ; No. ; Read acknowledge bit

; Check for acknowledgement ; No acknowledge from device

;-----------------------------------------------------------------------; Single bit receive from I2C to PIC ;-----------------------------------------------------------------------; Input : None ; Output : Data bit received ;------------------------------------------------------------------------

© 1997 Microchip Technology Inc.

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0087 0087 0088 0089 008A 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0095 0096 0097 0098 0099 009A 009A 009B 009C 009D 1683 1607 1283 13A1 1683 1587 3001 1283 1987 2895 1283 1C20 00A2 1420 1283 1E07 289A 1283 17A1 1683 0000 1187 3400 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 BITIN bsf bsf bcf bcf bsf bsf movlw bcf btfsc goto bcf btfss movwf bsf BIT1 bcf btfss goto bcf bsf ACKOK bsf nop bcf retlw STATUS,RP0 TRISC,SCL 0 ; Delay ; Return SCL to low STATUS,RP0 PORTC,SDA ACKOK STATUS,RP0 EEPROM,DI ; Read SDA pin, for ACK low STATUS,RP0 TRISC,SDA STATUS,RP0 EEPROM,DI STATUS,RP0 TRISC,SCL 1 STATUS,RP0 PORTC,SCL BIT1 STATUS,RP0 FLAG,ERR_1 ERCODE FLAG,ERR_1 ; Set SDA for input

; Clock high

; Skip if SCL

is high

; Remain as first error encountered ; Save error code ; Set error flag

; DI = 1

;-----------------------------------------------------------------------; Single bit data transmit from PIC to I2C ;-----------------------------------------------------------------------; Input : EEPROM register, bit DO ; Output : Bit transmitted over I2C ; Error bits set as necessary ;-----------------------------------------------------------------------BITOUT bcf btfss goto bsf bsf movlw bcf btfsc goto btfss movwf bsf goto ; BIT0 bsf bcf nop nop nop CLK1 bsf bsf movlw bcf btfsc goto bcf btfss movwf STATUS,RP0 TRISC,SCL 1 STATUS,RP0 PORTC,SCL BIT2 STATUS,RP0 FLAG,ERR_1 ERCODE STATUS,RP0 TRISC,SDA ; Output bit 0 ; Delay STATUS,RP0 EEPROM,DO BIT0 STATUS,RP0 TRISC,SDA 2 STATUS,RP0 PORTC,SDA CLK1 FLAG,ERR_1 ERCODE FLAG,ERR_1 CLK1

009E 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AB 00AC 00AD 00AE 00AF 00B0 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7 00B8

1283 1F21 28AB 1683 1607 3002 1283 1A07 28B0 1C20 00A2 1420 28B0

; Output bit 0

; Check for error code 2 ; ; ; ; Remain as first error encountered Save error code Set error flag SDA locked low by device

1683 1207 0000 0000 0000 1683 1587 3001 1283 1987 28BA 1283 1C20 00A2

; Error code 1 ; SCL locked low? ; No. ; Yes. ; Save error code

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00B9 00BA 00BA 00BB 00BC 00BD 00BE 1420 0000 0000 1683 1187 3400 00316 00317 00318 00319 00320 00321 00322 00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 bsf BIT2 nop nop bsf bcf retlw FLAG,ERR_1 ; Set error flag

STATUS,RP0 TRISC,SCL 0

; Return SCL to low

;-----------------------------------------------------------------------; START bit generation routine ;-----------------------------------------------------------------------; input : none ; output : initialize bus communication ;-----------------------------------------------------------------------;Generate START bit (SCL is high while SDA goes from high to low ;transition) and check status of the serial clock. BSTART bsf STATUS,RP0 bsf TRISC,SDA ; Make sure SDA is high bsf TRISC,SCL ; Set clock high movlw 1 ; Ready error status code 1 bcf STATUS,RP0 btfss PORTC,SCL ; Locked? call ERR ; SCL locked low by device, flag error bsf STATUS,RP0 bcf TRISC,SDA ; SDA goes low during SCL high nop ; Timing adjustment, 1.5uS @2MHz nop nop bcf TRISC,SCL ; Start clock train retlw 0 ;-----------------------------------------------------------------------; STOP bit generation routine ;-----------------------------------------------------------------------; Input : None ; Output : Bus communication, STOP condition ;-----------------------------------------------------------------------;Generate STOP bit (SDA goes from low to high during SCL high state) ;and check bus conditions. BSTOP bsf bcf bsf nop nop nop movlw bcf btfss call bsf bsf movlw btfss call bcf retlw STATUS,RP0 TRISC,SDA TRISC,SCL ; Return SDA to low ; Set SCL high

00BF 00BF 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC

1683 1607 1587 3001 1283 1D87 20DE 1683 1207 0000 0000 0000 1187 3400

00CD 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD

1683 1207 1587 0000 0000 0000 3001 1283 1D87 20DE 1683 1607 3004 1E07 20DE 1283 3400

1 STATUS,RP0 PORTC,SCL ERR STATUS,RP0 TRISC,SDA 4 TRISC,SDA ERR STATUS,RP0 0

; Ready error code 1 ; High? ; No, SCL locked low by device ; ; ; ; SDA goes low to high during SCL high Ready error code 4 High? No, SDA bus not release for STOP

;-----------------------------------------------------------------------; Two wire/I2C - CPU communication error status table and subroutine ;-----------------------------------------------------------------------; input : W-reg = error code

© 1997 Microchip Technology Inc.

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00382 00383 00384 00385 00386 00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 00447 ; output : ERCODE = error code ; FLAG(ERR_1) = 1 ; ; code error status mode ; -----------------------------------------------------; 1 : SCL locked low by device (bus is still busy) ; 2 : SDA locked low by device (bus is still busy) ; 3 : No acknowledge from device (no handshake) ; 4 : SDA bus not released for master to generate STOP bit ;-----------------------------------------------------------------------; ;Subroutine to identify the status of the serial clock (SCL) and serial ;(data SDA) condition according to the error status table.Codes ;generated are useful for bus/device diagnosis. ERR bcf btfss movwf bsf retlw STATUS,RP0 FLAG,ERR_1 ERCODE FLAG,ERR_1 0 ; Keep first error reported ; Save error code ; Set error flag

00DE 00DE 00DF 00E0 00E1 00E2

1283 1C20 00A2 1420 3400

;-----------------------------------------------------------------------; DELAY, Provide a 1.54mS delay ;-----------------------------------------------------------------------; Input : None ; Output : None ;-----------------------------------------------------------------------delay bcf clrf dly1 nop nop nop decfsz goto retlw STATUS,RP0 TEMP ;clear last location

00E3 00E3 00E4 00E5 00E5 00E6 00E7 00E8 00E9 00EA

1283 01AA 0000 0000 0000 0BAA 28E5 3400

TEMP, F dly1 0

;reduce count ;loop

;-------------------------------------------------------------------; Interrupt service routine ; Only the SSP interrupt is enabled. This routine will read the I2C ; data and output it on the LEDs. ;-------------------------------------------------------------------service_int bcf movwf swapf movwf bsf btfss goto bcf movf bsf btfss goto bcf movwf movwf IntOut bsf bsf bcf

00EB 00EB 00EC 00ED 00EE 00EF 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FA 00FB 00FC

118C 00B0 0E03 00B1 1683 1C14 28FA 1283 0813 1683 1E94 28FA 1283 0086 00AE 1683 158C 1283

PIR1,3 TEMP_W STATUS,W TEMP_STAT STATUS,RP0 SSPSTAT,0 IntOut STATUS,RP0 SSPBUF,W STATUS,RP0 SSPSTAT,5 IntOut STATUS,RP0 PORTB DISPVAL STATUS,RP0 PIE1,3 STATUS,RP0

; ; ; ;

Clear SSP interrupt Save W register Get STATUS register Save STATUS register

; Check Buffer Full Flag ; No data received, so exit ; Get I2C data ; If Address received last... ; exit without saving it ; Display received data on LEDs

; Re-enable SSP interrupt

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© 1997 Microchip Technology Inc.

AN578
00FD 00FE 00FF 0100 0101 0E31 0083 0EB0 0E30 0009 00448 00449 00450 00451 00452 00453 00454 00455 00456 00457 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 00468 00469 00470 00471 00472 00473 00474 00475 00476 00477 00478 00479 00480 00481 00482 00483 00484 00485 00486 00487 00488 00489 00490 00491 00492 00493 00494 00495 00496 00497 00498 00499 00500 00501 00502 00503 00504 00505 00506 00507 00508 00509 00510 00511 00512 00513 swapf movwf swapf swapf retfie TEMP_STAT,W STATUS TEMP_W,1 TEMP_W,W ; Restore STATUS register

; Restore W register

;-------------------------------------------------------------------; Keyboard scan routine ; This routine scans the keypad connected to PORT_B, and ; returns the pressed key in New_Key. ;-------------------------------------------------------------------ScanKbd bcf clrf movf btfss goto Kbdloop bcf rlf btfss goto movlw movwf Notdone clrf bsf movlw movwf bcf movf movwf movlw andwf btfsc goto clrf iorwf movwf movwf Debounce clrf bsf clrf bcf movf movwf clrf call call clrf bsf movlw movwf bcf movf movwf movf xorwf btfsc goto clrf clrf clrf KBDOUT PORTB STATUS,RP0 TRISB STATUS,RP0 DISPVAL,W PORTB TEMP SetupDelay SetupDelay PORTB STATUS,RP0 0Fh TRISB STATUS,RP0 ROW,W PORTB OLD_KEY,W PORTB,w STATUS,Z KBDOUT PORTB NEW_KEY OLD_KEY PORTB STATUS,RP0 00Fh TRISB STATUS,RP0 ROW,W PORTB 0Fh PORTB,W STATUS,Z KBDOUT PORTB ROW,W NEW_KEY OLD_KEY STATUS,C ROW, F STATUS,C Notdone 010h ROW ; Select next row to strobe STATUS,RP0 NEW_KEY OLD_KEY,w STATUS,Z Debounce ; Clear key register ; If key was pressed last pass through ; goto Debounce

0102 0102 0103 0104 0105 0106 0107 0107 0108 0109 010A 010B 010C 010D 010D 010E 010F 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 011A 011B 011C 011C 011D 011E 011F 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012D 012E 012F 0130 0131 0132 0133

1283 01AC 082D 1D03 291C 1003 0DAB 1C03 290D 3010 00AB 0186 1683 300F 0086 1283 082B 0086 300F 0506 1903 2933 0186 042B 00AC 00AD 0186 1683 0186 1283 082E 0086 01AA 216B 216B 0186 1683 300F 0086 1283 082B 0086 082D 0606 1903 2933 0186 01AC 01AD

; Start over at first row

; Set PORT_B for keypad read

; ; ; ;

Output Row Read colums Mask out rows Check for Key press

; No key pressed, exit ; Key pressed, save it

; Set LEDs

; Delay for key debounce

; Set PORT_B for keypad read

; Output Row ; Compare key with last key pressed

; Key released, clear registers

© 1997 Microchip Technology Inc.

DS00578B-page 13

AN578
0133 0134 0135 0136 0137 0138 0138 0139 013A 013B 013C 013D 013E 013E 013F 0140 0141 0142 0143 0144 0145 0146 0147 0148 0149 0149 014A 014B 014C 014D 014E 014F 0150 0151 0152 0153 0154 0155 0155 0156 0156 0157 0158 0159 015A 015B 015C 015D 015E 015F 0160 0161 0162 0163 0164 0165 0166 0167 0168 0169 016A 082E 0086 1683 0186 1283 300F 052C 00AA 1903 2955 30FF 3E01 0CAA 1C03 293E 00AA 0E2C 390F 1903 2955 00AF 30FF 3E01 0CAF 1C03 2949 00AF 1003 0DAF 0DAF 082F 072A 2156 00AC 0008 00AA 3001 008A 082A 0782 3446 3442 3430 3441 3445 3439 3438 3437 3444 3436 3435 3434 3443 3433 3432 3431 00514 00515 00516 00517 00518 00519 00520 00521 00522 00523 00524 00525 00526 00527 00528 00529 00530 00531 00532 00533 00534 00535 00536 00537 00538 00539 00540 00541 00542 00543 00544 00545 00546 00547 00548 00549 00550 00551 00552 00553 00554 00555 00556 00557 00558 00559 00560 00561 00562 00563 00564 00565 00566 00567 00568 00569 00570 00571 00572 00573 00574 00575 00576 00577 00578 00579 movf movwf bsf clrf bcf KEY_DEC movlw andwf movwf btfsc goto movlw DECL1 addlw rrf btfss goto movwf swapf andlw btfsc goto movwf movlw DECL2 addlw rrf btfss goto movwf bcf rlf rlf movf addwf call movwf DECOUT return DEC_TABL movwf movlw movwf movf addwf retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw retlw TEMP 01h PCLATH TEMP,W PCL, F 'F' 'B' '0' 'A' 'E' '9' '8' '7' 'D' '6' '5' '4' 'C' '3' '2' '1' ; Save key value ; Setup for second page of RAM ; Jump, return with ASCII value 001h TEMP1, F STATUS,C DECL2 TEMP1 STATUS,C TEMP1, F TEMP1, F TEMP1,W TEMP,W DEC_TABL NEW_KEY ; Count row ; Rotate row until it is found 001h TEMP, F STATUS,C DECL1 TEMP NEW_KEY,W 00Fh STATUS,Z DECOUT TEMP1 0FFH ; Count column ; Rotate column until it is found 00Fh NEW_KEY,W TEMP STATUS,Z DECOUT 0FFh ; Get column of key pressed ; If no key pressed, exit ; Initialize the W register DISPVAL,W PORTB STATUS,RP0 TRISB STATUS,RP0 ; Set LEDs

; Get row of key pressed

;If no key pressed, exit

; Move row to upper nibble

; Add column to row value ; Get ASCII value of key

;***************************************************************** ;*This routine is a software delay. * ;*At 4Mhz clock, the loop takes 3uS, so initialize TEMP with * ;*a value of 3 to give 9uS, plus the move etc should result in *

DS00578B-page 14

© 1997 Microchip Technology Inc.

AN578
00580 ;*a total time of > 10uS. * 00581 ;***************************************************************** 00582 00583 SetupDelay 00584 decfsz TEMP, F 00585 goto SetupDelay 00586 return 00587 00588 END

016B 016B 0BAA 016C 296B 016D 0008

MEMORY USAGE MAP ('X' = Used, 0000 0040 0080 00C0 0100 0140 : : : : : : X---X----------XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

'-' = Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXX-XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ----------------

XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: 352 1696

Errors : Warnings : Messages :

0 0 reported, 0 reported,

0 suppressed 29 suppressed

© 1997 Microchip Technology Inc.

DS00578B-page 15

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All rights reserved. © 1997, Microchip Technology Incorporated, USA. 6/97
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

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© 1997 Microchip Technology Inc.