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INTEGRATED CIRCUITS
DATA SHEET
PCF85xxC-2 family 256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
Product specification File under Integrated Circuits, IC12 1997 Feb 13
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.5.1 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION DEVICE SELECTION BLOCK DIAGRAM PINNING Pin description PCF8582C-2 Pin description PCF8594C-2 Pin description PCF8598C-2 I2C-BUS PROTOCOL Bus conditions Data transfer Device addressing Write operations Byte/word write Page write Remark Read operations Remark 9 10 11 12 13 14 15 15.1 15.2 15.2.1 15.2.2 15.3 15.3.1 15.3.2 15.3.3 16 17 18
PCF85xxC-2 family
LIMITING VALUES CHARACTERISTICS I2C-BUS CHARACTERISTICS WRITE CYCLE LIMITS EXTERNAL CLOCK TIMING PACKAGE OUTLINES SOLDERING Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Feb 13
2
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
1 FEATURES
PCF85xxC-2 family
· High reliability by using a redundant storage code · Endurance: 1000000 Erase/Write (E/W) cycles at Tamb = 22 °C · 10 years non-volatile data retention time · Pin and address compatible to: PCF8570, PCF8571, PCF8572 and PCF8581. 2 GENERAL DESCRIPTION
· Low power CMOS: maximum operating current: 2.0 mA (PCF8582C-2) 2.5 mA (PCF8594C-2) 4.0 mA (PCF8598C-2) maximum standby current 10 µA (at 6.0 V), typical 4 µA · Non-volatile storage of: 2 kbits organized as 256 × 8-bit (PCF8582C-2) 4 kbits organized as 512 × 8-bit (PCF8594C-2) 8 kbits organized as 1024 × 8-bit (PCF8598C-2) · Single supply with full operation down to 2.5 V · On-chip voltage multiplier · Serial input/output I2C-bus · Write operations: byte write mode 8-byte page write mode (minimizes total write time per byte) · Read operations: sequential read random read · Internal timer for writing (no external components) · Power-on-reset 3 QUICK REFERENCE DATA SYMBOL VDD IDDR PARAMETER supply voltage supply current read
The PCF85xxC-2 is a family of floating gate Electrically Erasable Programmable Read Only Memories (EEPROMs) with 2, 4 and 8 kbits (256, 512 and 1024 × 8-bit). By using an internal redundant storage code it is fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier. As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Up to eight PCF85xxC-2 devices may be connected to the I2C-bus. Chip select is accomplished by three address inputs (A0, A1 and A2). Timing of the E/W cycle is carried out internally, thus no external components are required. Pin 7 (PTC) must be connected to either VDD or left open-circuit. There is an option of using an external clock for timing the length of an E/W cycle.
CONDITIONS fSCL = 100 kHz VDD = 2.5 V VDD = 6 V - - - - - - - - - -
MIN. 2.5
MAX. 6.0 60 200 0.6 2.0 0.8 2.5 1.0 4.0 3.5 10
UNIT V µA µA mA mA mA mA mA mA µA µA
IDDW
supply current E/W PCF8582C-2 PCF8594C-2 PCF8598C-2
fSCL = 100 kHz VDD = 2.5 V VDD = 6 V VDD = 2.5 V VDD = 6 V VDD = 2.5 V VDD = 6 V VDD = 2.5 V VDD = 6 V
IDD(stb)
standby supply current
1997 Feb 13
3
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
4 ORDERING INFORMATION TYPE NUMBER PCF8582C-2P PCF8594C-2P PCF8598C-2P PCF8582C-2T PCF8594C-2T PCF8598C-2T 5 SO8 SO8 DIP8 plastic dual in-line package; 8 leads (300 mil) PACKAGE NAME DESCRIPTION
PCF85xxC-2 family
VERSION SOT97-1
plastic small outline package; 8 leads (straight); body width 3.9 mm plastic small outline package; 8 leads; body width 7.5 mm
SOT96-1 SOT176-1
DEVICE SELECTION Device selection code DEVICE CODE b7(1) 1 b6 0 b5 1 b4 0 b3 A2 CHIP ENABLE b2 A1 b1 A0 R/W b0 R/W
Table 1
SELECTION Bit Device Note
1. The Most Significant Bit (MSB) `b7' is sent first.
1997 Feb 13
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6
PCF85xxC-2 family
Product specification
Fig.1 Block diagram.
handbook, full pagewidth
1997 Feb 13 BLOCK DIAGRAM
I2C-BUS CONTROL LOGIC BYTE COUNTER SEQUENCER 3 4 EE CONTROL ADDRESS HIGH REGISTER DIVIDER ( 128) BYTE LATCH (8 bytes) ADDRESS POINTER 8 EEPROM
VDD
8
Philips Semiconductors
SCL
6
SDA
5
INPUT FILTER
n
ADDRESS SWITCH
SHIFT REGISTER
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
5
TIMER ( 16) 7 PTC
A2 A1
A0
3 2 1
TEST MODE DECODER
PCF85xxC-2
POWER-ON-RESET
OSCILLATOR
4
MGD927
VSS
The pin numbers in this block diagram refer to the PCF8582C-2. For PCF8594C-2 and PCF8598C-2 please see Chapter 7.
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
7 7.1 PINNING Pin description PCF8582C-2 PIN 1 2 3 4 5 6 7 8 DESCRIPTION address input 0 address input 1 address input 2 negative supply voltage serial data input/output (I2C-bus) serial clock input (I2C-bus) programming time control output positive supply voltage
A2 3 VSS 4
handbook, halfpage
PCF85xxC-2 family
SYMBOL A0 A1 A2 VSS SDA SCL PTC VDD 7.2
A0
1
8 V DD 7 PTC SCL SDA
A1 2
PCF8582C-2
6 5
MGD928
Fig.2 Pin configuration PCF8582C-2.
Pin description PCF8594C-2 PIN 1 2 3 4 5 6 7 8 DESCRIPTION write-protection input address input 1 address input 2 negative supply voltage serial data input/output (I2C-bus) serial clock input (I2C-bus) programming time control output positive supply voltage
A2 3 VSS 4
MGL001
SYMBOL WP A1 A2 VSS SDA SCL PTC VDD
handbook, 2 columns
WP
1
8 V DD 7 PTC SCL SDA
A1 2
PCF8594C-2
6 5
Fig.3 Pin configuration PCF8594C-2.
7.3
Pin description PCF8598C-2 PIN 1 2 3 4 5 6 7 8 DESCRIPTION write-protection input not connected address input 2 negative supply voltage serial data input/output (I2C-bus) serial clock input (I2C-bus) programming time control output positive supply voltage
n.c. 2
handbook, halfpage
SYMBOL WP n.c. A2 VSS SDA SCL PTC VDD
WP
1
8 V DD 7 PTC SCL SDA
PCF8598C-2
A2 3 VSS 4
MGL002
6 5
Fig.4 Pin configuration PCF8598C-2.
1997 Feb 13
6
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
8 I2C-BUS PROTOCOL
PCF85xxC-2 family
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The serial bus consists of two bidirectional lines: one for data signals (SDA), and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: · Data transfer may be initiated only when the bus is not busy. · During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. 8.1 Bus conditions
Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit. Within the I2C-bus specifications a low-speed mode (2 kHz clock rate) and a high speed mode (100 kHz clock rate) are defined. The PCF85xxC-2 operates in both modes. By definition a device that sends a signal is called a `transmitter', and the device which receives the signal is called a `receiver'. The device which controls the signal is called the `master'. The devices that are controlled by the master are called `slaves'. Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master generation of the STOP condition.
The following bus conditions have been defined: · Bus not busy: both data and clock lines remain HIGH. · Start data transfer: a change in the state of the data line, from HIGH-to-LOW, while the clock is HIGH, defines the START condition. · Stop data transfer: a change in the state of the data line, from LOW-to-HIGH, while the clock is HIGH, defines the STOP condition. · Data valid: the state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. 8.2 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes, transferred between the START and STOP conditions is limited to 7 bytes in the E/W mode and 8 bytes in the page E/W mode.
1997 Feb 13
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Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
8.3 Device addressing
PCF85xxC-2 family
Following a START condition the bus master must output the address of the slave it is accessing. The 4 MSBs of the slave address are the device type identifier (see Fig.5). For the PCF85xxC-2 this is fixed to `1010'. The next three significant bits address a particular device or memory page (page = 256 bytes of memory). A system could have up to eight PCF8582C-2 (or four PCF8594C-2 containing two memory pages each or two PCF8598C-2 containing four memory pages each, respectively) devices on the bus. The eight addresses are defined by the state of the A0, A1 and A2 inputs. The last bit of the slave address defines the operation to be performed. When set to logic 1 a read operation is selected. Address bits must be connected to either VDD or VSS.
After this STOP condition the E/W cycle starts and the bus is free for another transmission. Its duration is 10 ms per byte. During the E/W cycle the slave receiver does not send an acknowledge bit if addressed via the I2C-bus. 8.4.2 PAGE WRITE
The PCF85xxC-2 is capable of an eight-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transmit eight data bytes within one transmission. After receipt of each byte the PCF85xxC-2 will respond with an acknowledge. The typical E/W time in this mode is 9 × 3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms and sequential writing of these 8 bytes another typical 28 ms. After the receipt of each data byte the three low order bits of the word address are internally incremented. The high order five bits of the address remain unchanged. The slave acknowledges the reception of each data byte with an ACK. The I2C-bus data transfer is terminated by the master after the 8th byte with a STOP condition. If the master transmits more than eight bytes prior to generating the STOP condition, no acknowledge will be given on the ninth (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles. 8.4.3 REMARK
handbook, halfpage
1
0
1
0
A2
A1
A0 R/W
MBC793
Fig.5 Slave address.
8.4 8.4.1
Write operations BYTE/WORD WRITE
For a write operation the PCF85xxC-2 requires a second address field. This address field is a word address providing access to the 256 words of memory. Upon receipt of the word address the PCF85xxC-2 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master can now terminate the transfer by generating a STOP condition or transmit up to six more bytes of data and then terminate by generating a STOP condition.
A write to the EEPROM is always performed if the pin WP is LOW (not on PCF8582C-2). If WP is HIGH, then the upper half of the EEPROM is write-protected and no acknowledge will be given by the PCF85xxC-2 when one of the upper 256 EEPROM bytes (PCF8594C-2) or 512 EEPROM bytes (PCF8598C-2) is addressed. However, an acknowledge will be given after the slave address and the word address.
1997 Feb 13
8
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
PCF85xxC-2 family
handbook, full pagewidth
acknowledge from slave
acknowledge from slave
acknowledge from slave
acknowledge from slave
S
SLAVE ADDRESS
0 A
WORD ADDRESS
A
DATA
A
DATA
A
P
R/W auto increment word address auto increment word address
MBA701
Fig.6 Auto increment memory word address; two byte write.
handbook, full pagewidth
acknowledge from slave
acknowledge from slave
acknowledge from slave
acknowledge from slave
S
SLAVE ADDRESS
0 A
WORD ADDRESS
A
DATA N
A
DATA N + 1
A
R/W auto increment word address auto increment word address
acknowledge from slave
DATA N + 7
1
A P
last byte
MBA702
auto increment word address
Fig.7 Page write operation; eight bytes.
1997 Feb 13
9
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
8.5 Read operations 8.5.1 REMARK
PCF85xxC-2 family
Read operations are initiated in the same manner as write operations with the exception that the LSB of the slave address is set to logic 1. There are three basic read operations; current address read, random read and sequential read sequential read.
The lower 8 bits of the word address are incremented after each transmission of a data byte (read or write). The MSB of the word address, which is defined in the slave address, is not changed when the word address count overflows. Thus, the word address overflows from 255 to 0 and from 511 to 256.
handbook, full pagewidth
acknowledge from slave
acknowledge from slave
acknowledge from slave
acknowledge from master
S
SLAVE ADDRESS
0 A
WORD ADDRESS
A
S
SLAVE ADDRESS
1 A
DATA
A
R/W
at this moment master transmitter becomes master receiver and EEPROM slave receiver becomes slave transmitter
R/W
n bytes auto increment word address
no acknowledge from master
DATA
1
P
last byte
MBA703 - 1
auto increment word address
Fig.8 Master reads PCF85xxC-2 slave after setting word address (write word address; read data).
handbook, full pagewidth
acknowledge from slave
acknowledge from master
no acknowledge from master
S
SLAVE ADDRESS
1 A
DATA n bytes
A
DATA last bytes
1
P
R/W
auto increment word address
auto increment word address
MBA704 - 1
Fig.9 Master reads PCF85xxC-2 immediately after first byte (read mode).
1997 Feb 13
10
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IO Tstg Tamb PARAMETER supply voltage input voltage on any input pin input current on any input pin output current storage temperature operating ambient temperature Zi > 500 CONDITIONS
PCF85xxC-2 family
MIN. -0.3 - - -65 -40
MAX. +6.5 1 10 +150 +85 V V
UNIT
VSS - 0.8 +6.5
mA mA °C °C
10 CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = -40 to +85 °C; unless otherwise specified. SYMBOL Supplies VDD IDDR supply voltage supply current read fSCL = 100 kHz VDD = 2.5 V VDD = 6.0 V IDDW supply current E/W PCF8582C-2 PCF8594C-2 PCF8598C-2 IDD(stb) standby supply current fSCL = 100 kHz VDD = 2.5 V VDD = 6.0 V VDD = 2.5 V VDD = 6.0 V VDD = 2.5 V VDD = 6.0 V VDD = 2.5 V VDD = 6.0 V PTC output (pin 7) VIL VIH VIL VIH ILI fSCL CI LOW level input voltage HIGH level input voltage -0.8 0.9VDD -0.8 0.7VDD VI = VDD or VSS VI = VSS - 0 - 0.1VDD V VDD + 0.8 V 0.3VDD +6.5 ±1 100 7 V V µA kHz pF - - - - - - - - 0.6 2.0 0.8 2.5 1.0 4.0 3.5 10 mA mA mA mA mA mA µA µA - - 60 200 µA µA 2.5 6.0 V PARAMETER CONDITIONS MIN. MAX. UNIT
SCL input (pin 6) LOW level input voltage HIGH level input voltage input leakage current clock input frequency input capacitance
1997 Feb 13
11
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
SYMBOL SDA input/output (pin 5) VIL VIH VOL ILO CI tS LOW level input voltage HIGH level input voltage LOW level output voltage output leakage current input capacitance IOL = 3 mA; VDD(min) VOH = VDD VI = VSS Tamb = 55 °C PARAMETER CONDITIONS
PCF85xxC-2 family
MIN. -0.8 0.7VDD - - -
MAX.
UNIT
0.3VDD +6.5 0.4 1 7 -
V V V µA pF
Data retention time data retention time 10 years
11 I2C-BUS CHARACTERISTICS All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing from VSS to VDD; see Fig.10. SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT clock frequency bus free time between a STOP and START condition START condition hold time after which first clock pulse is generated LOW level clock period HIGH level clock period set-up time for STARt condition data hold time for bus compatible masters for bus devices tSU;DAT tr tf tSU;STO Note 1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter. data set-up time SDA and SCL rise time SDA and SCL fall time set-up time for STOP condition note 1 5 0 250 - - 4.0 - - - 1 300 - µs ns ns µs ns µs repeated start PARAMETER CONDITIONS 0 4.7 4.0 4.7 4.0 4.7 MIN. - - - - - MAX. 100 UNIT kHz µs µs µs µs µs
1997 Feb 13
12
PCF85xxC-2 family
Product specification
Fig.10 Timing requirements for the I2C-bus.
handbook, full pagewidth
1997 Feb 13
t LOW t HD;STA tf
Philips Semiconductors
SDA
t BUF
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
13
S
t HIGH t SU;DAT t SU;STA
SCL
P
S
P
t HD;STA tr t HD;DAT
MBA705
t SU;STO
P = STOP condition; S = START condition.
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
PCF85xxC-2 family
12 WRITE CYCLE LIMITS Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD. SYMBOL E/W cycle timing tE/W Endurance NE/W E/W cycle per byte Tamb = -40 to +85 °C Tamb = 22 °C 13 EXTERNAL CLOCK TIMING 100000 - - - cycles cycles 1000000 - E/W cycle time internal oscillator external clock - 4 7 - - 10 ms ms PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
handbook, full pagewidth
td
tr
t HIGH
tf
t LOW
PTC
1
2
257
SDA
SCL STOP
MBA697
Fig.11 One byte E/W cycle.
handbook, full pagewidth
td
tr
t HIGH
tf
t LOW n x 256 + 1
PTC
1
2
SDA
SCL STOP
MBA698
Fig.12 n bytes E/W cycle (n = 2 to 7).
1997 Feb 13
14
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
PCF85xxC-2 family
td
handbook, full pagewidth
tr
t HIGH
tf
t LOW
PTC
1
2
1153
SDA
SCL STOP
MBA699
Fig.13 Page mode.
handbook, full pagewidth SLAVE ADDRESS
WORD ADDRESS A DATA A DATA A P (1)
I C-bus S
2
0A
HIGH PTC LOW
undefined 1 1 1 td 0 2 2 2 257 513 1153
undefined clock (2) clock (3) clock (4)
MBA700
negative edge SCL 8-bit
(1) If an external clock is chosen, this information is latched internally by setting pin 7 (PTC) LOW after transmission of the eighth bits of the word address (negative edge of SCL). Thus the state of pin 7 may be previously undefined. Leaving pin 7 LOW causes a higher standby current. (2) 1-byte programming. (3) 2-byte programming. (4) One page (8 bytes) programming.
Fig.14 External clock.
1997 Feb 13
15
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
14 PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil)
PCF85xxC-2 family
SOT97-1
D seating plane
ME
A2
A
L
A1
c Z e b1 w M (e 1) b2 5 MH
b 8
pin 1 index E
1
4
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001AN EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Feb 13
16
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
PCF85xxC-2 family
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A X
c y HE v M A
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 w M L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 0.24 0.23 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.0098 0.057 0.069 0.0039 0.049
0.019 0.0098 0.014 0.0075
0.039 0.028 0.041 0.016 0.024
0.028 0.004 0.012
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Feb 13
17
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
PCF85xxC-2 family
SO8: plastic small outline package; 8 leads; body width 7.5 mm
SOT176-1
D
E
A X
c y HE v M A
Z 8 5
Q A2 A1 pin 1 index Lp L 1 e bp 4 w M detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 7.65 7.45 0.30 0.29 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.45 0.057 Lp 1.1 0.45 0.043 0.018 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 2.0 1.8 0.079 0.071
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT176-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 91-08-13 95-02-25
1997 Feb 13
18
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
15 SOLDERING 15.1 Introduction
PCF85xxC-2 family
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 15.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 15.3.2 WAVE SOLDERING
Wave soldering techniques can be used for all SO packages if the following conditions are observed: · A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. · The longitudinal axis of the package footprint must be parallel to the solder flow. · The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3.3 REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 15.3 15.3.1 SO REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
1997 Feb 13
19
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF85xxC-2 family
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Feb 13
20
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
NOTES
PCF85xxC-2 family
1997 Feb 13
21
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
NOTES
PCF85xxC-2 family
1997 Feb 13
22
Philips Semiconductors
Product specification
256 to 1024 × 8-bit CMOS EEPROMs with I2C-bus interface
NOTES
PCF85xxC-2 family
1997 Feb 13
23
Philips Semiconductors a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
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Printed in The Netherlands
417067/1200/01/pp24
Date of release: 1997 Feb 13
Document order number:
9397 750 01773