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MC68HC11A8
HCMOS Single-Chip Microcontroller

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

© MOTOROLA, INC. 1996

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

© MOTOROLA, INC. 1996

TABLE OF CONTENTS Paragraph Number Title
1 INTRODUCTION 1.1 1.1.1 1.1.2 1.2 1.3 1.4 Features .................................................................................................... 1-1 Hardware Features ............................................................................ 1-1 Software Features ............................................................................. 1-1 General Description ................................................................................... 1-1 Programmer's Model ................................................................................. 1-2 Summary of M68HC11 Family .................................................................. 1-3 2 SIGNAL DESCRIPTIONS AND OPERATING MODES 2.1 Signal Pin Descriptions ............................................................................. 2-1 2.1.1 Input Power (VDD) and Ground (VSS) ................................................ 2-1 2.1.2 Reset (RESET) .................................................................................. 2-1 2.1.3 Crystal Driver and External Clock Input (XTAL, EXTAL) ................... 2-1 2.1.4 E Clock Output (E) ............................................................................ 2-3 2.1.5 Interrupt Request (IRQ) ..................................................................... 2-3 2.1.6 Non-Maskable Interrupt (XIRQ) ......................................................... 2-3 2.1.7 Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/ LIR, MODB/VSTBY) 2-3 2.1.8 A/D Converter Reference Voltages (VRL, VRH) ................................. 2-4 2.1.9 Strobe B and Read/Write (STRB/R/W) ............................................. 2-4 2.1.10 Strobe A and Address Strobe (STRA/AS) ......................................... 2-4 2.1.11 Port Signals ....................................................................................... 2-4 2.1.11.1 Port A ........................................................................................ 2-5 2.1.11.2 Port B ........................................................................................ 2-5 2.1.11.3 Port C ........................................................................................ 2-5 2.1.11.4 Port D ........................................................................................ 2-5 2.1.11.5 Port E ........................................................................................ 2-6 2.2 Operating Modes ....................................................................................... 2-6 2.2.1 Single-Chip Operating Mode ............................................................. 2-6 2.2.2 Expanded Multiplexed Operating Mode ............................................ 2-6 2.2.3 Special Bootstrap Operating Mode ................................................... 2-8 2.2.4 Additional Boot Loader Program Options ........................................ 2-10 2.2.5 Special Test Operating Mode .......................................................... 2-10 3 ON-CHIP MEMORY 3.1 3.2 3.3 3.4 3.5 3.5.1 Memory Maps ............................................................................................ 3-1 RAM and I/O Mapping Register (INIT) ...................................................... 3-4 ROM .......................................................................................................... 3-5 RAM .......................................................................................................... 3-5 EEPROM ................................................................................................... 3-5 EEPROM Programming Control Register (PPROG) ......................... 3-6
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Page Number

MC68HC11A8 TECHNICAL DATA

3.5.2 3.5.2.1 3.5.2.2 3.5.2.3 3.5.2.4 3.5.2.5 3.5.3 3.5.3.1 3.5.3.2

Programming/Erasing Internal EEPROM .......................................... 3-7 Read .......................................................................................... 3-7 Programming ............................................................................. 3-7 Bulk Erase ................................................................................. 3-8 Row Erase ................................................................................. 3-8 Byte Erase ................................................................................. 3-9 System Configuration Register (CONFIG) ........................................ 3-9 Programming and Erasure of the CONFIG Register ............... 3-10 Operation of the Configuration Mechanism ............................. 3-12 4 PARALLEL I/O

4.1 4.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.5

General-Purpose I/O (Ports C and D) ....................................................... 4-1 Fixed Direction I/O (Ports A, B, and E) ...................................................... 4-1 Simple Strobed I/O .................................................................................... 4-2 Strobed Input Port C .......................................................................... 4-2 Strobed Output Port B ....................................................................... 4-2 Full Handshake I/O .................................................................................... 4-2 Input Handshake Protocol ................................................................. 4-3 Output Handshake Protocol .............................................................. 4-3 Parallel I/O Control Register (PIOC) ......................................................... 4-4 5 SERIAL COMMUNICATIONS INTERFACE

5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.8.1 5.8.2 5.8.3 5.8.4 5.8.5

Overview and Features ............................................................................. 5-1 SCI Two-Wire System Features ........................................................ 5-1 SCI Receiver Features ...................................................................... 5-1 SCI Transmitter Features .................................................................. 5-1 Data Format .............................................................................................. 5-1 Wake-Up Feature ...................................................................................... 5-2 Receive Data (RxD) .................................................................................. 5-2 Start Bit Detection ..................................................................................... 5-3 Transmit Data (TxD) .................................................................................. 5-5 Functional Description ............................................................................... 5-5 SCI Registers ............................................................................................ 5-5 Serial Communications Data Register (SCDR) ................................. 5-6 Serial Communications Control Register 1 (SCCR1) ........................ 5-8 Serial Communications Control Register 2 (SCCR2) ........................ 5-8 Serial Communications Status Register (SCSR) ............................ 5-10 Baud Rate Register (BAUD) ............................................................ 5-11 6 SERIAL PERIPHERAL INTERFACE

6.1 6.2 6.2.1 6.2.2 6.2.3

Overview and Features ............................................................................. 6-1 SPI Signal Descriptions ............................................................................. 6-1 Master In Slave Out (MISO) .............................................................. 6-1 Master Out Slave In (MOSI) .............................................................. 6-1 Serial Clock (SCK) ............................................................................ 6-2
MC68HC11A8 TECHNICAL DATA

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6.2.4 6.3 6.4 6.4.1 6.4.2 6.4.3

Slave Select (SS) .............................................................................. 6-2 Functional Description ............................................................................... 6-3 SPI Registers ............................................................................................ 6-4 Serial Peripheral Control Register (SPCR) ....................................... 6-4 Serial Peripheral Status Register (SPSR) ......................................... 6-5 Serial Peripheral Data l/O Register (SPDR) ...................................... 6-6 7 ANALOG-TO-DIGITAL CONVERTER

7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8

Conversion Process .................................................................................. 7-1 Channel Assignments ............................................................................... 7-1 Single-Channel Operation ......................................................................... 7-2 Multiple-Channel Operation ....................................................................... 7-2 Operation in STOP and WAIT Modes ....................................................... 7-3 A/D Control/Status Register (ADCTL) ....................................................... 7-3 A/D Result Registers 1, 2, 3, and 4 (ADR1, ADR2, ADR3, and ADR4) .... 7-5 A/D Power-Up and Clock Select ............................................................... 7-5 8 PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR

8.1 Programmable Timer ................................................................................. 8-1 8.1.1 Counter .............................................................................................. 8-1 8.1.2 Input Capture ..................................................................................... 8-1 8.1.3 Output Compare ................................................................................ 8-2 8.1.4 Output Compare 1 I/O Pin Control .................................................... 8-2 8.1.5 Timer Compare Force Register (CFORC) ......................................... 8-3 8.1.6 Output Compare 1 Mask Register (OC1M) ....................................... 8-3 8.1.7 Output Compare 1 Data Register (OC1D) ........................................ 8-4 8.1.8 Timer Control Register 1 (TCTL1) ..................................................... 8-4 8.1.9 Timer Control Register 2 (TCTL2) ..................................................... 8-5 8.1.10 Timer Interrupt Mask Register 1 (TMSK1) ........................................ 8-5 8.1.11 Timer Interrupt Flag Register 1 (TFLG1) ........................................... 8-5 8.1.12 Timer Interrupt Mask Register 2 (TMSK2) ........................................ 8-6 8.1.13 Timer Interrupt Flag Register 2 (TFLG2) ........................................... 8-7 8.2 Real-Time Interrupt ................................................................................... 8-8 8.3 Pulse Accumulator .................................................................................... 8-8 8.3.1 Pulse Accumulator Control Register (PACTL) .................................. 8-8 9 RESETS, INTERRUPTS, AND LOW POWER MODES 9.1 Resets ....................................................................................................... 9-1 9.1.1 External RESET Pin .......................................................................... 9-1 9.1.2 Power-On Reset ................................................................................ 9-1 9.1.2.1 CPU ........................................................................................... 9-2 9.1.2.2 Memory Map ............................................................................. 9-3 9.1.2.3 Parallel l/O ................................................................................. 9-3 9.1.2.4 Timer ......................................................................................... 9-3 9.1.2.5 Real-Time Interrupt ................................................................... 9-4
MC68HC11A8 TECHNICAL DATA MOTOROLA v

9.1.2.6 Pulse Accumulator .................................................................... 9-4 9.1.2.7 COP .......................................................................................... 9-4 9.1.2.8 SCI Serial l/O ............................................................................ 9-4 9.1.2.9 SPI Serial l/O ............................................................................. 9-4 9.1.2.10 A/D Converter ........................................................................... 9-4 9.1.2.11 System ...................................................................................... 9-4 9.1.3 Computer Operating Properly (COP) Reset ...................................... 9-5 9.1.4 Clock Monitor Reset .......................................................................... 9-6 9.1.5 Configuration Options Register (OPTION) ........................................ 9-6 9.2 Interrupts ................................................................................................... 9-7 9.2.1 Software Interrupt (SWI) .................................................................... 9-9 9.2.2 Illegal Opcode Trap ........................................................................... 9-9 9.2.3 Interrupt Mask Bits in Condition Code Register ................................ 9-9 9.2.4 Priority Structure .............................................................................. 9-10 9.2.5 Highest Priority I Interrupt Register (HPRIO) .................................. 9-10 9.3 Low-Power Modes ................................................................................... 9-17 9.3.1 WAIT Instruction .............................................................................. 9-17 9.3.2 STOP Instruction ............................................................................. 9-17 10 CPU, ADDRESSING MODES, AND INSTRUCTION SET 10.1 CPU Registers ......................................................................................... 10-1 10.1.1 Accumulators A and B ..................................................................... 10-1 10.1.2 Index Register X (IX) ....................................................................... 10-1 10.1.3 Index Register Y (IY) ....................................................................... 10-2 10.1.4 Stack Pointer (SP) ........................................................................... 10-2 10.1.5 Program Counter (PC) .................................................................... 10-2 10.1.6 Condition Code Register (CCR) ...................................................... 10-2 10.1.6.1 Carry/Borrow (C) ..................................................................... 10-3 10.1.6.2 Overflow (V) ............................................................................ 10-3 10.1.6.3 Zero (Z) ................................................................................... 10-3 10.1.6.4 Negative (N) ............................................................................ 10-3 10.1.6.5 Interrupt Mask (I) ..................................................................... 10-3 10.1.6.6 Half Carry (H) .......................................................................... 10-3 10.1.6.7 X Interrupt Mask (X) ................................................................ 10-3 10.1.6.8 Stop Disable (S) ...................................................................... 10-3 10.2 Addressing Modes ................................................................................... 10-3 10.2.1 Immediate Addressing ..................................................................... 10-4 10.2.2 Direct Addressing ............................................................................ 10-4 10.2.3 Extended Addressing ...................................................................... 10-4 10.2.4 Indexed Addressing ......................................................................... 10-4 10.2.5 Inherent Addressing ........................................................................ 10-4 10.2.6 Relative Addressing ........................................................................ 10-4 10.2.7 Prebyte ............................................................................................ 10-5 10.3 Instruction Set ......................................................................................... 10-5 A ELECTRICAL CHARACTERISTICS

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MC68HC11A8 TECHNICAL DATA

B MECHANICAL DATA AND ORDERING INFORMATION B.1 B.2 Pin Assignments ....................................................................................... B-1 Package Dimensions ................................................................................ B-3 C DEVELOPMENT SUPPORT C.1 C.1.1 C.2 C.2.1 C.3 C.3.1 C.4 C.4.1 M68HC11EVB -- Evaluation Board ......................................................... C-1 EVB Features ................................................................................... C-1 M68HC11EVBU -- Universal Evaluation Board ...................................... C-1 EVBU Features ................................................................................ C-1 M68HC11EVM -- Evaluation Module ...................................................... C-2 EVM Features .................................................................................. C-2 MMDS11 -- Modular Development System ............................................. C-2 MMDS11Features ............................................................................ C-3 SUMMARY OF CHANGES

MC68HC11A8 TECHNICAL DATA

MOTOROLA vii

MOTOROLA viii

MC68HC11A8 TECHNICAL DATA

LIST OF ILLUSTRATIONS Figure Page
1-1 Block Diagram ................................................................................................ 1-2 1-2 Programming Model ....................................................................................... 1-3 2-1 Common Crystal Connections ........................................................................ 2-2 2-2 External Oscillator Connections ..................................................................... 2-2 2-3 One Crystal Driving Two MCUs ..................................................................... 2-2 2-4 Address/Data Demultiplexing ......................................................................... 2-8 3-1 Memory Maps ................................................................................................. 3-1 5-1 Data Format ................................................................................................... 5-2 5-2 Sampling Technique Used on All Bits ............................................................ 5-3 5-3 Examples of Start Bit Sampling Techniques .................................................. 5-4 5-4 SCI Artificial Start Following a Framing Error ................................................. 5-4 5-5 SCI Start Bit Following a Break ...................................................................... 5-4 5-6 Serial Communications Interface Block Diagram ........................................... 5-7 5-7 Rate Generator Division ............................................................................... 5-12 6-1 Data Clock Timing Diagram ........................................................................... 6-2 6-2 Serial Peripheral Interface Block Diagram ..................................................... 6-3 6-3 Serial Peripheral Interface Master-Slave Interconnection .............................. 6-4 7-1 A/D Conversion Sequence ............................................................................. 7-2 7-2 A/D Pin Model ................................................................................................ 7-2 9-1 Reset Timing .................................................................................................. 9-2 9-2 Simple LVI Reset Circuit ................................................................................ 9-3 9-3 Interrupt Stacking Order ................................................................................. 9-9 9-4 Processing Flow Out of Resets (Sheet 1 of 2) ............................................. 9-12 9-4 Processing Flow Out of Resets (Sheet 2 of 2) ............................................. 9-13 9-5 Interrupt Priority Resolution (Sheet 1 of 2) ................................................... 9-14 9-5 Interrupt Priority Resolution (Sheet 2 of 2) ................................................... 9-15 9-6 Interrupt Source Resolution Within SCI ........................................................ 9-16 10-1 Programming Model ..................................................................................... 10-2 10-2 Special Operations ..................................................................................... 10-12 A-1 Test Methods .................................................................................................. A-4 A-2 Timer Inputs ................................................................................................... A-7 A-3 POR and External Reset Timing Diagram ...................................................... A-8 A-4 STOP Recovery Timing Diagram ................................................................... A-9 A-5 WAIT Recovery Timing Diagram .................................................................. A-10 A-6 Interrupt Timing Diagram .............................................................................. A-11 A-7 Port Write Timing Diagram ........................................................................... A-14 A-8 Port Read Timing Diagram ........................................................................... A-14 A-9 Simple Output Strobe Timing Diagram ......................................................... A-14 A-10 Simple Input Strobe Timing Diagram ........................................................... A-15 A-11 Port C Input Handshake Timing Diagram ..................................................... A-15 A-12 Port C Output Handshake Timing Diagram .................................................. A-15 A-13 Three-State Variation of Output Handshake Timing Diagram (STRA Enables Output Buffer) A-16 A-14 Multiplexed Expansion Bus Timing Diagram ................................................ A-21 A-8 a) SPI Master Timing (CPHA = 0) ................................................................ A-24
MC68HC11A8 TECHNICAL DATA MOTOROLA ix

A-8 A-15 A-15 A-15 A-15 B-1 B-2 B-3 B-4

b) SPI Master Timing (CPHA = 1) ................................................................ A-24 SPI Timing Diagram (1 of 2) ......................................................................... A-24 c) SPI Slave Timing (CPHA = 0) .................................................................. A-25 d) SPI Slave Timing (CPHA = 1) .................................................................. A-25 SPI Timing Diagrams (2 of 2) ....................................................................... A-25 52-Pin PLCC .................................................................................................. B-1 48-Pin DIP ...................................................................................................... B-2 64-Pin QFP ..................................................................................................... B-3 M68HC11 P/N Options ................................................................................... B-5

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MC68HC11A8 TECHNICAL DATA

LIST OF TABLES
Table Page

1-1 M68HC11 Family Devices ..................................................................................... 1-4 2-1 Operating Modes vs. MODA and MODB ............................................................... 2-3 2-2 Port Signal Summary............................................................................................. 2-7 2-3 Bootstrap Mode Interrupt Vectors.......................................................................... 2-9 3-1 Register and Control Bit Assignments ................................................................... 3-2 4-1 Handshake l/O Operations Summary .................................................................... 4-4 5-1 First Prescaler Stage ........................................................................................... 5-11 5-2 Second Prescaler Stage ...................................................................................... 5-12 5-3 Prescaler Highest Baud Rate Frequency Output................................................. 5-12 5-4 Transmit Baud Rate Output for a Given Prescaler Output .................................. 5-13 6-1 Serial Peripheral Rate Selection............................................................................ 6-5 7-1 Analog-to-Digital Channel Assignments ................................................................ 7-4 8-1 Real Time Interrupt Rate versus RTR1 and RTR0 ................................................ 8-9 9-1 COP Timeout Period versus CR1 and CR0........................................................... 9-5 9-2 IRQ Vector Interrupts............................................................................................. 9-8 9-3 Interrupt Vector Assignments ................................................................................ 9-8 9-4 SCI Serial System Interrupts ................................................................................. 9-9 9-5 Mode Bits Relationship ........................................................................................ 9-11 9-6 Highest Priority I Interrupt versus PSEL[3:0] ....................................................... 9-17 9-7 Pin State Summary for RESET, STOP, and WAIT.............................................. 9-18 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times............. 10-6 10-2 Cycle-by-Cycle Operation -- Inherent Mode ................................................... 10-13 10-3 Cycle-by-Cycle Operation -- Immediate Mode ............................................... 10-16 10-4 Cycle-by-Cycle Operation -- Direct Mode....................................................... 10-16 10-5 Cycle-by-Cycle Operation -- Extended Mode ................................................. 10-18 10-6 Cycle-by-Cycle Operation -- Indexed X Mode ................................................ 10-19 10-7 Cycle-by-Cycle Operation -- Indexed Y Mode ................................................ 10-21 10-8 Cycle-by-Cycle Operation -- Relative Mode ................................................... 10-22 A-1 Maximum Rating ................................................................................................... A-1 A-2 Thermal Characteristics ........................................................................................ A-1 A-3 DC Electrical Characteristics................................................................................. A-2 A-3 DC Electrical Characteristics (MC68L11A8) ........................................................ A-3 A-4 Control Timing ....................................................................................................... A-5 A-4 Control Timing (MC68L11A8) ............................................................................... A-6 A-5 Peripheral Port Timing......................................................................................... A-12 A-5 Peripheral Port Timing (MC68L11A8) ................................................................ A-13 A-6 Analog-To-Digital Converter Characteristics ....................................................... A-17 A-6 Analog-To-Digital Converter Characteristics (MC68L11A8) ............................... A-18 A-7 Expansion Bus Timing......................................................................................... A-19 A-7 Expansion Bus Timing (MC68L11A8) ................................................................ A-20 A-8 Serial Peripheral Interface (SPI) Timing.............................................................. A-22 A-8 Serial Peripheral Interface (SPI) Timing (MC68L11A8) ..................................... A-23
MC68HC11A8 TECHNICAL DATA MOTOROLA xi

A-9 EEPROM Characteristics .................................................................................... A-26 A-9 EEPROM Characteristics (MC68L11A8) ............................................................ A-26 B-1 Ordering Information ............................................................................................. B-4

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MC68HC11A8 TECHNICAL DATA

1 INTRODUCTION
The HCMOS MC68HC11A8 is an advanced 8-bit microcontroller (MCU) with highly sophisticated on-chip peripheral capabilities. A fully static design and high-density complementary metal-oxide semiconductor (HCMOS) fabrication process allow E-series devices to operate at frequencies from 3 MHz to dc, with very low power consumption. 1.1 Features The following are some of the hardware and software highlights. 1.1.1 Hardware Features · 8 Kbytes of ROM · 512 Bytes of EEPROM · 256 Bytes of RAM (All Saved During Standby) Relocatable to Any 4K Boundary · Enhanced 16-Bit Timer System: -- Four Stage Programmable Prescaler -- Three Input Capture Functions -- Five Output Compare Functions · 8-Bit Pulse Accumulator Circuit · Enhanced NRZ Serial Communications Interface (SCI) · Serial Peripheral Interface (SPI) · Eight Channel, 8-Bit Analog-to-Digital Converter · Real Time Interrupt Circuit · Computer Operating Properly (COP) Watchdog System · Available in Dual-In-Line or Leaded Chip Carrier Packages 1.1.2 Software Features · Enhanced M6800/M6801 Instruction Set · 16 x 16 Integer and Fractional Divide Features · Bit Manipulation · WAIT Mode · STOP Mode 1.2 General Description The high-density CMOS technology (HCMOS) used on the MC68HC11A8 combines smaller size and higher speeds with the low power and high noise immunity of CMOS. On-chip memory systems include 8 Kbytes of ROM, 512 bytes of electrically erasable programmable ROM (EEPROM), and 256 bytes of static RAM. A block diagram of the MC68HC11A8 is shown in Figure 1-1. Major peripheral functions are provided on-chip. An eight channel analog-to-digital (A/D) converter is included with eight bits of resolution. An asynchronous serial communications interface
MC68HC11A8 TECHNICAL DATA INTRODUCTION MOTOROLA 1-1

1

(SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main 16-bit free-running timer system has three input capture lines, five output compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. A clock monitor system generates a system reset in case the clock is lost or runs too slow. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software controlled operating modes, WAIT and STOP, are available to conserve additional power.

MODA/ LIR

MODB/ VSTBY

XTAL EXTAL

E

IRQ

XIRQ

RESET 8 KBYTES ROM VDD VSS

PERIODIC INTERRUPT

COP

1

MODE CONTROL

OSCILLATOR CLOCK LOGIC

INTERRUPT LOGIC 512 BYTES EEPROM CPU 256 BYTES RAM

VRH VRL

PULSE ACCUMULATOR

TIMER SYSTEM STROBE AND HANDSHAKE PARALLEL I/O

R/W AS

BUS EXPANSION ADDRESS

ADDRESS/DATA

SPI SS SCK MOSI MISO

SCI TxD RxD

A/D CONVERTER

PORT A

PORT B

CONTROL PORT C

CONTROL PORT D

PORT E

PC7/A7/D7 PC6/A6/D6 PC5/A5/D5 PC4/A4/D4 PC3/A3/D3 PC2/A2/D2 PC1/A1/D1 PC0/A0/D0

STRB/R/W STRA/AS

PD5/SS PD4/SCK PD3/MOSI PD2/MISO

*PE7/AN7 *PE6/AN6 *PE5/AN5 *PE4/AN4

PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/OC1 PA2/IC1 PA1/IC2 PA0/IC3

* NOT BONDED ON 48-PIN VERSION.
A8 BLOCK

Figure 1-1 Block Diagram 1.3 Programmer's Model In addition to being able to execute all M6800 and M6801 instructions, the MC68HC11A8 allows execution of 91 new opcodes. Figure 1-2 shows the seven CPU registers which are available to the programmer.

MOTOROLA 1-2

INTRODUCTION

PD1/TxD PD0/RxD

MC68HC11A8 TECHNICAL DATA

PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0

PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8

7 15

A

0 D IX IY SP PC

7

B

0 0

8-BIT ACCUMULATORS A & B OR 16-BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER

7 S

0 X H I N Z V C CONDITION CODES

CARRY/BORROW FROM MSB OVERFLOW ZERO NEGATIVE I-INTERRUPT MASK HALF CARRY (FROM BIT 3) X-INTERRUPT MASK STOP DISABLE

1

Figure 1-2 Programming Model 1.4 Summary of M68HC11 Family Table 1-1 and the following paragraphs summarize the current members of the M68HC11 family of MCUs. This technical data book describes the MC68HC11A8 version and can be used as a primary reference for several other versions of the M68HC11 family. However, with the exception of the CPU, some newer members differ greatly from the MC68HC11A8 MCU and their respective technical literature should be referenced. Several of the device series within the M68HC11 family have x1 and x0 versions. These are identical to the main member of the series but have some of their on-chip resources disabled. For instance, an MC68HC11A1 is identical to the MC68HC11A8 except that its ROM is disabled. An MC68HC11A0 has disabled EPROM and EEPROM arrays. Refer to Table 1-1. Nearly all series within the M68HC11 family have both a ROM version and an EPROM version. Any device in the M68HC11 family that has a 7 preceding the 11 is a device containing EPROM instead of ROM (e.g., MC68HC711E9). These devices operate exactly as the custom ROM-based version (e.g., MC68HC11E9) but can be programmed by the user. EPROM-based devices in a windowed package can be erased and reprogrammed indefinitely. EPROM-based devices in standard packages are one-time-programmable (OTP). Refer to Table 1-1.

MC68HC11A8 TECHNICAL DATA

INTRODUCTION

MOTOROLA 1-3

Table 1-1 M68HC11 Family Devices
Device MC68HC11A8 MC68HC11A7 MC68HC11A1 MC68HC11A0 MC68HC11D3 MC68HC711D3 MC68HC11D0 MC68HC11ED0 MC68HC11E9 MC68HC711E9 MC68HC11E8 MC68HC11E1 MC68HC11E0 MC68HC811E2 MC68HC11E20 MC68HC711E20 MC68HC11F1 MC68HC11G7 MC68HC11G5 MC68HC711G5 MC68HC11G0 MC68HC11K4 MC68HC711K4 MC68HC11K3 MC68HC11K1 MC68HC11K0 MC68HC11KA4 MC68HC711KA4 MC68HC11KA2 MC68HC711KA2 MC68HC11L6 MC68HC711L6 MC68HC11L5 MC68HC11L1 MC68HC11L0 MC68HC11M2 MC68HC711M2 MC68HC11N4 MC68HC711N4 MC68HC11P2 MC68HC711P2 RAM 256 256 256 256 192 192 192 512 512 512 512 512 512 256 768 768 1024 512 512 512 512 768 768 768 768 768 768 768 1024 1024 512 512 512 512 512 1280 1280 768 768 1024 1024 ROM 8K 8K 0 0 4K 0 0 0 12K 0 12K 0 0 0 20K 0 0 24K 16K 0 0 24K 0 24K 0 0 24K 0 32K 0 16K 0 16K 0 0 32K 0 24K 0 32K 0 EPROM 0 0 0 0 0 4K 0 0 0 12K 0 0 0 0 0 20K 0 0 0 16K 0 0 24K 0 0 0 0 24K 0 32K 0 16K 0 0 0 0 32K 0 24K 0 32K EEPROM COMMENTS 512 16-bit timer; 8 channel 8-bit A/D, SCI, SPI 0 512 0 0 16-bit timer; SCI, SPI 0 0 0 16-bit timer; SCI, SPI 512 16-bit timer; SCI, SPI, 8 channel 8-bit A/D 512 0 512 0 2048 16-bit timer; SCI, SPI, 8 channel 8-bit A/D, 2K EEPROM 512 16-bit timer; SCl, SPI, 8 channel 8-bit A/D, 512 20K ROM/EPROM 512 nonmultiplexed bus, 8 channel 8-bit A/D, 4 chip selects, SCI, SPI 0 nonmultiplexed bus, 8 channel 10-bit A/D, 4 channel PWM, 0 SCI, SPI, 66 I/O pins 0 0 640 nonmultiplexed bus, memory expansion to 1MB, 640 8 channel 8-bit A/D, 4 channel PWM, 4 chip selects 0 640 0 640 nonmultiplexed bus, 8 channel 8-bit A/D, SCI, SPI, 640 4 channel PWM 640 640 512 multiplexed bus, 16-bit timer; 8 channel 8-bit A/D, SCI, SPI 512 0 512 0 640 nonmultiplexed bus, 8 channel 8-bit A/D, 4 channel PWM, 640 DMA, on-chip math coprocessor, SCI, 2 SPI 640 nonmultiplexed bus, 12 channel 8-bit A/D, 2 channel 8bit D/A, 640 6 channel PWM, on-chip math coprocessor, SCI, SPI 640 nonmultiplexed bus, PLL, 8 channel 8-bit A/D, 4 channel PWM, 640 3 SCI (2 with Ml bus), SPI, 62 I/O pins

1

MOTOROLA 1-4

INTRODUCTION

MC68HC11A8 TECHNICAL DATA

2 SIGNAL DESCRIPTIONS AND OPERATING MODES
The signal descriptions and operating modes are presented in this section. When the microcontroller is in an expanded multiplexed operating mode, 18 pins change function to support a multiplexed address/data bus. 2.1 Signal Pin Descriptions The following paragraphs provide a description of the input/output signals. Reference is made, where applicable, to other sections that contain more detail about the function being performed. 2.1.1 Input Power (VDD) and Ground (VSS) Power is supplied to the microcontroller using these pins. VDD is the positive power input and VSS is ground. Although the MC68HC11A8 is a CMOS device, very fast signal transitions are present on many of its pins. Short rise and fall times are present even when the microcontroller is operating at slow clock rates. Special care must be taken to provide good power supply bypassing at the MCU. Recommended bypassing would include a 0.1 µF ceramic capacitor between the VDD and VSS pins and physically adjacent to one of the two pins. A bulk capacitance, whose size depends on the other circuitry in the system, should also be present on the circuit board. 2.1.2 Reset (RESET) This active low bidirectional control signal is used as an input to initialize the MC68HC11A8 to a known start-up state, and as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (COP) watchdog circuit. This reset signal is significantly different from the reset signal used on other Motorola MCUs. Please refer to 9 RESETS, INTERRUPTS, AND LOW POWER MODES before designing circuitry to generate or monitor this signal. 2.1.3 Crystal Driver and External Clock Input (XTAL, EXTAL) These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. The frequency applied to these pins shall be four times higher than the desired E clock rate. The XTAL pin is normally left unterminated when using an external CMOS compatible clock input to the EXTAL pin. However, a 10K to 100K load resistor to ground may be used to reduce RFI noise emission. The XTAL output is normally intended to drive only a crystal. The XTAL output may be buffered with a high-input-impedance buffer such as the 74HC04, or it may be used to drive the EXTAL input of another M68HC11. In all cases take extra care in the circuit board layout around the oscillator pins. Load capacitances shown in the oscillator circuits include all stray layout capacitances. Refer to Figure 2-1, Figure 2-2, and Figure 2-3 for diagrams of oscillator circuits.
MC68HC11A8 TECHNICAL DATA SIGNAL DESCRIPTIONS AND OPERATING MODES MOTOROLA 2-1

2

25 pF * EXTAL

MCU
XTAL

10 M

4xE CRYSTAL 25 pF *

* THIS VALUE INCLUDES ALL STRAY CAPACITANCES.
COMMON XTAL CONN

Figure 2-1 Common Crystal Connections

2

EXTAL

4xE CMOS-COMPATIBLE EXTERNAL OSCILLATOR

MCU
XTAL NC

EXT EXTAL CONN

Figure 2-2 External Oscillator Connections

25 pF * EXTAL

220 EXTAL

FIRST MCU
XTAL

10 M

4xE CRYSTAL 25 pF * NC

SECOND MCU
XTAL

* THIS VALUE INCLUDES ALL STRAY CAPACITANCES.
DUAL-MCU XTAL CONN

Figure 2-3 One Crystal Driving Two MCUs

MOTOROLA 2-2

SIGNAL DESCRIPTIONS AND OPERATING MODES

MC68HC11A8 TECHNICAL DATA

2.1.4 E Clock Output (E) This is the output connection for the internally generated E clock which can be used as a timing reference. The frequency of the E clock output is actually one fourth that of the input frequency at the XTAL and EXTAL pins. When the E clock output is low an internal process is taking place and, when high, data is being accessed. The E clock signal is halted when the MCU is in STOP mode. 2.1.5 Interrupt Request (IRQ) The IRQ input provides a means for requesting asynchronous interrupts to the MC68HC11A8. It is program selectable (OPTION register) with a choice of either negative edge-sensitive or level-sensitive triggering, and is always configured to levelsensitive triggering by reset. The IRQ pin requires an external pull-up resistor to VDD (typically 4.7K ohm). 2.1.6 Non-Maskable Interrupt (XIRQ) This input provides a means for requesting a non-maskable interrupt, after reset initialization. During reset, the X bit in the condition code register is set and any interrupt is masked until MCU software enables it. The XIRQ input is level sensitive and requires an external pull-up resistor to VDD. 2.1.7 Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/LIR, MODB/VSTBY) During reset, MODA and MODB are used to select one of the four operating modes. Refer to Table 2-1. Paragraph 2.2 Operating Modes provides additional information. Table 2-1 Operating Modes vs. MODA and MODB
MODB 1 1 0 0 MODA 0 1 0 1 Mode Selected Single Chip Expanded Multiplexed Special Bootstrap Special Test

2

After the operating mode has been selected, the LIR pin provides an open-drain output to indicate that an instruction is starting. All instructions are made up of a series of E clock cycles. The LIR signal goes low during the first E clock cycle of each instruction (opcode fetch). This output is provided as an aid in program debugging. The VSTBY signal is used as the input for RAM standby power. When the voltage on this pin is more than one MOS threshold (about 0.7 volts) above the VDD voltage, the internal 256-byte RAM and part of the reset logic are powered from this signal rather than the VDD input. This allows RAM contents to be retained without VDD power applied to the MCU. Reset must be driven low before VDD is removed and must remain low until VDD has been restored to a valid level.

MC68HC11A8 TECHNICAL DATA

SIGNAL DESCRIPTIONS AND OPERATING MODES

MOTOROLA 2-3

2.1.8 A/D Converter Reference Voltages (VRL, VRH) These two inputs provide the reference voltages for the analog-to-digital converter circuitry. 2.1.9 Strobe B and Read/Write (STRB/R/W) This signal acts as a strobe B output or as a data bus direction indicator depending on the operating mode. In single-chip operating mode, the STRB output acts as a programmable strobe for handshake with other parallel l/O devices. Refer to 4 PARALLEL I/O for additional information. In expanded multiplexed operating mode, R/W is used to control the direction of transfers on the external data bus. A low on the R/W signal indicates data is being written to the external data bus. A high on this signal indicates that a read cycle is in progress. R/W will stay low during consecutive data bus write cycles, such as in a double-byte store. The NAND of inverted R/W with the E clock should be used as the write enable signal for an external static RAM. 2.1.10 Strobe A and Address Strobe (STRA/AS) This signal acts as an edge detecting strobe A input or as an address strobe bus control output depending on the operating mode. In single-chip operating mode, the STRA input acts as a programmable strobe for handshake with other parallel l/O devices. Refer to 4 PARALLEL I/O for additional information. In expanded multiplexed operating mode, the AS output is used to demultiplex the address and data signals at port C. Refer to 2.2.2 Expanded Multiplexed Operating Mode for additional information. 2.1.11 Port Signals Ports A, D, and E signals are independent of the operating mode. Port B provides eight general purpose output signals in single-chip operating modes and provides eight high-order address signals when the microcontroller is in expanded multiplexed operating modes. Port C provides eight general purpose input/output signals when the microcontroller is in singlechip operating modes. When the microcontroller is in expanded multiplexed operating modes, port C is used for a multiplexed address/data bus. Table 2-2 shows a summary of the 40 port signals as they relate to the operating modes. Unused inputs and l/O pins configured as inputs should be terminated high or low.

2

MOTOROLA 2-4

SIGNAL DESCRIPTIONS AND OPERATING MODES

MC68HC11A8 TECHNICAL DATA

2.1.11.1 Port A Port A may be configured for: three input capture functions (IC1, IC2, IC3), four output compare functions (OC2, OC3, OC4, OC5), and either a pulse accumulator input (PAI) or a fifth output compare function (OC1). Refer to 8.1 Programmable Timer for additional information. Any port A pin that is not used for its alternate timer function may be used as a generalpurpose input or output line. 2.1.11.2 Port B While in single-chip operating modes, all of the port B pins are general-purpose output pins. During MCU reads of this port, the level sensed at the input side of the port B output drivers is read. Port B may also be used in a simple strobed output mode where an output pulse appears at the STRB signal each time data is written to port B. When in expanded multiplexed operating modes, all of the port B pins act as high order address output signals. During each MCU cycle, bits 8 through 15 of the address are output on the PB0-PB7 lines respectively. 2.1.11.3 Port C While in single-chip operating modes, all port C pins are general-purpose input/output pins. Port C inputs can be latched by providing an input transition to the STRA signal. Port C may also be used in full handshake modes of parallel l/O where the STRA input and STRB output act as handshake control lines. When in expanded multiplexed operating modes, all port C pins are configured as multiplexed address/data signals. During the address portion of each MCU cycle, bits 0 through 7 of the address are output on the PC0-PC7 lines. During the data portion of each MCU cycle (E high), pins 0 through 7 are bidirectional data signals (D0-D7). The direction of data at the port C pins is indicated by the R/W signal. 2.1.11.4 Port D Port D pins 0-5 may be used for general-purpose l/O signals. Port D pins alternately serve as the serial communications interface (SCI) and serial peripheral interface (SPI) signals when those subsystems are enabled. Pin PD0 is the receive data input (RxD) signal for the serial communication interface (SCI). Pin PD1 is the transmit data output (TxD) signal for the SCI. Pins PD2 through PD5 are dedicated to the SPI. PD2 is the master-in-slave-out (MISO) signal. PD3 is the master-out-slave-in (MOSI) signal. PD4 is the serial clock (SCK) signal and PD5 is the slave select (SS) input.

2

MC68HC11A8 TECHNICAL DATA

SIGNAL DESCRIPTIONS AND OPERATING MODES

MOTOROLA 2-5

2.1.11.5 Port E Port E is used for general-purpose inputs and/or analog-to-digital (A/D) input channels. Reading port E during the sampling portion of an A/D conversion could cause very small disturbances and affect the accuracy of that result. If very high accuracy is required, avoid reading port E during conversions. 2.2 Operating Modes There are four operating modes for the MC68HC11A8: single-chip operating mode, expanded multiplexed operating mode, special bootstrap operating mode, and special test operating mode. Table 2-1 shows how the operating mode is selected. The following paragraphs describe these operating modes. 2.2.1 Single-Chip Operating Mode In single-chip operating mode, the MC68HC11A8 functions as a monolithic microcontroller without external address or data buses. Port B, port C, strobe A, and strobe B function as general purpose l/O and handshake signals. Refer to 4 PARALLEL I/O for additional information. 2.2.2 Expanded Multiplexed Operating Mode In expanded multiplexed operating mode, the MC68HC11A8 has the capability of accessing a 64 Kbyte address space. This total address space includes the same onchip memory addresses used for single-chip operating mode plus external peripheral and memory devices. The expansion bus is made up of port B and port C, and control signals AS and R/W. Figure 2-4 shows a recommended way of demultiplexing low order addresses from data at port C. The address, R/W, and AS signals are active and valid for all bus cycles including accesses to internal memory locations.

2

MOTOROLA 2-6

SIGNAL DESCRIPTIONS AND OPERATING MODES

MC68HC11A8 TECHNICAL DATA

Table 2-2 Port Signal Summary
Port-Bit A-0 A-1 A-2 A-3 A-4 A-5 A-6 A-7 B-0 B-1 B-2 B-3 B-4 B-5 B-6 B-7 C-0 C-1 C-2 C-3 C-4 C-5 C-6 C-7 D-0 D-1 D-2 D-3 D-4 D-5 Single Chip and Bootstrap Mode PA0/IC3 PA1/IC2 PA2/IC1 PA3/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0/RXD PD1/TXD PD2/MISO PD3/MOSI PD4/SCK PD5/SS STRA STRB PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 PE4/AN4## PE5/AN5## PE6/AN6## PE7/AN7## Expanded Multiplexed and Special Test Mode PA0/IC3 PA1/IC2 PA2/IC1 PA3/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 A8 A9 A10 A11 A12 A13 A14 A15 A0/D0 A1/D1 A2/D2 A3/D3 A4/D4 A5/D5 A6/D6 A7/D7 PD0/RXD PD1/TXD PD2/MISO PD3/MOSI PD4/SCK PD5/SS AS R/W PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 PE4/AN4## PE5/AN5## PE6/AN6## PE7/AN7##

2

E-0 E-1 E-2 E-3 E-4 E-5 E-6 E-7 ## Not bonded in 48-pin versions

MC68HC11A8 TECHNICAL DATA

SIGNAL DESCRIPTIONS AND OPERATING MODES

MOTOROLA 2-7

PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 HC373 PC7/A7/D7 PC6/A6/D6 PC5/A5/D5 PC4/A4/D4 PC3/A3/D3 PC2/A2/D2 PC1/A1/D1 PC0/A0/D0 AS D1 D2 D3 D4 D5 D6 D7 D8 LE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 OE

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

R/W E

WE D7 D6 D5 D4 D3 D2 D1 D0
ADDR/DATA DEMUX

2

MC68HC11A8

Figure 2-4 Address/Data Demultiplexing 2.2.3 Special Bootstrap Operating Mode The bootstrap mode is considered a special operating mode as distinguished from the normal single-chip operating mode. This is a very versatile operating mode since there are essentially no limitations on the special purpose program that can be loaded into the internal RAM. The boot loader program is contained in the 192 byte bootstrap ROM. This ROM is enabled only if the MCU is reset in special bootstrap operating mode, and appears as internal memory space at locations $BF40-$BFFF. The boot loader program will use the SCI to read a 256 byte program into on-chip RAM at locations $0000-$00FF. After the character for address $00FF is received, control is automatically passed to that program at location $0000. The MC68HC11A8 communicates through the SCI port. After reset in special bootstrap operating mode, the SCI is running at E clock/16 (7812 baud for E clock equal 2 MHz). If the security feature was specified and the security bit is set, $FF is output by the SCI transmitter. The EEPROM is then erased. If erasure is unsuccessful, $FF is output again and erasure is attempted again. Upon successful erasure of the EEPROM, all internal RAM is written over with $FF. The CONFIG register is then erased. The boot loader program now proceeds as though the part had not been in security mode.

MOTOROLA 2-8

SIGNAL DESCRIPTIONS AND OPERATING MODES

MC68HC11A8 TECHNICAL DATA

If the part is not in security mode (or has completed the above erase sequence), a break character is output by the SCI transmitter. For normal use of the boot loader program, the user sends $FF to the SCI receiver at either E clock/16 (7812 baud for E clock = 2 MHz) or E clock/104 (1200 baud for E clock = 2 MHz). NOTE This $FF is not echoed through the SCI transmitter. Now the user must download 256 bytes of program data to be put into RAM starting at location $0000. These characters are echoed through the transmitter. When loading is complete, the program jumps to location $0000 and begins executing that code. If the SCI transmitter pin is to be used, an external pull-up resistor is required because port D pins are configured for wire-OR operation. In special bootstrap operating mode the interrupt vectors are directed to RAM as shown in Table 2-3. This allows the user to use interrupts by way of a jump table. For example: to use the SWI interrupt, a jump instruction would be placed in RAM at locations $00F4, $00F5, and $00F6. When an SWI is encountered, the vector (which is in the boot loader ROM program) will direct program control to location $00F4 in RAM which in turn contains a JUMP instruction to the interrupt service routine. Table 2-3 Bootstrap Mode Interrupt Vectors
Address 00C4 00C7 00CA 00CD 00D0 00D3 00D6 00D9 00DC 00DF 00E2 00E5 00E8 00EB 00EE 00F1 00F4 00F7 00FA 00FD BF40 (Boot) Vector SCI SPI Pulse Accumulator Input Edge Pulse Accumulator Overflow Timer Overflow Timer Output Compare 5 Timer Output Compare 4 Timer Output Compare 3 Timer Output Compare 2 Timer Output Compare 1 Timer Input Capture 3 Timer Input Capture 2 Timer Input Capture 1 Real Time Interrupt IRQ XIRQ SWI Illegal Opcode COP Fail Clock Monitor Reset

2

MC68HC11A8 TECHNICAL DATA

SIGNAL DESCRIPTIONS AND OPERATING MODES

MOTOROLA 2-9

2.2.4 Additional Boot Loader Program Options The user may transmit a $55 (only at E clock/16) as the first character rather than the normal $FF. This will cause the program to jump directly to location $0000, skipping the download. The user may tie the receiver to the transmitter (with an external pull-up resistor). This will cause the program to jump directly to the beginning of EEPROM ($B600). Another way to cause the program to jump directly to EEPROM is to transmit either a break or $00 as the first character rather than the normal $FF. Note that none of these options bypass the security check and so do not compromise those customers using security. Keep in mind that upon entry to the downloaded program at location $0000, some registers have been changed from their reset states. The SCI transmitter and receiver are enabled which cause port D pins 0 and 1 to be dedicated to SCI use. Also port D is configured for wired-OR operation. It may be necessary for the user to write to the SCCR2 and SPCR registers to disable the SCI and/or port D wire-OR operation. 2.2.5 Special Test Operating Mode The test mode is a special operating mode intended primarily for factory testing. This mode is very similar to the expanded multiplexed operating mode. In special test operating mode, the reset and interrupt vectors are fetched from external memory locations $BFC0$BFFF rather than $FFC0$FFFF. There are no time limits for protection of the TMSK2, OPTION, and INIT registers, so these registers may be written repeatedly. Also a special TEST1 register is enabled which allows several factory test functions to be invoked. The special test operating mode is not recommended for use by an end user because of the reduced system security; however, an end user may wish to come out of reset in special test operating mode. Then, after some initialization, the SMOD and MDA bits could be rewritten to select a normal operating mode to re-enable the protection features.

2

MOTOROLA 2-10

SIGNAL DESCRIPTIONS AND OPERATING MODES

MC68HC11A8 TECHNICAL DATA

3 ON-CHIP MEMORY
This section describes the on-chip ROM, RAM, and EEPROM memories. The memory maps for each mode of operation are shown and the RAM and l/O mapping register (INIT) is described. The INIT register allows the on-chip RAM and the 64 control registers to be moved to suit the needs of a particular application. 3.1 Memory Maps Composite memory maps for each mode of operation are shown in Figure 3-1. Memory locations are shown in the shaded areas and the contents of these shaded areas are shown to the right. These modes include single-chip, expanded multiplexed, special bootstrap, and special test. Single-chip operating modes do not generate external addresses. Refer to Table 3-1 for a full list of the registers.

3

$0000 EXT $1000 EXT

0000 00FF 1000 103F EXT EXT B600

256 BYTES RAM

64-BYTE REGISTER BLOCK

512 BYTES EEPROM

$B600 EXT EXT

B7FF BF40 BFFF BOOT ROM BFC0 BFFF 8 KBYTES ROM FFC0 FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST
A8 MEM MAP

SPECIAL MODES INTERRUPT VECTORS

$E000

E000

$FFFF

FFFF

NORMAL MODES INTERRUPT VECTORS

Figure 3-1 Memory Maps

MC68HC11A8 TECHNICAL DATA

ON-CHIP MEMORY

MOTOROLA 3-1

Table 3-1 Register and Control Bit Assignments (Sheet 1 of 2)
$1000 $1001 $1002 $1003 $1004 $1005 $1006 $1007 Bit 7 -- -- Bit 5 Bit 5 Bit 7 FOC1 OC1M7 OC1D7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 -- FOC2 OC1M6 OC1D6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOC3 OC1M5 OC1D5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOC4 OC1M4 OC1D4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOC5 OC1M3 OC1D3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 -- -- -- -- -- -- -- -- Bit 0 Bit 0 Bit 0 Bit 0 STAF Bit 7 Bit 7 Bit 7 STAI -- -- -- CWOM -- -- -- HNDS -- -- -- OIN -- -- -- PLS -- -- -- EGA -- -- -- INVB Bit 0 Bit 0 Bit 0 Bit 7 Bit 7 Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 -- Bit 0 Bit 0 PORTA Reserved PIOC PORTC PORTB Parallel I/O Control Register I/O Port C Output Port B I/O Port A

PORTCL Alternate Latched Port C Reserved DDRC PORTD DDRD PORTE CFORC OC1M OC1D TCNT Data Direction for Port C I/O Port D Data Direction for Port D Input Port E Compare Force Register OC1 Action Mask Register OC1 Action Data Register Timer Counter Register

3

$1008 $1009 $100A $100B $100C $100D $100E $100F $1010 $1011 $1012 $1013 $1014 $1015 $1016 $1017 $1018 $1019 $101A $101B $101C $101D $101E $101F

TIC1

Input Capture 1 Register

TIC2

Input Capture 2 Register

TIC3

Input Capture 3 Register

TOC1

Output Compare 1 Register

TOC2

Output Compare 2 Register

TOC3

Output Compare 3 Register

TOC4

Output Compare 4 Register

TCO5

Output Compare 5 Register

MOTOROLA 3-2

ON-CHIP MEMORY

MC68HC11A8 TECHNICAL DATA

Table 3-1 Register and Control Bit Assignments (Sheet 2 of 2)
$1020 $1021 $1022 $1023 $1024 $1025 $1026 $1027 $1028 $1029 $102A $102B $102C $102D $102E $102F $1030 $1031 $1032 $1033 $1034 $1035 thru $1038 $1039 $103A $103B $103C $103D $103E $103F ADPU Bit 7 ODD RBOOT RAM3 TILOP -- -- CSEL -- EVEN SMOD RAM2 MDA RAM1 OCCR -- IRQE -- DLY -- BYTE IRV RAM0 CBYP -- CME -- ROW PSEL3 REG3 DISR NOSEC -- ERASE PSEL2 REG2 FCM NOCOP CR1 -- EELAT PSEL1 REG1 FCOP ROMON CR0 Bit 0 EEPGM PSEL0 REG0 TCON EEON OC1I OC1F TOI TOF DDRA7 Bit 7 SPIE SPIF Bit 7 TCLR R8 TIE TRDE Bit 7 CCF Bit 7 Bit 7 Bit 7 Bit 7 -- -- -- -- T8 TCIE TC -- RIE RDRF -- SCAN -- -- -- -- OC2I OC2F RTII RTIF PAEN -- SPE WCOL -- -- SCP1 Bit 7 OM2 Bit 6 OL2 Bit 5 OM3 EDG1B OC3I OC3F PAOVI PAOVF PAMOD -- DWOM Bit 4 OL3 EDG1A OC4I OC4F PAII PAIF PEDGE -- MSTR MODF -- SCP0 M ILIE IDLE -- MULT -- -- -- -- -- RCKB WAKE TE OR -- CD -- -- -- -- RE NF -- CC -- -- -- -- RWU FE -- CB -- -- -- -- Bit 0 CA Bit 0 Bit 0 Bit 0 Bit 0 SBK -- SCR2 -- SCR1 Bit 0 SCR0 -- CPOL -- CPHA RTR1 -- SPR1 RTR0 Bit 0 SPR0 Bit 3 OM4 EDG2B OC5I OC5F Bit 2 OL4 EDG2A IC1I IC1F Bit 1 OM5 EDG3B IC2I IC2F PR1 Bit 0 OL5 EDG3A IC3I IC3F PR0 TCTL1 TCTL2 TMSK1 TFLG1 TMSK2 TFLG2 PACTL PACNT SPCR SPSR SPDR BAUD SCCR1 SCCR2 SCSR SCDR ADCTL ADR1 ADR2 ADR3 ADR4 Timer Control Register 1 Timer Control Register 2 Timer Interrupt Mask Register 1 Timer Interrupt Flag Register 1 Timer Interrupt Mask Register 2 Timer Interrupt Flag Register 2 Pulse Accumulator Control Register Pulse Accumulator Count Register SPI Control Register SPI Status Register SPI Data Register SCI Baud Rate Control SCI Control Register 1 SCI Control Register 2 SCI Status Register SCI Data (Read RDR, Write TDR) A/D Control Register A/D Result Register 1 A/D Result Register 2 A/D Result Register 3 A/D Result Register 4

3

Reserved

OPTION

System Configuration Options

COPRST Arm/Reset COP Timer Circuitry PPROG HPRIO INIT TEST1 CONFIG EEPROM Program Control Register Highest Priority I-Bit Int and Misc RAM and I/O Mapping Register Factory TEST Control Register COP, ROM, and EEPROM Enables

MC68HC11A8 TECHNICAL DATA

ON-CHIP MEMORY

MOTOROLA 3-3

In expanded multiplexed operating modes, memory locations are basically the same as the single- chip operating modes; however, the locations between the shaded areas (designated EXT) are for externally addressed memory and l/O. If an external memory or l/O device is located to overlap an enabled internal resource, the internal resource will take priority. For reads of such an address the data (if any) driving the port C data inputs is ignored and will not result in any harmful conflict with the internal read. For writes to such an address data is driven out of the port C data pins as well as to the internal location. No external devices should drive port C during write accesses to internal locations; however, there is normally no conflict since the external address decode and/ or data direction control should incorporate the R/W signal in their development. The R/W, AS, address, and write data signals are valid for all accesses including accesses to internal memory and registers. The special bootstrap operating mode memory locations are similar to the single-chip operating mode memory locations except that a bootstrap program at memory locations $BF40 through $BFFF is enabled. The reset and interrupt vectors are addressed at $BFC0$BFFF while in the special bootstrap operating mode. These vector addresses are within the 192 byte memory used for the bootstrap program. The special test operating mode memory map is the same as the expanded multiplexed operating mode memory map except that the reset and interrupt vectors are located at external memory locations $BFC0$BFFF. 3.2 RAM and I/O Mapping Register (INIT) There are 64 internal registers which are used to control the operation of the MCU. These registers can be relocated on 4K boundaries within the memory space, using the INIT register. Refer to Table 3-1 for a complete list of the registers. The registers and control bits are explained throughout this document. The INIT register is a special-purpose 8-bit register