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MOTOROLA

SEMICONDUCTOR
TECHNICAL DATA

Order this document by MC68HC11FTS/D

MC68HC11F1 MC68HC11FC0
Technical Summary 8-Bit Microcontroller
1 Introduction
The MC68HC11F1 is a high-performance member of the M68HC11 family of microcontroller units (MCUs). High-speed expanded systems required the development of this chip with its extra input/output (I/O) ports, an increase in static RAM (one Kbyte), internal chip-select functions, and a non-multiplexed bus which reduces the need for external interface logic. The timer, serial I/O, and analog-to-digital (A/ D) converter enable functions similar to those found in the MC68HC11E9. The MC68HC11FC0 is a low cost, high-speed derivative of the MC68HC11F1. It does not have EEPROM or an analog-to-digital converter. The MC68HC11FC0 can operate at bus speeds as high as six MHz. This document provides a brief overview of the structure, features, control registers, packaging information and availability of the MC68HC11F1 and MC68HC11FC0. For detailed information on M68HC11 subsystems, programming and the instruction set, refer to the M68HC11 Reference Manual (M68HC11RM/AD). 1.1 Features · MC68HC11 CPU · 512 Bytes of On-Chip Electrically Erasable Programmable ROM (EEPROM) with Block Protect (MC68HC11F1 only) · 1024 Bytes of On-Chip RAM (All Saved During Standby) · Enhanced 16-Bit Timer System -- 3 Input Capture (IC) Functions -- 4 Output Compare (OC) Functions -- 4th IC or 5th OC (Software Selectable) · On-Board Chip-Selects with Clock Stretching · Real-Time Interrupt Circuit · 8-Bit Pulse Accumulator · Synchronous Serial Peripheral Interface (SPI) · Asynchronous Nonreturn to Zero (NRZ) Serial Communication Interface (SCI) · Power saving STOP and WAIT Modes · Eight-Channel 8-Bit A/D Converter (MC68HC11F1 only) · Computer Operating Properly (COP) Watchdog System and Clock Monitor · Bus Speeds of up to 6 MHz for the MC68HC11FC0 and up to 5 MHz for the MC68HC11F1 · 68-Pin PLCC (MC68HC11F1 only), 64-Pin QFP (MC68HC11FC0 only), and 80-pin TQFP package options

This document contains information on a new product. Specifications and information herein are subject to change without notice.

© MOTOROLA INC., 1997

M

1.2 Ordering Information The following devices all have 1024 bytes of RAM. In addition, the MC68HC11F1 devices have 512 bytes of EEPROM. None of the devices contain on-chip ROM. Table 1 MC68HC11F1 Standard Device Ordering Information
Package Temperature 0° to +70° Frequency 5 MHz 2 MHz -40° to +85°C 80-Pin Thin Quad Flat Pack (TQFP) (14 mm X 14 mm, 1.4 mm thick) 3 MHz 4 MHz 5 MHz 2 MHz ­ 40° to + 105° C 3 MHz 4 MHz 2 MHz ­ 40° to + 125° C 0° to +70° 3 MHz 4 MHz 5 MHz 2 MHz ­ 40° to + 85° C 3 MHz 4 MHz 5 MHz 68-Pin PLCC ­ 40° to + 105° C 2 MHz 3 MHz 4 MHz 2 MHz ­ 40° to + 125° C 3 MHz 4 MHz MC Order Number MC68HC11F1PU5 MC68HC11F1CPU2 MC68HC11F1CPU3 MC68HC11F1CPU4 MC68HC11F1CPU5 MC68HC11F1VPU2 MC68HC11F1VPU3 MC68HC11F1VPU4 MC68HC11F1MPU2 MC68HC11F1MPU3 MC68HC11F1MPU4 MC68HC11F1FN5 MC68HC11F1CFN2 MC68HC11F1CFN3 MC68HC11F1CFN4 MC68HC11F1CFN5 MC68HC11F1VFN2 MC68HC11F1VFN3 MC68HC11F1VFN4 MC68HC11F1MFN2 MC68HC11F1MFN3 MC68HC11F1MFN4

Table 2 MC68HC11F1 Extended Voltage (3.0 to 5.5 V) Device Ordering Information
Package 68-Pin Plastic Leaded Chip Carrier (PLCC) 80-Pin Thin Quad Flat Pack (TQFP) Temperature 0° to +70°C ­40° to +85°C 0° to +70°C ­40° to +85°C Frequency 3 MHz 3 MHz 3 MHz 3 MHz MC Order Number MC68L11F1FN3 MC68L11F1CFN3 MC68L11F1PU3 MC68L11F1CPU3

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MC68HC11F1/FC0 MC68HC11FTS/D

Table 3 MC68HC11FC0 Standard Device Ordering Information
Package 64-Pin Quad Flat Pack (QFP) Temperature ­40° to +85°C 0° to 70° C ­40° to +85°C 0° to 70° C Frequency 4 MHz 5 MHz 6 MHz 4 MHz 5 MHz 6 MHz MC Order Number MC68HC11FC0CFU4 MC68HC11FC0CFU5 MC68HC11FC0FU6 MC68HC11FC0CPU4 MC68HC11FC0CPU5 MC68HC11FC0PU6

80-Pin Thin Quad Flat Pack (TQFP)

Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information
Package 64-Pin Quad Flat Pack (QFP) 80-Pin Thin Quad Flat Pack (TQFP) Temperature Frequency 3 MHz ­0° to +70°C 4 MHz 3 MHz 4 MHz MC Order Number MC68L11FC0FU3 MC68L11FC0FU4 MC68L11FC0PU3 MC68L11FC0PU4

MC68HC11F1/FC0 MC68HC11FTS/D

MOTOROLA 3

TABLE OF CONTENTS
Section Page

1
1.1 1.2 1.3

Introduction

1 Features ......................................................................................................................................1 Ordering Information ...................................................................................................................2 Block Diagrams ..........................................................................................................................6

2
2.1 2.2 2.3

3
3.1 3.2

4
4.1 4.2 4.3

5
5.1 5.2

6
6.1 6.2 6.3 6.4

7
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8

8
8.1 8.2

9
9.1 9.2

10
10.1 10.2

11
11.1 11.2 11.3

12
12.1 12.2

8 MC68HC11F1 Pin Assignments ..................................................................................................8 MC68HC11FC0 Pin Assignments .............................................................................................10 Pin Descriptions ........................................................................................................................12 Control Registers 14 MC68HC11F1 Control Registers ...............................................................................................14 MC68HC11FC0 Control Registers ............................................................................................16 Operating Modes and System Initialization 18 Operating Modes .......................................................................................................................18 Memory Maps ............................................................................................................................19 System Initialization Registers ..................................................................................................20 Resets and Interrupts 25 Interrupt Sources .......................................................................................................................25 Reset and Interrupt Registers ...................................................................................................26 Electrically Erasable Programmable ROM 29 EEPROM Operation ..................................................................................................................29 EEPROM Registers ...................................................................................................................29 EEPROM Programming and Erasure ........................................................................................31 CONFIG Register Programming ...............................................................................................32 Parallel Input/Output 33 Port A ........................................................................................................................................33 Port B ........................................................................................................................................33 Port C ........................................................................................................................................33 Port D ........................................................................................................................................33 Port E ........................................................................................................................................33 Port F .........................................................................................................................................33 Port G ........................................................................................................................................34 Parallel I/O Registers ................................................................................................................34 Chip-Selects 38 Chip-Select Operation ...............................................................................................................38 Chip-Select Registers ................................................................................................................38 Serial Communications Interface (SCI) 42 SCI Block Diagrams ..................................................................................................................42 SCI Registers ............................................................................................................................44 Serial Peripheral Interface 49 SPI Block Diagram ....................................................................................................................49 SPI Registers ............................................................................................................................50 Analog-to-Digital Converter 53 Input Pins ..................................................................................................................................54 Conversion Sequence ...............................................................................................................54 A/D Registers ............................................................................................................................55 Main Timer 57 Timer Operation ........................................................................................................................57 Timer Registers .........................................................................................................................59

Pin Assignments and Signal Descriptions

13
13.1 13.2

Pulse Accumulator 64 Pulse Accumulator Block Diagram ............................................................................................64 Pulse Accumulator Registers ....................................................................................................64

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MC68HC11F1/FC0 MC68HC11FTS/D

REGISTER INDEX
Register Address Page ADCTL ................ A/D Control/Status .........................................................$1030 ..........................55 BAUD .................. Baud Rate......................................................................$102B ..........................44 BPROT................ Block Protect..................................................................$1035 ..........................29 CFORC ............... Timer Force Compare....................................................$100B ..........................59 CONFIG .............. EEPROM Mapping, COP, EEPROM Enables ...............$103F ............. 24, 28, 30 COPRST ............. Arm/Reset COP Timer Circuitry.....................................$103A ..........................27 CSCTL ................ Chip-Select Control........................................................$105D ..........................39 CSGADR............. General-Purpose Chip-Select Address Register ........... $105E .........................40 CSGSIZ............... General-Purpose Chip-Select Size Register ................$105F ..........................40 CSSTRH ............. Clock Stretching.............................................................$105C ..........................38 DDRA .................. Port A Data Register......................................................$1001 ..........................34 DDRC.................. Data Direction Register for Port C .................................$1007 ..........................35 DDRD.................. Data Direction Register for Port D .................................$1009 ..........................36 DDRG.................. Data Direction Register for Port G .................................$1003 ..........................35 HPRIO................. Highest Priority Interrupt and Miscellaneous ................$103C ................... 20, 27 INIT ..................... RAM and I/O Mapping ...................................................$103D ................... 21, 22 OC1D .................. Output Compare 1 Data ................................................$100D ..........................59 OC1M.................. Output Compare 1 Mask ...............................................$100C ..........................59 OPT2................... System Configuration Option Register 2 .......................$1038 ............. 22, 36, 52 OPTION .............. System Configuration Options .......................................$1039 ............. 23, 26, 56 PACNT ................ Pulse Accumulator Count ..............................................$1027 ..........................66 PACTL................. Pulse Accumulator Control ...........................................$1026 ................... 63, 65 PORTA................ Port A Data ....................................................................$1000 ..........................34 PORTB................ Port B Data ....................................................................$1004 ..........................35 PORTC................ Port C Data ....................................................................$1006 ..........................35 PORTD................ Port D Data ....................................................................$1008 ..........................36 PORTE................ Port E Data ....................................................................$100A ..........................36 PORTF ................ Port F Data ....................................................................$1005 ..........................35 PORTG ............... Port G Data....................................................................$1002 ..........................34 PPROG ............... EEPROM Programming Control ....................................$103B ..........................30 SCCR1 ................ SCI Control 1 ................................................................$102C ..........................46 SCCR2 ................ SCI Control 2 ................................................................$102D ..........................46 SCDR .................. Serial Communications Data Register...........................$102F ..........................48 SCSR .................. SCI Status......................................................................$102E ..........................47 SPCR .................. Serial Peripheral Control ...............................................$1028 ..........................50 SPDR .................. SPI Data .......................................................................$102A ..........................51 SPSR .................. Serial Peripheral Status .................................................$1029 ..........................51 TCNT................... Timer Count ..................................................................$100E, $100F ..............59 TCTL1 ................. Timer Control 1 ..............................................................$1020 ..........................60 TCTL2 ................. Timer Control 2 ..............................................................$1021 ..........................61 TEST1 ................. Factory Test ..................................................................$103E ..........................24 TFLG1 ................. Timer Interrupt Flag 1 ...................................................$1023 ..........................61 TFLG2 ................. Timer Interrupt Flag 2 ...................................................$1025 ................... 62, 65 TI4O5 .................. Timer Input Capture 4/Output Compare 5 ....................$101E, $101F ..............60 TIC1­TIC3........... Timer Input Capture ......................................................$1010­$1015 ..............60 TMSK1 ................ Timer Interrupt Mask 1 ..................................................$1022 ..........................61 TMSK2 ................ Timer Interrupt Mask 2 ..................................................$1024 ................... 62, 64 TOC1­TOC4 ....... Timer Output Compare .................................................$1016­$101D ..............60

MC68HC11F1/FC0 MC68HC11FTS/D

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1.3 Block Diagrams
MODB/ VSTBY

VDD

VSS

E

4XOUT

XTAL

EXTAL

IRQ

XIRQ RESET

MODA/ LIR

OSCILLATOR POWER CLOCK LOGIC PAI/0C1 PORT A DDRA PULSE ACCUMULATOR TIMER SYSTEM INTERRUPT LOGIC COP MODE CONTROL A/D CONVERTER AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 CSPROG CSGEN CSIO1 CSIO2 VRH VRL PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

OC2/OC1 OC3/OC1 OC4/OC1 IC4/OC5/OC1 IC3 IC2 IC1

PERIODIC INTERRUPT 512 BYTES EEPROM

PORT G

PORT E DDRG PORT D

1024 BYTES STATIC RAM

CHIP SELECTS CPU CORE SCI RxD TxD

PD0 PD1

ADDRESS BUS ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

DATA BUS DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

DDRD

MISO MOSI SCK SS SPI

PD2 PD3 PD4 PD5

PORT C PORT B PORT F DDRC

Figure 1 MC68HC11F1 Block Diagram

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PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

R/W

MC68HC11F1/FC0 MC68HC11FTS/D

VDD

VSS

DS

E 4XOUT XTAL

EXTAL

IRQ

XIRQ RESET

MODA / LIR

MODB / VSTBY

OSCILLATOR POWER CLOCK LOGIC PAI/0C1 PORT A DDRA PULSE ACCUMULATOR TIMER SYSTEM INTERRUPT LOGIC COP MODE CONTROL

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

OC2/OC1 OC3/OC1 OC4/OC1 IC4/OC5/OC1 IC3 IC2 IC1

PORT G

PERIODIC INTERRUPT

CHIP SELECTS SCI RxD TxD PORT D

DDRG WAIT

CSPROG CSGEN CSIO1 CSIO2

PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0

1024 BYTES STATIC RAM

PD0 PD1

PE6 PE5 PE4 PE3 PE2 PE1

DDRD

CPU CORE

MISO MOSI SCK SS SPI

PD2 PD3 PD4 PD5

PORT E

ADDRESS BUS ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

DATA BUS DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PORT C DDRC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 R/W

PORT B

PORT F

PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Figure 2 MC68HC11FC0 Block Diagram

MC68HC11F1/FC0 MC68HC11FTS/D

PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7

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2 Pin Assignments and Signal Descriptions
2.1 MC68HC11F1 Pin Assignments

MODB/VSTBY

MODA/LIR

PC0/DATA0

PE7/AN7

PE3/AN3

PE6/AN6

PE2/AN2

9

8

7

6

5

4

3

2

PE5/AN5 62

4XOUT

EXTAL

XTAL

R/W

VRH

VSS

VRL

E

68

67

66

65

64

PC1/DATA1 PC2/DATA2 PC3/DATA3 PC4/DATA4 PC5/DATA5 PC6/DATA6 PC7/DATA7 RESET XIRQ IRQ PG7/CSPROG PG6/CSGEN PG5/CSIO1 PG4/CSIO2 PG3 PG2 PG1

1

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

63

61 60 59 58 57 56 55 54 53

PE1/AN1

PE4/AN4 PE0/AN0 PF0/ADDR0 PF1/ADDR1 PF2/ADDR2 PF3/ADDR3 PF4/ADDR4 PF5/ADDR5 PF6/ADDR6 PF7/ADDR7 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14

MC68HC11F1

52 51 50 49 48 47 46 45

35

36

37

38

39

40

29

30

31

32

33

34

41

42 PA0/IC3

PA7/PAI/OC1

Figure 3 MC68HC11F1 68-Pin PLCC Pin Assignments

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PA3/OC5/IC4/OC1

PA6/OC2/OC1

PA5/OC3/OC1

PA4/OC4/OC1

PB7/ADDR15

PA2/IC1

PD0/RxD

PD1/TxD

PD2/MISO

PD3/MOSI

PD4/SCK

PA1/IC2

PG0

PD5/SS

VDD

43

44

MC68HC11F1/FC0 MC68HC11FTS/D

PA3/OC5/IC4/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/PAI/OC1

PB7/ADDR15

PD3/MOSI

PD2/MISO

PD0/RXD

PD4/SCK

PD1/TXD

PA0/IC3

PA1/IC2

PA2/IC1

PD5/SS

PG0 62

VDD

NC

NC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

NC NC PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 PF2/ADDR2 PF1/ADDR1 PF0/ADDR0 PE0/AN0 PE4/AN4 NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 34 36 37 21 26 27 28 29 30 31 32 33 35 38 22 23 24 25 39 40

61 60 59 58 57 56 55 54 53 52

NC

NC PG1 PG2 PG3 PG4/CSIO2 PG5/CSIO1 PG6/CSGEN PG7/CSPROG IRQ XIRQ RESET PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 NC NC

MC68HC11F1

51 50 49 48 47 46 45 44 43 42 41

E

NC

NC

VRL

R/W

VSS

PE1/AN1

PE5/AN5

PE6/AN6

PE3/AN3

PE7/AN7

EXTAL

XTAL

VRH

NC

PE2AN2

MODA/LIR

4XOUT

Figure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP

MC68HC11F1/FC0 MC68HC11FTS/D

MODB/VSTBY

PC0/DATA0

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2.2 MC68HC11FC0 Pin Assignments

PA3/IC4/OC5/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/PAI/OC1

PB7/ADDR15

PD3/MOSI

PD2/MISO 51

PD4/SCK

64

62

61

60

59

58

57

56

55

54

53

52

63

50

49

PD0/RxD

PD1/TxD

PA0/IC3

PA1/IC2

PA2/IC1

PD5/SS

VDD

PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 PF2/ADDR2 PF1/ADDR1 PF0/ADDR0 VSS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

48 47 46 45 44 43 42

PG2 PG3 PG4/CSIO2 PG5/CSIO1 PG6/CSGEN PG7/CSPROG IRQ XIRQ RESET PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1

MC68HC11FC0

41 40 39 38 37 36 35 34 33

VDD

VSS

PE1

PE5

PE2

PE6

PE3

DS

E

WAIT

R/W

MODA/LIR

EXTAL

XTAL

Figure 5 MC68HC11FC0 64-Pin QFP Pin Assignments

MOTOROLA 10

MODB/VSTBY

PC0/DATA0

MC68HC11F1/FC0 MC68HC11FTS/D

PA3/IC4/OC5/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/PAI/OC1

PB7/ADDR15

PD3/MOSI

PD2/MISO

PD4/SCK

PD0/RXD 63

PD1/TXD

PA0/IC3

PA1/IC2

PA2/IC1

VDD

PD5/SS

PG0 62

NC

80

79

77

76

75

74

73

72

71

70

69

68

67

66

65

NC NC PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 PF2/ADDR2 PF1/ADDR1 PF0/ADDR0 VSS PE4 NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

78

64

61 60 59 58 57 56 55 54 53 52

NC

NC PG1 PG2 PG3 PG4/CSIO0 PG5/CSIO1 PG6/CSGEN PG7/CSPROG IRQ XIRQ RESET PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 NC NC

MC68HC11FC0

51 50 49 48 47 46 45 44 43 42 41

VSS

VDD

PE1

PE5

PE2

PE6

PE3

DS

E

NC

NC

WAIT

R/W

EXTAL

XTAL

NC

MODA/LIR

4XOUT

Figure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments

MC68HC11F1/FC0 MC68HC11FTS/D

MODB/VSTBY

PC0/DATA0

MOTOROLA 11

2.3 Pin Descriptions VDD and VSS VDD is the positive power input to the MCU, and VSS is ground. RESET This active-low input initializes the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or the COP watchdog circuits. XTAL and EXTAL These two pins provide the interface for either a crystal or a CMOS-compatible clock to drive the internal clock circuitry. The frequency applied to these pins is four times the desired bus frequency (E clock). E This pin provides an output for the E clock, the basic timing reference signal for the bus circuitry. The address bus is active when E is low, and the data bus is active when E is high. DS The data strobe output is the inverted E clock. DS is present on the MC68HC11FC0 only. WAIT This input is used to stretch the bus cycle to accomodate slower devices. The MCU samples the logic level at this pin on the rising edge of E clock. If it is high, the MCU holds the E clock high for the next four EXTAL clock cycles. If it is low, the E clock responds normally, going low two EXTAL cycles later. The WAIT pin is present on the MC68HC11FC0 only. 4XOUT This pin provides a buffered oscillator signal to drive another M68HC11 MCU. The 4XOUT pin is not present on the 64-pin QFP MC68HC11FC0 package. IRQ This active-low input provides a means of generating asynchronous, maskable interrupt requests for the CPU. XIRQ This interrupt request input can be made non-maskable by clearing the X bit in the MCU's condition code register. MODA/LIR and MODB/VSTBY The logic level applied to the MODA and MODB pins at reset determines the MCU's opreating mode (see Table 7 in 4 Operating Modes and System Initialization). After reset, MODA functions as LIR, an open-drain output that indicates the start of an instruction cycle. MODB functions as VSTBY, providing a backup battery to maintain the contents of RAM when VDD falls. R/W In expanded and test modes, R/W indicates the direction of transfers on the external data bus. VRH and VRL These pins provide the reference voltage for the analog-to-digital converter. Use bypass capacitors to minimize noise on these signals. Any noise on VRH and VRL will directly affect A/D accuracy. These pins are not present on the MC68HC11FC0.

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MC68HC11F1/FC0 MC68HC11FTS/D

Port Signals On the MC68HC11F1, 54 pins are arranged into six 8-bit ports (ports A, B, C, E, F, and G) and one 6-bit port (port D). On the MC68HC11FC0, either 52 or 49 pins are available, depending on the package. General-purpose I/O port signals are discussed briefly in the following pragraphs. For additional information, refer to 7 Parallel Input/Output. Port A Pins Port A is an 8-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data direction register (DDRA). Port A pins share functions with the 16-bit timer system. Out of reset, PA[7:0] are general-purpose high-impedance inputs. Port B Pins Port B is an 8-bit output-only port. In single-chip modes, port B pins are general-purpose output pins (PB[7:0]). In expanded modes, port B pins act as the high-order address lines ADDR[15:8]. Port C Pins Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data direction register (DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. In expanded modes, port C pins are configured as data bus pins DATA[7:0]. Port D Pins Port D is a 6-bit general-purpose I/O port with a data register (PORTD) and a data direction register (DDRD). The six port D lines PD[5:0] can be used for general-purpose I/O or for the serial communications interface (SCI) or serial peripheral interface (SPI) subsystems. Port E Pins Port E is an 8-bit input-only port that is also used as the analog input port for the analog-to-digital converter. Port E pins that are not used for the A/D system can be used as general-purpose inputs. However, PORTE should not be read during the sample portion of an A/D conversion sequence. NOTE The A/D system is not available on the MC68HC11FC0. PE7 and PE0 are not available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0 are not available on the 64-pin MC68HC11FC0. Port F Pins Port F is an 8-bit output-only port. In single-chip mode, port F pins are general-purpose output pins PF[7:0]. In expanded mode, port F pins act as the low-order address outputs ADDR[7:0]. Port G Pins Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are alternate functions of PG[7:4]. NOTE PG[1:0] are not available on the 64-pin MC68HC11FC0.

MC68HC11F1/FC0 MC68HC11FTS/D

MOTOROLA 13

3 Control Registers
The MC68HC11F1 and MC68HC11FC0 control registers determine most of the system's operating characteristics. They occupy a 96-byte relocatable memory block. Their names and bit mnemonics are summarized in the following table. Addresses shown are the default locations out of reset. 3.1 MC68HC11F1 Control Registers Table 5 MC68HC11F1 Register and Control Bit Assignments
$1000 $1001 $1002 $1003 $1004 $1005 $1006 $1007 $1008 $1009 $100A $100B $100C $100D $100E $100F $1010 $1011 $1012 $1013 $1014 $1015 $1016 $1017 $1018 $1019 $101A $101B $101C $101D $101E $101F $1020 $1021 Bit 7 PA7 DDA7 PG7 DDG7 PB7 PF7 PC7 DDC7 0 0 PE7 FOC1 OC1M7 OC1D7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 OM2 EDG4B 6 PA6 DDA6 PG6 DDG6 PB6 PF6 PC6 DDC6 0 0 PE6 FOC2 OC1M6 OC1D6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 OL2 EDG4A 5 PA5 DDA5 PG5 DDG5 PB5 PF5 PC5 DDC5 PD5 DDD5 PE5 FOC3 OC1M5 OC1D5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 OM3 EDG1B 4 PA4 DDA4 PG4 DDG4 PB4 PF4 PC4 DDC4 PD4 DDD4 PE4 FOC4 OC1M4 OC1D4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 OL3 EDG1A 3 PA3 DDA3 PG3 DDG3 PB3 PF3 PC3 DDC3 PD3 DDD3 PE3 FOC5 OC1M3 OC1D3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 OM4 EDG2B 2 PA2 DDA2 PG2 DDG2 PB2 PF2 PC2 DDC2 PD2 DDD2 PE2 0 0 0 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 OL4 EDG2A 1 PA1 DDA1 PG1 DDG1 PB1 PF1 PC1 DDC1 PD1 DDD1 PE1 0 0 0 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 OM5 EDG3B Bit 0 PA0 DDA0 PG0 DDG0 PB0 PF0 PC0 DDC0 PD0 DDD0 PE0 0 0 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 OL5 EDG3A PORTA DDRA PORTG DDRG PORTB PORTF PORTC DDRC PORTD DDRD PORTE CFORC OC1M OC1D TCNT (High) TCNT (Low) TIC1 (High) TIC1 (Low) TIC2 (High) TIC2 (Low) TIC3 (High) TIC3 (Low) TOC1 (High) TOC1 (Low) TOC2 (High) TOC2 (Low) TOC3 (High) TOC3 (Low) TOC4 (High) TOC4 (Low) TI4/O5 (High) TI4/O5 (Low) TCTL1 TCTL2

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MC68HC11F1/FC0 MC68HC11FTS/D

Table 5 MC68HC11F1 Register and Control Bit Assignments (Continued)
Bit 7 $1022 $1023 $1024 $1025 $1026 $1027 $1028 $1029 $102A $102B $102C $102D $102E $102F $1030 $1031 $1032 $1033 $1034 $1035 $1036 $1037 $1038 $1039 $103A $103B $103C $103D $103E $103F $1040 to $105B $105C $105D $105E $105F I01SA I01EN GA15 I01AV I01SB I01PL GA14 I02AV I02SA I02EN GA13 0 I02SB I02PL GA12 GNPOL GSTHA GCSPR GA11 GAVLD GSTGB PCSEN GA10 GSIZA PSTHA PSIZA 0 GSIZB PSTHB PSIZB 0 GSIZC GWOM 0 Bit 7 ODD RBOOT RAM3 TILOP EE3 CWOM 0 6 EVEN SMOD RAM2 0 EE2 CLK4X IRQE 5 0 MDA RAM1 OCCR EE1 LIRDV DLY 4 BYTE IRV RAM0 CBYP EE0 0 CME 3 ROW PSEL3 REG3 DISR 1 SPRBYP FCME 2 ERASE PSEL2 REG2 FCM NOCOP 0 CR1 1 EELAT PSEL1 REG1 FCOP 1 0 CR0 Bit 0 EEPGM PSEL0 REG0 0 EEON OC1I OC1F TOI TOF 0 Bit 7 SPIE SPIF Bit 7 TCLR R8 TIE TDRE Bit 7 CCF Bit 7 Bit 7 Bit 7 Bit 7 0 6 OC2I OC2F RTII RTIF PAEN 6 SPE WCOL 6 SCP2 T8 TCIE TC 6 0 6 6 6 6 0 5 OC3I OC3F PAOVI PAOVF PAMOD 5 DWOM 0 5 SCP1 0 RIE RDRF 5 SCAN 5 5 5 5 0 4 OC4I OC4F PAII PAIF PEDGE 4 MSTR MODF 4 SCP0 M ILIE IDLE 4 MULT 4 4 4 4 PTCON 3 I4/O5I I4/O5F 0 0 0 3 CPOL 0 3 RCKB WAKE TE OR 3 CD 3 3 3 3 BPRT3 2 IC1I IC1F 0 0 I4/05 2 CPHA 0 2 SCR2 0 RE NF 2 CC 2 2 2 2 BPRT2 1 IC2I IC2F PR1 0 RTR1 1 SPR1 0 1 SCR1 0 RWU FE 1 CB 1 1 1 1 BPRT1 Bit 0 IC3I IC3F PR0 0 RTR0 Bit 0 SPR0 0 Bit 0 SCR0 0 SBK 0 Bit 0 CA Bit 0 Bit 0 Bit 0 Bit 0 BPRT0 TMSK1 TFLG1 TMSK2 TFLG2 PACTL PACNT SPCR SPSR SPDR BAUD SCCR1 SCCR2 SCSR SCDR ADCTL ADR1 ADR2 ADR3 ADR4 BPROT Reserved Reserved OPT2 OPTION COPRST PPROG HPRIO INIT TEST1 CONFIG Reserved Reserved CSSTRH CSCTL CSGADR CSGSIZ

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MOTOROLA 15

3.2 MC68HC11FC0 Control Registers Table 6 MC68HC11FC0 Register and Control Bit Assignments
$1000 $1001 $1002 $1003 $1004 $1005 $1006 $1007 $1008 $1009 $100A $100B $100C $100D $100E $100F $1010 $1011 $1012 $1013 $1014 $1015 $1016 $1017 $1018 $1019 $101A $101B $101C $101D $101E $101F $1020 $1021 $1022 $1023 $1024 $1025 Bit 7 PA7 DDA7 PG7 DDG7 PB7 PF7 PC7 DDC7 0 0 PE7 FOC1 OC1M7 OC1D7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 OM2 EDG4B OC1I OC1F TOI TOF 6 PA6 DDA6 PG6 DDG6 PB6 PF6 PC6 DDC6 0 0 PE6 FOC2 OC1M6 OC1D6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 OL2 EDG4A OC2I OC2F RTII RTIF 5 PA5 DDA5 PG5 DDG5 PB5 PF5 PC5 DDC5 PD5 DDD5 PE5 FOC3 OC1M5 OC1D5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 OM3 EDG1B OC3I OC3F PAOVI PAOVF 4 PA4 DDA4 PG4 DDG4 PB4 PF4 PC4 DDC4 PD4 DDD4 PE4 FOC4 OC1M4 OC1D4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 OL3 EDG1A OC4I OC4F PAII PAIF 3 PA3 DDA3 PG3 DDG3 PB3 PF3 PC3 DDC3 PD3 DDD3 PE3 FOC5 OC1M3 OC1D3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 OM4 EDG2B I4/O5I I4/O5F 0 0 2 PA2 DDA2 PG2 DDG2 PB2 PF2 PC2 DDC2 PD2 DDD2 PE2 0 0 0 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 OL4 EDG2A IC1I IC1F 0 0 1 PA1 DDA1 PG1 DDG1 PB1 PF1 PC1 DDC1 PD1 DDD1 PE1 0 0 0 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 OM5 EDG3B IC2I IC2F PR1 0 Bit 0 PA0 DDA0 PG0 DDG0 PB0 PF0 PC0 DDC0 PD0 DDD0 PE0 0 0 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 OL5 EDG3A IC3I IC3F PR0 0 PORTA DDRA PORTG DDRG PORTB PORTF PORTC DDRC PORTD DDRD PORTE CFORC OC1M OC1D TCNT (High) TCNT (Low) TIC1 (High) TIC1 (Low) TIC2 (High) TIC2 (Low) TIC3 (High) TIC3 (Low) TOC1 (High) TOC1 (Low) TOC2 (High) TOC2 (Low) TOC3 (High) TOC3 (Low) TOC4 (High) TOC4 (Low) TI4/O5 (High) TI4/O5 (Low) TCTL1 TCTL2 TMSK1 TFLG1 TMSK2 TFLG2

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MC68HC11F1/FC0 MC68HC11FTS/D

Table 6 MC68HC11FC0 Register and Control Bit Assignments (Continued)
Bit 7 $1026 $1027 $1028 $1029 $102A $102B $102C $102D $102E $102F $1030 to $1037 $1038 $1039 $103A $103B $103C $103D $103E $103F $1040 to $105B $105C $105D $105E $105F I01SA I01EN GA15 I01AV I01SB I01PL GA14 I02AV I02SA I02EN GA13 0 I02SB I02PL GA12 GNPOL GSTHA GCSPR GA11 GAVLD GSTGB PCSEN GA10 GSIZA PSTHA PSIZA 0 GSIZB PSTHB PSIZB 0 GSIZC RBOOT RAM5 TILOP 0 SMOD RAM4 0 0 MDA RAM3 OCCR 0 IRV RAM2 CBYP 0 PSEL3 RAM1 DISR 0 PSEL2 RAM0 FCM NOCOP PSEL1 REG1 FCOP 0 PSEL0 REG0 0 0 GWOM 0 Bit 7 CWOM 0 6 CLK4X IRQE 5 LIRDV DLY 4 0 CME 3 SPRBYP FCME 2 0 CR1 1 0 CR0 Bit 0 0 Bit 7 SPIE SPIF Bit 7 TCLR R8 TIE TDRE Bit 7 6 PAEN 6 SPE WCOL 6 SCP2 T8 TCIE TC 6 5 PAMOD 5 DWOM 0 5 SCP1 0 RIE RDRF 5 4 PEDGE 4 MSTR MODF 4 SCP0 M ILIE IDLE 4 3 0 3 CPOL 0 3 RCKB WAKE TE OR 3 2 I4/05 2 CPHA 0 2 SCR2 0 RE NF 2 1 RTR1 1 SPR1 0 1 SCR1 0 RWU FE 1 Bit 0 RTR0 Bit 0 SPR0 0 Bit 0 SCR0 0 SBK 0 Bit 0 PACTL PACNT SPCR SPSR SPDR BAUD SCCR1 SCCR2 SCSR SCDR Reserved Reserved OPT2 OPTION COPRST Reserved HPRIO INIT TEST1 CONFIG Reserved Reserved CSSTRH CSCTL CSGADR CSGSIZ

MC68HC11F1/FC0 MC68HC11FTS/D

MOTOROLA 17

4 Operating Modes and System Initialization
The 16-bit address bus can access 64 Kbytes of memory. Because the MC68HC11F1 and MC68HC11FC0 are intended to operate principally in expanded mode, there is no internal ROM and the address bus is non-multiplexed. Both devices include 1 Kbyte of static RAM, a 96-byte control register block, and 256 bytes of bootstrap ROM. The MC68HC11F1 also includes 512 bytes of EEPROM. RAM and registers can be remapped on both the MC68HC11F1 and the MC68HC11FC0. On both the MC68HC11F1 and the MC68HC11FC0, out of reset RAM resides at $0000 to $03FF and registers reside at $1000 to $105F. On the MC68HC11F1, RAM and registers can both be remapped to any 4Kbyte boundary. On the MC68HC11FC0, RAM can be remapped to any 1-Kbyte boundary, and registers can be remapped to any 4-Kbyte boundary in the first 16 Kbytes of address space. RAM and control register locations are defined by the INIT register, which can be written only once within the first 64 E-clock cycles after a reset in normal modes. It becomes a read-only register thereafter. If RAM and the control register block are mapped to the same boundary, the register block has priority of the first 96 bytes. In expanded and special test modes in the MC68HC11F1, EEPROM is located from $xE00 to $xFFF, where x represents the value of the four high-order bits of the CONFIG register. EEPROM is enabled by the EEON bit of the CONFIG register. In single-chip and bootstrap modes, the EEPROM is located from $FE00 to $FFFF. 4.1 Operating Modes Bootstrap ROM resides at addresses $BF00­$BFFF, and is only available when the MCU operates in special bootstrap operating mode. Operating modes are determined by the logic levels applied to the MODB and MODA pins at reset. In single-chip mode, the MCU functions as a self-contained microcontroller and has no external address or data bus. Ports B, C and F are available for general-purpose I/O (GPIO). Ports B and F are outputs only; each of the port C pins can be configured as input or output. CAUTION The MC68HC11FC0 must not be configured to boot in single-chip mode because it has no internal ROM or EEPROM. Operation of the device in single-chip mode will result in erratic behavior. In expanded mode, the MCU can access external memory. Ports B and F provide the address bus, and port C is the data bus. Special bootstrap mode is a variation of single chip mode that provides access to the internal bootstrap ROM. In this mode, the user can download a program into on-chip RAM through the serial communication interface (SCI). Special test mode, a variation of expanded mode, is primarily used during Motorola's internal production testing, but can support emulation and debugging during program development. Table 7 shows a summary of operating modes, mode select pins, and control bits in the HPRIO register. Table 7 Hardware Mode Select Summary
Input Pins MODB MODA 1 0 1 1 0 0 0 1 Mode Description Single Chip Expanded Special Bootstrap Special Test Control Bits in HPRIO (Latched at Reset) RBOOT SMOD MDA 0 0 0 0 0 1 1 1 0 0 1 1

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MC68HC11F1/FC0 MC68HC11FTS/D

4.2 Memory Maps
x000 1024 BYTES RAM1 $03FF -- -- EXTERNAL $1000 -- $105F -- -- -- -- -- -- -- y05F -- -- EXTERNAL y000 96-BYTE REGISTER FILE2 x3FF

$0000 --

--

--

--

EXTERNAL

EXTERNAL

$BFC0 $BF00 -- -- -- -- 256 BYTES BOOTSTRAP ROM SPECIAL MODE INTERRUPT VECTORS3 $BFFF RESERVED4 $FE00 -- $FFC0 -- $FFFF -- SINGLE CHIP MODA = 0 MODB = 1 -- -- EXPANDED -- -- SPECIAL BOOTSTRAP MODA = 0 MODB = 0 -- -- SPECIAL TEST MODA = 1 MODB = 0 512 BYTES EEPROM5 $FFC0 NORMAL MODE INTERRUPT VECTORS $FFFF

$BFFF --

--

--

--

MODA = 1 MODB = 1

NOTES: 1. RAM can be remapped to any 4-Kbyte boundary ($x000). "x" represents the value contained in RAM[3:0] in the INIT register. 2. The register block can be remapped to any 4-Kbyte boundary ($y000). "y" represents the value contained in REG[3:0] in the INIT register. 3. Special test mode vectors are externally addressed. 4. In special test mode the address locations $zD00--$zDFF are not externally addressable. "z" represents the value of bits EE[3:0] in the CONFIG register. 5. EEPROM can be remapped to any 4-Kbyte boundary ($z000). "z" represents the value contained in EE[3:0] in the CONFIG register.

Figure 7 MC68HC11F1 Memory Map

MC68HC11F1/FC0 MC68HC11FTS/D

MOTOROLA 19

$0000 --

--

--

-- 1024 BYTES RAM1

$03FF --

-- EXTERNAL

--

-- EXTERNAL

$1000 -- $105F --

-- --

-- --

-- -- 96-BYTE REGISTER FILE2

EXTERNAL

EXTERNAL

$BFC0 $BF00 -- -- -- -- 256 BYTES BOOTSTRAP ROM SPECIAL MODE INTERRUPT VECTORS $BFFF $FFC0 $FE00 -- $FFC0 -- $FFFF -- SINGLE CHIP MODA = 0 MODB = 1 -- -- EXPANDED -- -- SPECIAL BOOTSTRAP MODA = 0 MODB = 0 -- -- SPECIAL TEST MODA = 1 MODB = 0 NORMAL MODE INTERRUPT VECTORS $FFFF

$BFFF --

--

--

--

MODA = 1 MODB = 1

NOTES: 1. RAM can be remapped to any 1-Kbyte boundary, depending on the value contained in the RAM field in the INIT register. 2. The register block can be remapped to $0000, $2000, or $3000, depending on the value contained in REG[1:0] in the INIT register.

Figure 8 MC68HC11FC0 Memory Map 4.3 System Initialization Registers HPRIO -- Highest Priority Interrupt and Miscellaneous
Bit 7 RBOOT RESET: 0 0 1 0 6 SMOD 0 0 1 1 5 MDA 0 1 0 1 4 IRV 0 0 1 1 3 PSEL3 0 0 0 0 2 PSEL2 1 1 1 1 1 PSEL1 0 0 0 0 Bit 0 PSEL0 1 1 1 1 Single-Chip Expanded Bootstrap Special Test

$x03C

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MC68HC11F1/FC0 MC68HC11FTS/D

RBOOT -- Read Bootstrap ROM RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT can only be written in special modes but can be read anytime. 0 = Boot loader ROM disabled and not in memory map 1 = Boot loader ROM enabled and in memory map at $BF00­$BFFF SMOD and MDA -- Special Mode Select and Mode Select A The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge of reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge of reset. These two bits can be read at any time. They can be written at any time in special modes. Neither bit can be written in normal modes. SMOD cannot be set once it has been cleared. Refer to Table 8. Table 8 Hardware Mode Select Summary
Input Pins MODB 1 1 0 0 MODA 0 1 0 1 Mode Description Single Chip Expanded Special Bootstrap Special Test Control Bits in HPRIO (Latched at Reset) RBOOT 0 0 1 0 SMOD 0 0 1 1 MDA 0 1 0 1

IRV -- Internal Read Visibility This bit can be read at any time. It can be written at any time in special modes, but only once in normal modes. In single-chip and bootstrap modes, IRV has no meaning or effect. 0 = Internal reads not visible 1 = Data from internal reads is driven on the external data bus PSEL[3:0] -- See 5.2 Reset and Interrupt Registers, page 27. INIT -- RAM and I/O Mapping (MC68HC11FC0 only)
Bit 7 RAM5 RESET: 0 6 RAM4 0 5 RAM3 0 4 RAM2 0 3 RAM1 0 2 RAM0 0 1 REG1 0 Bit 0 REG0 1

$x03D

The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. NOTE The register diagram above applies to the MC68HC11FC0 only. A diagram and bit descriptions of the INIT register in the MC68HC11F1 are provided elsewhere in this section. RAM[5:0] -- Internal RAM Map Position These bits determine the upper six bits of the RAM address and allow mapping of the RAM to any oneKbyte boundary. REG[1:0] -- Register Block Map Position These bits determine the location of the register block, as shown in Table 9. Table 9 Register Block Location
REG[1:0] 00 01 10 11 Register Block Address $0000 ­ $005F $1000 ­ $105F $2000 ­ $205F $3000 ­ $305F

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INIT -- RAM and I/O Mapping (MC68HC11F1 only)
Bit 7 RAM3 RESET: 0 6 RAM2 0 5 RAM1 0 4 RAM0 0 3 REG3 0 2 REG4 0 1 REG1 0 Bit 0 REG0 1

$x03D

The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. NOTE The register diagram above applies to the MC68HC11F1 only. A diagram and bit descriptions of the INIT register in the MC68HC11FC0 are provided elsewhere in this section. RAM[3:0] -- Internal RAM Map Position These bits determine the upper four bits of the RAM address and allow mapping of the RAM to any fourKbyte boundary. Refer to Table 10. REG[3:0] -- 96-Byte Register Block Map Position These bits determine bits the upper 4 bits of the register block and allow mapping of the register block to any four-Kbyte boundary. Refer to Table 10. Table 10 RAM and Register Mapping
RAM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Location $0000-$03FF $1000-$13FF $2000-$23FF $3000-$33FF $4000-$43FF $5000-$53FF $6000-$63FF $7000-$73FF $8000-$83FF $9000-$93FF $A000-$A3FF $B000-$B3FF $C000-$C3FF $D000-$D3FF $E000-$E3FF $F000-$F3FF REG[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Location $0000-$005F $1000-$105F $2000-$205F $3000-$305F $4000-$405F $5000-$505F $6000-$605F $7000-$705F $8000-$805F $9000-$905F $A000-$A05F $B000-$B05F $C000-$C05F $D000-$D05F $E000-$E05F $F000-$F05F

OPT2 -- System Configuration Option Register 2
Bit 7 GWOM RESET 0 6 CWOM 0 5 CLK4X 1 4 LIRDV 0 3 -- 0 2 SPRBYP 0 1 -- 0 Bit 0 -- 0

$x038

GWOM -- Port G Wired-OR Mode Option Refer to 7.8 Parallel I/O Registers, page 36.

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MC68HC11F1/FC0 MC68HC11FTS/D

CWOM -- Port C Wired-OR Mode Option Refer to 7.8 Parallel I/O Registers, page 37. CLK4X -- 4XCLK Output Enable This bit can only be written once after reset in all modes. 0 = 4XOUT clock output is disabled 1 = Buffered oscillator is driven on the 4XOUT clock output LIRDV -- Load Instruction Register Driven In order to detect consecutive instructions in a high-speed application, LIR can be driven high for one quarter of an E-clock cycle during each instruction fetch. 0 = LIR signal is not driven high. 1 = LIR signal is driven high. Bits 3, 1, 0 -- Not implemented. Reads always return zero and writes have no effect. SPRBYP -- See 10.2 SPI Registers, page 52. OPTION -- System Configuration Options
Bit 7 ADPU RESET: 0 6 CSEL 0 5 IRQE* 0 4 DLY* 1 3 CME 0 2 FCME* 0 1 CR1* 0 Bit 0 CR0* 0

$x039

*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.

ADPU -- A/D Power-Up This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero and writes have no effect. 0 = A/D system disabled 1 = A/D system enabled CSEL -- Clock Select This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero and writes have no effect. 0 = A/D and EEPROM use system E clock 1 = A/D and EEPROM use internal RC clock IRQE -- IRQ Select Edge Sensitive Only 0 = Low level recognition 1 = Falling edge recognition DLY -- Enable Oscillator Start-Up Delay on Exit from STOP 0 = No stabilization delay on exit from STOP 1 = Stabilization delay of 4064 E-clock cycles is enabled on exit from STOP CME -- Clock Monitor Enable 0 = Clock monitor disabled; slow clocks can be used 1 = Slow or stopped clocks cause clock failure reset FCME -- Force Clock Monitor Enable 0 = Clock monitor circuit follows the state of the CME bit 1 = Clock monitor circuit is enabled until the next reset In order to use both STOP and the clock monitor, the CME bit should be written to zero prior to executing a STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if the user intends to use the STOP instruction. CR[1:0] -- COP Timer Rate Select Refer to 5.2 Reset and Interrupt Registers, page 27.

MC68HC11F1/FC0 MC68HC11FTS/D

MOTOROLA 23

CONFIG -- EEPROM Mapping, COP, EEPROM Enables
Bit 7 EE3 RESET U 6 EE2 U 5 EE1 U 4 EE0 U 3 1 1 2 NOCOP U 1 1 1 Bit 0 EEON U

$x03F

U = Unaffected by reset

Bits 7:3 -- See 6.2 EEPROM Registers, page 30. (These bits are implemented on the MC68HC11F1 only.) NOCOP -- COP System Disable 0 = COP enabled (forces reset on time-out) 1 = COP disabled (does not force reset on time-out) TEST1 -- Factory Test
Bit 7 TILOP RESET: 0 6 0 0 5 OCCR 0 4 CBYP 0 3 DISR -- 2 FCM 0 1 FCOP 0 Bit 0 0 0

$x03E

These bits can only be written in test and bootstrap modes. TILOP -- Test Illegal Opcode This test mode allows serial testing of all illegal opcodes without servicing an interrupt after each illegal opcode is fetched. 0 = Normal operation (trap on illegal opcodes) 1 = Inhibit LIR when an illegal opcode is found Bit 6 -- Not implemented. Reads always return zero and writes have no effect. OCCR -- Output Condition Code Register to Timer Port 0 = Normal operation 1 = Condition code bits H, N, Z, V and C are driven on PA[7:3] to allow a test system to monitor CPU operation CBYP -- Timer Divider Chain Bypass 0 = Normal operation 1 = The 16-bit free-running timer is divided into two 8-bit halves and the prescaler is bypassed. The system E clock drives both halves directly. DISR -- Disable Resets from COP and Clock Monitor In test and bootstrap modes, this bit is reset to one to inhibit clock monitor and COP resets. In normal modes, DISR is reset to zero. 0 = Normal operation 1 = COP and Clock Monitor failure do not generate a system reset FCM -- Force Clock Monitor Failure 0 = Normal operation 1 = Generate an immediate clock monitor failure reset. Note that the CME bit in the OPTION register must also be set in order to force the reset. FCOP -- Force COP Watchdog Failure 0 = Normal operation 1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register must be cleared (COP enabled) in order to force the reset. Bit 0 -- Not implemented. Reads always return zero and writes have no effect.

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MC68HC11F1/FC0 MC68HC11FTS/D

5 Resets and Interrupts
There are three sources of reset on the MC68HC11F1 and MC68HC11FC0, each having its own reset vector: · RESET pin · Clock monitor failure · Computer operating properly (COP) failure There are 22 interrupt sources serviced by 18 interrupt vectors. (The SCI interrupt vector services five SCI interrupt sources.) Three of the interrupt vectors are non-maskable: · Illegal opcode trap · Software interrupt · XIRQ pin (pseudo non-maskable interrupt) The other 19 interrupts, generated mostly by on-chip peripheral systems, are maskable. Maskable interrupts are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts have a default priority arrangement out of reset. However, any one interrupt source can be elevated to the highest maskable priority position by writing to the HPRIO register. This register can be written at any time, provided the I bit in the CCR is set. In addition to the global I bit, all maskable interrupt sources except the external interrupt (IRQ pin) are subject to local enable bits in control registers. Each of these interrupt sources also sets a corresponding flag bit in a control register that can be polled by software. Several of these flags are automatically cleared during the normal course of responding to the interrupt requests. For example, the RDRF flag is set when a byte has been received in the SCI. The normal response to an RDRF interrupt request is to read the SCI status register to check for receive errors, then to read the received data from the SCI data register. It is precisely these two steps that are required to clear the RDRF flag, so no further instructions are necessary. 5.1 Interrupt Sources The following table summarizes the interrupt sources, vector addresses, masks, and flag bits.

MC68HC11F1/FC0 MC68HC11FTS/D

MOTOROLA 25

Table 11 Interrupt and Reset Vector Assignments
Vector Address FFC0, C1 to FFD4, D5 FFD6, D7 Interrupt Source CCR Mask Local Mask Flag Bit

Reserved SCI Serial System SCI Transmit Complete SCI Transmit Data Register Empty SCI Idle Line Detect SCI Receiver Overrun SCI Receive Data Register Full

--

--

--

TCIE I Bit TIE ILIE RIE RIE I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit X Bit None None None None None SPIE PAII PAOVI TOI I4/O5I OC4I OC3I OC2I OC1I IC3I IC2I IC1I RTII None None None None NOCOP CME None

TC TDRE IDLE OR RDRF SPIF PAIF PAOVF TOF I4/O5F OC4F OC3F OC2F OC1F IC3F IC2F IC1F RTIF None None None None None None None

FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF

SPI Serial Transfer Complete Pulse Accumulator Input Edge Pulse Accumulator Overflow Timer Overflow Timer Input Capture 4/Output Compare 5 Timer Output Compare 4 Timer Output Compare 3 Timer Output Compare 2 Timer Output Compare 1 Timer Input Capture 3 Timer Input Capture 2 Timer Input Capture 1 Real-Time Interrupt IRQ XIRQ Pin Software Interrupt Illegal Opcode Trap COP Failure Clock Monitor Fail RESET

5.2 Reset and Interrupt Registers OPTION -- System Configuration Options
Bit 7 ADPU RESET: 0 6 CSEL 0 5 IRQE* 0 4 DLY* 1 3 CME 0 2 FCME* 0 1 CR1* 0 Bit 0 CR0* 0

$x039

*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.

Bits [7:6], [4:2] Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56. IRQE -- IRQ Select Edge Sensitive Only 0 = Low level recognition 1 = Falling edge recognition

MOTOROLA 26

MC68HC11F1/FC0 MC68HC11FTS/D

CR[1:0] -- COP Timer Rate Select The COP system is driven by a constant frequency of E/215. CR[1:0] specify an additional divide-by factor to arrive at the COP time-out rate. Table 12 COP Watchdog Time-Out Periods
Frequency 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz Any E Tolerance -0/+32.768 ms -0/+16.384 ms -0/+10.923 ms -0/+8.192 ms -0/+6.554 ms -0/+5.461 ms -0/+215/E CR[1:0] = 00 32.768 ms 16.384 ms 10.923 ms 8.192 ms 6.554 ms 5.461 ms 215/E CR[1:0] = 01 131.072 ms 65.536 ms 43.691 ms 32.768 ms 26.214 ms 21.845 217/E CR[1:0] = 10 524.288 ms 262.144 ms 174.763 ms 131.072 ms 104.858 ms 87.381 ms 219/E CR[1:0] = 11 2.097 s 1.049 s 699.051 ms 524.288 ms 419.430 ms 349.525 ms 221/E

COPRST -- Arm/Reset COP Timer Circuitry
Bit 7 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 0 0

$x03A

Write $55 to COPRST to arm the COP watchdog clearing mechanism. Then write $AA to COPRST to reset the COP timer. Performing instructions between these two steps is possible provided both steps are completed in the correct sequence before the timer times out. HPRIO -- Highest Priority I-Bit Interrupt and Miscellaneous
Bit 7 RBOOT RESET: 6 SMOD 5 MDA 4 IRV 3 PSEL3 0 2 PSEL2 1 1 PSEL1 0 Bit 0 PSEL0 1

$x03C

Bits [7:4] -- See 4.3 System Initialization Registers, page 20. PSEL[3:0] -- Interrupt Priority Select Bits Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt source to have priority over other I-bit related sources. Table 13 Highest Priority Interrupt Selection
PSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Interrupt Source Promoted Timer Overflow Pulse Accumulator Overflow Pulse Accumulator Input Edge SPI Serial Transfer Complete SCI Serial System Reserved (Default to IRQ) IRQ (External Pin) Real-Time Interrupt Timer Input Capture 1 Timer Input Capture 2 Timer Input Capture 3

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Table 13 Highest Priority Interrupt Selection (Continued)
PSEL[3:0] 1011 1100 1101 1110 1111 Interrupt Source Promoted Timer Output Compare 1 Timer Output Compare 2 Timer Output Compare 3 Timer Output Compare 4 Timer Output Compare 5/Input Capture 4

CONFIG -- EEPROM Mapping, COP, EEPROM Enables
Bit 7 EE3 RESET U 6 EE2 U 5 EE1 U 4 EE0 U 3 1 1 2 NOCOP U 1 1 1 Bit 0 EEON U

$x03F

Bits 7:3, 1:0 -- See 6.2 EEPROM Registers, page 30. NOCOP -- COP System Disable 0 = COP enabled (forces reset on time-out) 1 = COP disabled (does not force reset on time-out)

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6 Electrically Erasable Programmable ROM
The MC68HC11F1 has 512 bytes of electrically erasable programmable ROM (EEPROM). A nonvolatile, EEPROM-based configuration register (CONFIG) controls whether the EEPROM is present or absent and determines its position in the memory map. In single-chip and bootstrap modes the EEPROM is positioned at $FE00­$FFFF. In expanded and special test modes, the EEPROM can be repositioned to any 4-Kbyte boundary ($xE00­$xFFF). NOTE EEPROM is available on the MC68HC11F1 only. 6.1 EEPROM Operation The EEON bit in CONFIG controls whether the EEPROM is present in the memory map. When EEON = 1, the EEPROM is enabled. When EEON = 0, the EEPROM is disabled and removed from the memory map. EEON is forced to one out of reset in single-chip and special bootstrap modes to enable EEPROM. EEON is forced to zero out of reset in special test mode to remove EEPROM from the memory map, although test software can turn it back on. In normal expanded mode, EEON is reset to the value last programmed into CONFIG. An on-chip charge pump develops the high voltage required for programming and erasing. When the E-clock frequency is 1 MHz or above, the charge pump is driven by the E-clock. When the E-clock frequency is less than 1 MHz, select the internal RC oscillator to drive the EEPROM charge pump by writing one to the CSEL bit in the OPTION register. Refer to the discussion of the OPTION register in 4.3 System Initialization Registers, page 23. 6.2 EEPROM Registers BPROT -- Block Protect
Bit 7 0 RESET 0 6 0 0 5 0 0 4 PTCON 1 3 BPRT3 1 2 BPRT2 1 1 BPRT1 1 Bit 0 BPRT0 1

$x035

Bits [7:5] -- Not implemented. Reads always return zero and writes have no effect. PTCON -- Protect for CONFIG 0 = CONFIG register can be programmed or erased normally 1 = CONFIG register cannot be programmed or erased BPRT[3:0] -- Block Protect Bits for EEPROM 0 = Protection disabled 1 = Protection enabled Table 14 Block Protect Bits for EEPROM
Bit Name BPRT3 BPRT2 PBRT1 BPRT0 Block Protected $xEE0­xFFF $xE60­xEDF $xE20­xE5F $xE00­xE1F Block Size 288 Bytes 128 Bytes 64 Bytes 32 Bytes

NOTE Block protect register bits can be written to zero (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special modes. Block protect register bits can be written to one (protection enabled) at any time.

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PPROG -- EEPROM Programming Control
Bit 7 ODD RESET 0 6 EVEN 0 5 0 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0 Bit 0 EEPGM 0

$x03B

ODD -- Program Odd Rows (TEST) EVEN -- Program Even Rows (TEST) ROW and BYTE -- Row Erase Select Bit and Byte Erase Select The value of these bits determines the manner in which EEPROM is erased. Bit encodings are shown in 6.2 EEPROM Registers, page 30. Table 15 ROW and BYTE Encodings
BYTE 0 0 1 1 ROW 0 1 0 1 Action Bulk Erase (All 512 Bytes) Row Erase (16 Bytes) Byte Erase Byte Erase

ERASE -- Erase/Normal Control for EEPROM 0 = Normal read or program mode 1 = Erase mode EELAT -- EEPROM Latch Control 0 = EEPROM address and data bus configured for normal reads 1 = EEPROM address and data bus configured for programming or erasing EEPGM -- EEPROM Program Command 0 = Program or erase voltage to EEPROM array switched off 1 = Program or erase voltage to EEPROM array switched on CONFIG -- EEPROM Mapping, COP, EEPROM Enables
Bit 7 EE3 RESET U 6 EE2 U 5 EE1 U 4 EE0 U 3 1 1 2 NOCOP U 1 1 1 Bit 0 EEON U

$x03F

U = Unaffected by reset.

The CONFIG register is used to assign EEPROM a location in the memory map and to enable or disable EEPROM operation. Bits in this register are user-programmed except when forced to certain values, as noted in the following bit descriptions. EE[3:0] -- EEPROM Map Position EEPROM is located at $xE00 ­ $xFFF, where x is the value represented by these four bits. In singlechip and bootstrap modes, EEPROM is forced to $FE00 ­ $FFFF, regardless of the state of these bits. On factory-fresh devices, EE[3:0] = $0. Bit 3 -- Not implemented. Reads always return one and writes have no effect. NOCOP -- COP System Disable 0 = COP enabled (forces reset on time-out) 1 = COP disabled (does not force reset on time-out)

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Bit 1 -- Not implemented. Reads always return one and writes have no effect. EEON -- EEPROM Enable This bit is forced to one in single-chip and bootstrap modes. In test mode, EEON is forced to zero out of reset. In expanded mode, the EEPROM obeys the state of this bit. 0 = EEPROM is removed from the memory map. 1 = EEPROM is present in the memory map. Refer to 6.4 CONFIG Register Programming for instructions on programming this register. 6.3 EEPROM Programming and Erasure Programming and erasing the EEPROM is controlled by the PPROG register, subject to the block protect (BPROT) register value. To erase the EEPROM, ensure that the proper bits of the BPROT register are cleared, and then complete the following steps: 1. Write to PPROG with the ERASE and EELAT bits set and the BYTE and ROW bits set or cleared as appropriate. 2. Write to the appropriate EEPROM address with any data. Row erase ($xE00­$xE0F, $xE10­ $xE1F,... $xFF0­$xFFF) requires a single write to any location in the row. Perform bulk erase by writing to any location in the array. 3. Write to PPROG with the ERASE, EELAT, and EEPGM bits set and the BYTE and ROW bits set or cleared as appropriate. 4. Delay for 10 ms (20 ms for low-voltage operation). 5. Clear the EEPGM bit in PPROG to turn off the high voltage. 6. Clear the PPROG register to reconfigure EEPROM address and data buses for normal operations. To program the EEPROM, ensure that the proper bits of the BPROT register are cleared, and then complete the following steps: 1. 2. 3. 4. 5. 6. Write to PPROG with the EELAT bit set. Write data to the desired address. Write to PPROG with the EELAT and EEPGM bits set. Delay for 10 ms (20 ms for low-voltage operation). Clear the EEPGM bit in PPROG to turn off the high voltage. Clear the PPROG register to reconfigure EEPROM address and data buses for normal operations.

6.3.1 Programming a Byte The following example shows how to program an EEPROM byte. This example assumes that the appropriate bits in BPROT are cleared and that the data to be programmed is present in accumulator A.
PROG LDAB STAB STAA LDAB STAB JSR CLR #$02 $103B $FE00 #$03 $103B DLY10 $103B EELAT=1, EEPGM=0 Set EELAT bit Store data to EEPROM address EELAT=1, EEPGM=1 Turn on programming voltage Delay 10 ms Turn off high voltage and set to READ mode

6.3.2 Bulk Erase The following example shows how to bulk erase the 512-byte EEPROM. The CONFIG register is not affected in this example. Note that when the CONFIG register is bulk erased, CONFIG and the 512-byte array are all erased.
BULKE LDAB STAB #$06 $103B ERASE=1, EELAT=1, EEPGM=0 Set EELAT bit

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STAB LDAB STAB JSR CLR

$FE00 #$07 $103B DLY10 $103B

Store any data to any EEPROM address EELAT=1, EEPGM=1 Turn on programming voltage Delay 10 ms Turn off high voltage and set to READ mode

6.3.3 Row Erase The following example shows how to perform a fast erase of large sections of EEPROM. This example assumes that index register X contains the address of a location in the desired row.
ROWE LDAB STAB STAB LDAB STAB JSR CLR #$0E $103B $xxxx #$0F $103B DLY10 $103B ROW=1, ERASE=1, EELAT=1, EEPGM=0 Set to ROW erase mode Store any data to any address in ROW ROW=1, ERASE=1, EELAT=1, EEPGM=1 Turn on high voltage Delay 10 ms Turn off high voltage and set to READ mode

6.3.4 Byte Erase The following is an example of how to erase a single byte of EEPROM. This example assumes that index register X contains the address of the byte to be erased.
BYTEE LDAB STAB STAB LDAB STAB JSR CLR #$16 $103B $0,X #$17 $103B DLY10 $103B BYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=0 Set to BYTE erase mode Store any data to address to be erased BYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=1 Turn on high voltage Delay 10 ms Turn off high voltage and set to READ mode

6.4 CONFIG Register Programming Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to erase and program this register. The procedure for programming is the same as for programming a byte in the EEPROM array, except that the CONFIG register address is used. CONFIG can be programmed or erased (including byte erase) while the MCU is operating in any mode, provided that PTCON in BPROT is clear. To change the value in the CONFIG register, complete the following procedure. Do not initiate a reset until the procedure is complete. The new value will not take effect until after the next reset sequence. 1. Erase the CONFIG register. 2. Program the new value to the CONFIG address. 3. Initiate reset.

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7 Parallel Input/Output
On the MC68HC11F1, either 54 or 51 pins are available for general-purpose I/O, depending on the package. These pins are arranged into ports A, B, C, D, E, F, and G. On the MC68HC11FC0, either 52 or 49 pins are available, depending on the package. I/O functions on some ports (B, C, F, and G) are affected by the mode of operation selected. In the single-chip and bootstrap modes, they are configured as parallel I/O data ports. In expanded and test modes, they are configured as follows: · Ports B and F are configured as the address bus. · Port C is configured as the data bus. · Port G bit 7 is configured as the optional program chip select CSPROG. In addition, in expanded and test modes the R/W signal is configured as data bus direction control. The remaining ports (A, D, and E) are unaffected by mode changes. 7.1 Port A Port A is an eight-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data direction register (DDRA). Port A pins are available for shared use among the main timer, pulse accumulator, and general I/O functions, regardless of mode. Four pins can be used for timer output compare functions (OC), three for input capture (IC), and one as either a fourth IC or a fifth OC. 7.2 Port B Port B is an eight-bit general-purpose output-only port in single-chip modes. In expanded modes, port B pins act as high-order address lines ADDR[15:8], and accesses to PORTB (the port B data register) are mapped externally. 7.3 Port C Port C is an eight-bit general-purpose I/O port with a data register (PORTC) and a data direction register (DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. Port C can be configured for wired-OR operation in single-chip modes by setting the CWOM bit in the OPT2 register. In expanded modes, port C is the data bus DATA[7:0], and accesses to PORTC (the port C data register) are mapped externally. 7.4 Port D Port D is a six-bit general-purpose I/O port with a data register (PORTD) and a data direction register (DDRD). In all modes, the six port D lines (PD[5:0]) can be used for general-purpose I/O or for the serial communications interface (SCI) or serial peripheral interface (SPI) subsystems. Port D can also be configured for wired-OR operation. 7.5 Port E Port E is an eight-bit input-only port that is also used (on the MC68HC11F1 only) as the analog input port for the analog-to-digital converter. Port E pins that are not used for the A/D system can be used as general-purpose inputs. However, PORTE should not be read during the sample portion of an A/D conversion sequence. NOTE PE7 and PE0 are not available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0 are not available on the 64-pin MC68HC11FC0. 7.6 Port F Port F is an eight-bit output-only port. In single-chip mode, port F pins are general-purpose output pins PF[7:0]. In expanded mode, port F pins act as low-order address outputs ADDR[7:0].

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7.7 Port G Port G is an eight-bit general-purpose I/O port with a data register (PORTG) and a data direction register (DDRG). When enabled, the upper four lines (PG[7:4] can be used as chip-select outputs in expanded modes. When any of these pins are not being used for chip selects, they can be used for general-purpose I/O. Port G can be configured for wired-OR operation by setting the GWOM bit in the OPT2 register.