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SEMICONDUCTOR
APPLICATION NOTE

Transporting M68HC11 Code to M68HC16 Devices
By Michael Greenberg and Harold Roberson

1 INTRODUCTION
Devices in the Motorola M68HC16 modular microcontroller family are built up from standard modules that interface via a common internal bus. Modularity facilitates rapid development of devices tailored for specific applications. The standard central processing unit in the M68HC16 family is the 16-bit CPU16 module. Both the CPU16 programming model and the CPU16 instruction set are designed for compatibility with the M68HC11 CPU, and M68HC11 applications can be ported to the CPU16 with moderate effort. However, because the CPU16 has additional capabilities, the functions of certain M68HC11 instructions have been modified and some M68HC11 CPU instructions have been replaced by instructions specific to the CPU16. In addition, the M68HC11 CPU and CPU16 manage interrupts differently. This note is intended to assist programmers who wish to transport code from the M68HC11 CPU to the CPU16. It compares the capabilities of the two processors, provides information concerning differences in the respective instruction sets, and discusses cases that need special attention. For more detailed information, please refer to the M68HC11 Reference Manual (M68HC11RM/AD) and to the CPU16 Reference Manual (CPU16RM/AD).

2 M68HC11 CPU
The M68HC11 CPU treats all peripheral, I/O, and memory locations as addresses in its memory map. There are no special instructions for I/O that are distinct from those used for memory. This architecture also allows accessing an operand from an external memory location with no execution-time penalty. 2.1 Programming Model M68HC11 CPU registers are an integral part of the processing unit and are not addressed as memory locations. Figure 1 shows the programming model. The following paragraphs describe the registers.
20 16 15 A D IX IY SP PC CCR 8 7 B 0 BIT POSITION ACCUMULATORS A AND B ACCUMULATOR D (A : B) INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER

Figure 1 M68HC11 CPU Programming Model

© MOTOROLA INC, 1996

2.1.1 Accumulators The M68HC11 CPU has two general-purpose 8-bit accumulators (A and B). Accumulators A and B can be concatenated into a general-purpose 16-bit double accumulator (D). Although most operations can use A or B interchangeably, the following exceptions apply: · The ABX and ABY instructions add the contents of B to the contents of IX or IY, but there are no equivalent instructions that use A rather than B. · The TAP and TPA instructions transfer data from A to the CCR, or from the CCR to A, but there are no equivalent instructions that use B rather than A. · The DAA instruction is used to adjust the content of A after BCD arithmetic operations, but there is no equivalent instruction for B. · Add, subtract, and compare instructions that operate on both A and B (ABA, SBA, and CBA) only operate in one direction, making it important to place an operand in the correct accumulator. 2.1.2 Index Registers The M68HC11 CPU has two 16-bit index registers (IX and IY). When an indexed addressing mode is used, a 16-bit value contained in an index register is added to an 8-bit offset provided by an instruction to create an effective address. The index registers can also be used as counters or as temporary storage registers. Because of M68HC11 opcode mapping, most instructions that use IY require an extra byte of machine code and an extra cycle of execution time. 2.1.3 Stack Pointer The M68HC11 CPU stack pointer (SP) is 16 bits wide. The stack can be located anywhere in address space and can be any size up to the amount of memory available in the system. Stack entries are byte-width. The SP contains the 16-bit address of the next free location in the stack, rather than the address of the latest stack entry. SP is decremented each time data is pushed on the stack, and incremented each time data is pulled from the stack. The stack grows downward from high to low memory as it is filled. 2.1.4 Program Counter The 16-bit program counter (PC) contains the address of the next instruction to be executed. The PC can be initialized with one of six possible vectors, depending on operating mode and the cause of reset. 2.1.5 Condition Code Register As Figure 2 shows, this 8-bit register contains five condition code indicators (H, N, Z, V and C), two interrupt masking bits (I and X), and a stop disable bit (S). In the M68HC11 CPU, condition codes are automatically updated by most instructions. However, pushes, pulls, Add B to X (ABX), Add B to Y (ABY), and transfer/exchange instructions do not affect the condition codes.
7 S 6 X 5 H 4 I 3 N 2 Z 1 V 0 C

Figure 2 M68HC11 CPU Condition Code Register S -- STOP Enable 0 = Stop clock when STOP instruction is executed. 1 = Perform NOP when STOP instruction is executed. X -- X Interrupt Mask Setting X disables interrupts from the XIRQ pin. X can be set only by hardware RESET or XIRQ acknowledge. X can be cleared by a TAP instruction or by an RTI (when bit 6 of the value restored from the stack to the CCR is cleared). H -- Half Carry Flag Set when a carry from A3 or B3 occurs during BCD addition.

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I -- Interrupt Mask I is a global mask that disables maskable interrupt sources. While I is set, no maskable interrupts are processed. After reset, I is set and can only be cleared by software. I is normally cleared when CCR content is restored by the RTI instruction at the end of an interrupt service routine. N -- Negative Flag Set when the MSB of a result register is set. Z -- Zero Flag Set when all bits of a result register are zero. V -- Overflow Flag Set when two's complement overflow occurs as the result of an operation. C -- Carry Flag Set when carry or borrow occurs during arithmetic operation. Also used during shift and rotate 2.2 Memory Management All M68HC11 devices have a contiguous 64 Kbyte address space that is accessed by means of a 16-line address bus. Some devices have the upper eight address lines multiplexed with the data bus lines, while others have non-multiplexed address and data buses. Some variants also have address extension capabilities -- the CPU address space remains 64 Kbytes, but on-chip logic and extra address lines are provided to implement bank-switching in external memory. Extended memory is accessed by means of two windows of a pre-defined size and extend. 2.3 Data Types The M68HC11 CPU supports the following data types: · Bit data · 8-bit and 16-bit signed and unsigned integers · 16-bit unsigned fractions · 16-bit addresses A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 CPU is an 8-bit CPU, there are no special requirements for alignment of instructions or operands. 2.4 Addressing Modes The M68HC11 CPU uses six basic types of addressing. Each type consists of one or more addressing modes. All modes except inherent mode use an effective address. The effective address is the memory address from which an argument is fetched or stored, or the address from which execution is to proceed. An effective address can be specified within an instruction, or it can be calculated. Table 1 shows the various M68HC11 CPU addressing modes. Table 1 M68HC11 CPU Addressing Modes
Mode Direct Extended Immediate Indexed Inherent Relative Mnemonic DIR EXT IMM IND, X IND, Y INH REL Description Low-order byte of effective address follows opcode Effective address follows opcode Argument follows opcode Effective address formed by adding unsigned 8-bit offset from instruction to index register content Opcode contains information necessary for execution When a branch is taken, effective address formed by adding signed 8bit offset from instruction to PC content.

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2.4.1 Direct Mode In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00­$FF are thus accessed directly, using two-byte instructions. Execution time is reduced by eliminating the additional memory access required for the high-order address byte. In most applications, this 256-byte area is reserved for frequently referenced data. M68HC11 memory can be configured so that combinations of internal registers, RAM or external memory occupy these addresses. 2.4.2 Extended Mode In the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. 2.4.3 Immediate Mode In the immediate addressing mode an argument is contained in the byte(s) immediately following the opcode. The number of bytes following the opcode matches the size of the register or memory location being operated on. The effective address is the address of the byte following the instruction. 2.4.4 Indexed Modes In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (IX or IY) -- the sum is the effective address. This addressing mode allows referencing any memory location in the 64 Kbyte address space. 2.4.5 Inherent Modes In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations that use only the index registers or accumulators, as well as control instructions with no arguments, are included in this addressing mode. 2.4.6 Relative Mode The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. Otherwise, control proceeds to the next instruction. 2.5 Instructions The M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. A four-page opcode map has been implemented to expand the number of instructions. An additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. As its name implies, the additional byte precedes the opcode. A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. The operands contain information the CPU needs for executing the instruction. Complete instructions can be from one to five bytes long. 2.6 Instruction Execution The M68HC11 CPU fetches and executes instruction bytes sequentially from byte addresses. The program counter is incremented by one after each opcode or operand byte fetch.

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2.7 Changes in Program Flow M68HC11 jump, branch, and subroutine instructions initiate changes in program flow. When program flow changes, instructions are fetched from a new address. When a change in flow is temporary, a return address is stored, so that execution of the original instruction stream can resume after the change in flow. The jump (JMP) instruction uses direct, extended and indexed addressing modes. Jumps are unconditional changes in flow. No return PC value is stacked prior to executing a jump instruction. The M68HC11 CPU supports a number of 8-bit relative displacement branch instructions, as well as specialized bit condition branches that use the direct and indexed addressing modes. Branch instructions are conditional changes in flow. A change occurs only if a pre-defined condition is satisfied. No return PC value is stacked prior to executing a branch instruction. Subroutines are called by special branch (BSR) or jump (JSR) instructions. The RTS instruction returns control to the calling routine after a subroutine has executed. JSR uses the direct, indexed, and extended addressing modes; BSR uses only relative addressing mode. When a subroutine instruction is executed, the PC points to the address of the instruction that follows the instruction that calls the subroutine. Both calling instructions stack the high and low bytes of this return PC value. The return PC is pulled from the stack when RTS is executed at the end of a subroutine. 2.8 Reset And Interrupt Vectors Reset and interrupt operations load the M68HC11 CPU program counter with a vector that points to a new location from which instructions are to be fetched. Table 2 shows vector assignments for a typical M68HC11 device. 2.9 Resets Resets are generally used to initialize the MCU or to recover from catastrophic failure. A reset immediately stops program execution and forces the program counter to a known starting address. Internal registers and control bits are initialized so the MCU can resume operation in a known state. There are four possible sources of reset. External reset and power-on reset share a vector. The computer operating properly system and the clock monitor each have a vector. The M68HC11 CPU distinguishes between internal and external reset conditions by measuring the time it takes the MCU RESET line to return to logic level one after assertion. When a reset condition is sensed, an internal circuit drives the RESET pin low for four ECLK cycles, then releases it. Two ECLK cycles later, the logic level of the RESET line is sampled. If it is still low, the CPU assumes that an external reset has occurred. If it is high, the CPU assumes that reset was initiated internally. A positive transition on Vdd generates a power-on reset, which is used only for power-up conditions. A 4064 clock cycle delay after the oscillator becomes active allows the clock generator to stabilize. If RESET is low at the end of 4064 clock cycles, the CPU remains in reset condition until RESET goes high. The MCU includes a computer operating properly (COP) system to help protect against software failures. When the system is enabled, software is responsible for keeping a free-running watchdog timer from timing out. If the software fails to update the timer control register, a system reset occurs. The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges are detected within the delay period, the clock monitor can generate a system reset. When a reset condition is recognized, the internal registers and control bits are forced to an initial state. Depending on the cause of the reset and the operating mode, the reset vector can be fetched from one of the six possible locations shown in Table 3 . The M68HC11 CPU fetches the appropriate vector during the first three cycles after reset, then begins fetching instructions from the address pointed to by the vector. The stack pointer and other CPU registers are indeterminate immediately after reset, but the X and I interrupt mask bits in the CCR are set to mask interrupt requests. AN1283/D MOTOROLA 5

Table 2 M68HC11 Interrupt and Reset Vector Assignments
Vector Address FFC0, C1 ­ FFD4, D5 Reserved SCI Serial System · SCI Transmit Complete · SCI Transmit Data Register Empty FFD6, D7 · SCI Idle Line Detect · SCI Receiver Overrun · SCI Receive Data Register Full FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF SPI Serial Transfer Complete Pulse Accumulator Input Edge Pulse Accumulator Overflow Timer Overflow Timer Input Capture 4/Output Compare 5 Timer Output Compare 4 Timer Output Compare 3 Timer Output Compare 2 Timer Output Compare 1 Timer Input Capture 3 Timer Input Capture 2 Timer Input Capture 1 Real-Time Interrupt Parallel I/O Handshake IRQ XIRQ Pin Software Interrupt Illegal Opcode Trap COP Failure Clock Monitor Fail RESET I X None None None None None I I I I I I I I I I I I I Interrupt Source CCR Mask Bit -- I TCIE TIE ILIE RIE RIE SPIE PAII PAOVI TOI I4/O5I OC4I OC3I OC2I OC1I IC3I IC2I IC1I RTII STAI None None None None NOCOP CME None Local Mask --

Table 3 Reset Vectors
Cause of Reset RESET pin Power-on reset Clock monitor reset COP system reset Normal Mode Vector $FFFE, FFFF $FFFE, FFFF $FFFC, FFFD $FFFA, FFFB Special Test or Bootstrap $BFFE, BFFF $BFFE, BFFF $BFFC, BFFD $BFFA, BFFB

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2.10 Interrupts An interrupt temporarily suspends normal program execution while an interrupt service routine is being executed. After an interrupt has been serviced, the main program resumes as if there had been no interruption. Maskable interrupts are recognized only when the CCR I bit is cleared. Maskable interrupts are generated by on-chip peripheral systems, and are enabled by control bits in MCU registers associated with these systems. Nonmaskable interrupt sources are not masked by the I bit. The three nonmaskable interrupt sources are the illegal opcode trap, the software interrupt instruction, and the XIRQ pin. Operation of the XIRQ pin is enabled by the CCR X bit. Upon reset, both the X bit and the I bit are set, which inhibits both maskable interrupts and XIRQ interrupts. After reset, software can clear both X and I to enable interrupt recognition. Once cleared, the X bit cannot be set by software. An interrupt request can be recognized at any time, but the CPU does not respond to a request until completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the current instruction. When the CPU begins to service an interrupt, the contents of the CPU registers are pushed onto the stack in the order shown in Table 4 . Table 4 Stacking Order on Entry to Interrupts
Memory Location CPU Registers SP SP ­ 1 SP ­ 2 SP ­ 3 SP ­ 4 SP ­ 5 SP ­ 6 SP ­ 7 SP ­ 8 PCL PCH IYL IYH IXL IXH ACCA ACCB CCR

After the CCR value is stacked, the appropriate mask bit is set to inhibit further interrupts. When an I-bitrelated interrupt occurs, the I bit is set after stacking, but the X bit is not affected. When an X-bit-related interrupt occurs, both the X and I bits are set after stacking. After stacking and masking take place, the priority of pending requests is evaluated, and the interrupt vector for the highest priority pending source is fetched. Execution of the interrupt service routine begins at the address pointed to by the vector. At the end of the interrupt service routine, the return from interrupt instruction (RTI) is executed and the stacked registers are restored from the stack (restoring the CCR restores the X and I bits to their pre-interrupt request state), and normal program execution resumes. 2.11 Reset and Interrupt Priority Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur. There are six nonmaskable reset and interrupt sources. The priority hierarchy for these sources is as follows: 1. POR or RESET pin 2. Clock monitor reset 3. COP watchdog reset 4. XIRQ interrupt 5. Illegal opcode interrupt 6. Software interrupt (SWI) AN1283/D MOTOROLA 7

Maskable interrupt sources have the following priorities: 1. IRQ Interrupt 2. Real-time interrupt 3. Timer input capture 1 4. Timer input capture 2 5. Timer input capture 3 6. Timer output compare 1 7. Timer output compare 2 8. Timer output compare 3 9. Timer output compare 4 10. Timer input capture 4/output compare 5 11. Timer overflow 12. Pulse accumulator overflow 13. Pulse accumulator input edge 14. SPI transfer complete 15. SCI system Any single interrupt source can be designated as the highest-priority interrupt by writing an appropriate value to the PSEL bits in the HPRIO register. Priority relationships of other maskable interrupts remain the same. An interrupt that is assigned highest priority is still subject to global masking by the I bit. Interrupt vectors are not affected by priority assignment.

3 CPU16 MODULE
The M68HC16 central processing unit (CPU16) was designed to provide compatibility with the M68HC11 CPU and to provide additional capabilities associated with 16- and 32-bit data sizes, 20-bit addressing, and digital signal processing. The CPU16 treats all peripheral, I/O, and memory locations as parts of a pseudolinear 1 Megabyte address space. There are no special instructions for I/O that are separate from instructions for addressing memory. Address space is made up of 16 64-Kbyte banks. Specialized bank addressing techniques and support registers provide transparent access across bank boundaries. The CPU16 interacts with external devices and with other modules within the microcontroller via a standardized bus and bus interface. There are bus protocols for memory and peripheral accesses, as well as for managing an hierarchy of interrupt priorities. 3.1 Programming Model CPU16 registers are an integral part of the CPU and are not addressed as memory locations. The CPU16 register model contains all the resources of the M68HC11 CPU, plus additional resources. Figure 3 shows the CPU16 programming model. Registers are discussed in detail in the following paragraphs.

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20

16 15 A

8 7 B D E

0 BIT POSITION ACCUMULATORS A AND B ACCUMULATOR D (A : B) ACCUMULATOR E INDEX REGISTER X INDEX REGISTER Y INDEX REGISTER Z STACK POINTER PROGRAM COUNTER PK CONDITION CODE REGISTER/ PC EXTENSION REGISTER ADDRESS EXTENSION REGISTER STAACK EXTENSION REGISTER MAC MULTIPLIER REGISTER MAC MULTIPLICAND REGISTER MAC ACCUMULATOR MSB [35:16] MAC ACCUMULATOR LSB [15:0] YMSK MAC XY MASK REGISTER

XK YK ZK SK PK CCR

IX IY IZ SP PC

EK

XK

YK

ZK SK

H IR AM (MSB) AM (LSB) XMSK

Figure 3 CPU16 Programming Model 3.1.1 Accumulators The CPU16 has two 8-bit accumulators (A and B) and one 16-bit accumulator (E). In addition, accumulators A and B can be concatenated into a second 16-bit double accumulator (D). Accumulators A, B, and D are general-purpose registers used to hold operands and results during mathematical and data manipulation operations. Accumulator E can be used in the same way as accumulator D, and also extends CPU16 capabilities. It allows more data to be held within the CPU16 during operations, simplifies 32-bit arithmetic and digital signal processing, and provides a practical 16-bit accumulator offset indexed addressing mode. 3.1.2 Index Registers The CPU16 has three 16-bit index registers (IX, IY, and IZ). Each index register has an associated 4-bit extension field (XK, YK, and ZK). Concatenated registers and extension fields provide 20-bit indexed addressing and support data structure functions anywhere in the CPU16 address space. AN1283/D MOTOROLA 9

IX and IY can perform the same operations as M68HC11 CPU registers of the same names, but the CPU16 instruction set provides additional indexed operations. IZ can perform the same operations as IX and IY, and also provides an additional indexed addressing capability that replaces M68HC11 CPU direct addressing mode. Initial IZ and ZK extension field values are included in the RESET exception vector, so that ZK : IZ can be used as a direct page pointer out of reset. 3.1.3 Stack Pointer The CPU16 stack pointer (SP) is 16 bits wide. An associated 4-bit extension field (SK) provides 20-bit stack addressing. Stack implementation in the CPU16 is from high to low memory. The stack grows downward as it is filled. SK : SP are decremented each time data is pushed on the stack, and incremented each time data is pulled from the stack. SK : SP point to the next available stack address, rather than to the address of the latest stack entry. Although the stack pointer is normally incremented or decremented by word address, it is possible to push and pull byte-sized data. Setting the stack pointer to an odd value causes misalignment, which affects performance. 3.1.4 Program Counter The CPU16 program counter (PC) is 16 bits wide. An associated 4-bit extension field (PK) provides 20-bit program addressing. CPU16 instructions are fetched from even word boundaries. PC0 always has a value of zero, to assure that instruction fetches are made from word-aligned addresses. 3.1.5 Condition Code Register The 16-bit condition code register can be divided into two functional blocks. The 8 MSB, which correspond to the CCR in the M68HC11 CPU, contain the low-power stop control bit and processor status flags. The 8 LSB contain the interrupt priority field, the DSP saturation mode control bit, and the program counter address extension field. Figure 4 shows the condition code register. Detailed descriptions of each status indicator and field in the register follow the figure.
15 S MV 14 13 H EV 12 11 N 10 Z V 9 C 8 7 IP 6 5 SM 4 3 2 PK 1 0

Figure 4 CPU16 Condition Code Register S -- STOP Enable 0 = Stop clock when LPSTOP instruction is executed. 1 = Perform NOP when LPSTOP instruction is executed. MV -- Accumulator M overflow flag Set when overflow into AM35 has occurred. H -- Half Carry Flag Set when a carry from A3 or B3 occurs during BCD addition. EV -- Extension Bit Overflow Flag Set when an overflow into AM31 has occurred. N -- Negative Flag Set when the MSB of a result register is set. Z -- Zero Flag Set when all bits of a result register are zero. MOTOROLA 10 AN1283/D

V -- Overflow Flag Set when two's complement overflow occurs as the result of an operation. C -- Carry Flag Set when carry or borrow occurs during arithmetic operation. Also used during shift and rotate to facilitate multiple word operations. IP[2:0] -- Interrupt Priority Field The priority value in this field (0 to 7) is used to mask interrupts. SM -- Saturate Mode Bit When SM is set, if either EV or MV is set, data read from AM using TMER or TMET will be given maximum positive or negative value, depending on the state of the AM sign bit before overflow. PK[3:0] -- Program Counter Address Extension Field This field is concatenated with the program counter to form a 20-bit address. 3.1.6 Address Extension Register and Address Extension Fields There are six 4-bit address extension fields. EK, XK, YK, and ZK are contained by the address extension register, PK is part of the CCR, and SK stands alone. Extension fields are the bank portions of 20-bit concatenated bank : byte addresses used in the CPU16 pseudolinear memory management scheme. All extension fields except EK correspond directly to a register. XK, YK, and ZK extend registers IX, IY, and IZ; PK extends the PC; and SK extends the SP. EK holds the 4 MSB of the 20-bit address used by extended addressing mode. 3.1.7 Multiply and Accumulate Registers The multiply and accumulate (MAC) registers are part of a CPU submodule that performs repetitive signed fractional multiplication and stores the cumulative result. These operations are part of control-oriented digital signal processing. There are four MAC registers. Register H contains the 16-bit signed fractional multiplier. Register I contains the 16-bit signed fractional multiplicand. Accumulator M is a specialized 36-bit product accumulation register. XMSK and YMSK contain 8-bit mask values used in modulo addressing. The CPU16 has a special subset of signal processing instructions that manipulate the MAC registers and perform signal processing calculation. 3.2 Memory Management The CPU16 uses bank switching to provide a 1 Megabyte address space. There are 16 banks within the address space. Each bank is made up of 64 Kbytes addressed from $0000 to $FFFF. Banks are selected by means of address extension fields associated with individual CPU16 registers. CPU16 addressing is pseudolinear -- a 20-bit extended address can access any byte location in the appropriate address space. In addition, address space can be split into discrete 1 Megabyte program and data spaces by externally decoding the SIM function code outputs. When this technique is used, instruction fetches and reset vector fetches access program space, while exception vector fetches (other than for reset), data accesses, and stack accesses are made in data space. 3.2.1 Address Extension All CPU16 resources that are used to generate addresses are effectively 20 bits wide. These resources include extended index registers, program counter, and stack pointer. All addressing modes use 20-bit addresses. 20-bit addresses are formed from a 16-bit byte address generated by an individual CPU16 register and a 4-bit bank address contained in an associated extension field. The byte address corresponds to ADDR[15:0] and the bank address corresponds to ADDR[19:16]. AN1283/D MOTOROLA 11

3.3 Data Types The CPU16 uses the following types of data: · Bits · 4-bit signed integers · 8-bit (byte) signed and unsigned integers · 8-bit, 2-digit binary coded decimal numbers · 16-bit (word) signed and unsigned integers · 32-bit (long word) signed and unsigned integers · 16-bit signed fractions · 32-bit signed fractions · 36-bit signed fixed-point numbers · 20-bit effective address consisting of 16-bit byte address and 4-bit extension There are 8 bits in a byte, 16 bits in a word. Bit set and clear instructions use both byte and word operands. Bit test instructions use byte operands. Negative integers are represented in two's-complement form. Four-bit signed integers, packed two to a byte, are used only as X and Y offsets in MAC and RMAC operations. Thirty-two-bit integers are used only by extended multiply and divide instructions, and by the associated LDED and STED instructions. Binary coded decimal numbers are packed, two digits per byte. BCD operations use byte operands. 16-bit fractions are used in both fractional multiplication and division, and as multiplicand and multiplier operands in the MAC unit. Bit 15 is the sign bit. There is an implied radix point between bits 15 and 14. There are 15 bits of magnitude -- the range of values is ­1 ($8000) to 1 ­ 2-15 ($7FFF). Signed 32-bit fractions are used only by fractional multiplication and division instructions. Bit 31 is the sign bit. An implied radix point lies between bits 31 and 30. There are 31 bits of magnitude -- the range of values is ­1 ($80000000) to 1 ­ 2-31 ($7FFFFFFF). Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit. Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and 30. There are 31 bits of magnitude, but use of the extension bits allows representation of numbers in the range ­16 ($800000000) to 15.999969482 ($7FFFFFFFF). 20-bit addresses are formed by combining a 16-bit byte address with a 4-bit address extension. 3.4 Memory Organization A word is composed of two consecutive bytes. A word address is normally an even byte address. Byte 0 of a word has a lower 16-bit address than Byte 1. Long words and 32-bit signed fractions consist of two consecutive words, and are normally accessed at the address of Byte 0 in Word 0. Instruction fetches always access word addresses. Word operands are normally accessed at even byte addresses, but may be accessed at odd byte addresses, with a substantial performance penalty. To be compatible with the M68HC11 CPU, misaligned word transfers and misaligned stack accesses are allowed. Transferring a misaligned word requires two successive byte transfer operations. 3.5 Addressing Modes The CPU16 uses 9 basic types of addressing. There are one or more addressing modes within each type. Table 5 shows the addressing modes.

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Table 5 CPU16 Addressing Modes
Mode Accumulator Offset Mnemonic E,X E,Y E,Z Extended Immediate EXT EXT20 IMM8 IMM16 IND8, X Indexed 8-Bit IND8, Y IND8, Z IND16, X Indexed 16-Bit IND16, Y IND16, Z IND20, X Indexed 20-Bit Inherent Post-Modified Index Relative IND20, Y IND20, Z INH IXP REL8 REL16 Description Index Register X with Accumulator E offset Index Register Y with Accumulator E offset Index Register Z with Accumulator E offset Extended 20-bit Extended 8-bit Immediate 16-bit Immediate Index Register X with unsigned 8-bit offset Index Register Y with unsigned 8-bit offset Index Register Z with unsigned 8-bit offset Index Register X with signed 16-bit offset Index Register Y with signed 16-bit offset Index Register Z with signed 16-bit offset Index Register X with signed 20-bit offset Index Register Y with signed 20-bit offset Index Register Z with signed 20-bit offset Inherent Signed 8-bit offset added to Index Register X after effective address is used 8-bit relative 16-bit relative

All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an operand or an extension field to form a 20-bit effective address. Bank switching is transparent to most instructions. ADDR[19:16] of the effective address are changed to make an access across a bank boundary. However, extension field values do not change as a result of effective address computation. 3.5.1 Immediate Addressing Modes In the immediate modes, an argument is contained in a byte or word immediately following the instruction. For IMM8 and IMM16 modes, the effective address is the address of the argument. There are three specialized forms of IMM8 addressing. The AIS, AIX/Y/Z, ADDD and ADDE instructions decrease execution time by sign-extending the 8-bit immediate operand to 16 bits, then adding it to an appropriate register. The MAC and RMAC instructions use an 8-bit immediate operand to specify two signed 4-bit index register offsets. The PSHM and PULM instructions use an 8-bit immediate mask operand to indicate which registers must be pushed to or pulled from the stack. 3.5.2 Extended Addressing Modes Regular extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective address is formed by concatenating the EK field and the 16-bit byte address. EXT20 mode is used only by the JMP and JSR instructions. These instructions contain a 20-bit effective address that is zero-extended to 24 bits to give the instruction an even number of bytes. 3.5.3 Indexed Addressing Modes In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used to calculate the effective address. For 8-bit indexed modes an 8-bit unsigned offset contained in the instruction

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is added to the value contained in an index register and its extension field. For 16-bit modes, a 16-bit signed offset contained in the instruction is added to the value contained in an index register and its extension field. For 20-bit modes, a 20-bit signed offset (zero-extended to 24 bits) is added to the value contained in an index register. These modes are used for JMP and JSR instructions only. 3.5.4 Inherent Addressing Mode Inherent mode instructions use information directly available to the processor to determine the effective address. Operands (if any) are system resources and are thus not fetched from memory. 3.5.5 Accumulator Offset Addressing Mode Accumulator offset modes form an effective address by sign-extending the content of accumulator E to 20 bits, then adding the result to an index register and its associated extension field. This mode allows use of an index register and an accumulator within a loop without corrupting accumulator D. 3.5.6 Relative Addressing Modes Relative modes are used for branch and long branch instructions. If a branch condition is satisfied, a byte or word signed two's-complement offset is added to the concatenated PK field and program counter. The new PK : PC value is the effective address. 3.5.7 Post-Modified Index Addressing Mode Post-modified index mode is used by the MOVB and MOVW instructions. A signed 8-bit offset is added to index register X after the effective address formed by XK : IX is used. 3.6 Instructions The instruction set is based upon that of the M68HC11 CPU, but the opcode map has been rearranged to maximize performance with a 16-bit data bus. Much M68HC11 code can run on the CPU16 following reassembly. The user must take into account changed instruction times, the interrupt mask, and the new interrupt stack frame. CPU16 instructions consist of an 8-bit opcode, which may be preceded by an 8-bit prebyte and followed by one or more operands. Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone, but Page 1, 2, and 3 opcodes are pointed to by a prebyte code on Page 0. The prebytes are $17 (Page 1), $27 (Page 2), and $37 (Page 3). Operands can be 4 bits, 8 bits or 16 bits in length. However, because the CPU16 fetches 16-bit instruction words from even byte boundaries, each instruction must contain an even number of bytes. Operands are organized as bytes, words, or a combination of bytes and words. Four-bit operands are either zero-extended to 8 bits, or packed two to a byte. The largest instructions are six bytes in length. Size, order, and function of operands are evaluated when an instruction is decoded. A Page 0 opcode and an 8-bit operand can be fetched simultaneously. Instructions that use 8-bit indexed, immediate, and relative addressing modes have this form. Code written with these instructions is very compact. 3.7 CPU16 Pipeline Mechanism This description is a simplified model of the mechanism the CPU16 uses to fetch and execute instructions. Functional divisions in the model do not necessarily correspond to distinct architectural subunits of the microprocessor.

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There are three functional blocks involved in fetching, decoding, and executing instructions. These are the microsequencer, the instruction pipeline, and the execution unit. These elements function concurrently -- at any given time, all three may be active. 3.7.1 Microsequencer The microsequencer controls the order in which instructions are fetched, advanced through the pipeline, and executed. It increments the program counter and generates multiplexed external tracking signals IPIPE0 and IPIPE1 from internal signals that control execution sequence. 3.7.2 Instruction Pipeline The pipeline is a three stage FIFO that holds instructions while they are decoded and executed. As many as three instructions can be in the pipeline at one time (single-word instructions, one held in stage C, one being executed in stage B, and one latched in stage A). 3.7.3 Execution Unit The execution unit evaluates opcodes, interfaces with the microsequencer to advance instructions through the pipeline, and performs instruction operations. 3.8 Execution Process A prefetch mechanism in the microsequencer reads instruction words from memory and increments the program counter. When instruction execution begins, the program counter points to an address six bytes after the address of the first word of the instruction being executed. Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are evaluated in stage B. The execution unit can access operands in either stage A or stage B (stage B accesses are limited to 8-bit operands). When execution is complete, opcodes are moved from stage B to stage C, where they remain until the next instruction is complete. The number of machine cycles necessary to complete an execution sequence varies according to the complexity of the instruction. 3.9 Changes in Program Flow When program flow changes, instructions are fetched from a new address. Before execution can begin at the new address, instructions and operands from the previous instruction stream must be removed from the pipeline. If a change in flow is temporary, a return address must be stored, so that execution of the original instruction stream can resume after the change in flow. At the time an instruction that causes a change in program flow executes, PK : PC point to the address of the first word of the instruction + $0006. During execution of the instruction, PK : PC is loaded with the address of the first word of the new instruction stream. However, stages A and B still contain words from the old instruction stream. The CPU16 prefetches to advance the new instruction to stage C, and fills the pipeline from the new instruction stream. 3.9.1 Jumps The CPU16 jump instruction uses 20-bit extended and indexed addressing modes. It consists of an 8-bit opcode with a 20-bit argument. No return PK : PC is stacked for a jump. 3.9.2 Branches The CPU16 supports 8-bit relative displacement (short), and 16-bit relative displacement (long) branch instructions, as well as specialized bit condition branches that use indexed addressing modes. CPU16 short branches are generally equivalent to M68HC11 CPU branches, although opcodes are not identical. M68HC11 BHI and BLO are replaced by CPU16 BCC and BCS.

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Short branch instructions consist of an 8-bit opcode and an 8-bit operand contained in one word. Long branch instructions consist of an 8-bit prebyte and an 8-bit opcode in one word, followed by an operand word. Bit condition branches consist of an 8-bit opcode and an 8-bit operand in one word, followed by one or two operand words. When a branch instruction executes, PK : PC point to an address equal to the address of the first word of the instruction plus $0006. The range of displacement for each type of branch is relative to this value. In addition, because prefetches are automatically aligned to word boundaries, only even offsets are valid. An odd offset value is rounded down. 3.9.3 Subroutines Subroutines can be called by short (BSR) or long (LBSR) branches, or by a jump (JSR). The RTS instruction returns control to the calling routine. BSR consists of an 8-bit opcode with an 8-bit operand. LBSR consists of an 8-bit prebyte and an 8-bit opcode in one word, followed by an operand word. JSR consists of an 8-bit opcode with a 20-bit argument. RTS consists of an 8-bit prebyte and an 8-bit opcode in one word. When a subroutine instruction is executed, PK : PC contain the address of the calling instruction plus $0006. All three calling instructions stack return PK : PC values prior to processing instructions from the new instruction stream. In order for RTS to work with all three calling instructions, however, the value stacked by BSR must be adjusted. LBSR and JSR are two-word instructions. In order for program execution to resume with the instruction immediately following them, RTS must subtract $0002 from the stacked PK : PC value. BSR is a one-word instruction -- it subtracts $0002 from PK : PC prior to stacking so that execution will resume correctly. 3.10 Exceptions An exception is an event that preempts normal instruction process. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. Each exception has an assigned vector that points to an associated handler routine. Exception processing includes all operations required to transfer control to a handler routine, but does not include execution of the handler routine itself. Keep the distinction between exception processing and execution of an exception handler in mind while reading this section. 3.10.1 Exception Vectors An exception vector is the address of a routine that handles an exception. Exception vectors are contained in a data structure called the exception vector table, which is located in the first 512 bytes of Bank 0. All vectors except the reset vector consist of one word and reside in data space. The reset vector consists of four words that reside in program space. There are 52 predefined or reserved vectors, and 200 user-defined vectors. Each vector is assigned an 8-bit number. Vector numbers for some exceptions are generated by external devices; others are supplied by the processor. There is a direct mapping of vector number to vector table address. The processor left shifts the vector number one place (multiplies by two) to convert it to an address. Table 6 shows the exception vectors. 3.10.2 Exception Stack Frame During exception processing, the contents of the program counter and condition code register are stacked at a location pointed to by SK : SP. Unless it is altered during exception processing, the stacked PK : PC value is the address of the next instruction in the current instruction stream, plus $0006. Figure 5 shows the exception stack frame.

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Table 6 Exception Vector Table
Vector Number 0 Vector Address 0000 0002 0004 0006 4 5 6 7 8 9­E F 10 11 12 13 14 15 16 17 18 19 ­ 37 38 ­ FF 0008 000A 000C 000E 0010 0012 ­ 001C 001E 0020 0022 0024 0026 0028 002A 002C 002E 0030 0032 ­ 006E 0070 ­ 01FE Address Space P P P P D D D D D D D D D D D D D D D D D D Type of Exception Reset -- Initial ZK, SK, and PK Reset -- Initial PC Reset -- Initial SP Reset -- Initial IZ Breakpoint Bus Error Software Interrupt Instruction (SWI) Illegal Instruction Division by Zero Unassigned, Reserved Uninitialized Interrupt Unassigned, Reserved Level 1 Interrupt Autovector Level 2 Interrupt Autovector Level 3 Interrupt Autovector Level 4 Interrupt Autovector Level 5 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector Spurious Interrupt Unassigned, Reserved User-Defined Interrupts

Low Address Condition Code Register High Address Program Counter

SP After Exception Stacking SP Before Exception Stacking

Figure 5 Exception Stack Frame Format 3.10.3 Exception Processing Sequence Exception processing is performed in four distinct phases. 1. Priority of all pending exceptions is evaluated, and the highest priority exception is processed first. 2. Processor state is stacked, then the CCR PK extension field is cleared. 3. An exception vector number is acquired and converted to a vector address. 4. The content of the vector address is loaded into the PC, and the processor jumps to the exception handler routine. There are variations within each phase for differing types of exceptions. However, all vectors but the reset vectors contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located within Bank 0 or vectors must point to a jump table.

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3.10.4 Types of Exceptions Exceptions can be either internally or externally generated. External exceptions, which are defined as asynchronous, include interrupts, bus errors, breakpoints, and resets. Internal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception. 3.10.4.1 Asynchronous Exceptions Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing is synchronized. For all asynchronous exceptions but reset, exception processing begins at the first instruction boundary following recognition of an exception. Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than reset, is equal to the address of the next instruction in the current instruction stream plus $0006. The RTI instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value in order to resume execution of the interrupted instruction stream. 3.10.4.2 Synchronous Exceptions Synchronous exception processing is part of an instruction definition. Exception processing for synchronous exceptions will always be completed, and the first instruction of the handler routine will always be executed, before interrupts are detected. Because of pipelining, the value of PK : PC at the time a synchronous exception executes is equal to the address of the instruction that causes the exception plus $0006. Since RTI always subtracts $0006 upon return, the stacked PK : PC must be adjusted so that execution will resume with the following instruction. For this reason $0002 is added to the PK : PC value before it is stacked. 3.10.4.3 Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation. Asynchronous exceptions have higher priorities than synchronous exceptions. Exception processing for multiple exceptions is done by priority, from lowest to highest. Priority governs the order in which exception processing occurs, not the order in which exception handlers are executed. Unless a bus error, a breakpoint, or a reset occurs during exception processing, the first instruction of all exception handler routines is guaranteed to execute before another exception is processed. Since interrupt exceptions have higher priority than synchronous exceptions, this means that the first instruction in an interrupt handler will be executed before other interrupts are sensed. Bus error, breakpoint, and reset exceptions that occur during exception processing of a previous exception are processed before the first instruction of that exception's handler routine. The converse is not true -- if an interrupt occurs during bus error exception processing, for example, the first instruction of the bus error handler is executed before interrupts are sensed. This permits the exception handler to mask interrupts during execution. 3.11 RTI Instruction The return-from-interrupt (RTI) instruction is used to terminate all exception handlers except the reset handler. RTI restores context so that normal execution can resume. Asynchronous interrupts are serviced at instruction boundaries, and a value of PK : PC + $0006 is stacked when exception processing begins. RTI subtracts $0006 from the stacked value so that the pipeline is refilled from the correct address. RTI is not used in the reset handler because the system is re-initialized and there is no context to restore. SWI initiates interrupt exception processing without an external service request. The PK : PC value at the time of execution is the first word address of SWI plus $0006. If this value were stacked, execution of RTI at the end of the handler would cause SWI to execute again. To prevent this, SWI adds $0002 to the PK : PC value prior to stacking.

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3.12 Resets Reset procedures handle system initialization and recovery from catastrophic failure. M68HC16 microcontrollers perform resets with a combination of hardware and software. The system integration module determines whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM selection based on hardware mode-select inputs, then passes control to the CPU16. Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in order to allow completion of write cycles in progress at the time RESET is asserted. Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset exception, and cannot be restarted. Only essential tasks are performed during reset exception processing. Other initialization tasks must be accomplished by the exception handler routine. The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint assertions. Generally, module pins default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. 3.12.1 Reset Timing The RESET input must be asserted for a specified minimum period in order for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor timeout period) in order to protect write cycles from being aborted by reset. While RESET is asserted, SIM pins are either in an inactive, high-impedance state or are driven to their inactive states. When an external device asserts RESET for the proper period, reset control logic clocks the signal into an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset to the entire system. If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET until the internal reset signal is negated. After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cycles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one, reset exception processing begins. If, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-impedance state for 10 cycles, then it is tested again. The process repeats until RESET is released. During power-on reset, an internal circuit in the SIM drives the IMB internal and external reset lines. The circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SIM pins are initialized. When VDD reaches the specified minimum value, the clock synthesizer VCO begins operation. Clock frequency ramps up to the specified limp mode frequency. The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse. The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15 milliseconds. During this period, module port pins may be in an indeterminate state. While input-only pins can be put in a known state by means of external pull-up resistors, external logic on input/output or output-only pins must condition the lines during this time. Active drivers require high-impedance buffers or isolation resistors to prevent conflict.

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3.13 Interrupts Interrupt recognition and servicing involve complex interaction between the central processing unit, the system integration module, and a device or module requesting interrupt service. The CPU16 provides for eight levels of interrupt priority (0­7), seven automatic interrupt vectors, and 200 assignable interrupt vectors. All interrupts with priorities less than 7 can be masked by the interrupt priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asynchronous exception. Interrupt recognition is based on the states of interrupt request signals IRQ[7:1] and the IP mask value. Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the highest priority. The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7) from being recognized and processed. When IP contains %000, no interrupt is masked. During exception processing, the IP field is set to the priority of the interrupt being serviced. Interrupt request signals can be asserted by external devices or by microcontroller modules. Request lines are connected internally by means of a wired NOR -- simultaneous requests of differing priority can be made. Internal assertion of an interrupt request signal does not affect the logic state of the corresponding MCU pin. External interrupt requests are routed to the CPU16 via the external bus interface and SIM interrupt control logic. The CPU treats external interrupt requests as though they come from the SIM. External IRQ[6:1] are active-low level-sensitive inputs. External IRQ7 is an active-low transition-sensitive input. IRQ7 requires both an edge and a voltage level for validity. IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted. Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete. The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the CPU does not recognize the occurrence of the request in any way. 3.13.1 Interrupt Acknowledge and Arbitration Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs a CPU space read from address $FFFFF : [IP] : 1. The CPU space read cycle performs two functions: it places a mask value corresponding to the highest priority interrupt request on the address bus, and it acquires an exception vector number from the interrupt source. The mask value also serves two purposes: it is latched into the CCR IP field in order to mask lowerpriority interrupts during exception processing, and it is decoded by modules that have requested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them. Modules that have requested interrupt service decode the IP value placed on the address bus at the beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond to the cycle. Arbitration between simultaneous requests of the same priority is performed by means of serial contention between module interrupt arbitration (IARB) field bit values.

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Each module that can make an interrupt service request, including the SIM, has an IARB field in its configuration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111 (highest priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious interrupt exception when an interrupt from that module is recognized. Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000. Initialization software must assign different IARB values in order to implement an arbitration scheme. Each module must be assigned a unique IARB value. When two or more IARB fields have the same nonzero value, the CPU16 attempts to interpret multiple vector numbers simultaneously, with unpredictable consequences. Arbitration must always take place, even when a single source requests service. This point is important for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SIM wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by a bus error, which causes a spurious interrupt exception to be taken. When arbitration is complete, the dominant module must place an interrupt vector number on the data bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt acknowledge cycle is transferred to the external bus, an external device must decode the mask value and respond with a vector number, then generate bus cycle termination signals. If the device does not respond in time, a spurious interrupt exception is taken. The periodic interrupt timer (PIT) in the SIM can generate internal interrupt requests of specific priority at predetermined intervals. By hardware convention, PIT interrupts are serviced before external interrupt service requests of the same priority. 3.13.2 Interrupt Processing Summary A valid interrupt service request has been detected and is pending. The CPU finishes higher priority exception processing or reaches an instruction boundary. Processor state is stacked, then the CCR PK extension field is cleared. FC[2:0] are driven to %111 (CPU space) encoding. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111, indicating an interrupt acknowledge CPU space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged; ADDR0 = %1. Request priority is latched into the CCR IP field from the address bus. Modules or external peripherals that have requested interrupt service decode ADDR[3:1]. IARB contention takes place. The interrupt vector number is generated, in one of four ways: If contention has not produced a dominant interrupt source (IARB = %0000), the CPU16 generates the spurious interrupt vector number. If contention has produced a dominant interrupt source, it supplies the vector number. If the autovector signal is asserted, the CPU16 generates a vector number that corresponds to interrupt request priority. If the bus monitor asserts the bus error signal, the CPU16 generates the spurious interrupt vector number. The CPU16 converts the vector number to a vector address. The content of the vector address is loaded into the PC. The exception handler routine begins to execute.

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3.14 Development Support The CPU16 incorporates powerful tools for tracking program execution and for system debugging. These tools are deterministic opcode tracking, breakpoint exceptions, and background debugging mode. Judicious use of CPU16 capabilities permits in-circuit emulation and system debugging using a bus state analyzer, a simple serial interface, and a terminal. Refer to CPU16 Reference Manual (CPU16RM/AD) for more information.

4 COMPARISON OF INSTRUCTION SETS
This section provides detailed analysis of differences between M68HC11 instructions and CPU16 instructions. Topics include functionally equivalent instructions, instructions with the same mnemonic that operate differently, functions that perform the same operation in a different way, and unimplemented instructions. 4.1 Functionally Equivalent Instructions The CPU16 has a number of instructions that are functionally equivalent to M68HC11 instructions -- a CPU16 instruction with a different mnemonic that performs the same task as an M68HC11 instruction. The following paragraphs give the mnemonic of the M68HC11 instruction, then discuss the equivalent CPU16 operation. 4.1.1 BHS The BHS mnemonic is used in the M68HC11 CPU instruction set to differentiate a branch based on a comparison of unsigned numbers from a branch based on operations that clear the Carry bit. The CPU16 uses only the BCC mnemonic. 4.1.2 BHO The BLO mnemonic is used in the M68HC11 CPU instruction set to differentiate a branch based on a comparison of unsigned numbers from a branch based on operations that set the Carry bit. The CPU16 uses only the BCS mnemonic. 4.1.3 CLC The CLC instruction has been replaced by ANDP. ANDP performs AND between the content of the condition code register and an unsigned immediate operand, then replaces the content of the CCR with the result. The PK extension field (CCR[3:0]) is not affected. The following code can be used to clear the C bit in the CCR: ANDP #$FEFF The ANDP instruction can clear the entire CCR, except for the PK extension field, at once. 4.1.4 CLI The CLI instruction has been replaced by ANDP. ANDP performs AND between the content of the condition code register and an unsigned immediate operand, then replaces the content of the CCR with the result. The PK extension field (CCR[3:0]) is not affected. The following code can be used to clear the IP field in the CCR: ANDP #$FF1F The ANDP instruction can clear the entire CCR, except for the PK extension field, at once.

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4.1.5 CLV The CLV instruction has been replaced by ANDP. ANDP performs AND between the content of the condition code register and an unsigned immediate operand, then replaces the content of the CCR with the result. The PK extension field (CCR[3:0]) is not affected. The following code can be used to clear the V bit in the CCR: ANDP #$FDFF The ANDP instruction can clear the entire CCR, except for the PK extension field, at once. 4.1.6 DES The DES instruction has been replaced by AIS. AIS adds a 20-bit value to concatenated SK and SP. The 20-bit value is formed by sign-extending an 8-bit or 16-bit signed immediate operand. The following code can be used to perform a DES: AIS ­1 CPU16 stacking operations normally use 16-bit words and even word addresses, while M68HC11 CPU stacking operations normally use bytes and byte addresses. If the CPU16 stack pointer is misaligned as a result of a byte operation, performance can be degraded. 4.1.7 DEX The DEX instruction has be