Text preview for : Eltax_AVR-800_service_manual.pdf part of Eltax avr-800 service manual in two parts (pdf format) for Eltax AVR-800 receiver (also made as Centrum Titan 500 receiver)
Back to : Eltax_AVR-800_service_man | Home
AVR-800
6.1 Channel
Home Theatre Receiver
SERVICE MANUAL
CONTENTS
Specifications .......................................................... 2
Measurements And Adjustments ............................ 3
Troubleshooting....................................................... 5
IC Internal Diagrams ............................................... 6
Electrical Parts List................................................ 27
Block Diagram ....................................................... 33
Wiring Diagram...................................................... 35
Schematic Diagrams ............................................. 37
Printed Circuit Boards ........................................... 45
Exploded View....................................................... 53
SPECIFICATIONS
Amplifier Section AM Tuner Section
Output Power Tuning Range:
Stereo Mode : 120W/CH 522 kHz 1,620 kHz (9 kHz steps)
(1% THD 1KHz 8ohm DIN) Usable Sensitivity: 55 dB/m
Surround Mode : 92W/CH Total Harmonic Distortion: 0.8% at 85 dB/m
(1% THD 1KHz 8ohm DIN) Signal-to-Noise Ratio: 45 dB at 85 dB/m
Video Section
THD : 0.01% Input Sensitivity/Impedance: 1.0 Vp-p/75 ohms
Output Level/Impedance: 1.0 Vp-p/75 ohms
DOLBY DIGITAL Mode:
Surround : 0 ~ 15 ms General
Center : 0 ~ 5 ms
Back surround : 0 ~ 20 ms
Power Requirements:
230 V AC, 50 Hz
DOLBY PRO LOGIC Mode (Surround):
Music : 0~5 ms
Power Consumption:
320W
Movie : 10~25 ms
Emulation : 10~25 ms
AC Outlets:
Switched x 1, 100 W max.
Frequency Response:
*LINE: 10 Hz 70 kHz, +1/ 3 dB
Signal-to-Noise Ratio: Dimensions (W x H x D)
435 x 165 x 350 mm (17-1/8" x 6-1/2" x 13-3/4")
*LINE: 100dB (IHF-A)
Tone Control: Weight (net):12Kg
BASS: ± 10 dB at 100 Hz
TREBLE: ± 10 dB at 10 kHz
Digital Audio Section
Sampling Frequency: 32 kHz, 44.1 kHz, 48 kHz, 96 kHz
DIGITAL Input Level/Impedance:
DIGITAL 1, 2 (OPTICAL): 15 dBm -- 21 dBm
DIGITAL 3 (COAXIAL): 0.5 Vp-p / 75 ohms
* LINE means CD, TAPE, VCR/VID 1, TV/VID 2, AUX/VID 3 and
DVD/CD.
FM Tuner Section
(Without notes 100.1 MHz, 65 dBf) < Improvements may result in specifications and features
Tuning Range: changing without notice.
87.5 MHz 108.0 MHz (50 kHz steps)
Usable Sensitivity (IHF): < Illustrations may differ slightly from production models.
Mono: 11.2 dBf
50 dB Quieting Sensitivity:
Mono: 15.3 dBf
Stereo: 38.5 dBf
Capture Ratio: 2.0 dB
Image Rejection Ratio: 45 dB
AM Suppression Ratio: 55 dB
Total Harmonic Distortion (1 kHz):
Mono: 0.2%
Stereo: 0.3%
Frequency Response: 30 Hz 15 kHz, +1/ 1.5 dB
Stereo Separation (1 kHz): 40 dB
Signal-to-Noise Ratio:
Mono: 70 dB
Stereo: 65 dB
-2-
MEASUREMENTS AND ADJUSTMENTS
ALIGNMENT INSTRUCTIONS
EQUIPMENT NEEDED
AM Signal Generator
FM Signal Generator
Oscilloscope
VTVM(AC,DC)
Test loop antenna(AM Adjustment)
Dummy antenna(FM Adjustment)
IMPORTANT
1.Check power-source voltage.
2.Set the function switch to band aligned.
3.Keep the signal input as low as possible to adjust accurately.
4.Modulation and modulation frequency.
Item Modulation Modulation frequency
Band
AM 30% 400Hz
FM 100%(40KHz Dev.) 400Hz
TUNER MODULE
ADJUSTMENT POINT
KST-M9014MS1(0)-70
-3-
FM/AM AUTO STOP LEVEL ADJUSTMENT
FM Signal Generator .. .. .. .. Connect to FM ANT Jack (FM IN) through the dummy.
AM Signal Generator .. .. .. .. Connect to AM ANT. Coil the through the Loop anten na.
BAND Step Signal Generator Adjust for Adjustment
1 999§Õ 82dB TUNED Display ON SVR03
AM
2 999§Õ 81dB TUNED Display OFF SVR03
1 100.10§Ö 25dB TUNED Display ON SVR01
FM
2 100.10§Ö 24dB TUNED Display OFF SVR01
AC EVM OSCILLOSOPE
AM SG
KHz
OUT
AM LOOP ANTENNA
OUTPUT
60 cm
AC EVM OSCILLOSOPE
FM SG
MHz
OUT
75 ohm
OUTPUT
FM ANT.
-4-
TROUBLESHOOTING
Problem Probable Cause Remedy
Amplifier
When listening to the music in stereo, Speakers are connected wrong. After checking, if needed, reconnect.
left/right speakers sounds reversed.
Low hum or buzzer sound. Power line of a fluorescent light is installed Place this product as far away as possible
near this product. from electric devices with interference.
Sound is only heard from one channel. One of the input cords is disconnected. Connect the input cords securely.
The BALANCE control is set to one side. Adjust the BALANCE control.
Sound cuts off during listening to the Speaker impedance is less than prescribed After turning off the power and then
music or no sound even though power is for this unit. turning it on again, reduce the volume or
ON. change to the correct 8 ohm speakers.
No sound. A/B Speaker selectors are turned off. Press the A or B speaker selector as applicable.
Low bass response. Speaker polarity (+/) is reversed. Check all speakers for correct polarity.
Tuner
An unusual hissing noise is heard when A slight noise may be heard because the · Try reducing the treble sound by turning
listening to the broadcast in stereo, but not method used for modulation of FM stereo the treble controls.
heard when listening monaurally. broadcasts is different than that used for · Try changing the location, height and/or
monaural broadcasts. direction of the antenna.
Noise is excessive in both stereo and · Set the FM mode to monaural by
Poor location and/or direction of the
monaural broadcasts. pressing the STEREO/MONO button.
antenna.
(Note that the broadcast will then be
Transmitting station is too far away. heard as monaural sound).
· If an indoor antenna is being used,
Sound is distorted and/or the volume level Broadcast signals are being disturbed. change to an outdoor antenna.
becomes low. · Try using an antenna with more
Excessive distortion in the sound of stereo Speaker system connections are not elements.
broadcasts. correct.
Surround Effects The center and rear speakers only operate when the unit is set on a Surround Sound mode and
the source material being played is recorded or broadcast in Dolby Digital EX, DTS/ES, Dolby Pro LogicII
surround sound. Stereo broadcasts or recordings will produce some rear channel effects when played in a
surround mode. However, mono sources will not produce any sound from the rear speakers.
No sound from the Surround speakers. SURROUND ON/OFF button is set to OFF. Set the button to the desired surround
mode position.
Source being played is not recorded or Use surround or stereo source.
broadcast in surround sound or stereo.
One or more rear speaker wires is not Check all rear speaker wires for good
making good contact. connection.
No sound from the center speaker. SURROUND mode button is not set to DOLBY Set the button to Dolby Digital EX, DTS/ES,
DIGITAL, DTS, DOLBY PRO LOGICII or 3 STEREO. Dolby Pro LogicII or 3 STEREO.
No sound from the surround back speaker The surround back speaker cable Connect the cable correctly.
connection is incomplete Surround mode
is not EX/ES mode. Set surround mode EX/ES Make the
Surround back = NONE has been selected correct setting.
in SPEAKERS Configuration.
No suond from the front speaker. 'Short pin's not insert EQ jack Insert the 'short pin' Connect the speaker
When speaker A and B is selected both A and B.
Simultaneously, but speaker B is Not
connection. Select speaker A only
Remote Control Unit
The batteries are exhausted. Replace with new batteries.
Remote control not working.
The remote control unit is too far from the Operate the remote control unit
receiver or out of the effective range. within the effective range.
-5-
IC INTERNAL DIAGRAMS
TC9163AF (FUNCTION/INPUT) : IC51
BLOCK DIAGRAM
TC9164AF (FUNCTION/INPUT) : IC53
BLOCK DIAGRAM
Vss GND VDD
1 14 28
L-S 1 2 27 R-S 1
L-S 2 3 26 R-S 2
L-S 3 4 25 R-S 3
L-S 4 5 24 R-S 4
LATCH CIRCUIT
LEVEL SHIFTER
LEVEL SHIFTER
LATCH CIRCUIT
L-COM 1 6 23 R-COM1
L-S 5 7 22 R-S5
L-S 6 8 21 R-S 6
L-COM2 9 20 R-COM 2
L-S 7 10 19 R-S 7
L-S 8 11 18 R-S 8
L-COM 3 12 17 R-COM3
ST 13 16 DATA
15 CK
SHIFT REGISTER
-6-
TC9162AF (FUNCTIOIC
(FUNCTION/INPUT) : IC54
BLOCK DIAGRAM
Vss GND VDD
1 14 28
L-S 1 2 27 R-S 1
L-S 2 3 26 R-S 2
L-COM 1 4 25 R-COM1
L-S 3 5 24 R-S 3
LATCH CIRCUIT
LEVEL SHIFTER
LEVEL SHIFTER
LATCH CIRCUIT
L-S 4 6 23 R-S 4
L-COM 2 7 22 R-COM 2
L-S 5 8 21 R-S 5
L-S 6 9 20 R-S 6
L-COM 3 10 19 R-COM3
L-S 7 11 18 R-S 7
L-COM 4 12 17 R-COM 4
ST 13 16 DATA
15 CK
SHIFT REGISTER
TC9459F(VOLUME) : IC55
BLOCK DIAGRAM
-7-
M62446FP(VOLUME) : IC56
BLOCK DIAGRAM
PIN CONFIGRATION
-8-
AK5381 (A/D CONVERTER) : IC57
VA AGND VD DGND MCLK
Clock Divider
Decimation
AINL
Modulator Filter
LRCK
SCLK
Decimation
AINR
Modulator Filter
Serial I/O SDTO
Interface
VCOM Voltage Reference
CKS2 CKS1 CKS0 PDN DIF
PIN / FUNCTION
No. Pin Name I/O Function
1 AINR I Rch Analog Input Pin
2 AINL I Lch Analog Input Pin
3 CKS1 I Mode Select 1 Pin
Common Voltage Output Pin, VA/2
4 VCOM O
Bias voltage of ADC input.
5 AGND - Analog Ground Pin
6 VA - Analog Power Supply Pin, 4.5 5.5V
7 VD - Digital Power Supply Pin, 2.7 5.5V(fs=4k 48kHz), 3.0 5.5V(fs=48k 96kHz)
8 DGND - Digital Ground Pin
Audio Serial Data Output Pin
9 SDTO O
"L" Output at Power-down mode.
Output Channel Clock Pin
10 LRCK I/O
"L" Output in Master Mode at Power-down mode.
11 MCLK I Master Clock Input Pin
Audio Serial Data Clock Pin
12 SCLK I/O
"L" Output in Master Mode at Power-down mode.
Power Down Mode Pin
13 PDN I
"H": Power up, "L": Power down
Audio Interface Format Pin
14 DIF I
"H" : 24bit I2S Compatible, "L" : 24bit MSB justified
15 CKS2 I Mode Select 2 Pin
16 CKS0 I Mode Select 0 Pin
Note: All digital input pins should not be left floating.
-9-
AK4358 (D/A CONVERTER) : IC58
DZF Audio
LOUT1+ I/F MCLK
LOUT1-
SCF DAC DATT
LRCK
BICK
ROUT1+
SCF DAC DATT SDTI1
ROUT1-
PCM SDTI2
SDTI3
LOUT2+
SCF DAC DATT SDTI4
LOUT2-
ROUT2+ Control 3-wire
ROUT2-
SCF DAC DATT
Register or I2C
LOUT3+
LOUT3-
SCF DAC DATT DCLK
DSDL1
ROUT3+ DSDR1
ROUT3-
SCF DAC DATT DSDL2
DSD DSDR2
LOUT4+
SCF DAC DATT DSDL3
LOUT4-
DSDR3
DSDL4
ROUT4+ DSDR4
ROUT4-
SCF DAC DATT
AK4358
PIN LAYOUT (To be determined)
ROUT1+
ROUT2+
ROUT3+
LOUT2+
LOUT3+
LOUT4+
ROUT1-
ROUT3-
ROUT2-
LOUT4-
LOUT2-
LOUT3-
38
37
48
47
46
45
44
43
42
41
40
39
LOUT1- 1 36 AVSS
LOUT1+ 2 35 AVDD
DZF3 3 34 VREFH
DZF2 4 33 ROUT4+
DZF1 5 AK4358VQ 32 ROUT4-
CAD0 6 31 DIF0
NC 7 30 DSDR3
Top View
PDN 8 29 DSDL3
BICK 9 28 DSDR2
MCLK 10
TBD 27 DSDL2
DVDD 11 26 DSDR1
DVSS 12 25 DSDL1
15
24
13
14
16
17
18
19
20
21
22
23
CSN/CAD1
CCLK/SCL
CDTI/SDA
DSDR4
DSDL4
SDTI4
SDTI1
SDTI2
SDTI3
LRCK
DCLK
I2C
- 10 -
PIN DESCRIPTION
No. Pin Name I/O Function
1 LOUT1- O DAC 1 Lch Negative Analog Output Pin
2 LOUT1+ O DAC 1 Lch Positive Analog Output Pin
3 DZF3 O Zero Input Detect 3 Pin
4 DZF2 O Zero Input Detect 2 Pin
5 DZF1 O Zero Input Detect 1 Pin
6 CAD0 I Chip Address 0 Pin
Auto Setting Mode Disable Pin(Pull-down Pin)
7 ACKSN I
"L":Auto Setting Mode, "H":Manual Setting Mode
Power-Down Mode Pin
8 PDN I When at"L",the AK4358 is in the power-down mode and is held in
reset.
9 BICK I Audio Serial Data Clock Pin
Master Clock Input Pin
10 MCLK I
An external TTL clock should be input on this pin.
11 DVDD - Digital Power Supply Pin. +4.75~+5.25V
12 DVSS - Digital Ground Pin
13 SDTI4 I DAC4 Audio Serial Data Input Pin
14 SDTI1 I DAC1 Audio Serial Data Input Pin
15 SDTI2 I DAC2 Audio Serial Data Input Pin
16 SDTI3 I DAC3 Audio Serial Data Input Pin
17 LRCK I L/R Clock Pin
Control Mode Select Pin
18 I2C I
"L":3-wire Serial, "H":I²C Bus
Control Data Clock Pin
19 CCLK/SCL I
I2C="L":CCLK(3-wire Serial),I2C="H":SCL(I²C Bus)
Control Data Input Pin
20 CDTI/SDA I/O
I2C="L":CDTI(3-wire Serial),I2C="H":SDA(I²C Bus)
Chip Select Pin
21 CSN/CAD1 I
I2C="L":Csn(3-wire Serial),I2C="H":CAD1(I²C Bus)
22 DCLK I DSD Clock Pin
23 DSDL4 I DAC4 DSD Lch Data Input Pin
24 DSDR4 I DAC4 DSD Rch Data Input Pin
25 DSDL1 I DAC1 DSD Lch Data Input Pin
26 DSDR1 I DAC1 DSD Rch Data Input Pin
27 DSDL2 I DAC2 DSD Lch Data Input Pin
28 DSDR2 I DAC2 DSD Rch Data Input Pin
29 DSDL3 I DAC3 DSD Lch Data Input Pin
30 DSDR3 I DAC3 DSD Rch Data Input Pin
31 DIF0 I Audio Data Interface Format 0 Pin
32 ROUT4- O DAC4 Rch Negative Analog Output Pin
33 ROUT4+ O DAC5 Rch Positive Analog Output Pin
34 VREFH I Positive Voltage Reference Input Pin
35 A VDD - Analog Power Supply Pin. +4.75~+5.25V
36 A VSS - Analog Ground Pin
37 LOUT4- O DAC4 Lch Negative Analog Output Pin
38 LOUT4+ O DAC4 Lch Positive Analog Output Pin
39 ROUT3- O DAC3 Rch Negative Analog Output Pin
40 ROUT3+ O DAC3 Rch Positive Analog Output Pin
41 LOUT3- O DAC3 Lch Negative Analog Output Pin
42 LOUT3+ O DAC3 Lch Positive Analog Output Pin
43 ROUT2- O DAC2 Rch Negative Analog Output Pin
44 ROUT2+ O DAC2 Rch Positive Analog Output Pin
45 LOUT2- O DAC2 Lch Negative Analog Output Pin
46 LOUT2+ O DAC2 Lch Positive Analog Output Pin
47 ROUT1- O DAC1 Rch Negative Analog Output Pin
48 ROUT1+ O DAC1 Rch Positive Analog Output Pin
- 11 -
AUDIO DSP (CS493264 - CLG) : IC59
PIN ASSIGNMENT.(CS493264)
VD1
DGND1
MCLK
AUDATA3, XMT958
SCLK
WR,DS,EMWR,GPIO10 LRCLK
RD,R/W,EMOE,GPIO11 AUDATA0
A1,SCDIN AUDATA1
A0,SCCLK AUDATA2
DATA7,EMAD7,GPIO7 6 5 4 3 2 1 44 43 42 41 40 DC
7 39
DATA6,EMAD6,GPIO6 DD
8 38
DATA5,EMAD5,GPIO5 9 37 RESET
10 36
DATA4,EMAD4,GPIO4 CS493XXX-CLG AGND
11 44-pin PLCC 35
VD2 12 34 VA
13 33
DGND2 14
Top View 32 FILT1
DATA3,EMAD3,GPIO3 15 31 FILT2
16 30
DATA2,EMAD2,GPIO2 CLKSEL
17 29
DATA1,EMAD1,GPIO1 18 19 20 21 22 23 24 25 26 27 28 CLKIN
DATA0,EMAD0,GPIO0 CMPREQ,LRCLKN2
CS CMPCLK,SCLKN2
SCDIO,SCDOUT,PSEL,GPIO9 CMPDAT,SCLKN2,RCV958
ABOOT,INTREQ LRCLKN1
EXTMEM,GPIO8 SCLKN1,STCCLK2
DGND3
SDATAN1
VD3
(TOP VIEW)
BlOCK DIAGRAM(CS493264)
RD, WR, SCDIO,
DATA7:0, R/W, DR, SCDOUT,
EMAD7:0, EMOE, EMWR, PSEL, A0, A1, A800T EXTMEM.
RESET GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK SCDIN INTERQ GPIO8
CMPDAT DD
SDATAN2 Parallel or Serial Host Interface DC
Compressed
CMPCLK Data Input Framer
SCLKN2 Interface Shifter
CMPREQ 24-Bit MCLK
LRCLKN2 Input DSP Processing
Buffer
Controller SCLK
SCLKN1 RAM RAM
STCCLK2 Digital Output
Program Data
Audio Formatter
LRCLKN1 Memory Memory RAM LRCLK
Input
SDATAN1 Interface RAM Input ROM ROM Output
Buffer Program Data Buffer AUDA
Memory Memory
CLKIN PLL
STC XMT95
CLKSEL Clock Manager
FILTD FILTS VA AGND DGND(3:1) VD(3:1)
- 12 -
PIN DESCRIPTION.(CS493264)
PIN No. Pin Name I/O Function
1,12,23 +VD1 - Digital Power supply. Normally +2.5v
2,13,24 DGND - Digital Ground
3 AUD3 O SPDIF transmitter output/Digital audio output(N.C)
4 WR I Host write strobe pin(connected to GND with an external resistor)
5 RD I Host parallel output enable pin(pulled up with an external resistor)
6 CS_DA I SPI Serial data input pin
7 CS_CK I Serial control clock input pin
8 EMAD7 I/O
9 EMAD6 I/O
10 EMAD5 I/O
11 EMAD4 I/O Serial data IN/OUTPUT pins(pulled up with an external resistor)
14 EMAD3 I/O
15 EMAD2 I/O
16 EMAD1 I/O
17 EMAD0 I/O
18 CS_CE I Host parallel chip select pin
19 SCDIO(AK_DOUT) O Serial control port data ouput pin
20 INTREQ O Control port interrupt request output pin
21 EXTMEM I/O External Memory Chip Selector(pulled up with an external resistor)
22 SDATAN1(SDI) I PCM audio data input number 1 pin
25 SCLKN1(BICK) I PCM audio input bit clock pin
26 LRCLKN1(LRCK) I PCM audio input sample rate clock pin
27 CMPDAT(SDI) I PCM audio data input number 2 pin
28 CMPCLK(BICK) I PCM audio input bit clock pin
29 CREQ(LRCK) I PCM audio input sample rate clock pin
30 CLKIN(XIN) I Master clock input(used external clock)
31 CLKSEL(GND) I DSP clock mode select pin: connect the GND
32 FILT1 Connects to an external filter for the on-chip phase-locked loop
33 FILT1 Connects to an external filter for the on-chip phase-locked loop
34 +2.5V - Analog Power supply for clock generator . Normally +2.5V
35 AGND - Analog ground supply for clock generator PLL.
36 RESET(CS_RST) I Master reset input pin
37 DBDATA - Reserved pin and should be pulled up with an external resistor.
38 DBCLK - Reserved pin and should be pulled up with an external resistor.
39 AUD2(SDO2) O PCM multi-format digital-audio data ouput2 pin
40 AUD1(SDO1) O PCM multi-format digital-audio data ouput1 pin
41 AUD0(SDO0) O PCM multi-format digital-audio data ouput0 pin
42 LRCLK I Audio output sample rate clock pin
43 SCLK(BICK) I Audio ouput bit clock pin
44 MCLK I Audio master clock output pin
- 13 -
TC74HCU04(INVERTER) : IC60
- 14 -
AK4114VQ(DIR) : IC66
TOP VIEW
TEST1
VCOM
AVDD
AVSS
AVSS
AVSS
INT1
RX3
RX2
RX1
RX0
R
37
48
47
46
45
44
43
42
41
40
39
38
IPS0/RX4 1 36 INT0
AVSS 2 35 OCKS0/CSN/CAD0
DIF0/RX5 3 34 OCKS1/CCLK/SCL
TEST2 4 33 CM1/CDTI/SDA
DIF1/RX6 5 AK4114VQ 32 CM0/CDTO/CAD1
AVSS 6 31 PDN
DIF2/RX7 7 30 XTI
Top View
IPS1/IIC 8 29 XTO
P/SN 9 28 DAUX
XTL0 10 27 MCKO2
XTL1 11 26 BICK
VIN 12 25 SDTO
24
13
14
15
16
17
18
19
20
21
22
23
MCKO1
LRCK
DVSS
DVDD
TVDD
NC
BOUT
VOUT
COUT
UOUT
TX0
TX1
BLOCK DIAGRAM
AVSS AVDD R XTI XTO
RX0 X'tal
RX1 Clock Oscillator
RX2 8 to 3 Recovery Clock MCKO1
RX3 Input Generator MCKO2
RX4
Selector
RX5 DEM
RX6
DAIF LRCK
RX7 Audio
BICK
Decoder I/F
SDTO
TX0
DAUX
TX1
PDN
DIT
DVDD CSN
Error & Q-subcode CCLK
DVSS AC-3/MPEG µP I/F
STATUS buffer CDTO
TVDD Detect Detect CDTI
VIN B,C,U,VOUT INT0 INT1 P/S="L" IIC
- 15 -
DIR IC PIN FUNCTION
PIN/FUNCTION
No. Pin Name I/O Function
IPS0 I Input Channel Select 0 Pin in Parallel Mode
1
RX4 I Receiver Channel 4 Pin in Serial Mode (Internal biased pin)
No Connect
2 NC(AVSS) I
No internal bonding. This pin should be connected to AVSS.
DIF0 I Audio Data Interface Format 0 Pin in Parallel Mode
3
RX5 I Receiver Channel 5 Pin in Serial Mode (Internal biased pin)
TEST 2 pin
4 TEST2 I
This pin should be connect to AVSS.
DIF1 I Audio Data Interface Format 1 Pin in Parallel Mode
5
RX6 I Receiver Channel 6 Pin in Serial Mode (Internal biased pin)
No Connect
6 NC(AVSS) I
No internal bonding. This pin should be connected to AVSS.
DIF2 I Audio Data Interface Format 2 Pin in Parallel Mode
7
RX7 I Receiver Channel 7 Pin in Serial Mode (Internal biased pin)
IPS1 I Input Channel Select 1 Pin in Parallel Mode
8 IIC Select Pin in Serial Mode.
IIC I
"L": 4-wire Serial, "H": IIC
Parallel/Serial Select Pin
9 P/SN I
"L": Serial Mode, "H": Parallel Mode
10 XTL0 I X'tal Frequency Select 0 Pin
11 XTL1 I X'tal Frequency Select 1 Pin
12 VIN I V-bit Input Pin for Transmitter Output
13 TVDD I Input Buffer Power Supply Pin, 3.3V or 5V
No Connect
14 NC I
No internal bonding. This pin should be open or connected to DVSS.
15 TX0 O Transmit Channel (Through Data) Output 0 Pin
When TX bit = "0", Transmit Channel (Through Data) Output 1 Pin.
16 TX1 O
When TX bit = "1", Transmit Channel (DAUX Data) Output Pin (Default).
Block-Start Output Pin for Receiver Input
17 BOUT O
"H" during first 40 flames.
18 COUT O C-bit Output Pin for Receiver Input
19 UOUT O U-bit Output Pin for Receiver Input
20 VOUT O V-bit Output Pin for Receiver Input
21 DVDD I Digital Power Supply Pin, 3.3V
22 DVSS I Digital Ground Pin
23 MCKO1 O Master Clock Output 1 Pin
24 LRCK I/O Channel Clock Pin
25 SDTO O Audio Serial Data Output Pin
26 BICK I/O Audio Serial Data Clock Pin
27 MCKO2 O Master Clock Output 2 Pin
28 DAUX I Auxiliary Audio Data Input Pin
29 XTO O X'tal Output Pin
30 XTI I X'tal Input Pin
- 16 -
PIN/FUNCTION (Continued)
No. Pin Name I/O Function
Power-Down Mode Pin
31 PDN I
When "L", the AK4114 is powered-down and reset.
CM0 I Master Clock Operation Mode 0 Pin in Parallel Mode
32 CDTO O Control Data Output Pin in Serial Mode, IIC= "L".
CAD1 I Chip Address 1 Pin in Serial Mode, IIC= "H".
CM1 I Master Clock Operation Mode 1 Pin in Parallel Mode
33 CDTI I Control Data Input Pin in Serial Mode, IIC= "L".
SDA I/O Control Data Pin in Serial Mode, IIC= "H".
OCKS1 I Output Clock Select 1 Pin in Parallel Mode
34 CCLK I Control Data Clock Pin in Serial Mode, IIC= "L"
SCL I Control Data Clock Pin in Serial Mode, IIC= "H"
OCKS0 I Output Clock Select 0 Pin in Parallel Mode
35 CSN I Chip Select Pin in Serial Mode, IIC="L".
CAD0 I Chip Address 0 Pin in Serial Mode, IIC= "H".
36 INT0 O Interrupt 0 Pin
37 INT1 O Interrupt 1 Pin
38 AVDD I Analog Power Supply Pin, 3.3V
External Resistor Pin
39 R -
18k +/-1% resistor should be connected to AVSS externally.
Common Voltage Output Pin
40 VCOM -
0.47µF capacitor should be connected to AVSS externally.
41 AVSS I Analog Ground Pin
Receiver Channel 0 Pin (Internal biased pin)
42 RX0 I
This channel is default in serial mode.
No Connect
43 NC(AVSS) I
No internal bonding. This pin should be connected to AVSS.
44 RX1 I Receiver Channel 1 Pin (Internal biased pin)
TEST 1 pin.
45 TEST1 I
This pin should be connected to AVSS.
46 RX2 I Receiver Channel 2 Pin (Internal biased pin)
No Connect
47 NC(AVSS) I
No internal bonding. This pin should be connected to AVSS.
48 RX3 I Receiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins should not be left floating.
- 17 -
LA7952 (VIDEO SWITCH) : IC77,78
NJM2296M (VIDEO SWITCH) : IC79
BLOCK DIAGAM
V+ SW2 SW1 SW5
16 10 14 2
Vin1 13
20K
S5
Vin2 9 S1
6.2dB
Amp
75
dirver 1 Vout1
20K S2
20K
Vin3 7 S6
S4
20K 6.2dB
Amp
75
dirver 15 Vout2
20K
Vin4 5
20K S3
75
S7
6.2dB
Amp dirver 11 Vout3
Vin5 3
20K 20K
4 6 12 8
SW3 SW4 V-
GND
- 18 -
MB90F476AFPG(FLASH U-COM) : IC91
BLOCK DIAGAM
Clock control CPU
X0, X1 RSTX 5 circuit
X0, X1A F2MC-16LX family core
RAM Interrupt controller
PPG0, 1
ROM
8-/16-bit PPG PPG2, 3
PPG4, 5
2
EI OS
AIN0, 1
Communication 8-/16-bits UD counter BIN0, 1
prescaler ZIN0, 1
2
SIN0 EXTC
SOT0 UART µPG MT00
SCK0 MT01
I/O expanded Chip select CS0, 1, 2, 3
SIN1, 2
serial
SOT1, 2 interface x 2
channels I/O timer
SCK1, 2
16-bit input capture x 2 IN0, 1
AVCC
16-bit output conveyer x 6 OUT0, 1, 2,
AVRH. L A/D converter
(10 bits) 16-bit free-run timer 3, 4, 5
AVSS
ADTG 16-bit reload timer TIN0
AN0 to 7 x 2 channels TOT0
PWC0 16-bit PWC SCL
I2C interface
PWC1 3 channels SDA
PWC2
8
External interrupt IRQ0 to 7
I/O port
8 8 8 8 8 8 8 8 8 8 4
P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0
P07 P17 P27 P37 P47 P57 P67 P77 P87 P97 PA3
Fig. 1.1 Block Diagram (MB90470)
P00 to P07 (8): Provided with input pull-up resistor setting register
P10 to P17 (8): Provided with input pull-up resistor setting register
P40 to P47 (8): Provided with open-drain setting register
P70 to P75 (6): Provided with open-drain setting register
P76 to P77 (2): Open-drain
Note: In the figure above, the I/O port shares the pins with each internal functional block. When the pins
are used as internal module pins, they cannot be used as I/O port pins.
- 19 -
TOP VIEW
P17/AD15/D15
P16/AD14/D14
P15/AD13/D13
P14/AD12/D12
P13/AD11/D11
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P0