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Hi3520 H.264
02
2010-01-19
N/A
©
518129
http://www.hisilicon.com
+86-755-28788858
+86-755-28357515
[email protected]
© 20092010
©
Hi3520
About This Document.....................................................................................................................1
1 Product Description...................................................................................................................1-1
1.1 System Architecture ....................................................................................................................................1-1
1.1.1 Overview ...........................................................................................................................................1-1
1.1.2 Processor System...............................................................................................................................1-2
1.1.3 Graphics Processing ..........................................................................................................................1-2
1.1.4 Video Encoding and Decoding..........................................................................................................1-3
1.1.5 Encryption/Decryption Engine..........................................................................................................1-3
1.1.6 Memory Controller Interface.............................................................................................................1-3
1.1.7 Ethernet Interface ..............................................................................................................................1-4
1.1.8 Video Interface ..................................................................................................................................1-4
1.1.9 Audio Interface..................................................................................................................................1-4
1.1.10 MMC/SD/SDIO Controller .............................................................................................................1-5
1.1.11 PCI Interface....................................................................................................................................1-5
1.1.12 USB Interface..................................................................................................................................1-5
1.1.13 Other Peripheral Interface ...............................................................................................................1-5
1.1.14 Hardware Feature ............................................................................................................................1-6
1.2 Application Scenario ...................................................................................................................................1-6
2 Hardware .....................................................................................................................................2-1
2.1 Pin Description ............................................................................................................................................2-1
2.1.1 Power Pins.........................................................................................................................................2-2
2.1.2 SIO Pins ..........................................................................................................................................2-21
2.1.3 VDAC Pins......................................................................................................................................2-23
2.1.4 DDRA Pins......................................................................................................................................2-25
2.1.5 DDRB Pins......................................................................................................................................2-30
2.1.6 EBI Pins ..........................................................................................................................................2-33
2.1.7 GMAC Pins .....................................................................................................................................2-36
2.1.8 VO Pins ...........................................................................................................................................2-37
2.1.9 PCI Pins...........................................................................................................................................2-39
2.1.10 SYS Pins........................................................................................................................................2-43
2.1.11 I2C Pins ..........................................................................................................................................2-44
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2.1.12 JTAG Pins .....................................................................................................................................2-44
2.1.13 UART Pins ....................................................................................................................................2-44
2.1.14 USB Pins .......................................................................................................................................2-45
2.1.15 VI Pins...........................................................................................................................................2-46
2.2 Description of the Software Multiplexing Pins .........................................................................................2-48
2.2.1 VI Pin Multiplexing.........................................................................................................................2-48
2.2.2 VO Pin Multiplexing .......................................................................................................................2-52
2.2.3 I2C Pin Multiplexing.......................................................................................................................2-56
2.2.4 SIO Pin Multiplexing ......................................................................................................................2-56
2.2.5 EBI Pin Multiplexing ......................................................................................................................2-57
2.2.6 GMAC Pin Multiplexing.................................................................................................................2-57
2.2.7 PCI Pin Multiplexing ......................................................................................................................2-58
2.3 Description of Hardware Multiplexing Pins..............................................................................................2-59
2.3.1 EBI Pin Multiplexing ......................................................................................................................2-59
2.3.2 PCI Pin Multiplexing ......................................................................................................................2-62
2.4 Summary of IO Config Registers ..............................................................................................................2-63
2.5 Description of the IO Config Registers .....................................................................................................2-67
2.6 Recommended Sequence of Power-On and Power-Off...........................................................................2-108
2.7 External Interrupts...................................................................................................................................2-109
2.8 Electrical Specifications ..........................................................................................................................2-109
2.8.1 DC/AC Parameters ........................................................................................................................2-109
2.8.2 Recommended Operating Conditions............................................................................................ 2-110
2.9 PCB Routing Recommendations ............................................................................................................. 2-111
2.10 Timing Parameters................................................................................................................................. 2-111
2.10.1 Primitives of Timing Diagrams ................................................................................................... 2-111
2.10.2 Timings of the DDR2 Interface ................................................................................................... 2-111
2.10.3 Timing of the GMAC Interface ................................................................................................... 2-114
2.10.4 Timing of the VI Interface........................................................................................................... 2-119
2.10.5 Timing of the VO Interface ......................................................................................................... 2-119
2.10.6 Timings of the PCI Interface .......................................................................................................2-120
2.10.7 Timing of the I2C Interface ..........................................................................................................2-121
2.10.8 Timing of the MMC Interface .....................................................................................................2-122
2.10.9 Timing of the SSP Interface.........................................................................................................2-123
2.10.10 Timing of the UART Interface...................................................................................................2-125
2.10.11 Timings of SIO Interfaces..........................................................................................................2-126
2.10.12 Timing of the SMI Interface ......................................................................................................2-128
2.11 Package and Pinout................................................................................................................................2-128
2.11.1 Package........................................................................................................................................2-128
2.11.2 Pinout ..........................................................................................................................................2-131
2.11.3 Pin Arrangement Table ................................................................................................................2-136
3 System ..........................................................................................................................................3-1
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3.1 Reset ............................................................................................................................................................3-1
3.1.1 Overview ...........................................................................................................................................3-1
3.1.2 Reset Signal Control..........................................................................................................................3-1
3.1.3 Reset Configuration...........................................................................................................................3-2
3.2 Clock ...........................................................................................................................................................3-3
3.2.1 Overview ...........................................................................................................................................3-3
3.2.2 Clock Control ....................................................................................................................................3-3
3.2.3 Clock Configuration..........................................................................................................................3-5
3.3 Processor and Address Space Mapping of the Memory ............................................................................3-16
3.3.1 Processor .........................................................................................................................................3-16
3.3.2 Address Space Mapping of the Memory .........................................................................................3-17
3.4 Interrupt System ........................................................................................................................................3-30
3.4.1 Overview .........................................................................................................................................3-30
3.4.2 Features ...........................................................................................................................................3-30
3.4.3 Function Description .......................................................................................................................3-30
3.4.4 Register Summary ...........................................................................................................................3-34
3.4.5 Register Description........................................................................................................................3-35
3.5 Direct Memory Access Controller.............................................................................................................3-40
3.5.1 Overview .........................................................................................................................................3-40
3.5.2 Features ...........................................................................................................................................3-40
3.5.3 Function Description .......................................................................................................................3-41
3.5.4 Operating Mode...............................................................................................................................3-44
3.5.5 Register Summary ...........................................................................................................................3-45
3.5.6 Register Description........................................................................................................................3-48
3.6 CIPHER.....................................................................................................................................................3-67
3.6.1 Overview .........................................................................................................................................3-67
3.6.2 Features ...........................................................................................................................................3-67
3.6.3 Function Description .......................................................................................................................3-68
3.6.4 Operating Mode...............................................................................................................................3-78
3.6.5 Register Summary ...........................................................................................................................3-80
3.6.6 Register Description........................................................................................................................3-81
3.7 Timer .........................................................................................................................................................3-95
3.7.1 Overview .........................................................................................................................................3-95
3.7.2 Features ...........................................................................................................................................3-96
3.7.3 Function Description .......................................................................................................................3-96
3.7.4 Operating Mode...............................................................................................................................3-97
3.7.5 Register Summary ...........................................................................................................................3-98
3.7.6 Register Description........................................................................................................................3-98
3.8 Watchdog.................................................................................................................................................3-107
3.8.1 Overview .......................................................................................................................................3-107
3.8.2 Features .........................................................................................................................................3-107
3.8.3 Signal Description .........................................................................................................................3-108
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3.8.4 Function Description .....................................................................................................................3-108
3.8.5 Operating Mode.............................................................................................................................3-109
3.8.6 Register Summary ......................................................................................................................... 3-110
3.8.7 Register Description...................................................................................................................... 3-111
3.9 Real Time Clock...................................................................................................................................... 3-115
3.9.1 Overview ....................................................................................................................................... 3-115
3.9.2 Features ......................................................................................................................................... 3-115
3.9.3 Function Description ..................................................................................................................... 3-115
3.9.4 Operating Mode............................................................................................................................. 3-115
3.9.5 Register Summary ......................................................................................................................... 3-117
3.9.6 Regitsr Description........................................................................................................................ 3-117
3.10 System Controller..................................................................................................................................3-121
3.10.1 Overview .....................................................................................................................................3-121
3.10.2 Features .......................................................................................................................................3-121
3.10.3 Function Description ...................................................................................................................3-121
3.10.4 Register Summary .......................................................................................................................3-127
3.10.5 Register Description ....................................................................................................................3-129
3.11 Power Management and Low-Power Mode Control .............................................................................3-173
3.11.1 Overview .....................................................................................................................................3-173
3.11.2 System Operating Modes ............................................................................................................3-174
3.11.3 Clock Gating and Clock Frequency Adjustment .........................................................................3-174
3.11.4 DDR Low-Power Contorl............................................................................................................3-175
4 Memory Controller ....................................................................................................................4-1
4.1 DDR Controller ...........................................................................................................................................4-1
4.1.1 Overview ...........................................................................................................................................4-1
4.1.2 Features .............................................................................................................................................4-1
4.1.3 Signal Description .............................................................................................................................4-1
4.1.4 Function Description .........................................................................................................................4-4
4.1.5 Operating Mode...............................................................................................................................4-12
4.1.6 Register Summary ...........................................................................................................................4-13
4.1.7 Register Description........................................................................................................................4-14
4.2 SMI Controller ..........................................................................................................................................4-29
4.2.1 Overview .........................................................................................................................................4-29
4.2.2 Features ...........................................................................................................................................4-29
4.2.3 Signal Description ...........................................................................................................................4-30
4.2.4 Function Description .......................................................................................................................4-31
4.2.5 Operating Mode...............................................................................................................................4-35
4.2.6 Register Summary ...........................................................................................................................4-38
4.2.7 Register Description........................................................................................................................4-39
4.3 NAND Flash Controller ............................................................................................................................4-52
4.3.1 Overview .........................................................................................................................................4-52
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4.3.2 Features ...........................................................................................................................................4-52
4.3.3 Description of NANDC Interfaces ..................................................................................................4-53
4.3.4 Function Description .......................................................................................................................4-54
4.3.5 Operating Modes .............................................................................................................................4-56
4.3.6 Register Summary ...........................................................................................................................4-65
4.3.7 Register Description........................................................................................................................4-66
5 GMAC ..........................................................................................................................................5-1
5.1 Overview .....................................................................................................................................................5-1
5.2 Feature.........................................................................................................................................................5-1
5.3 Signal Description .......................................................................................................................................5-2
5.4 Function Description ...................................................................................................................................5-3
5.4.1 Typical Application ...........................................................................................................................5-3
5.4.2 Frame Format ....................................................................................................................................5-4
5.4.3 Uplink and Downlink Frame Management .......................................................................................5-4
5.4.4 Flow Control of the GMAC ..............................................................................................................5-7
5.4.5 Packet Receive Interrupt Management..............................................................................................5-7
5.4.6 Packet Filtering .................................................................................................................................5-7
5.5 Operating Mode...........................................................................................................................................5-7
5.5.1 Reading and Writing the PHY...........................................................................................................5-7
5.5.2 Transmitting and Receiving Packets .................................................................................................5-7
5.6 GMAC Register Summary ..........................................................................................................................5-7
5.7 Register Description ....................................................................................................................................5-7
6 Video Interface ...........................................................................................................................6-1
6.1 VIU..............................................................................................................................................................6-1
6.1.1 Overview ...........................................................................................................................................6-1
6.1.2 Features .............................................................................................................................................6-1
6.1.3 Signal Description .............................................................................................................................6-2
6.1.4 Function Description .........................................................................................................................6-4
6.1.5 Operating Mode...............................................................................................................................6-20
6.1.6 Register Summary ...........................................................................................................................6-24
6.1.7 Register Description........................................................................................................................6-27
6.2 VOU ..........................................................................................................................................................6-75
6.2.1 Overview .........................................................................................................................................6-75
6.2.2 Features ...........................................................................................................................................6-75
6.2.3 Signal Description ...........................................................................................................................6-77
6.2.4 Function Description .......................................................................................................................6-80
6.2.5 Operating Mode...............................................................................................................................6-84
6.2.6 Register Summary ...........................................................................................................................6-88
6.2.7 Register Description......................................................................................................................6-105
7 Audio Interface...........................................................................................................................7-1
7.1 Overview .....................................................................................................................................................7-1
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7.2 Features .......................................................................................................................................................7-1
7.2.1 Features of the PCM Interface...........................................................................................................7-1
7.2.2 Features of the I2S Interface ..............................................................................................................7-1
7.3 Signal Description .......................................................................................................................................7-2
7.4 Function Description ...................................................................................................................................7-3
7.5 Operating Mode...........................................................................................................................................7-8
7.6 Register Summary ..................................................................................................................................... 7-11
7.7 Register Description ..................................................................................................................................7-13
8 MMC/SD/SDIO Controller ......................................................................................................8-1
8.1 Overview .....................................................................................................................................................8-1
8.2 Features .......................................................................................................................................................8-1
8.3 Signal Description .......................................................................................................................................8-2
8.4 Function Description ...................................................................................................................................8-3
8.5 Operating Mode...........................................................................................................................................8-8
8.5.1 Pin Multiplexing................................................................................................................................8-8
8.5.2 Clock Gating .....................................................................................................................................8-8
8.5.3 Soft Reset ..........................................................................................................................................8-8
8.6 Register Summary .....................................................................................................................................8-18
8.7 Register Description ..................................................................................................................................8-19
9 PCI.................................................................................................................................................9-1
9.1 Overview .....................................................................................................................................................9-1
9.2 Features .......................................................................................................................................................9-1
9.3 Signal Description .......................................................................................................................................9-2
9.4 Function Description ...................................................................................................................................9-4
9.5 Operating Mode...........................................................................................................................................9-6
9.5.1 Pin Multiplexing................................................................................................................................9-6
9.5.2 Clock Gating .....................................................................................................................................9-7
9.5.3 Clock Configuration..........................................................................................................................9-7
9.5.4 Soft Reset ..........................................................................................................................................9-8
9.5.5 Configuring the Operating Mode ......................................................................................................9-8
9.5.6 Transmitting Data Through the Window ...........................................................................................9-8
9.5.7 Transmitting Data Through the DMA Channel .................................................................................9-9
9.6 Register Summary ..................................................................................................................................... 9-11
9.6.1 Registers at the AHB Side ............................................................................................................... 9-11
9.6.2 Registers for the Header Region of the PCI Configuration Space ..................................................9-12
9.7 Register Description ..................................................................................................................................9-14
9.7.1 Registers at the AHB Side ...............................................................................................................9-14
9.7.2 Registers in the PCI Configuration Space .......................................................................................9-29
10 USB 2.0 Host............................................................................................................................10-1
10.1 Overview .................................................................................................................................................10-1
10.2 Features ...................................................................................................................................................10-1
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10.3 Function Description ...............................................................................................................................10-1
10.4 Operating Mode.......................................................................................................................................10-3
10.4.1 Interface Signals............................................................................................................................10-3
10.4.2 Typical Application .......................................................................................................................10-4
10.4.3 Clock Gating .................................................................................................................................10-4
10.4.4 Soft Reset ......................................................................................................................................10-5
10.5 Register Summary ...................................................................................................................................10-5
10.6 Register Description ................................................................................................................................10-5
11 Other Peripheral Interfaces..................................................................................................11-1
11.1 I2C Interface............................................................................................................................................. 11-1
11.1.1 Overview ....................................................................................................................................... 11-1
11.1.2 Features ......................................................................................................................................... 11-1
11.1.3 Signal Description ......................................................................................................................... 11-1
11.1.4 Function Description ..................................................................................................................... 11-2
11.1.5 Operating Mode............................................................................................................................. 11-4
11.1.6 Register Summary ......................................................................................................................... 11-8
11.1.7 Register Descriptions..................................................................................................................... 11-9
11.2 UART .................................................................................................................................................... 11-31
T
11.2.1 Overview ..................................................................................................................................... 11-31
11.2.2 Features ....................................................................................................................................... 11-31
11.2.3 Signal Description ....................................................................................................................... 11-31
11.2.4 Function Description ................................................................................................................... 11-33
11.2.5 Operating Mode........................................................................................................................... 11-35
11.2.6 Register Summary ....................................................................................................................... 11-38
11.2.7 Register Description .................................................................................................................... 11-39
11.3 SPI ......................................................................................................................................................... 11-52
11.3.1 Overview ..................................................................................................................................... 11-52
11.3.2 Features ....................................................................................................................................... 11-52
11.3.3 Signal Description ....................................................................................................................... 11-53
11.3.4 Function Description ................................................................................................................... 11-53
11.3.5 Operating Mode........................................................................................................................... 11-62
11.3.6 Register Summary ....................................................................................................................... 11-65
11.3.7 Register Description .................................................................................................................... 11-65
11.4 IR ........................................................................................................................................................... 11-73
11.4.1 Overview ..................................................................................................................................... 11-73
11.4.2 Features ....................................................................................................................................... 11-73
11.4.3 Signal Description ....................................................................................................................... 11-73
11.4.4 Function Description ................................................................................................................... 11-73
11.4.5 Operating Mode........................................................................................................................... 11-82
11.4.6 Register Summary ....................................................................................................................... 11-85
11.4.7 Register Description .................................................................................................................... 11-85
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11.5 GPIO...................................................................................................................................................... 11-98
11.5.1 Overview ..................................................................................................................................... 11-98
11.5.2 Features ....................................................................................................................................... 11-98
11.5.3 Signal Description ....................................................................................................................... 11-98
11.5.4 Function Description ................................................................................................................. 11-103
11.5.5 Operating Mode......................................................................................................................... 11-103
11.5.6 Register Summary ..................................................................................................................... 11-107
11.5.7 Register Description .................................................................................................................. 11-108
12 Test Interface...........................................................................................................................12-1
12.1 Overview .................................................................................................................................................12-1
12.2 Operating Modes .....................................................................................................................................12-1
12.3 JTAG Debugging.....................................................................................................................................12-1
12.3.1 JTAG Interface Signals..................................................................................................................12-1
12.3.2 Debugging Mode...........................................................................................................................12-2
13 Video Processing Module.....................................................................................................13-1
13.1 Video Codec ............................................................................................................................................13-1
13.1.1 Overview .......................................................................................................................................13-1
13.1.2 Features .........................................................................................................................................13-1
13.2 TDE .........................................................................................................................................................13-2
13.2.1 Overview .......................................................................................................................................13-2
13.2.2 Features .........................................................................................................................................13-2
A Acronyms and Abbreviations............................................................................................... A-1
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Figure 1-1 Logic block diagram of the Hi3520 ................................................................................................1-1
Figure 1-2 Block diagram of the Hi3520 in a 16-channel CIF DVR................................................................1-7
Figure 1-3 Block diagram of the Hi3520 in a 4-channel D1 DVR ...................................................................1-8
Figure 1-4 Block diagram of the Hi3520 in an 8-channel D1 DVR .................................................................1-9
Figure 2-1 Primitives of timing diagrams..................................................................................................... 2-111
Figure 2-2 Write timing of dqs_out relative to dq_out, CKP, and CKN ....................................................... 2-112
Figure 2-3 Write timing of dqs_out relative to CK....................................................................................... 2-112
Figure 2-4 Write timing of cmd/addr relative to CK .................................................................................... 2-112
Figure 2-5 DDR2 SDRAM output timing .................................................................................................... 2-113
Figure 2-6 100 Mbit/s receive timing of the MII interface ........................................................................... 2-114
Figure 2-7 10 Mbit/s receive timing of the MII interface ............................................................................. 2-115
Figure 2-8 100 Mbit/s transmit timing of the MII interface ......................................................................... 2-115
Figure 2-9 10 Mbit/s transmit timing of the MII interface ........................................................................... 2-115
Figure 2-10 Receive timing of the RGMII interface .................................................................................... 2-116
Figure 2-11 Transmit timing of the RGMII interface ................................................................................... 2-116
Figure 2-12 Read timing of the MDIO interface .......................................................................................... 2-117
Figure 2-13 Write timing of the MDIO interface.......................................................................................... 2-117
Figure 2-14 Timing parameter diagram of the MDIO interface ................................................................... 2-118
Figure 2-15 Transmit timing of the MDIO interface .................................................................................... 2-118
Figure 2-16 Timing of the VI interface......................................................................................................... 2-119
Figure 2-17 Timing of the VO interface ....................................................................................................... 2-119
Figure 2-18 Timing of the VO concatenated input interface ........................................................................2-120
Figure 2-19 Timing of the PCI interface (using the inside clock of the Hi3520) .........................................2-120
Figure 2-20 Timing of the PCI interface (using the external clock of the Hi3520) ......................................2-121
Figure 2-21 Transfer timing of the I2C interface ..........................................................................................2-121
Figure 2-22 Timing of the MMC Interface...................................................................................................2-122
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Figure 2-23 SSP_SPICK clock timing of the SSP interface .........................................................................2-123
Figure 2-24 Timing of the SSP interface in master mode (sph = 0)..............................................................2-123
Figure 2-25 Timing of the SSP interface in master mode (sph = 1)..............................................................2-124
Figure 2-26 Timing of the UART interface ..................................................................................................2-126
Figure 2-27 Receive timing of the I2S interface ...........................................................................................2-127
Figure 2-28 Transmit timing of the I2S interface ..........................................................................................2-127
Figure 2-29 Receive timing of the PCM interface........................................................................................2-127
Figure 2-30 Transmit timing of the PCM interface ......................................................................................2-128
Figure 2-31 Package dimensions (top view).................................................................................................2-129
Figure 2-32 Package dimensions (bottom view) ..........................................................................................2-129
Figure 2-33 Detail B .....................................................................................................................................2-130
Figure 2-34 Package dimensions (side view) ...............................................................................................2-130
Figure 2-35 Detail A .....................................................................................................................................2-130
Figure 2-36 Schematic colors in each pinout diagram..................................................................................2-132
Figure 2-37 Hi3520 pinout (rows AT, columns 116)................................................................................2-133
Figure 2-38 Hi3520 pinout (rows AT, columns 1732)..............................................................................2-134
Figure 2-39 Hi3520 pinout (rows UAM, columns 116) ...........................................................................2-135
Figure 2-40 Hi3520 pinout (rows UAM, columns 1732) .........................................................................2-136
Figure 3-1 Reset signal control diagram...........................................................................................................3-1
Figure 3-2 Functional block diagram of the clock management module..........................................................3-4
Figure 3-3 Address space mapping during the booting from the NOR flash..................................................3-18
Figure 3-4 Address distribution after the remapping is cleared during the booting from the NOR flash. ......3-20
Figure 3-5 Address space mapping during the booting from the NAND flash...............................................3-21
Figure 3-6 Address distribution after the remapping is cleared during the booting from the NAND flash. ...3-22
Figure 3-7 Address space mapping during the booting from the DDR...........................................................3-24
Figure 3-8 Address distribution after the remapping is cleared during the booting from the DDR................3-25
Figure 3-9 Functional block diagram of the INT............................................................................................3-31
Figure 3-10 Functional block diagram of the DMAC ....................................................................................3-41
Figure 3-11 Diagram of updating channel registers through LLI ...................................................................3-42
Figure 3-12 Structure of the DMAC LLIs ......................................................................................................3-60
Figure 3-13 3DES encryption of the 3-key operation and 2-key operation ....................................................3-68
Figure 3-14 3DES decryption of the 3-key operation and 2-key operation ....................................................3-69
Figure 3-15 ECB mode of the AES and DES algorithms ...............................................................................3-69
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Figure 3-16 ECB mode of the 3DES algorithm..............................................................................................3-70
Figure 3-17 CBC mode of the AES and DES algorithms ...............................................................................3-71
Figure 3-18 CBC mode of the 3DES algorithm..............................................................................................3-72
Figure 3-19 S-bit CFB mode of the AES and DES algorithms.......................................................................3-73
Figure 3-20 S-bit CFB mode of the 3DES algorithm .....................................................................................3-74
Figure 3-21 OFB mode of the AES algorithm ................................................................................................3-75
Figure 3-22 S-bit OFB mode of the DES algorithm .......................................................................................3-76
Figure 3-23 S-bit OFB mode of the 3DES algorithm ..........................