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MB120 IDTV
SERVICE MANUAL
Table of Contents
1. 2. A. B. 3. A. B. C. D. E. 4. A. B. C. D. E. F. G. 5. 6. INTRODUCTION .......................................................................................................................................................... 2 TUNER ........................................................................................................................................................................... 3 SI2151 Terrestrial and Cable TV Tuner: ..................................................................................................................... 3 M88TS2022 Satellite Tuner ........................................................................................................................................ 5 AUDIO AMPLIFIER STAGES...................................................................................................................................... 6 MAIN AMPLIFIER (U8) (10W/12W options) ............................................................................................................... 6 SUBWOOFER AMPLIFIER (U9) (12 W) ........................................................................................................................ 8 HEADPHONE AMPLIFIER (U59) ................................................................................................................................ 10 SUBWOOFER PREAMPLIFIER (U30) .......................................................................................................................... 12 SCART AUDIO AMPLIFIER (U31) ............................................................................................................................... 12 POWER STAGE ........................................................................................................................................................... 12 TPS54528 ................................................................................................................................................................. 13 TPS54628 ................................................................................................................................................................. 15 TPS54821 ................................................................................................................................................................. 17 FDS4685 ................................................................................................................................................................... 19 NTGS3446 ................................................................................................................................................................ 20 APL5910 ................................................................................................................................................................... 21 LM1117 .................................................................................................................................................................... 23 MICROCONTROLLER (MSTAR MSD95M0D) ........................................................................................................ 24 VIDEO BACK-END PROCESSOR (MSTAR) ........................................................................................................... 31 MST7410FE ................................................................................................................................................................... 31 7. 2Gb DDR3 SDRAM ..................................................................................................................................................... 34 Hynix H5TQ2G63GFR .................................................................................................................................................... 34 8. 4Gb DDR3L SDRAM ................................................................................................................................................... 35 Hynix H5TQ4G63GFR .................................................................................................................................................... 35 9. 32GBIT (4G X 8 BIT) NAND FLASH MEMORY ..................................................................................................... 37 MT29F4G08ABAEAWP .................................................................................................................................................. 37 10. 16M-BIT [16M x 1] CMOS SERIAL FLASH EEPROM ............................................................................................ 39 A. B. MX25L1606E SPI Flash ............................................................................................................................................. 39 M25Q32FV SPI Flash ................................................................................................................................................ 41
11. DEMODULATOR STAGE .......................................................................................................................................... 43 12. LNB SUPPLY AND CONTROL IC ............................................................................................................................ 46 TPS65233 ...................................................................................................................................................................... 46 13. SOFTWARE UPDATE ................................................................................................................................................ 47 Main SW update ........................................................................................................................................................... 47
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14. TROUBLESHOOTING ................................................................................................................................................ 48 A. B. C. D. E. F. G. H. . No Backlight Problem .............................................................................................................................................. 48 CI Module Problem .................................................................................................................................................. 50 Staying in Stand-by Mode ........................................................................................................................................ 52 IR Problem................................................................................................................................................................ 54 Keypad Touchpad Problems .................................................................................................................................... 55 USB Problems ........................................................................................................................................................... 56 No Sound Problem ................................................................................................................................................... 57 Standby On/Off Problem ......................................................................................................................................... 58 No Signal Problem .................................................................................................................................................... 58
15. GENERAL BLOCK DIAGRAM ................................................................................................................................. 59
1. INTRODUCTION
17MB120 main board is driven by MStar SOC. This IC is a single chip iDTV solution that supports channel decoding, MPEG decoding, and media-center functionality enabled by a high performance AV CODEC and CPU. This IC also supports 4K2K (UHD). Key features includes, Combo Front-End Demodulator A multi standart A/V format decoder The MACEpro video processor Home theatre sound processor Internet and Variety of Connectivity Support Dual-stream decoder for 3D contents Multi-purpose CPU for OS and multimedia Peripheral and power management
Supported peripherals are: 2 1 RF input VHF I, VHF III, UHF 1 Satellite input 1 Side AV (CVBS, R/L_Audio) 1 SCART socket(Common) 1 YPbPr / Back S-Video(Common) 1 PC input(Common) 4 HDMI input(Common) 1 Common interface(Common) 1 Optic S/PDIF output(Common) 1 Stereo audio input for PC(Common) 1 Subwoofer output(Common) 1 Headphone(Common) 1x USB3.0 and 2xUSB2.0(Common) 1 Ethernet-RJ45 (Common) 1 External Touchpad(Common)
2. TUNER
A. SI2151 TERRESTRAL AND CABLE TV TUNER:
Description: The Si2151 is Silicon Labs' sixth-generation hybrid TV tuner supporting all worldwide terrestrial and cable TV standards. Requiring no external balun, SAW filters, wirewound inductors or LNAs, the Si2151 offers the lowest-cost BOM for a hybrid TV tuner. Also included are an integrated power-on reset circuit and an option for single power supply operation. As with prior-generation Silicon Labs TV tuners, the Si2151 maintains very high linearity and low noise to deliver superior picture quality and a higher number of received stations when compared to other silicon tuners. The Si2151 offers increased immunity to WiFi and LTE interference, eliminating the need for external filtering. For the best performance with next-generation digital TV standards, such as DVB-T2/C2, the Si2151 delivers industry-leading phase noise performance. Features: Worldwide hybrid TV tuner o Analog TV: NTSC, PAL/SECAM o Digital TV: ATSC/QAM, DVBT2/T/C2/C, ISDB-T/C, DTMB 1.7 MHz, 6 MHz, 7 MHz, 8 MHz, and 10 MHz channel bandwidths 42-1002 MHz frequency range Industry-leading margin to A/74, NorDig, DTG, ARIB, EN55020, OpenCableTM,DTMB Lowest BOM for a hybrid TV tuner o No balun, SAW filters, or external inductors required o Increased ESD protection on 4pins Best-in-class real-world reception o Lowest phase noise o High Wi-Fi and LTE immunity Low power consumption o 3.3 V and 1.8 V power supplies o Integrated 1.8 V LDO for 3.3 V singlesupply operation Integrated power-on reset circuit Standard CMOS process 3x3 mm, 24-pin QFN package RoHS compliant
Figure 1.1 Si2151 Pin description
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Table 1.1 Pin Functions
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B. M88TS2022 SATELLTE TUNER
Features and General Description
Pin Assigment
5
Absolute Maximum Ratings and Recommended Operating Conditions
3. AUDIO AMPLIFIER STAGES
A. MAIN AMPLIFIER (U8) (10W/12W OPTONS)
Description AD82587D is a digital audio amplifier capable of driving a pair of 8 ohm, 20W or a single 4 ohm, 40W speaker, both which operate with play music at a 24V supply without external heat-sink or fan requirement. Using I2C digital control interface, the user can control AD82587D's input format selection, DRC (dynamic range control), mute and volume control functions. AD82587D has many built-in protection circuits to safeguard AD82587D from connection errors. Features 16/18/20/24-bit input with I2S, Left-alignment and Right-alignment data format PSNR & DR(A-weighting) Loudspeaker: 97dB (PSNR), 105dB (DR) @ 24V Multiple sampling frequencies (Fs) 32kHz / 44.1kHz / 48kHz and 64kHz / 88.2kHz / 96kHz and 128kHz/176.4kHz/192kHz System clock = 64x, 128x, 256x, 384x, 512x, 768x,1024x Fs 256x~1024x Fs for 32kHz / 44.1kHz / 48kHz 128x~512x Fs for 64kHz / 88.2kHz / 96kHz 64x~256x Fs for 128kHz /176.4kHz/192kHz Supply voltage 3.3V for digital circuit 10V~26V for loudspeaker driver 6
Loudspeaker output power for Stereo@ 24V 10W x 2ch into 8_ @ 0.16% THD+N 15W x 2ch into 8_ @ 0.18% THD+N 20W x 2ch into 8_ @ 0.24% THD+N Loudspeaker output power for Mono@ 24V 20W x 1ch into 4_ @ 0.17% THD+N 30W x 1ch into 4_ @ 0.2% THD+N 40W x 1ch into 4_ @ 0.24% THD+N Sounds processing including: Volume control (+24dB~-103dB, 0.125dB/step) Dynamic range control Power clipping Channel mixing User programmed noise gate with hysteresis window DC-blocking high-pass filter Anti-pop design Short circuit and over-temperature protection I2C control interface with selectable device address Internal PLL LV Under-voltage shutdown and HV Under-voltage detection Power saving mode Dynamic temperature control
Figure 3.2: Pin description
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Figure 3.3: Functional Block Diagram
Table3.1: Absolute Maximum Ratings
Table3.2: Recommended Operating Conditions
B. SUBWOOFER AMPLIFIER (U9) (12 W)
Description AD82586C is a digital audio amplifier capable of driving a pair of 8 ohm, 20W operating at 24V supply without external heat-sink or fan requirement with play music. AD82586C has 20 bands EQ function and can operate 20W stereo or 40W mono optionally. AD82586C can provide advanced audio processing capabilities, such as volume control, 20 bands speaker EQ, audio mixing, 3D surround and DRC (dynamic range control). These functions are fully programmable via a simple I2C control interface. Robust protection circuits are provided to protect AD82586C from damage due to accidental erroneous operating condition. AD82586C is more tolerant to noise and PVT (Process, Voltage, and Temperature) variation than the analog Class-AB or Class-D audio amplifier counterpart implemented by analog circuit design. AD82586C is pop free during instantaneous power switch because of its built-in, robust anti-pop circuit. 8
Features 16/18/20/24-bits input with I2S, Left-alingment and Right-alingment data format PSNR & DR (A-weighting) Loudspeaker: 99dB (PSNR), 104dB (DR) @24V Multiple sampling frequencies (Fs) 32kHz / 44.1kHz / 48kHz and 64kHz / 88.2kHz / 96kHz and 128kHz / 176.4kHz / 192kHz System clock = 64x, 128x, 192x, 256x, 384x, 512x, 576x, 768x, 1024x Fs 64x~1024x Fs for 32kHz / 44.1kHz / 48kHz 64x~512x Fs for 64kHz / 88.2kHz / 96kHz 64x~256x Fs for 128kHz / 176.4kHz / 192kHz Supply voltage 3.3V for digital circuit 10V~26V for loudspeaker driver Loudspeaker output power at 24V 10W x 2CH into 8 ohm @0.17% THD+N for stereo 20W x 2CH into 8 ohm @0.26% THD+N for stereo Sound processing including: 20 bands parametric speaker EQ Volume control (+24dB~-103dB, 0.125dB/step) Dynamic Range Control (DRC) Dual band DRC Power clipping 3D surround sound Channel mixing Noise gate with hysteresis window Bass/Treble tone control DC-blocking high-pass filter Anti-pop design Short circuit and over-temperature protection I2C control interface with selectable device address Support hardware and software reset Internal PLL LV Under-Voltage shutdown and HV Under-Voltage detection Power saving mode
Figure 3.4: Pin description 9
Figure 3.5: Functional Block Diagram
Table 3.3: Absolute Maximum Ratings
Table 3.4: Recommended Operating Conditions
C. HEADPHONE AMPLIFIER (U59)
Description The AD22657B is a 2-Vrms cap-less stereo line driver. The device is ideal for single supply electronics. Cap-less design can eliminate output dc-blocking capacitors for better low frequency response and save cost. The AD22657B is capable of delivering 2-Vrms output into a 10k ohm load with 3.3V supply. The gain settings can be set by users from 1V/V to 10V/V externally. The AD22657B has under voltage protection to prevent POP noise. Build-in shutdown control and de-pop control sequence also help AD22657B to be a popless device. The AD22657B is available in a 10-pin MSOP package. Features Operation Voltage: 3V to 3.6V Cap-less Output Eliminates Output Capacitors Improves Low Frequency Response Reduces POP/Clicks Low Noise and THD 10
Typical SNR 107dB Typical Vn 7uVrms Typical THD+N < 0.02% Maximum Output Voltage Swing into 2.5k Load 2Vrms at 3.3V Supply Voltage Single-ended Input External Gain Setting from 1V/V to 10V/V Fast Start-up Time: 0.5ms Integrated De-Pop Control External Under Voltage Protection Thermal Protection Less External Components Required +/-8kV IEC ESD Protection at line outputs
Figure 3.6: Pin description
Table 3.5: Pin functions
Table3.6: Recommended operating conditions
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D. SUBWOOFER PREAMPLIFIER (U30)
AD22657B is used for subwoofer out, as well.
E. SCART AUDIO AMPLIFIER (U31)
AD22657B is used for scart audio amplifier, as well.
4. POWER STAGE
Figure 4.1: Power socket and options. Power socket is used for taking voltages which are 12V, 5V and VDD_Audio. These voltages are produced in power board. Also socket is used for giving dimming, backlight and standby signals with power board. It is shown at figure 4.1.
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Figure 4.2: General illustration of voltage stages on main board. VDD_Audio goes directly to the audio side, through power socket other incoming voltages from power card are converted several voltages, shown in figure 8. List of the components are: TPS54528 TPS54628 TPS54821 FDS4685 NTGS3446 APL5910 LM1117
A. TPS54528
General Description The TPS54528 is an adaptive on-time D-CAP2 mode synchronous buck converter.The TPS54528 enables system designers to complete the suite of various end-equipment power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54528 uses the D-CAP2 mode control that provides a fast transient response with no external compensation components. The adaptive on-time control supports seamless transition between PWM mode at higher load conditions and Eco-mode operation at light loads. Eco-mode allows the TSP54528 to maintain high efficiency during lighter load conditions. The TPS54528 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR)output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between 0.76 V and 6 V. The device also features an adjustable soft start time. The TPS54528 is available in the 8-pin DDA package, and designed to operate from -40 C to 85 C. 13
Features D-CAP2 Mode Enables Fast Transient Response Low Output ripple and Allows Ceramic Output Capacitor Wide VIN Input Voltage Range: 4.5 V to 18 V Output Voltage Range: 0.76 V to 6 V Highly Efficient Integrated FETs Optimized for Lower Duty Cycle Applications- 65 mOhm (High Side) and 36 mOhm (Low Side) High Efficiency, less than 10 mikroAmper at shutdown High Initial Bandgap Reference Accuracy Adjustable Soft Start Pre-Biased Soft Start 650-kHz Switching Frequency (fSW) Cycle By Cycle Over Current Limit Auto-Skip Eco-mode for High Efficiency at Light Load Applications Wide Range of Applications for Low Voltage System Digital TV Power Supply High Definition Blu-ray Disc Players Networking Home Terminal Digital Set Top Box(STB)
Table 4.1: Recommended operating conditions
Figure 4.3: Pin Description
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Table 4.2: Pin functions.
B. TPS54628
General Description The TPS54628 is an adaptive on-time D-CAP2 mode synchronous buck converter.The TPS54628 enables system designers to complete the suite of various end-equipment power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54628 uses the D-CAP2 mode control that provides a fast transient response with no external compensation components. The adaptive on-time control supports seamless transition between PWM mode at higher load conditions and Eco-mode operation at light loads. Eco-mode allows the TSP54628 to maintain high efficiency during lighter load conditions. The TPS54628 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR)output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between 0.76 V and 7 V. The device also features an adjustable soft start time. The TPS54628 is available in the 8-pin DDA and 10-pin DRC packages, and is designed to operate over the ambient temperature range of -40C to 85C. Features D-CAP2 Mode Enables Fast Transient Response Low Output ripple and Allows Ceramic Output Capacitor Wide VIN Input Voltage Range: 4.5 V to 18 V Output Voltage Range: 0.76 V to 7 V Highly Efficient Integrated FETs Optimized for Lower Duty Cycle Applications- 36 mOhm (High Side) and 28 mOhm (Low Side) High Efficiency, less than 10 µA at shutdown High Initial Bandgap Reference Accuracy Adjustable Soft Start Pre-Biased Soft Start 650-kHz Switching Frequency (fSW) Cycle By Cycle Over Current Limit Auto-Skip Eco-mode for High Efficiency at Light Load Applications Wide Range of Applications for Low Voltage System Digital TV Power Supply High Definition Blu-ray Disc Players Networking Home Terminal Digital Set Top Box(STB)
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Table 4.3: Recommended operating conditions
Figure 4.4: Pin Description
Table 4.4: Pin functions.
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C. TPS54821
General Description The TPS54821 in thermally enhanced 3.5 mm x 3.5 mm QFN package is a full featured 17 V, 8 A synchronous step down converter which is optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor's footprint. The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and the open drain power good pins. Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit which turns off the low-side MOSFET to prevent excessive reverse current. Hiccup protection will be triggered if the overcurrent condition has persisted for longer than the preset time. Thermal hiccup protection disables the device when the die temperature exceeds the thermal shutdown temperature and enables the part again after the built-in thermal shutdown hiccup time. Features Integrated 26 m / 19 m MOSFETs Split Power Rail: 1.6 V to 17 V on PVIN 200 kHz to 1.6 MHz Switching Frequency Synchronizes to External Clock 0.6V ±1% Voltage Reference Over Temperature Low 2 A Shutdown Quiescent Current Monotonic Start-Up into Pre-biased Outputs 40°C to 125°C Operating Junction Temperature Range Adjustable Input Undervoltage Lockout Adjustable Slow Start/Power Sequencing Power Good Output Monitor for Undervoltage and Overvoltage Adjustable Input Undervoltage Lockout
Applications Digital TV Power Supplies Set Top Boxes Blu-ray DVDs Home Terminals
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Table 4.5: Recommended operating conditions
Figure 4.5: Pin Description
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Table 4.6: Pin functions.
D. FDS4685
General Description This P-Channel MOSFET is a rugged gate version of Fairchild Semiconductor's advanced PowerTrench process. It has been optimized for power management applications requiring a wide range of gate drive voltage ratings (4.5V 20V). Features 8.2 A, 40 V RDS(ON) = 0.027 @ VGS = 10 V RDS(ON) = 0.035 @ VGS = 4.5 V Fast switching speed High performance trench technology for extremely lowRDS(ON) High power and current handling capability
Figure 4.6: Pins
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Table 4.7: Absolute maximum ratings
E. NTGS3446
Features Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS Specified at Elevated Temperature Pb-Free Package is Available Applications Power Management in portable and battery-powered products, i.e. computers, printers, PCMCIA cards, cellular and cordless Lithium Ion Battery Applications Notebook PC
Figure 4.7: Pin description
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Table 4.8: Maximum ratings
F. APL5910
General Description The APL5910 is a 1A ultra low dropout linear regulator. The IC needs two supply voltages, one is a control voltage (VCNTL) for the control circuitry, the other is a main supply voltage (VIN) for power conversion, to reduce power dissipation and provide extremely low dropout voltage. The APL5910 integrates many functions. A Power-On- Reset (POR) circuit monitors both supply voltages on VCNTL and VIN pins to prevent erroneous operations. The functions of thermal shutdown and current-limit protect the device against thermal and current over-loads. A POK indicates that the output voltage status with a delay time set internally. It can control other converter for power sequence. The APL5910 can be enabled by other power systems. Pulling and holding the EN voltage below 0.4V shuts off the output. The APL5910 is available in a SOP-8P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance to extend power range of applications. Features Ultra Low Dropout - 0.12V (Typical) at 1AOutput Current 0.8V Reference Voltage High Output Accuracy - ±1.5%over Line, Load, and Temperature Range Fast Transient Response Adjustable Output Voltage Power-On-Reset Monitoring on Both VCNTL and VIN Pins 21
Internal Soft-Start Current-Limit and ShortCurrent-Limit Protections Thermal Shutdown with Hysteresis Open-Drain VOUT Voltage Indicator (POK) Low Shutdown Quiescent Current (< 30mA ) Shutdown/Enable Control Function Simple SOP-8P Package with Exposed Pad Lead Free and Green Devices Available (RoHS Compliant)
Applications Motherboards, VGA Cards Notebook PCs Add-in Cards
Figure: Pin configuration.
Table 4.9: Recommended operating conditions.
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Table 4.10: Pin description.
G. LM1117
General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor's industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to assure output voltage accuracy to within ±1%. The LM1117 series is available in LLP, TO-263, SOT-223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability. Features Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions Space Saving SOT-223 and LLP Packages Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0.2% (Max) Load Regulation 0.4% (Max) Temperature Range: - LM1117 0°C to 125°C - LM1117I -40°C to 125°C Applications 2.85V Model for SCSI-2 Active Termination Post Regulator for Switching DC/DC Converter High Efficiency Linear Regulators Battery Charger Battery Powered Instrumentation
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5. MICROCONTROLLER (MSTAR MSD95M0D)
General Description
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Features
25
26
27
28
29
Table 5.1: Recommended operating conditions.
Table 5.2: Absolute Maximum Ratings
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6. VIDEO BACK-END PROCESSOR (MSTAR)
MST7410FE
General Description
Table 6.1: Recommended operating conditions
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Features
32
Block Diagram
Figure 6.1: Block diagram
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7. 2GB DDR3 SDRAM
HYNX H5TQ2G63GFR
Description The H5TQ2G83GFR-xxC, H5TQ2G63GFR-xxC, H5TQ2G83GFR-xxI, H5TQ2G63GFR-xxI, H5TQ2G83GFRxxL, H5TQ2G63GFR-xxL, H5TQ2G83GFR-xxJ, H5TQ2G63GFR-xxJ are a 2, 147, 483, 648bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Features
Table 7.1: Recommended operating conditions.
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8. 4GB DDR3L SDRAM
HYNX H5TQ4G63GFR
Description The H5TC4G83CFR-xxA(I,L,J),H5TQC4G63CFR-xxA(I,L,J) are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The datapaths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Features
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Table 8.1: Absolute Maximum DC Ratings
Table 8.2: Recommended operating conditions.
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9. 32GBIT (4G X 8 BIT) NAND FLASH MEMORY
MT29F4G08ABAEAWP
Key Features
Description Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see Device and Array Organization. 37
Figure 9.1:Functional block diagram
Table 9.1: DC Characteristics and Operating Conditions (3.3V)
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10. 16M-BIT [16M X 1] CMOS SERIAL FLASH EEPROM
A. MX25L1606E SPI FLASH
Features General Single Power Supply Operation 2.7 to 3.6 volt for read, erase, and program operations Serial Peripheral Interface compatible -- Mode 0 and Mode 3 8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (Dual Output mode) structure 16M: 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output mode) structure 256 Equal Sectors with 4K byte each (8Mb) 512 Equal Sectors with 4K byte each (16Mb) Any Sector can be erased individually 16 Equal Blocks with 64K byte each (8Mb) 32 Equal Blocks with 64K byte each (16Mb) Any Block can be erased individually Program Capability Byte base Page base (256 bytes) Latch-up protected to 100mA from -1V to Vcc +1V Performance High Performance Fast access time: 86MHz serial clock Serial clock of Dual Output mode : 80MHz Fast program time: 1.4ms(typ.) and 5ms(max.)/page Byte program time: 9us (typical) Fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block Low Power Consumption Low active read current: 16Mb: 25mA(max.) at 86MHz; 8Mb: 12mA(max.) at 86MHz Low active programming current: 20mA (max.) Low active erase current: 20mA (max.) Low standby current: 25uA (max.) Deep power-down mode 5uA (typical) Typical 100,000 erase/program cycles 20 years of data retention Software Features Input Data Format 1-byte Command code Advanced Security Features Block lock protection The BP3-BP0(16Mb) ; BP2-BP0(8Mb) status bit defines the size of the area to be software protection against program and erase instructions Additional 512 bit secured OTP for unique identifier Auto Erase and Auto Program Algorithm Automatically erases and verifies data at selected sector Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)6 P/N: PM1548 REV. 1.2, JUL. 02, 2010 MX25L8006E MX25L1606E 39
Status Register Feature Electronic Identification JEDEC 1-byte manufacturer ID and 2-byte device ID RES command for 1-byte Device ID REMS commands for 1-byte manufacturer ID and 1-byte device ID
Hardware Features PACKAGE 16-pin SOP (300mil), MX25L1606E only 8-pin SOP (150mil) 8-pin SOP (200mil) 8-pin PDIP (300mil) 8-land WSON (6x5mm) 8-land USON (4x4mm) All Pb-free devices are RoHS Compliant General Description The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output. The device provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles.
Figure 10.1: Pin configuration.
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Table 10.1: Pin description.
B. M25Q32FV SPI FLASH
Key Features New Family of SpiFlash Memories - W25Q32FV: 32M-bit/ 4M-byte - Standard SPI: CLK, /CS, DI, DO, /WP, /Hold - Dual SPI:CLK, /CS, IO0, IO1, /WP, /Hold - Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 - QPI: CLK, /CS, IO0, IO1, IO2, IO3 - Software & Hardware Reset Highest Performance Serial Flash - 104MHz Single, Dual/Quad SPI clocks - 208/416Mhz equivalent Dual/Quad SPI - 50 MB/S continuous data transfer rate - More than 100,000 erase/program cycles - More than 20-year retention Efficient "Continuous Read" and QPI Mode - Continuous Read with 8/16/32/64-Byte Wrap - As few as 8 clocks to address memory - Quad Peripheral Interface (QPI) reduces instruction overhead - Allows true XIP (execute in place) operation - Outperforms X16 Parallel Flash Low Power, Wide Temperature Range - Single 2.7 to 3.6V supply - 4mA active current, <1uA Power-down(typ.) - -40C to +85C operating range Flexible Architecture with 4KB sectors - Uniform Sector/Block Erase (4K/32K/64K-Byte) - Program 1 to 256 byte per programmable page - Erase/Program Suspend&Resume Advanced Security Features - Software and Hardware Write-Protect - Power Supply Lock-Down and OTP protection - Top/Bottom, Complement array protection - Individual Block/Sector array protection - 64-Bit Unique ID for each device - Discoverable Parameters (SFDP) Register 41
- 3x256-Bytes Security Registers with OTP locks - Volatile & Non-volatile Status Register Bits Space Efficient Packaging - 8-pin SOIC 208-mil / VSOP 208-mil - 8-pad WSON 6x5-mm / 8x6-mm - 16-pin SOIC 300-mil (additional / RESET pin) - 8-pin PDIP 300-mil - 24-ball TFBGA 8x6-mm (6x4/5x5 ball array) - Contact Winbond for KGB and other options General Description This W25Q32FV (32M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1uA for power-down. All devices are offered in space-saving packages. The W25Q32FV array is organized into 16,384 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time.Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q32FV has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. The W25Q32FV support the standart Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2clocks instruction cycle Quad Peripharel Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (D0), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Duad I/O and 416Mhz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standart Asynchronous 8 an 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory Access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP(execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standart manufacturer and device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
Figure 10.2: Pin configuration.
42
Table 10.2: Pin description.
11. DEMODULATOR STAGE
A. MSB1246 DVB-T2
Features
43
General Description The MSB1246 is a single chip demodulator supporting DVB-T2, DVB-T, DVB-C, DVB-S2 and DVB-S standards. The device integrates a house keeping microcontroller that takes care of all real time and algorithmic tasks simplifying the host control interface. For DVB-T2/T/C, the MSB1246 front end can accept tuners that provide IF or low IF output. For DVBS2/S, the MSB1246 front end can accept tuners that provide zero-IF output. A high rejection channel filter has been included easing the channel filtering requirement of the tuner whilst still meeting the stringent requirements for adjacent channel interference. The MSB1246 may be clocked directly using a crystal, typically 24MHz. The MSB1246 is capable of blind acquisition of DVB-T/T2, DVB-C and DVB-S2/S signals. All parameters may be detected in this mode enabling fast and accurate auto scanning. Its frequency recovery circuit is able to compensate for all typical tuner and broadcast frequency errors.
44
Block Diagram
Pinning
45
Absolute Maximum Ratings and Recommended Operating Conditions
12. LNB SUPPLY AND CONTROL IC
TPS65233
General Description Designed for analog and digital satellite receivers, the TPS65233 is a monolithic voltage regulator with I2C interface, specifically to provide the 13-V/18-V power supply and the 22-kHz tone signaling to the LNB downconverter in the antenna dish or to the multi-switch box. It offers a complete solution with very low component count, low power dissipation together with simple design and I2C standard interfacing. TPS65233 features high power efficiency. The boost converter integrates a 120-m power MOSFET running at 500-kHz switching frequency. Drop out voltage at the linear regulator is 0.8 V to minimize power loss. TPS65233 provides multiple ways to generate the 22-kHz signal. Integrated linear regulator with push-pull output stage generates clean 22-kHz tone signal superimposed at the output even at zero loading. Current limit of linear regulator can be programmed by external resistor with ±10% accuracy. Full range of diagnostic read by I2C is available for system monitoring.
46
Features
Pinouts
13. SOFTWARE UPDATE
MAIN SW UPDATE
In MB120 project, please follow software update procedure: 1. mb120_en.bin, RomBoot.bin, PM51.bin and usb_auto_update_G6F.txt documents should be copied directly inside of a flash memory (not in a folder). 2. Insert flash memory to the TV when TV is powered off. 3. While pushing the OK button in remote control, power on and wait. TV will power-up itself. 4. If First Time Installation screen comes, it means software update procedure is successful.
47
14. TROUBLESHOOTING
A. NO BACKLGHT PROBLEM
Problem: If TV is working, led is normal and there is no picture and backlight on the panel. Possible couses: Backlight pin, dimming pin, backlight supply, stby on/off pin BACKLIGHT_ON/OFF pin should be high when the backlight is ON. R89 must be low when the backlight is OFF. If it is a problem, please check Q10 and the panel cables. Also it can be tested in TP137 on main board
Dimming pin should be high or square wave in open position. If it is low, please check S97 for Mstar side and panel or power cables, connectors.
48
Backlight power supply should be in panel specs. Please check Q44, shown below; also it can be checked TP175.
STBY_ON/OFF_NOT should be low for tv on condition, please check Q23's collector.
49
B. CI MODULE PROBLEM
Problem: CI is not working when CI module inserted. Possible couses: Supply, suply control pin, detect pins, mechanical positions of pins. CI supply should be 5V when CI module inserted. If it is not 5V please check CI_PWR_CTRL, this pin should be low.
Please check mechanical position of CI module. Is it inserted properly or not? Detect ports should be low. If it is not low please check CI connector pins, CI module pins.
50
51
C. STAYNG N STAND-BY MODE
Problem: Staying in stand-by mode, no other operation This problem indicates a short on Vcc voltages. Protect pin should be logic high while normal operation. When there is a short circuit protect pin will be logic low. If you detect logic low on protect pin, unplug the TV set and control voltage points with a multimeter to find the shorted voltage to ground.
52
53
D. IR PROBLEM
Problem: LED or IR not working Check LED card supply on MB120 chasis.
54
E. KEYPAD TOUCHPAD PROBLEMS
Problem: Keypad or Touchpad is not working Check keypad supply on MB120.
55
F. USB PROBLEMS
Problem: USB is not working or no USB Detection. Check USB Supply, It should be nearly 5V. Also USB Enable should be logic high. For USB 3.0 ports:
For Side USB 2.0 port:
56
For Back USB 2.0 port:
G. NO SOUND PROBLEM
Problem: No audio at main TV speaker outputs. Check supply voltages of 24V_VCC, VDD_AUDIO_MAIN and 3.3V_AMP with a voltage-meter. There may be a problem in headphone connector or headphone detect circuit (when headphone is connected, speakers are automatically muted). Measure voltage at HP_DETECT pin, it should be 3.3v.
57
H. STANDBY ON/OFF PROBLEM
Problem: Device can not boot, TV hangs in standby mode. There may be a problem about power supply. Check main supplies with a voltage-meter. Also there may be a problem about SW. Try to update TV with latest SW. Additionally it is good to check SW printouts via Teraterm. These printouts may give a clue about the problem. You can use mini scart for terraterm connection.
. NO SGNAL PROBLEM
Problem: No signal in TV mode. Check tuner supply voltage 3V3_TUNER and. Check tuner options are correctly set in Service menu. Check voltage at TUNER_SCL and TUNER_SDA pin of tuner.
58
14. GENERAL BLOCK DIAGRAM
2x20W 5V_VCC 5V_VCC
TPS2553 USB Power Supply Switch (USB2)
Small SubW Out
5V_VCC
TPS2553 USB Power Supply Switch (USB3)
3840x2160 @120Hz
1920x1080 @120Hz
(256Mx16bit) (1866 MT/s)
Subwoofer
SC AUDIO_OUT
ESMT AD82587D Audio Amp ESMT AD82586C Audio Amp
Bathroom Amp.
TPS2553 USB Power Supply Switch (USB1)
1V5_VCC 1V5_VCC 1V5_VCC 1V5_VCC
16 Lane VbyONE Out
DDR3 RAM
DDR3 RAM
HP / LINEOUT
DDR3 RAM
DDR3 RAM
SUBW. Pre Amp.
12V_VCC or 24V_VCC
AZ099-4S ESD Protection
AZ099-4S ESD Protection
AZ099-4S ESD Protection
DAC
DSP_SUB_OUT I2S AUD_OUT SC_L/R_OUT SPDIF OUT 3V3_STBY 3V3_W_WOWL 3D_SYNC_O
BLUETOOTH (SG,HP,SPK,AIR MOUSE)
3840x2160@60Hz 1920x1080@60Hz
25
24
23
22
1V8_EMMC 3V3_VCC 1V5_VCC 3V3_STBY 1V_G6F_CPU 1V_G6F_CORE 21 20 19 18 17
RJ12
13 12 11 10 9 8
SPI (16Mbit)
16
15
14
7
6
5
4
3
2
1
Dimming
RAM INTERFACE
POWER
LINE OUT
GPIO
Hotel TV
I2S I/O
SPDIF I/O
ETHERNET
SPI FLASH
.
A B C
WOWL_DET
INTERNAL WI-FI INTERFACE
4x USB 2.0
D USB3 2.0 E F USB2 2.0
Dimming Circuitry
Dimming_Main
Dimming(MFC)
MFC 11
1x USB 3.0 IRIN
HW Reset Block
G H
USB1 3.0
UHD 100Hz
POWER INPUT 1V 1.5V 3.3V
I2C
I2C
J K L M N
IR_IN
LED
5V_STBY
LVDS / VbyONE OUTPUT
RESET CIRCUIT
CEC TMDS_4 I2C_4
3V3_STBY
VbyOne 4k2k@60Hz
G6F
HDMI INTERFACE
P R T U V W Y AA AB XIN/ XOUT AC AD XTAL (24 Mhz) TMDS_2 I2C_2 TMDS_3 I2C_3
HDMI 4
LVDS VByONE
LVDS 1920x1080p@60Hz
SOC
600 MHz 4k2k @60Hz 444 -> 8bit 422 -> 12bit
SC_Pin8 HP_DETECT PROTECT
DIFP/M IN
AE
OUT
HP_L/R
TS1_SIGNALS
DEMOD 2-TS
RGB/HS/VS
3V3_VCC
ATV
NAND Flash (512Mx8bit)
YPbPr Audio R/L In
NAND_CONTROL
SC1 CVBS_OUT
DEMOD 1 TS
PCM/NAND_DATA
YPbPr
CI_TS1
EMMC
PCM_ADDRESS
SC RGB/FB SC CVBS_IN SC AUDIO_IN
Slim SAV
3V3_STBY
KEYBOARD
I2C KEYBOARD
MSB1240 T-T2-C-S-S2
SAT_ADC
MSB1240 T-T2-C-S-S2
AGC DVB_T2
I2C
VIDEO AMP.
DIGITAL IF_T/T2/C
3V3_STBY
TOUCHPAD
XTAL (24 Mhz)
DIGITAL IF_T/T2/C
24V_VCC 12V_VCC 3V3_VCC 5V_VCC 1V_VCC
SI2151 Silicon Tuner (2)
SI2151 Silicon Tuner (1)
SAV/VGA/YPbPr Audio_In
SPI FLASH 4MB
KEYBOARD Dimming_Main
GPIO
WOWL_DET
TMDS_1 ARC
NAND TS0 TS1 TS2 TS3 TS4 CI I/O I I I I FLASH
MST_TS0
HP
ANALOG AUDIO/VIDEO INTERFACE
YPbPr/SOY
CVBS_IN .
HDMI 1 MHL SLIM SCART
SPI FLASH
RAM INTERFACE
I2C_1
PROTECT 12V_VCC
3V3_VCC_TUNER
3V3_VCC LNB_Voltage 1
LNA BGU7045
3V3_VCC_TUNER
12V_VCC
3V3_VCC 1V25_VCC
SC_Pin8
SHORT CCT PROTECTION
AV2018 Digital Satellite Tuner
AV2018 Digital Satellite Tuner
HDMI 2
HDMI 3
XIN/XOUT CI_TS0
SAT_ADC
AGC_DVB_T2
LNBP LNBH29
1V25_VCC
LNBP LNBH29
SC AUDIO_OUT LNB_Voltage 2
59
I2C
XTAL (24 Mhz)
I2C
17MB120 Block Diagram
1
CN14
2 C350 100n 10V 4 6 8 12V_STBY 10 12 14 16 18 S8 20 R847 33R C352 100n 10V
2
2
1 3 5 7 9 11 13 15 17 TP136 S16 19 TP298 S15 24V_VCC S6 3V3_VCC 10V 100n 10V 100n C354 Q21 BC848B
1
3
4
5
6
TP141 5V_VCC 12V_VCC C544 10u 10V R133 4k7 1 2 3 1 EN
2
7
F47 F46 60R 60R R371 10k C724 22u 16V 0R
8
POWER SOCKET
C348 10V 100n VDD_AUDIO 12V_STBY 12V_STBY C351 TP135 S7 5V_STBY C356 DIMMING TP138 C355 10V 100n TP137 10V 100n 100n 10V C709
2 1
12V_VCC SW W/IPS20 S13
TP139 12V_STBY 1
1
5V_VCC SW W/IPS20
5V_STBY 6 5 4 TP140 Q45 NTGS3446
S10 S11 S12 Q43 FDS4685 8 7 6 5
5V DC-DC
C727 C723 22u 16V C493 100n 16V R679 120k
R1=124k7 R2=22k
22p 50V R525 4k7 VFB_5V_VCC R678 22k R2
FS2
1 2
12V_STBY
A
12V_STBY C353
7A/32VDC FS1
1 2
12V_VCC
R1
2
1
A
5V_VCC
220n 25V R575 33k
2 3
1
7A/32VDC 12V_STBY
2
100n 10V 12V_STBY
R667 47R
R576 33k
1
1
R668 47R
VIN 8
Vout=0.765x(1+(R1/R2)) S17
C494 16V 100n L26 10u C677 22u 6V3 C676 22u 6V3 S22 S21 TP142 S18 S19 TP148 S20 5V_STBY
2
4
VFB_5V_VCC 100nC492 16V C665 1u 16V
2 VFB
U22
VBST 7 SSW 6 GND 5
2
BACKLIGHT_ON/OFF STBY_ON/OFF
R591 6k8
R53 1k
3 VREG5 4 VSS 8n2 50V
TPS54528
R52 1k
3
Q22 BC848B
C711
STBY_ON/OFF
2
1
3D_EN_PW
R370 10k
2
STBY_ON/OFF_NOT
TPS54628 ADJ/6A 30084920
C675 22u 6V3
B
10k R377
1
B
C349
12V_VCC
F48 0R 60R 22u 16V C726 22u 16V C725 R372 10k
3V3_VCC
C496 100n 16V C728 R696 33k 22p 50V R688 680R VFB_3V3_VCC R694 10k R2 5V_VCC 3V3_VCC
1 2
1V8_VCC
R131 4k7 10u 10V 1 POK
1
3V3_STBY LDO
R697 10R R2 R699 910R
GND 8 FB 7
R1
U26
2 EN 3 VIN R698 150R
R134 4k7
2
Vout=0.765x(1+(R1/R2))
VIN 8 C495 SSW 6 GND 5 30074386 3u3 4A4 L1 16V 10u C678 100n 22u 6V3 TP143 3V3_VCC C679 22u 6V3
60R
1 2
APL5910
VOUT 6 NC 5 100n C357 10V
1 EN VFB_3V3_VCC 2 VFB
F49 5V_VCC
2
C545 S250
1
U23
VBST 7
C
C712 C666 1u 16V
R177 1k
3 VREG5 4 VSS 8n2 50V
TPS54528
4 VCNTL C546 10u 10V
5V_STBY 10V 10u
U57 LM1117 3 IN ADJ 1 C2308 OUT 2 VOUT 4
TP297 3V3_STBY C2309 22u 6V3
R1
R1=33k68 R2=10k
C
Vout=0.8x(1+(R1/R2)) R1=1k15 R2=920R
TP144 C695 22u 6V3
1V8_VCC
30069495
LDO AP2111H 3.3V/600MA SOT223
1V15_VCC_DEMOD
EN_G6F_CORE
1V_G6F_CORE
R695 10k L9 2u4 C472 22u 6V3 C464 22n 6V3 10 9 C473 22u 6V3 C452 22u 6V3 C450 22u 6V3 C442 100n 16V 13 12 11
TP90
5V_VCC 3V3_VCC
1
2
R132 4k7 10u 10V
EN_MFC_CORE
D
60R
2
1 POK
1
GND 8 FB 7 VOUT 6 NC 5 C358 100n 10V C697
U27
2 EN 3 VIN
R705 470R R526 4k7
R2
L10 1V_G6F_CORE 2u4 C455 22u 6V3 C465 22n 6V3 C456 22u 6V3 C454 22u 6V3
6V3 100u C466
TP91
1V_MFC_CORE
C444 100n 16V 13 12 11
1V_MFC_CORE C453 22u 6V3 S125 R256 10k
D
R1 1V15_VCC_DEMOD TP146
APL5910
2
1
BOOT
PH_1
PH_0
EN
SS/TR
S119
C458
SS/TR
4 VCNTL C548 10u 10V
22u 6V3
C460 39p R254 50V C445 4k7 4n7 50V G6F_CORE_FB
C461 39p R255 50V C446 4k7 4n7 50V
BOOT
PH_1
PH_0
EN
S121 C459
F51 5V_VCC
C547 S252
10
9
PVIN_0
PVIN_1
PVIN_0
PVIN_1
R347 10k
GND_0
GND_1
R348 10k
GND_0
GND_1
Vout=0.8x(1+(R1/R2)) R1=4k7 R2=10k47
E
3V3_STBY R376 10k
1
14 1
PWRGD RT/CLK
U32 TPS54821
VIN
COMP VSENSE
8 7
14 1
PWRGD RT/CLK
U33 TPS54821
VIN
COMP VSENSE
8 7
MFC_CORE_FB
R1
R1
MFC_CHIP_VDET
560p 50V
560p 50V
E
2 3 4 5 6 G6F_CORE_FB R359 499R R249 100k MFC_CORE_FB
R373 10k
2
3
4
5
2
STBY_ON/OFF Q23 R136 100k
6
3V3_STBY
1
2
STBY_ON/OFF_NOT C5V6 D33
R54 1k
R358 499R
16V 10u C2284
16V 10u C2283
10u C448
10u 16V C447
C2316
16V
10u C449
16V
C463
10u 16V
10u 16V
R2
10u 16V C2285
12V_VCC
R356 9k1
12V_VCC
R357 9k1 R355 7k5
BC848B
R258 33k
R352 8k2
R345 33k
R353 8k2
R2
R354 7k5
CORE_RESET S116 EN_G6F_CORE
CORE_RESET S122 EN_MFC_CORE
F
Vout=0.6x(1+(R1/R2)) R1=10k
1 2 3
Vout=0.6x(1+(R1/R2)) Vout=0.95V R1=10k
5 6
F
R2=17k1
Vout=0.95V
4
R2=17k1
VESTEL PROJECT NAME : 17MB120-R2
SCH NAME :01_POWER_1 DRAWN BY :AKIN ZOHRE
A3
T. SHT: 17
11-09-2015_18:25
7
8
AX M
1
2
3
4
5
6
7
8
1V5_DDR_STR W/FAST POWER ON
R738 51k R1 C877 2p NC 50V C693 22u 6V3 L24 3u3 C429 100n 16V C721 22u 16V C694 22u 6V3 TP276 1V5_DDR_STR 1N5819 12V_VCC 22u 16V C722 D47 1N5819 R2 100k R27 D48 NC FEEDBACK 5V_STBY C11 R499 47k
1V5_VCC
R500 47k R1 C876 2p NC 50V C691 22u 6V3 L23 3u3 C428 100n 16V R328 10k C719 22u 16V F32 12V_VCC 60R 22u 16V C720 R128 4k7 C692 22u 6V3 TP257 1V5_VCC R739 51k
MFC_CORE_FB R350 470R
A
16V C12 FEEDBACK D28 100n 1N4148 STR_EN
1
A
R MFC_VID[0]
6 BOOT R329 10k
GND 1
6 BOOT 100n16V
GND 1
R366 200k
C457 nc 10n 16V Q32 2N7002 R44 1k MFC_VID0
2
5 EN LX 2 RT6213BHGJ6F 4 FB VIN 3
U46
5 EN LX 2 RT6213BHGJ6F 4 FB VIN 3
U45
R26 100k R2
1
2
B
Vout=0.765x(1+(R1/R2)) R1=98k R2=100k 30091220 TPS562200 ADJ/2A SOT23
B
Vout=0.765x(1+(R1/R2))30091219 R1=98k R2=100k TPS563200 ADJ/3A SOT23
1V_G6F_CPU
R1
3V3_WOWL W/WOWL
R771 37k4 33k R1 C874 R754 100R 4k7
MFC_VID[0]
C687 22u 6V3 L21 3u3 C426 100n 16V C716 22u 16V 3V3_WOWL 1N5819 12V_VCC 22u 16V C715 D39 1N5819 D46 NC 5V_STBY C688 22u 6V3
R2 17k1 14k6
Vout 0,95 V 1,01 V
C
C
G6F_CPU_FB
1k8 R769 C875
10k R693 C9 FEEDBACK2 C689 22u 6V3 L22 3u3 C427 100n 16V R327 10k C717 22u 16V F31 12V_VCC 60R 22u 16V C718 R127 4k7 S117 CORE_RESET R770 12k R2 C690 22u 6V3 TP277 1V_G6F_CPU D27 1N4148 WOWL_EN
1
2p NC 50V
L
TP278
2p NC 50V C10 6 BOOT 100n16V GND 1
100n 16V R326 10k
6 BOOT
GND 1
2
5 EN LX 2 RT6213BHGJ6F 4 FB VIN 3
U44
5 EN LX 2 RT6213BHGJ6F 4 FB VIN 3
U43
H
R367 59k
FEEDBACK2
R2
1
2
Vout=0.765x(1+(R1/R2)) 30091219 TPS563200 ADJ/3A SOT23 R1=11k8 R2=63k
R363 4k02
D
Vout=0.765x(1+(R1/R2)) R1=37k5 R2=12k 30091220 TPS562200 ADJ/2A SOT23
G6F_CORE_FB
D
R362 20k
VID[0] VID[1]
R349 150R
R2 17k1 15k 12k2 10k9
Vout 0,95 V 1 V 1,09 V 1,15 V
F E
E
G6F_CPU_FB
R365 15k
R257 120k
VID[0]
R351 8k2
VID[1] L H L H
R2 63k 47k2 29k5 24k2
Vout 0,95 V 1 V 1,12 V 1,19 V
R VID[1]
R361 20k
L
R VID[0]
L H L H
R360 2k7
L
C451 nc 10n 16V R800 1k R801 1k
L
R VID[1] R364 40k2 R VID[0] R368 180k
L
C437 10n 16V nc
Q52 2N7002
Q51 2N7002
H
CORE_VID0 CORE_VID1
H
F
Q30 2N7002 C346 10n 16V nc
Q31 2N7002
H
CPU_VID0 CPU_VID1
C443 nc 10n 16V
R42 1k R41 1k
H
VESTEL PROJECT NAME : 17MB120-R2
SCH NAME :02_POWER_2 DRAWN BY :AKIN ZOHRE
A3
T. SHT: 17
05-09-2015_12:33
1
2
3
4
5
6
7
8
AX M
1
AB_AVDD B2 D9 G7 K2 K8 N1 N9 R1 R9
2
A1 A8 C1 C9 D2 E9 F1 H2 H9 A_REF_DQ
3
CD_AVDD B2 D9 G7 K2 K8 N1 N9 R1 R9
4
A1 A8 C1 C9 D2 E9 F1 H2 H9 C_REF_DQ
5
1 2 3 4 R186 100R R1 8 R2 7 R3 6 R4 5 R181 100R R1 8 R2 7 R3 6 R4 5 R185 100R R1 1 R2 2 R3 3 R4 4 DDR_VTT C894 10V 100n C269 10V 100n
6
7 U6 MSD95M0D
AB_A0 AB_A1 AB_A2 AB_A3 AB_A4 AB_A5 AB_A6 AB_A7 AB_A8 AB_A9 AB_A10 AB_A11 AB_A12 AB_A13 AB_A14 AB_A15 AB_BA0 AB_BA1 AB_BA2 AB_RASN AB_CASN AB_WEN S309 AB_ODT F17 C17 E17 F18 B18 E18 A17 D17 C16 E16 B19 B17 D20 F16 B16 E20 E19 C18 F19 G22 F21 E21 F20 C19 F15 A20 B20 E15 D15 C23 B22 B24 C21 B25 C20 C24 B21 C22 A23 B23 D23 D26 E22 D27 F23 E26 D22 E25 E24 D24 E23 C28 C26 B29 A26 C29 C25 A29 B26 B27 B28 C27 E29 C31 E27 D31 D29 D30 E28 C30 B31 A31 B30 AB_DDR3_A0 AB_DDR3_A1 AB_DDR3_A2 AB_DDR3_A3 AB_DDR3_A4 AB_DDR3_A5 AB_DDR3_A6 AB_DDR3_A7 AB_DDR3_A8 AB_DDR3_A9 AB_DDR3_A10 AB_DDR3_A11 AB_DDR3_A12 AB_DDR3_A13 AB_DDR3_A14 AB_DDR3_A15 AB_DDR3_BA0 AB_DDR3_BA1 AB_DDR3_BA2 AB_DDR3_RASN AB_DDR3_CASN AB_DDR3_WEN AB_DDR3_ODT AB_DDR3_CKE AB_DDR3_RESETN AB_DDR3_CK AB_DDR3_CKN A_DDR3_CSN B_DDR3_CSN A_DDR3_DQL0 A_DDR3_DQL1 A_DDR3_DQL2 A_DDR3_DQL3 A_DDR3_DQL4 A_DDR3_DQL5 A_DDR3_DQL6 A_DDR3_DQL7 A_DDR3_DML A_DDR3_DQSL A_DDR3_DQSLN A_DDR3_DQU0 A_DDR3_DQU1 A_DDR3_DQU2 A_DDR3_DQU3 A_DDR3_DQU4 A_DDR3_DQU5 A_DDR3_DQU6 A_DDR3_DQU7 A_DDR3_DMU A_DDR3_DQSU A_DDR3_DQSUN B_DDR3_DQL0 B_DDR3_DQL1 B_DDR3_DQL2 B_DDR3_DQL3 B_DDR3_DQL4 B_DDR3_DQL5 B_DDR3_DQL6 B_DDR3_DQL7 B_DDR3_DML B_DDR3_DQSL B_DDR3_DQSLN B_DDR3_DQU0 B_DDR3_DQU1 B_DDR3_DQU2 B_DDR3_DQU3 B_DDR3_DQU4 B_DDR3_DQU5 B_DDR3_DQU6 B_DDR3_DQU7 B_DDR3_DMU B_DDR3_DQSU B_DDR3_DQSUN 1 CD_DDR3_A0 CD_DDR3_A1 CD_DDR3_A2 CD_DDR3_A3 CD_DDR3_A4 CD_DDR3_A5 CD_DDR3_A6 CD_DDR3_A7 CD_DDR3_A8 CD_DDR3_A9 CD_DDR3_A10 CD_DDR3_A11 CD_DDR3_A12 CD_DDR3_A13 CD_DDR3_A14 CD_DDR3_A15 CD_DDR3_BA0 CD_DDR3_BA1 CD_DDR3_BA2 CD_DDR3_RASN CD_DDR3_CASN CD_DDR3_WEN CD_DDR3_ODT CD_DDR3_CKE CD_DDR3_RESETN CD_DDR3_CK CD_DDR3_CKN C_DDR3_CSN D_DDR3_CSN C_DDR3_DQL0 C_DDR3_DQL1 C_DDR3_DQL2 C_DDR3_DQL3 C_DDR3_DQL4 C_DDR3_DQL5 C_DDR3_DQL6 C_DDR3_DQL7 C_DDR3_DML C_DDR3_DQSL C_DDR3_DQSLN C_DDR3_DQU0 C_DDR3_DQU1 C_DDR3_DQU2 C_DDR3_DQU3 C_DDR3_DQU4 C_DDR3_DQU5 C_DDR3_DQU6 C_DDR3_DQU7 C_DDR3_DMU C_DDR3_DQSU C_DDR3_DQSUN D_DDR3_DQL0 D_DDR3_DQL1 D_DDR3_DQL2 D_DDR3_DQL3 D_DDR3_DQL4 D_DDR3_DQL5 D_DDR3_DQL6 D_DDR3_DQL7 D_DDR3_DML D_DDR3_DQSL D_DDR3_DQSLN D_DDR3_DQU0 D_DDR3_DQU1 D_DDR3_DQU2 D_DDR3_DQU3 D_DDR3_DQU4 D_DDR3_DQU5 D_DDR3_DQU6 D_DDR3_DQU7 D_DDR3_DMU D_DDR3_DQSU D_DDR3_DQSUN H28 K31 J29 K27 K30 J28 K32 H31 J32 G30 L30 J30 L29 G31 J31 M28 L28 L31 K28 N28 N27 L27 M27 M31 G32 N32 M30 G29 F32 T31 P30 T30 P31 U30 N31 U31 N30 R31 T32 R30 P27 U29 P28 U27 R28 V28 P29 U28 T28 T27 R27 AA31 W31 AA30 W32 AB31 V31 AB32 V30 W30 Y30 Y31 Y28 AB27 V27 AB29 W28 AB28 W27 AA27 Y27 AA28 Y29
8
A
AB_A0 AB_A1 AB_A2 AB_A3 AB_A4 AB_A5 AB_A6 AB_A7 AB_A8 AB_A9 AB_A10 AB_A11 AB_A12 AB_A13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 J1 L1 M7 L9 T7 J9 M2 N8 M3 J7 K7 K9 L2 J3 K3 L3 T2 L8
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 NC1 NC2 NC3 NC4 NC5 NC6 BA0 BA1 BA2 CK_0 CK_1 CKE CS RAS CAS WE
VREF_DQ VREF_CA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSL_0 DQSL_1 DQSU_1 DQSU_0 DML DMU ODT VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9
H1 M8 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 F3 G3 B7 C7 E7 D3 K1 A_DQL0 A_DQL1 A_DQL2 A_DQL3 A_DQL4 A_DQL5 A_DQL6 A_DQL7 A_DQU0 A_DQU1 A_DQU2 A_DQU3 A_DQU4 A_DQU5 A_DQU6 A_DQU7 A_DQSL A_DQSLN A_DQSUN A_DQSU A_DML A_DMU AB_ODT
CD_A0 CD_A1 CD_A2 CD_A3 CD_A4 CD_A5 CD_A6 CD_A7 CD_A8 CD_A9 CD_A10 CD_A11 CD_A12 CD_A13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 J1 L1 M7 L9 T7 J9 M2 N8 M3 J7 K7 K9 L2 J3 K3 L3 T2 L8
VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 NC1 NC2 NC3 NC4 NC5 NC6 BA0 BA1 BA2 CK_0 CK_1 CKE CS RAS CAS WE
VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9
AB_A14 AB_A8 AB_A11 AB_A6
VREF_DQ VREF_CA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSL_0 DQSL_1 DQSU_1 DQSU_0 DML DMU ODT VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9
H1 M8 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 F3 G3 B7 C7 E7 D3 K1 C_DQL0 C_DQL1 C_DQL2 C_DQL3 C_DQL4 C_DQL5 C_DQL6 C_DQL7 C_DQU0 C_DQU1 C_DQU2 C_DQU3 C_DQU4 C_DQU5 C_DQU6 C_DQU7 C_DQSL C_DQSLN C_DQSUN C_DQSU C_DML C_DMU CD_ODT
AB_A1 AB_A4 AB_A12 AB_BA1
1 2 3 4
C893 10V 100n C263 10V 100n
AB_A7 AB_A9 AB_A13
8 7 6 5
AB_A15 AB_A14
CD_A15 CD_A14
U2 H5TQ2G63BFR-PB
U5 H5TQ2G63BFR-PB
AB_BA2 AB_BA0 AB_A15 AB_WEN
B
AB_BA0 AB_BA1 AB_BA2 AB_CK AB_CKN AB_CKE A_CSN AB_RASN AB_CASN AB_WEN AB_RESETN 240R R5
CD_BA0 CD_BA1 CD_BA2 CD_CK CD_CKN CD_CKE C_CSN CD_RASN CD_CASN CD_WEN CD_RESETN 240R R8
AB_A2 AB_A5 AB_A0 AB_A3
R184 100R R1 8 R2 7 R3 6 R4 5 R183 100R 1 R1 8 2 R2 7 3 R3 6 4 R4 5 1 2 3 4 R182 100R 8 R1 1 7 R2 2 6 R3 3 5 R4 4 R229 100R NCR228 100R NCR227 100R R230 100R R231 100R
C892 10V 100n C268 10V 100n C895 10V 100n C891 10V 100n C267 10V 100n C890 10V 100n C266 10V 100n AB_CKE
CD_A0 CD_A1 CD_A2 CD_A3 CD_A4 CD_A5 CD_A6 CD_A7 CD_A8 CD_A9 CD_A10 CD_A11 CD_A12 CD_A13 CD_A14 CD_A15 CD_BA0 CD_BA1 CD_BA2 CD_RASN CD_CASN CD_WEN CD_ODT S314 CD_CKE CD_RESETN S313 S312 CD_CK CD_CKN
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9
A
S310 AB_RESETN AB_CK AB_CKN S311 A_CSN B_CSN A_DQL0 A_DQL1 A_DQL2 A_DQL3 A_DQL4 A_DQL5 A_DQL6 A_DQL7 A_DML A_DQSL A_DQSLN A_DQU0 A_DQU1 A_DQU2 A_DQU3 A_DQU4 A_DQU5 A_DQU6 A_DQU7 A_DMU A_DQSU A_DQSUN B_DQL0 B_DQL1 B_DQL2 B_DQL3 B_DQL4 B_DQL5 B_DQL6 B_DQL7 B_DML B_DQSL B_DQSLN B_DQU0 B_DQU1 B_DQU2 B_DQU3 B_DQU4 B_DQU5 B_DQU6 B_DQU7 B_DMU B_DQSU B_DQSUN
B
C_CSN D_CSN C_DQL0 C_DQL1 C_DQL2 C_DQL3 C_DQL4 C_DQL5 C_DQL6 C_DQL7 C_DML C_DQSL C_DQSLN C_DQU0 C_DQU1 C_DQU2 C_DQU3 C_DQU4 C_DQU5 C_DQU6 C_DQU7 C_DMU C_DQSU C_DQSUN D_DQL0 D_DQL1 D_DQL2 D_DQL3 D_DQL4 D_DQL5 D_DQL6 D_DQL7 D_DML D_DQSL D_DQSLN D_DQU0 D_DQU1 D_DQU2 D_DQU3 D_DQU4 D_DQU5 D_DQU6 D_DQU7 D_DMU D_DQSU D_DQSUN
AB_RASN AB_CASN AB_ODT AB_A10 B_CKE AB_RESETN B_CK B_CKN
C889 10V 100n C265 10V 100n C888 10V 100n C264 10V 100n C887 10V 100n C886 10V 100n C270 10V 100n
RESET ZQ
RESET ZQ
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
C
AB_AVDD B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 B_REF_DQ CD_AVDD B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 D_REF_DQ
B1 B9 D1 D8 E2 E8 F9 G1 G9
C
D
AB_A0 AB_A1 AB_A2 AB_A3 AB_A4 AB_A5 AB_A6 AB_A7 AB_A8 AB_A9 AB_A10 AB_A11 AB_A12 AB_A13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 J1 L1 M7 L9 T7 J9 M2 N8 M3 J7 K7 K9 L2 J3 K3 L3 T2 L8
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 NC1 NC2 NC3 NC4 NC5 NC6 BA0 BA1 BA2 CK_0 CK_1 CKE CS RAS CAS WE
VREF_DQ VREF_CA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSL_0 DQSL_1 DQSU_1 DQSU_0 DML DMU ODT VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9
H1 M8 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 F3 G3 B7 C7 E7 D3 K1 B_DQL0 B_DQL1 B_DQL2 B_DQL3 B_DQL4 B_DQL5 B_DQL6 B_DQL7 B_DQU0 B_DQU1 B_DQU2 B_DQU3 B_DQU4 B_DQU5 B_DQU6 B_DQU7 B_DQSL B_DQSLN B_DQSUN B_DQSU B_DML B_DMU AB_ODT
CD_A0 CD_A1 CD_A2 CD_A3 CD_A4 CD_A5 CD_A6 CD_A7 CD_A8 CD_A9 CD_A10 CD_A11 CD_A12 CD_A13
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 J1 L1 M7 L9 T7 J9 M2 N8 M3 J7 K7 K9 L2 J3 K3 L3 T2 L8
VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 NC1 NC2 NC3 NC4 NC5 NC6 BA0 BA1 BA2 CK_0 CK_1 CKE CS RAS CAS WE
VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9
CD_A14 CD_A8 CD_A11 CD_A6
VREF_DQ VREF_CA DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSL_0 DQSL_1 DQSU_1 DQSU_0 DML DMU ODT VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9
H1 M8 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 F3 G3 B7 C7 E7 D3 K1 D_DQL0 D_DQL1 D_DQL2 D_DQL3 D_DQL4 D_DQL5 D_DQL6 D_DQL7 D_DQU0 D_DQU1 D_DQU2 D_DQU3 D_DQU4 D_DQU5 D_DQU6 D_DQU7 D_DQSL D_DQSLN D_DQSUN D_DQSU D_DML D_DMU CD_ODT
CD_A1 CD_A4 CD_A12 CD_BA1
R192 100R R1 8 R2 7 R3 6 R4 5 R187 100R 1 R1 8 2 R2 7 3 R3 6 4 R4 5 1 2 3 4 8 7 6 5 R191 100R R1 1 R2 2 R3 3 R4 4
DDR_VTT C905 10V 100n C277 10V 100n
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9
C904 10V 100n C272 10V 100n
CD_A7 CD_A9 CD_A13
AB_A15 AB_A14
CD_A15 CD_A14
U3 H5TQ2G63BFR-PB
U4 H5TQ2G63BFR-PB
CD_BA2 CD_BA0 CD_A15 CD_WEN
R190 100R 1 R1 8 2 R2 7 3 R3 6 4 R4 5 1 2 3 4 R189 100R R1 8 R2 7 R3 6 R4 5
C903 10V 100n C276 10V 100n C902 10V 100n C901 10V 100n C275 10V 100n C900 10V 100n C274 10V 100n
D
AB_BA0 AB_BA1 AB_BA2 B_CK B_CKN B_CKE B_CSN
CD_BA0 CD_BA1 CD_BA2 D_CK D_CKN D_CKE D_CSN CD_RASN CD_CASN CD_WEN CD_RESETN 240R R7
CD_A2 CD_A5 CD_A0 CD_A3
E
CD_RASN CD_CASN CD_ODT CD_A10 D_CKE CD_RESETN D_CK D_CKN
AB_RASN AB_CASN AB_WEN AB_RESETN 240R R6
RESET ZQ
RESET ZQ
R188 100R R1 1 R2 2 R3 3 R4 4 R234 100R NC R233 100R NC R232 100R R235 100R R236 100R 8 7 6 5
C899 10V 100n C273 10V 100n C898 100n C271 100n C897 100n C896 100n C278 100n
CD_AVDD C2306 100n 16V C2307 100n 16V C2305 100n 16V C2304 100n 16V C2303 100n 16V
E
10V 10V 10V 10V 10V
DDR TERMINATION
10V 10u C21 16V 100n C13 1 DDQ 2 VTT 3 GND 16V 100n C16 VTTREF 8 16V 100n C15 R9 22R
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
10V 10u C23 1V5_VCC TP89 DDR_VTT
U1
EN 7 REF 6
R28 100k
3V3_VCC 1V5_VCC
AB_CKN
CD_CKN
for STR
AB_AVDD R129 4k7
A_REF_DQ AB_CK C260 100n 10V C384 1n 50V C259 100n 10V R172 1k R171 1k R170 1k R169 1k
B_REF_DQ C383 1n 50V
for STR
CD_AVDD R130 4k7
C_REF_DQ CD_CK C261 100n 10V C385 1n 50V C262 100n 10V R173 1k R174 1k R176 1k R175 1k
D_REF_DQ C386 1n 50V C14 100n 16V AB_AVDD C2287 100n 16V CD_AVDD C2295 100n 16V S326 CD_CKE D_CKE C2294 100n 16V C2293 100n 16V C2296 100n 16V C2297 100n 16V C2298 100n 16V C2288 100n 16V C2289 100n 16V C2290 100n 16V C2291 100n 16V C2292 100n 16V C24 10u 10V C22 10u 10V
MP20073DH
4 VTTSEN
VDRV 5 16V 100n C17
3V3_VCC C25 4u7 10V
R31 56R R32 56R
R33 56R R34 56R
CD_AVDD
AB_AVDD
B_CKE R45 1k
C30 10n 16V
AB_AVDD
AB_RESETN
CD_RESETN D_CKE R46 1k C31 10n 16V
C29 10n 16V
AB_CK AB_CKN
R10 22R R11 22R
CD_AVDD
F
F
B_CK B_CKN S325 AB_CKE B_CKE
C32 10n 16V
CD_CK CD_CKN
R12 22R R13 22R
D_CK D_CKN
VESTEL PROJECT NAME : 17MB120-R2
SCH NAME :03_G6F_DDR3 DRAWN BY :NAMIK GOKCEDAGLI
A3
T. SHT: 17
08-09-2015_17:32
1
2
3
4
5
6
7
8
AX M
1
2
3
4
5
6
7
8
ARC
CN1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 R501 47k R502 47k HDMIA_2P HDMIA_2N HDMIA_1P HDMIA_1N HDMIA_0P HDMIA_0N HDMIA_CKP HDMIA_CKN CEC R237 100R HDMIA_SCL R238 100R HDMIA_SDA HDMIA_5V HDMIA_HPD NC 47k R510 NC 33R R431 HDMI20A_DET
CN3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HDMIC_2P HDMIC_2N HDMIC_1P HDMIC_1N HDMIC_0P HDMIC_0N HDMIC_CKP HDMIC_CKN CEC S295 ARC R243 100R 100R R244 HDMIC_5V HDMIC_HPD R506 47k R505 47k R435 33R NC 47k R513 HDMID_5V 10k R336 R50 1k HDMIC_SCL HDMIC_SDA HDMIA_5V R47 1k
A
HDMIA_HPD Q16 BC848B R331 10k
HDMIA_0N HDMIA_0P HDMIA_1N HDMIA_1P HDMIA_2N HDMIA_2P HDMIA_CKN HDMIA_CKP HDMIA_SCL HDMIA_SDA
HDMI20A_DET HDMID_0N HDMID_0P HDMID_1N HDMID_1P HDMID_2N HDMID_2P HDMID_CKN HDMID_CKP HDMID_SCL HDMID_SDA
T2 T3 U1 V2 V3 W2 R1 R2 R6 T5 Y2 U4 L1 M2 M3 N2 P2 P1 K2 K3 L4 L5 M4 M5 D2 D3 E2 E3 F2 F1 C3 D1 H6 H5 K6 J6 G2 G3 H2 H3 J2 J1 F3 G1 J4 K5 H4 J5 V6 P3 AG7 AH6 AH5
HDMIA_0N HDMIA_0P HDMIA_1N HDMIA_1P HDMIA_2N HDMIA_2P HDMIA_CKN HDMIA_CKP HDMIA_SCL HDMIA_SDA HDMIA_HPD HDMIA_5V HDMIB_0N HDMIB_0P HDMIB_1N HDMIB_1P HDMIB_2N HDMIB_2P HDMIB_CKN HDMIB_CKP HDMIB_SCL HDMIB_SDA HDMIB_HPD HDMIB_5V HDMIC_0N HDMIC_0P HDMIC_1N HDMIC_1P HDMIC_2N HDMIC_2P HDMIC_CKN HDMIC_CKP HDMIC_SCL HDMIC_SDA HDMIC_HPD HDMIC_5V HDMID_0N HDMID_0P HDMID_1N HDMID_1P HDMID_2N HDMID_2P HDMID_CKN HDMID_CKP HDMID_SCL HDMID_SDA HDMID_HPD HDMID_5V HDMI_CEC HDMI_ARC MHL_CD MHL_VBUS_EN MHL_OCD
VBY0P VBY0N VBY1P VBY1N VBY2P/LVB0P VBY2N/LVB0N VBY3P/LVB1P VBY3N/LVB1N VBY4P/LVB2P VBY4N/LVB2N VBY5P/LVBCKP VBY5N/LVBCKN VBY6P/LVB3P VBY6N/LVB3N LOCKN/LVA3N HTPDN/LVA3P VBY7P/LVB4P VBY7N/LVB4N OSD0P/LVA0P OSD0N/LVA0N OSD1P/LVA1P OSD1N/LVA1N OSD2P/LVA2P OSD2N/LVA2N OSD3P/LVACKN OSD3N/LVACKN OSDLCKN/LVA4N OSDHTPDN/LVA4P 2
AF31 AF32 AG31 AG32 AH30 AH31 AJ32 AJ31 AK31 AK32 AL31 AL32 AL30 AK30 AL25 AK24 AL29 AK29 AM28 AK28 AK27 AL28 AL26 AK26 AK25 AM26 AL24 AK23
HDMID_HPD Q19 BC848B