Text preview for : Dell-Inspiron.pdf part of dell inspiration vostro 1720 m08 quanta schematic diagram
Back to : Dell-Inspiron.pdf | Home
1
2
3
4
5
6
7
8
Corsica\Gilligan - DISCRETE
M08 M/B PCB
A
VER : X02
POWER
SYSTEM RESET CIRCUIT BATT CHARGER RUN POWER SW
A
Merom
PG 38 PG 40 (Symbol Rev.09) PG 39 667/800 MHz FSB (478 Micro-FCPGA) PG 3,4
POWER
REGULATOR
+1.5V_RUN/+1.05V_VCCP
CLOCK
CK505M+LP PG 43 PG 42 CPU VR DC/DC
+3.3V_ALW/+5V_ALW/+15V_ALW
PG 45 PG 17
AC/BATT CONNECTOR PG 41
REGULATOR PG 44
+1.25V/+1.8V_SUS/+0.9V_DDR_VTT
+3.3V_SUS/+5V_SUS/+3.3V_M +5V/+3.3V/+1.8V/+1.25_RUN
VGA CONN.
Crestline
B
LVDS TVOUT VGA
Panel Connector S-Video PG 19 CRT CONN. PG 19 Camera PG 33
DDR2-SODIMM1
PG 15,16
533/667 MHZ DDR II
PCIEx16
PCI EXPRESS GFX
PG 18
B
1299 uFCBGA PG 5,6,7,8,9,10
DDR2-SODIMM2
PG 15,16
533/667 MHZ DDR II (Symbol Rev.09) USB2.0 (P5) IDE DMI interface 33MHz PCI SATA0 BCM4401 (B0)
+3.3V_LAN
CD-ROM
PG 23 SATA - HDD PG 23 SATA - HDD PG 23
LAN
RJ45/Magnetics PG 36
ICH8-M
676 BGA
SATA1 IHDA MDC CONN SPI PG 26
PG 11,12,13,14
C
AUDIO/AMP
PG 32
(Symbol Rev.09)
33MHz PCI PCIEx1 USB2.0 (P6) PCIEx1 USB2.0 (P9) PCIEx2 USB2.0 (P7)
PG 35 (Symbol Rev.09)
CARDBUS/1394
R5C833 PG 20,21,22
C
EXPRESS-CARD
R5538 PG 26
LPC
D-Micro PG 33 Dash BD
D
Audio Jacks PG 33
Tip Ring BC TP/KB & Media/Dash BD Conn PS/2
MINI-CARD x1 WWAN PG 25
SIO
MEC5025 128KB Flash TMKBC 128 Pins VTQFP PG 28 SPI BC
SIO
ECE5011 Expander USB 2.0 Hub(4) 128 Pins VTQFP PG 29
MINI-CARD x2 WLAN PG 24 USB2.0 (P0,P2) USB2.0 (P3,P8) (EXT SIDE) (EXT BACK) External USB PG 27
D
KB Touchpad
PG 31 Media BD
C G 31FM5MB0011 31GM2MB0004 41FM5SS0017 41GM2SS0000
1 2 3
FLASH
PG 30
CIR PG 31
FAN & THERMAL
EMC4001 PG 34
Title Size Date:
QUANTA COMPUTER
Schematic Block Diagram1 Document Number M-08 Tuesday, March 06, 2007
7
Rev 0.1 Sheet 1
8
of
51
4
5
6
1
2
3
4
5
6
7
8
INDEX Pg#
1 2 3-4
A
Power & Ground DNI LIST Label
DC_IN+ PBATT+ PBATT+ PWR_SRC RTC_PWR3_3V +VCC_CORE +15V_ALW +3.3V_RUN +3.3V_SUS +3.3V_ALW +5V_RUN +5V_SUS +5V_HDD +5V_MOD +5V_ALW +VDDA +1.5V_RUN +1.05V_VCCP +1_8V_SUS +1.8V_RUN +0.9V_DDR_VTT +3.3V_LAN
Description Schematic Block Diagram Front Page Merom Crestline ICH8M DDRII SO-DIMM(200P) Clock Generator VGA LCD Conn. & SSP CRT Conn SATA & IDE Conn PCCARD/Conn & 1394 Express Card & Smart Card Mini Card MDC Conn. SIO (MEC5004) SIO (MEC5018) SERIAL PORT & USB Flash ROM TP,BT & FIR Switch,Keyboard & LED FAN & Thermal Audio CODEC(STAC9200)/Phone Jack LOM (BCM5752)/Switch Docking Conn/Q-Switch System Reset Circuit Battery Selector & Charger DDR2_1.8VSUS, 0.9V 1.5VSUS,1.05V(VTT) 1.25V,1.05VM CPU_MAX8786(3phase) D/D Power RUN Power Switch VGA DC/DC DCIN/Batt Conn.
Pg#
Description
AC ADAPTER (19V) MAIN BATTERY + (10~17V) SECOND BATTERY + (10~17V)
Control Signal
A
5-10 11-14 15-16 17 18-21 22 23 24 25
B
MAIN POWER (10~19V) RTC & +3.3V_RTC_LDO(3.3V) CPU CORE POWER (1.5V) LARGE POWER (15V) SLP_S3# CTRLD POWER SLP_S5# CTRLD POWER 8051 POWER (3.3V) SLP_S3# CTRLD POWER SLP_S5# CTRLD POWER HDD POWER (5V) MODULE POWER (5V) LCD/CHARGE POWER (5V) AUDIO ANALOG POWER (5V) CALISTOGA/ICH7 POWER CPU/CALISTOGA/ICH7 POWER SODIMM POWER SDVO POWER SODIMM POWER LAN POWER AUDIO_AVDD_ON RUN_ON RUN_ON SUSPWROK_5V RUN_ON RUN_ON AUX_EN
C
RUNPWROK SUS_ON RUN_ON SUS_ENABLE ALWON/THERM_STP# RUN_ON SUS_ON +5V_RUN HDDC_EN
B
26 27 28 29 30 31 32 33 34 35
C
36-37 38-39 40-41 42 43-44 45 46 47 48 49
GND AGND_ISL6260
ALL PAGES
DIGITAL GROUND CPU GND DC/DC POWER GND
AGND1 AGND2 8731AGND
VTT POWER GND VTT POWER GND CHARGER GND
D
50 51 52 53 54
1
D
Title
QUANTA COMPUTER
Index, DNI, Power & Ground Document Number M-08 Monday, March 05, 2007
7
PAD& SCREW
Size
EMI CAP
Date:
2 3 4 5 6
Rev 0.1 Sheet 2
8
of
51
1
2
3
4
5
6
7
8
<5> H_A#[3..16]
H_A#[3..16] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#[0..4] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35] H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6
U15A A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# R344 56 2 1 R340 CPU_PROCHOT# 1 H_THERMDA H_THERMDC H_THERMTRIP# R330 56 1 2 H_RESET# R346 56 H_IERR# 1 2 H_ADS# <5> H_BNR# <5> H_BPRI# <5> H_DEFER# <5> H_DRDY# <5> H_DBSY# <5> H_BR0# <5> +1.05V_VCCP H_INIT# <11> H_LOCK# <5> H_RESET# <5> H_RS#0 <5> H_RS#1 <5> H_RS#2 <5> H_TRDY# <5> H_HIT# <5> H_HITM# <5>
<5> H_D#[0..63]
H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
U15B D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL[0] BSEL[1] BSEL[2] D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
H_D#[0..63]
H_D#[0..63]
<5>
CONTROL
IERR# INIT# LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
<5> H_ADSTB#0 <5> H_REQ#[0..4]
DATA GRP 2
A
A
DATA GRP 0
ADDR GROUP 0 ADDR GROUP 0
<5> H_DSTBN#0 <5> H_DSTBP#0 <5> H_DINV#0 <5> H_D#[0..63] H_D#[0..63] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
H_DSTBN#2 <5> H_DSTBP#2 <5> H_DINV#2 <5> H_D#[0..63] H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#[0..63] <5>
<5> H_A#[17..35]
XDP/ITP SIGNALS
+1.05V_VCCP ITP_DBRESET# <13,29> 2
B
THERMAL
PROCHOT# THERMDA THERMDC THERMTRIP# D21 A24 B25 C7
<5> H_ADSTB#1 <11> H_A20M# <11> H_FERR# <11> H_IGNNE# <11> <11> <11> <11> H_STPCLK# H_INTR H_NMI H_SMI#
+1.05V_VCCP 0_NC 2 EC_CPU_PROCHOT# H_THERMDA <34> H_THERMDC <34> H_THERMTRIP# <34> +1.05V_VCCP
R402 1K/F <28>
DATA GRP 3
Layout Note: Place voltage divider within 0.5" of GTLREF pin
1
2
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
1
RESERVED
Merom Ball-out Rev 1a
C
Populate ITP700Flex for bringup
+1.05V_VCCP
For Support XDP: 1. ITP_BPM#5 need PU 51ohms to +1.05V_VCCP. 2. Change R4 & R361 to 51 ohms. 3. Changed R6 & R346 to 51 ohms. 4. Depopulate R2 and changed R8 to 1K/F.
2
2
2
800
200
0
1
0
R398 54.9/F 1 1
R400 27.4/F 1
R392 54.9/F 1
2
ADDR GROUP 1
DATA GRP 1
<5> H_DSTBN#1 <5> H_DSTBP#1 <5> H_DINV#1
H_DSTBN#3 <5> H_DSTBP#3 <5> H_DINV#3 <5> COMP0 COMP1 COMP2 COMP3
B
R404 2K/F
H CLK
BCLK[0] BCLK[1] A22 A21
V_CPU_GTLREF AD26 CPU_TEST1 C23 CPU_TEST2 D25 CPU_TEST3 C24 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26 <6,17> CPU_MCH_BSEL0 <6,17> CPU_MCH_BSEL1 <6,17> CPU_MCH_BSEL2 B22 B23 C21
MISC COMP[1]
Note: H_DPRTSTP need to daisy chain from ICH8 to IMVP6 to CPU.
H_DPRSTP# <6,11,45> H_DPSLP# <11> H_DPWR# <5> H_PWRGOOD <11> H_CPUSLP# <5> H_PSI# <45>
ICH ICH
CLK_CPU_BCLK <17> CLK_CPU_BCLK# <17>
Merom Ball-out Rev 1a H_THERMDA C163 1 2 H_THERMDC R331 1K/F_NC CPU_TEST1 1 2 R106 1K/F_NC CPU_TEST2 1 2 C520 0.1U/10V_NC CPU_TEST4 2 1 R332 0_NC CPU_TEST6 1 2 PAD T17 PAD T97 CPU_TEST3 CPU_TEST5
2200P/50V_NC
For the purpose of testability, route these signals through a ground referenced Z0 = 55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.
C
Place C close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal.
FSB 533 667
BCLK 133 166
BSEL2 0 0
BSEL1 0 1
BSEL0 1 1
COMP0 COMP1 COMP2 COMP3
Layout Note: Place couple 0.1uF Decoupling caps with in 0.1" ITP connector.
R409 150 +1.05V_VCCP JITP1 1 2 5 7 3 12 11 8 9 10 14 16 18 20 22 TDI TMS TCK TDO TRST# RESET# FBO BCLKN BCLKP GND0 GND1 GND2 GND3 GND4 GND5 BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# NC0 NC1 GND_0 GND_1 23 21 19 17 15 13 4 6 29 30 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#51 R403 VTT0 VTT1 VTAP 27 28 26 +3.3V_ALW +3.3V_SUS
R388 27.4/F
1
1
1
R352 51/F 2 2
R354 51 2
R408 39/F 2
1
ITP700 layout guidelines
ITP_TDI ITP_TMS ITP_TCK ITP_TDO ITP_TRST# H_RESET# ITP_TCK 0_NCR414 0_NCR414 2 C476 0.1U/10V 2 1 C472 0.1U/10V 2 1
Signal
2 0 R416
Resistor Value Connect To Resistor Placement 150 ohm ± 5% 39 ohm ± 1% 500 to 680 ohm ± 5% 27 ohm ± 1% VCCP VCCP GND Place the pull-up near CPU Within 200ps of ITP connector Place the pull-down near CPU Connect to TCK pin of CPU and then connect it to FBO pin of ITP connector in daisy chain. Place the pull-down near TCK0 pin of ITP connector
TDI TMS
R353 1 R351 1
2 0 22.6/F 2
Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.
1
Layout Note: Place R8 close ITP.
DBR# DBA#
25 24
ITP_DBRESET#
R412 2
150 1
1
TRST#
TCK
GND
D
<17> CLK_CPU_ITP# <17> CLK_CPU_ITP
D
+1.05V_VCCP
TDO
51 ohm ± 5% 22.6 ohm ± 1% series resistor and pullup 51 ohm ± 1%.
VCCP
Place the pull-up near ITP Connect to CPURST# pin of GMCH through the series resistor placed within 200ps of ITP connector. Place the pull-up after the series resistor from ITP connector.
R350 27/F 2 1 R406 649/F 2 1
ITP_TCK ITP_TRST#
2 51_NC
RESET#
VCCP
DELL CONFIDENTIAL/PROPRIETARY
Title Merom Processor (HOST BUS) Size Date: Document Number M-08 Monday, March 05, 2007
7
Reserved for support XDP debug.
ITP700Flex_NC
Rev 0.1 Sheet 3
8
of
51
1
2
3
4
5
6
1
2
3
4
5
6
7
8
+VCC_CORE U15C +VCC_CORE A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE . AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26
+VCC_CORE U15D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] . P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
All use 10U 4V(+-20%,X6S,0805)Pb-Free.
1 1 1 1 2 C205 10U/4V C206 10U/4V
1
A
2
2
2
2
C492 10U/4V
C203 10U/4V
C204 10U/4V
A
+VCC_CORE
1
1
1
1
2
2
2
2
8 inside cavity, north side, secondary layer.
+VCC_CORE
1
1
1
2
2
2
2
2
C503 10U/4V
C502 10U/4V
C506 10U/4V
1
1 C505 10U/4V C504 10U/4V
2
C508 10U/4V
C507 10U/4V
C207 10U/4V
C208 10U/4V
1 C462 10U/4V
+1.05V_VCCP
1 + C487 220U/4V 2
+VCC_CORE
B
B
1
1
1
2
2
2
2
2
C448 10U/4V
C447 10U/4V
C501 10U/4V
1
1 C442 10U/4V C449 10U/4V
+1.5V_RUN
8 inside cavity, south side, secondary layer.
+VCC_CORE
1
1 2
2
2
2
6 inside cavity, north side, primary layer.
+VCC_CORE
2
2
2
C491 10U/4V
C458 10U/4V
C443 10U/4V
C444 10U/4V
C445 10U/4V
C446 10U/4V
AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7 VCCSENSE VSSSENSE
VID0 VID1 VID2 VID3 VID4 VID5 VID6
<45> <45> <45> <45> <45> <45> <45>
C430 0.01U/25V
C440 10U/4V
1
1
1
1
1
1
VCCSENSE <45> VSSSENSE <45>
1
1
1
1
1
C
1
2
Layout Note: Place C105 near PIN B26.
Merom Ball-out Rev 1a C189 10U/4V +VCC_CORE 1 R413 100/F 2
C
2
2
2
2
2
6 inside cavity, south side, primary layer.
2
C184 10U/4V
C185 10U/4V
C186 10U/4V
C187 10U/4V
C188 10U/4V
VCCSENSE VSSSENSE +1.05V_VCCP 1 1 1 + C250 100U/25V C459 0.1U/10V 2 2 + C53 100U/25V 2 + C98 100U/25V_NC 2 1 1 +PWR_SRC
60
+ C249 100U/25V
R410 100/F 2
Merom Ball-out Rev 1a
1
1
1
1
2
2
2
2
2
2
C490 0.1U/10V
C461 0.1U/10V
C489 0.1U/10V
C460 0.1U/10V
1
C488 0.1U/10V
1
Layout out: Place these inside socket cavity on North side secondary.
D
Layout Note: Need to add 100uF cap on PWR_SRC for cap singing. Place on PWR_SRC near +VCC_CORE.
Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil. Place PU and PD within 2 inch of CPU.
D
DELL CONFIDENTIAL/PROPRIETARY
Title Merom Processor (POWER) Size Date:
1 2 3 4 5 6
Document Number M-08 Monday, March 05, 2007
7
Rev 0.1 Sheet 4
8
of
51
1
2
3
4
5
6
7
8
U19A <3> H_D#[0..63]
A
H_A#[3..35] H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING H_RCOMP H_SCOMP H_SCOMP# E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B3 C2 W1 W2 B6 E5 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP H_SCOMP H_SCOMP# H_CPURST# H_CPUSLP#
H_A#[3..35]
<3>
A
+1.05V_VCCP
1 R360 221/F 2 H_SWING R368 100/F 2 2 1
B
1
C465 0.1U/10V
B
+1.05V_VCCP
R401 54.9/F 2 2
R399 54.9/F H_SCOMP H_SCOMP# H_RCOMP
H_ADS# <3> H_ADSTB#0 <3> H_ADSTB#1 <3> H_BNR# <3> H_BPRI# <3> H_BR0# <3> H_DEFER# <3> H_DBSY# <3> CLK_MCH_BCLK <17> CLK_MCH_BCLK# <17> H_DPWR# <3> H_DRDY# <3> H_HIT# <3> H_HITM# <3> H_LOCK# <3> H_TRDY# <3>
1
R361 24.9/F
HOST
1
1
C
Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing.
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
2
K5 L2 AD13 AE13 M7 K3 AD2 AH11 L7 K2 AC2 AJ10 M14 E13 A11 H13 B12 E12 D7 D8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
<3> <3> <3> <3> <3> <3> <3> <3> <3> <3> <3> <3>
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
C
+1.05V_VCCP 2
R357 1K/F 1
<3> H_RESET# <3> H_CPUSLP#
<3> <3> <3> <3> <3>
H_REF 1
B9 A9
H_RS#0 <3> H_RS#1 <3> H_RS#2 <3>
H_AVREF H_DVREF CRESTLINE_1p0
R362 2K/F 2
1
C456 0.1U/10V
AJ0QP210T00
D
Layout Note: Place the 0.1 uF decoupling capacitor within 100 mils from GMCH pins.
2
D
DELL CONFIDENTIAL/PROPRIETARY
Title Crestline (HOST) Size Date:
1 2 3 4 5 6
Document Number M-08 Tuesday, March 06, 2007
7
Rev 0.1 Sheet 5
8
of
51
1
2
3
4
5
6
7
8
+1.8V_SUS P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 1
U19B RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 J40 H39 E39 E40 C37 D35 K40 L41 L43 N41 N40 D46 C45 D44 E42 G51 E51 F49 G50 E50 F48 G44 B47 B45 E44 A47 A45
U19C L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 VCC3G_PCIE_R
+VCC_PEG R389 24.9/F 1 2
1
R421 1K/F 2 SM_RCOMP_VOH 1 C564 0.01U/25V 1 C559 2.2U/10V
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1
AV29 BB23 BA25 AV23 AW30 BA23 AW25 AW23 BE29 AY32 BD39 BG37 BG20 BK16 BG16 BE13 BH18 BJ15 BJ14 BE16 BL15 BK14 BK31 BL31 AR49 AW4
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
<15> <15> <15> <15> <15> <15> <15> <15> <15,16> <15,16> <15,16> <15,16> <15,16> <15,16> <15,16> <15,16>
+1.8V_SUS
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
N43 M43 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44 M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
R424 20/F SMRCOMPP SMRCOMPN 2
A
R425 3.01K/F 2
SM_RCOMP_VOL 1 1 1 C563 0.01U/25V C560 2.2U/10V
MUXING
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT0 M_ODT1 M_ODT2 M_ODT3 SMRCOMPP SMRCOMPN SM_RCOMP_VOH SM_RCOMP_VOL <15,16> <15,16> <15,16> <15,16>
R422 20/F 2
R426 1K/F 2
Santa Rosa Platform MOW WW15 For 4Gb DRAM support, change Pin-BJ29 to DDR_A_MA14, change Pin-BE24 to DDR_B_MA14.
<15,16> DDR_A_MA14 <15,16> DDR_B_MA14 +3.3V_RUN R375 1 R383 1
B
2
1
DDR_A_MA14 DDR_B_MA14
2 10K 2 10K
PM_EXTTS#0 PM_EXTTS#1
+1.05V_VCCP R395 56 1 2 THERMTRIP_MCH#
CLK
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
B42 C42 H48 H47 K44 K45 CLK_MCH_3GPLL <17> CLK_MCH_3GPLL# <17>
PCI-EXPRESS
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
PCIE_MRX_GTX_N0 PCIE_MRX_GTX_N1 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N5 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N7 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_N13 PCIE_MRX_GTX_N14 PCIE_MRX_GTX_N15 PCIE_MRX_GTX_P0 PCIE_MRX_GTX_P1 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P4 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_P6 PCIE_MRX_GTX_P7 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_P14 PCIE_MRX_GTX_P15 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15
PCIE_MRX_GTX_N[0..15] <18>
2
2
1
A
1
LVDS LVDS
2
2
GRAPHICS
PCIE_MRX_GTX_P[0..15] <18>
DDR
MCH_CLVREF V_DDR_MCH_REF C522 0.1U/10V
2
1
2
RSVD RSVD
Non-iAMT
+1.25V_RUN 1
R405 1K/F
R407 392/F
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
PCIE_MTX_GRX_N[0..15] <18>
B
E27 G27 K27 F27 J27 L27 M35 P33
TVA_DAC TVB_DAC TVC_DAC
TV TV
TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 TV_DCONSEL_1
Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.
<3,17> CPU_MCH_BSEL0 <3,17> CPU_MCH_BSEL1 <3,17> CPU_MCH_BSEL2 PAD PAD R377 2 PAD PAD PAD R366 2 PAD PAD PAD PAD PAD PAD R391 2 +3.3V_RUN PAD PAD R381 2 R382 2 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AN47 AJ38 AN42 AN46 AM47 AJ39 AN41 AN45 AJ46 AJ41 AM40 AM44 AJ47 AJ42 AM39 AM43
DMI_MRX_ITX_N0 DMI_MRX_ITX_N1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N3 DMI_MRX_ITX_P0 DMI_MRX_ITX_P1 DMI_MRX_ITX_P2 DMI_MRX_ITX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
<12> <12> <12> <12> <12> <12> <12> <12> <12> <12> <12> <12> <12> <12> <12> <12>
PCIE_MTX_GRX_P[0..15] <18>
DMI
T80 T26 T94 T84 T85 T95 T89 T90 T79 T82 T88 T92 T91
1 4.02K/F_NC
1 4.02K/F_NC
1 4.02K/F_NC 1 4.02K/F_NC
GRAPHICS VID
C
1 4.02K/F_NC
CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
H32 G32 K29 J29 F29 E29 K33 G35 F33 C32 E33
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
VGA VGA
CFG CFG
C
CRESTLINE_1p0 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN E35 A39 C38 B39 E36 T83 PAD T19 PAD T20 PAD T22 PAD T21 PAD
<13> PM_BMBUSY# <3,11,45> H_DPRSTP# <15> PM_EXTTS#0 <15> PM_EXTTS#1 <13,38> ICH_PWRGD <34> THERMTRIP_MCH# <13,45> DPRSLPVR
G41 L39 L36 J36 AW49 PLTRST#_R AV20 THERMTRIP_MCH# N20 G36 1 2 PM_EXTTS#0 PM_EXTTS#1 R363 PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD T37 T38 T42 T44 T43 T41 T40 T36 T35 T30 T25 T29 T27 T24 T23 T39 0 TP_NC1 TP_NC2 TP_NC3 TP_NC4 TP_NC5 TP_NC6 TP_NC7 TP_NC8 TP_NC9 TP_NC10 TP_NC11 TP_NC12 TP_NC13 TP_NC14 TP_NC15 TP_NC16 BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
CFG5 CFG9 CFG16
D
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
ME
AM49 AK50 AT43 AN49 AM50
CL_CLK0 <13> CL_DATA0 <13> ICH_CL_PWROK <13,28> ICH_CL_RST0# <13> MCH_CLVREF
CFG19
CFG20
Low=DMIx2 DMI X2 Select High=DMIx4(Default) Low= Reveise Lane PCI Express Graphic Lane High=Normal operation FSB Dynamic Low=Dynamic ODT Disable ODT High=Dynamic ODT Enable(default). DMI Lane Low=Normal(default). Reversal High=Lane Reversed Low=Only SDVO or PCIEx1 is SDVO/PCIE operational (defaults) Concurrent High=SDVO and PCIEx1 are operating Operation simultaneously via PEG port
MISC
2
CRESTLINE_1p0
R396 20K 1 1
2
PM PM NC NC
SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2
H35 K36 G39 G40 A37 R32
Low=No SDVO Device Present (default) SDVO_CRTL_DATA SDVO Present. High=SDVO Device Present
CLK_3GPLLREQ# <17> MCH_ICH_SYNC# <13>
D
DELL CONFIDENTIAL/PROPRIETARY
R356 0 PLTRST#_R 2 100 R415 1 R160 1 R161 1 0_0402 2 0_0402_NC 2 PLTRST# <12,28> SB_NB_PCIE_RST# <12> Title Crestline (VGA,DMI) Size Date: Document Number M-08 Tuesday, March 06, 2007
7
Rev 0.1 Sheet 6
8
of
51
1
2
3
4
5
6
1
2
3
4
5
6
7
8
<15> DDR_A_D[0..63] DDR_A_D0 AR43 DDR_A_D1AW44 DDR_A_D2 BA45 DDR_A_D3 AY46 DDR_A_D4 AR41 DDR_A_D5 AR45 DDR_A_D6 AT42 DDR_A_D7AW47 DDR_A_D8 BB45 DDR_A_D9 BF48 DDR_A_D10 BG47 DDR_A_D11BJ45 DDR_A_D12 BB47 DDR_A_D13 BG50 DDR_A_D14 BH49 DDR_A_D15 BE45 DDR_A_D16 AW43 DDR_A_D17 BE44 DDR_A_D18 BG42 DDR_A_D19 BE40 DDR_A_D20 BF44 DDR_A_D21 BH45 DDR_A_D22 BG40 DDR_A_D23 BF40 DDR_A_D24 AR40 DDR_A_D25 AW40 DDR_A_D26 AT39 DDR_A_D27 AW36 DDR_A_D28 AW41 DDR_A_D29 AY41 DDR_A_D30 AV38 DDR_A_D31 AT38 DDR_A_D32 AV13 DDR_A_D33 AT13 DDR_A_D34 AW11 DDR_A_D35 AV11 DDR_A_D36 AU15 DDR_A_D37 AT11 DDR_A_D38 BA13 DDR_A_D39 BA11 DDR_A_D40 BE10 DDR_A_D41 BD10 DDR_A_D42 BD8 DDR_A_D43 AY9 DDR_A_D44 BG10 DDR_A_D45AW9 DDR_A_D46 BD7 DDR_A_D47 BB9 DDR_A_D48 BB5 DDR_A_D49 AY7 DDR_A_D50 AT5 DDR_A_D51 AT7 DDR_A_D52 AY6 DDR_A_D53 BB7 DDR_A_D54 AR5 DDR_A_D55 AR8 DDR_A_D56 AR9 DDR_A_D57 AN3 DDR_A_D58 AM8 DDR_A_D59 AN10 DDR_A_D60 AT9 DDR_A_D61 AN9 DDR_A_D62 AM9 DDR_A_D63 AN11
U19D SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 CRESTLINE_1p0 SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVEN# SA_WE# BB19 BK19 BF29 BL17 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BE18 AY20 BA19 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_CAS# DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_RAS# DDR_A_WE#
<15> DDR_B_D[0..63] DDR_A_BS0 <15,16> DDR_A_BS1 <15,16> DDR_A_BS2 <15,16> DDR_A_CAS# <15,16> DDR_A_DM[0..7] <15> DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
U19E SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 CRESTLINE_1p0 SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVEN# SB_WE# AY17 BG18 BG36 BE17 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 AV16 AY18 BC17 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_CAS# DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_RAS# DDR_B_WE# DDR_B_BS0 <15,16> DDR_B_BS1 <15,16> DDR_B_BS2 <15,16> DDR_B_CAS# <15,16> DDR_B_DM[0..7] <15>
A
A
DDR_A_DQS[0..7]
<15>
DDR_B_DQS[0..7]
<15>
A
MEMORY
DDR_A_DQS#[0..7]
<15>
MEMORY
B
DDR_B_DQS#[0..7]
<15>
B
DDR_A_MA[0..13]
<15,16>
DDR_B_MA[0..13]
<15,16>
B
SYSTEM
DDR
DDR
SYSTEM
DDR_A_RAS# <15,16> T102 PAD DDR_A_WE# <15,16>
DDR_B_RAS# <15,16> T103 PAD DDR_B_WE# <15,16>
C
C
D
D
DELL CONFIDENTIAL/PROPRIETARY
Title Crestline (DDR2) Size Date:
1 2 3 4 5 6
Document Number M-08 Monday, March 05, 2007
7
Rev 0.1 Sheet 7
8
of
51
5
4
3
2
1
+3.3V_RUN U19G +VCC_GMCH AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 R341 1 VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83 T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 10 2 +VCC_GMCH_L D29 1 2 AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 U19F VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
SDMK0340L-7-F
+1.05V_VCCP
D
+VCC_GMCH 1 1 1 + 1 1
2
2
2
VCC_13
Layout Note: Inside GMCH cavity.
2
2
R30
Layout Note: 370 mils from edge.
C202 220U/2.5V
C192 22U/4V
C512 0.22U/10V
C513 0.22U/10V
C517 0.1U/10V
+VCC_SM AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
POWER
POWER
VSS SCB
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 A3 B2 C1 BL1 BL51 A51
C
C
VCC GFX NCTF
VCC SM
VCC NCTF
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
VCC CORE
D
VSS NCTF
+1.05V_VCCP
Layout Note: Inside GMCH cavity.
+VCC_AXM 1 1 1
2
2
B
A
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
Non-iAMT
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
2
C523 0.1U/10V
C521 0.1U/10V
C526 0.1U/10V
2
2
Layout Note: Place close to GMCH edge.
2
C239 22U/4V
C527 0.22U/10V
C529 0.22U/10V
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
VCC AXM NCTF
VCC AXM
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
AT33 +VCC_AXM AT31 AK29 AK24 AK23 AJ26 AJ23
B
1
1
1
CRESTLINE_1p0
VCC GFX
+1.8V_SUS
+VCC_SM
VCC SM LF
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
AW45 BC39 BE39 BD17 BD4 AW8 AT6
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 1 1 1 1 1 1 1 C531 0.1U/10V C537 0.1U/10V C549 0.22U/10V C547 0.22U/10V C557 0.47U/10V C536 1U/10V C534 1U/10V
1
1
1
+ 2 C530 0.1U/10V C572 330U/6.3V
2
2
Layout Note: Place C901 where LVDS and DDR2 taps.
Layout Note: Place on the edge.
A
2
2
2
2
2
2
2
DELL CONFIDENTIAL/PROPRIETARY
CRESTLINE_1p0 Title Crestline (VCC,NCTF) Size Date:
5 4 3 2
Document Number M-08 Monday, March 05, 2007 Sheet
1
2
C253 22U/4V
1 C254 22U/4V
Rev 0.1 8 of 51
5
4
3
2
1
U19H J32 A33 B33 A30 B32
D
VCCSYNC VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 VCCA_DAC_BG VSSA_DAC_BG VCCA_DPLLA
VTT
B49 H49
PLL
Non-iAMT 45mA MAx.
+1.25V_RUN L36 2 1 BLM11A121S 1 +VCCA_HPLL 1 +3.3V_RUN C519 0.1U/10V
VCCA_DPLLB VCCA_HPLL VCCA_MPLL
+VCCA_HPLL +VCCA_MPLL
AL2 AM2 A41 B41
A LVDS
2
FB_120ohm+-25%_100mHz _200mA_0.2ohm DC
VCCA_LVDS VSSA_LVDS
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 AT23 AU28 AU24 AT29 AT25 AT30 AR29 B23 B21 A21 AJ50 BK24 BK23 BJ24 BJ23
VCC_HV
1 1 C497 2.2U/6.3V C493 4.7U/10V
+1.05V_VCCP 2
CRT
D30 CH751H-40HPT_NC 1 +1.05V_VCCP 1 +VCC_HV_L
2
2
Place on the edge.
2
R342 10_NC
D
1
1
1 C499 4.7U/10V + C235 220U/4V
2
2
C496 0.47U/6.3V
+3.3V_RUN
Non-iAMT
+1.25V_RUN +1.25V_RUN PJP17
Place on the edge.
+VCC_AXD_L 1 1 1 L39 2+VCC_AXD_R 0 2
2
2
C241 22U/10V
K50 L37 BLM11A121S 1 R411 0.5/F/0603 1 2 K49 +VCCA_MPLL 1 C466 0.1U/10V +VCCA_PEG_PLL U51 AW18 AV19 AU19 AU18 AU17 2 2 1 1 C525 4.7U/6.3V C532 22U/4V +VCCA_SM C541 22U/4V 1 C524 1U/10V AT22 AT21 AT19 AT18 AT17 AR17 AR16 BC29 BB29 C25 B25 C27 B27 B28 A28 M32 L29 N28 +1.25V_RUN
B
A PEG
VCCA_PEG_BG VSSA_PEG_BG VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2 VCCD_CRT VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS_1 VCCD_LVDS_2
AXD
2
VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 VCC_AXD_NCTF VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI
1
2
2
C533 1U/10V
C251 22U/10V
Reserved L81 pad for inductor.
+VCC_AXF 1 1 2 C452 1U/10V C453 10U/6.3V
Place caps close to VCC_AXD.
1
2
2
C242 22U/10V
POWER
A SM
AXF
1
+VCCA_MPLL_L 2
C528 0.1U/10V PJP16 +1.25V_RUN 1 1 + C246 100U/6.3V
SM CK
Non-iAMT
PJP18 +1.25V_RUN 1 2
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
+VCC_SM_CK 2
1
C
+1.25V_RUN C518 0.1U/10V
Place caps close to VCC_AXF
2
+VCC_AXF
C
2
1
2
2
2
A CK
VCC_TX_LVDS VCC_HV_1 VCC_HV_2 VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
A43 +3.3V_RUN C40 B40 1 AD51 W50 W51 V49 V50 AH50 AH51 A7 F2 AH1 C463 0.1U/10V
+VCCA_SM_CK 1 1 1 1 C548 22U/4V C538 1U/10V C539 1U/10V C555 0.1U/10V
TV
2
2
2
2
HV
PEG
2
+VCC_PEG L25 2 1 91nH/1.5A 1
+1.05V_VCCP
+1.5V_RUN 1 1 C450 10U/6.3V C483 0.1U/10V 1 C451 0.022U/16V
D TV/CRT
DMI
2
2
2
VCC_RXR_DMI_1 VCC_RXR_DMI_2
+VCC_RXR_DMI 2
+ 2 C216 220U/4V
91uH+-20%_1.5A
C514 10U/6.3V +1.05V_VCCP L27 2
B
AN2 L35 1 2 BLM21PG221SN1D +1.25V_RUN 1 1 +VCCA_PEG_PLL 1 +VCCA_PEG_PLL C457 0.1U/10V C500 0.1U/10V U48 J41 H42
VTTLF
LVDS
Non-iAMT
VTTLF1 VTTLF2 VTTLF3
+VTTLF1 +VTTLF2 +VTTLF3 1
1
91nH/1.5A
1
1 2
2
C494 10U/6.3V
2
C509 0.1U/10V +VTTLF1 +VTTLF2 +VTTLF3 1 1 1 C516 0.47U/10V C473 0.47U/10V C454 0.47U/10V
2
2
FB_220ohm+-25%_100MHz _2A_0.1ohm DC
1
R394 1/F/0603
+ CRESTLINE_1p0 C233 220U/4V
91uH+-20%_1.5A
C515 10U/6.3V
2
2
1
2
2
2
+VCC_SM_CK 1
L38 1uH/300mA 2
+1.8V_SUS 1
1uH+-20%_300mA
R423 1/F/0603
1
1 2 2
2
2
C252 22U/10V
1 C550 0.1U/10V
+VCC_SM_CK_L C552 10U/6.3V
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title Crestline (POWER) Size Date:
5 4 3 2
Document Number M-08 Monday, March 05, 2007 Sheet
1
Rev 0.1 9 of 51
5
4
3
2
1
U19I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 CRESTLINE_1p0 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
U19J VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 CRESTLINE_1p0 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
D
D
VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
VSS
C
C
VSS
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Title Crestline (VSS) Size Date: Document Number M-08 Monday, March 05, 2007 Sheet
1
Rev 0.1 10 of 51
5
4
3
2
1
2
3
4
5
6
7
8
32.768KHZ
1
W1 ICH_RTCX1 1 1 2 C378 15P/50V 4 1 3
R251 0 2 ICH_RTCX2 2 1
R272 332K/F ICH_INTVRMEN 2 1
1 R283 332K/F ICH_LAN100_SLP
A
R259 2
10M 1
+RTC_CELL
+RTC_CELL
A
32.768KHZ 2
2
C369 15P/50V
1 R265 0_NC 2
R282 0_NC 2
+RTC_CELL
ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
2
ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05) ICH_LAN100_SLP Low = Internal VR Disabled High = Internal VR Enabled(Default)
+1.05V_VCCP
1
ICH_INTVRMEN
R238 20K ICH_RTCRST# ICH_INTRUDER# C359 1U/10V ICH_RTCX1 ICH_RTCX2 ICH_RTCRST#
Low = Internal VR Disabled High = Internal VR Enabled(Default)
U8A AG25 AF24 AF23 RTCX1 RTCX2
R269 1M 2 1
Reserved for Intel Nineveh design.
T76 PAD R23 R24 1 1 2 33 2 10 ACZ_BIT_CLK T73 T75 T16 T70 T72 T74 PAD PAD PAD PAD PAD PAD T5 +1.5V_PCIE_ICH PAD
1
1
INTRUDER# INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GLAN_DOCK#/GPIO13 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M#
ICH_INTVRMEN AF25 ICH_LAN100_SLP AD21 GLAN_CLK LAN_RSTSYNC B24 D22 C21 B21 C22 D21 E20 C20 AH21 D25 C25 AJ16 AJ15 AE14 AJ17 AH17 AH15 AD13 ACZ_SDOUT AE13
G9 E6 AF13 AG26 AF26 AE26 AD24 AG29 AF27 AE24 AC20 AH14 AD23 AG28 AA24 AE27 AA23 V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 AA4 AA1 AB3 Y6 Y5 W4 W3 Y2 Y3 Y1 W5
LPC_LDRQ0# LPC_LDRQ1# SIO_A20GATE H_DPRSTP# H_DPSLP# H_FERR#
PAD PAD
T68 T63
H_DPRSTP# H_DPSLP# H_FERR#
2
SIO_A20GATE <28> H_A20M# <3> H_DPRSTP# <3,6,45> H_DPSLP# <3> H_FERR# <3> H_PWRGOOD <3> H_IGNNE# <3> 1 H_INIT# <3> H_INTR <3> SIO_RCIN# <28> H_NMI <3> H_SMI# <3> H_STPCLK# <3> SIO_A20GATE SIO_RCIN# 1 2 +3.3V_RUN
B
2
2
1
1
C46 27P/50V_NC
C47 27P/50V_NC
CPUPWRGD/GPIO49
R256 10K
2 R248 10K +1.05V_VCCP 2 R268 56 1
23
LAN / GLAN
B
<26> ICH_AZ_MDC_BITCLK <32> ICH_AZ_CODEC_BITCLK
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
DPRSTP# DPSLP# FERR#
CPU
IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#
<26> <32> <26> <32> <26> <32>
ICH_AZ_MDC_SYNC ICH_AZ_CODEC_SYNC ICH_AZ_MDC_RST# ICH_AZ_CODEC_RST# ICH_AZ_MDC_SDOUT ICH_AZ_CODEC_SDOUT
R228 R229 R230 R231 R236 R237
1 1 1 1 1 1
2 2 2 2 2 2
33 33 33 33 33 33
ACZ_SYNC ACZ_RST# ACZ_SDOUT
R306 24.9/F 1 2 GLAN_COMP ACZ_BIT_CLK ACZ_SYNC ACZ_RST#
SIO_RCIN#
IHDA
Place all series terms close to ICH8 except for SDIN input lines,which should be close to source.Placement of R23, R228, R230 & R236 should equal distance to the T split trace point as R24, R229, R231 & R237 respective. Basically,keep the same distance from T for all series termination resistors.
THERMTRIP#_ICH PAD IDE_DD[0..15] IDE_DD0 IDE_DD1 IDE_DD2 IDE_DD3 IDE_DD4 IDE_DD5 IDE_DD6 IDE_DD7 IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15 IDE_DA0 IDE_DA1 IDE_DA2 IDE_DCS1# IDE_DCS3# T61 IDE_DD[0..15] <23> THERMTRIP#_ICH
<32> ICH_AZ_CODEC_SDIN0 <26> ICH_AZ_MDC_SDIN1 T8 PAD T48 PAD
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT
TP8 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DA0 DA1 DA2 DCS1# DCS3# DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
<32> SPEAKER_DET# <30> RTC_BAT_DET# <23> SATA_TX0<23> SATA_TX0+ <23> SATA_TX2<23> SATA_TX2+ C361 C360 C362 C363 2 2 2 2 1 3900P/25V 1 3900P/25V 1 3900P/25V 1 3900P/25V SATA_TX0-_C SATA_TX0+_C SATA_TX2-_C SATA_TX2+_C <23> SATA_RX0<23> SATA_RX0+
SPEAKER_DET# AE10 RTC_BAT_DET# AG14 SATA_ACT#_R AF10 AF6 AF5 AH5 AH6 AG3 AG4 AJ4 AJ3 AF2 AF1 AE4 AE3 AB7 AC6 R250 24.9/F 2 1 SATABIAS AG1 AG2
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS ICH8M REV 1.0
C
1
ICH_INTRUDER# AD22
RTC LPC
RTCRST#
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
1
E5 F5 G8 F6 C4
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
<28> <28> <28> <28>
2
2
R257 56_NC
R264 56_NC
2 R276 56
LPC_LFRAME# <28>
C
SATA_TX0-_C SATA_TX0+_C
SATA
Distance between the ICH-8 M and cap on the "P" signal should be identical distance between the ICH-6 M and cap on the "N" signal for same pair.
9/20 Move from SATA port 1
<23> SATA_RX2<23> SATA_RX2+ SATA_TX2-_C SATA_TX2+_C
IDE
IDE_DA0 <23> IDE_DA1 <23> IDE_DA2 <23> IDE_DCS1# <23> IDE_DCS3# <23> IDE_DIOR# <23> IDE_DIOW# <23> IDE_DDACK# <23> IDE_IRQ <23> IDE_DIORDY <23> IDE_DDREQ <23>
This circuit is only needed if the platform has the SNIFFER.
<29,37> LED_MASK# 2
+3.3V_RUN 1
<17> CLK_PCIE_SATA# <17> CLK_PCIE_SATA
R263 10K 2
Place within 500mils of ICH8 ball
AJ0QN230T00
+3.3V_RUN R244 2 R495 2 1 100K RTC_BAT_DET# 1 100K SPEAKER_DET#
<37> SATA_ACT#
3 Q29 2N7002W-7-F
1
SATA_ACT#_R
+3.3V_RUN 2
D
XOR Chain Entrance Strap
ICH RSVD 0 0 1 1 HDA SDOUT Description
1
R235 1K_NC ACZ_SDOUT ICH_RSVD 2 R22 1K_NC 1 <13>
D
R278 0_NC 1 2
0 1 0 1
RSVD Enter XOR Chain Normal Operation (Default) Set PCIE port config bit 1
DELL CONFIDENTIAL/PROPRIETARY
Title ICH8-M (CPU,IDE,SATA,LPC,AC97,LAN) Size Date: Document Number M-08 Tuesday, March 06, 2007
7
Rev 0.1 Sheet 11
8
of
51
1
2
3
4
5
6
1
2
3
4
5
6
7
8
Place TX DC blocking caps close ICH8.
<25> PCIE_TX1<25> PCIE_TX1+ <24> PCIE_TX2<24> PCIE_TX2+ <24> PCIE_TX3<24> PCIE_TX3+
A
U8D PCIE_TXN1_C PCIE_TXP1_C
WWAN
C101 C106 C114 C116 C127 C120 1 1 1 1 1 1 2 2 2 2 2 2 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V PCIE_TXN2_C PCIE_TXP2_C PCIE_TXN3_C PCIE_TXP3_C PCIE_TXN4_C PCIE_TXP4_C <24> PCIE_RX2<24> PCIE_RX2+
WLAN
<24> PCIE_RX3<24> PCIE_RX3+
PCIE_TXN2_C PCIE_TXP2_C
M27 M26 L29 L28 K27 K26 J29 J28 H27 H26 G29 G28 F27 F26 E29 E28 D27 D26 C29 C28
PCI-Express Direct Media Interface
C90 C97
1 1
2 2
0.1U/10V 0.1U/10V
PCIE_TXN1_C PCIE_TXP1_C
<25> PCIE_RX1<25> PCIE_RX1+
P27 P26 N29 N28
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP
V27 V26 U29 U28 Y27 Y26 W29 W28 AB26 AB25 AA29 AA28 AD27 AD26 AC29 AC28 T26 T25 Y23 Y24 G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 F2 F3 USBRBIAS DMI_COMP R281 2
DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_MRX_ITX_N0 DMI_MRX_ITX_P0 DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_MRX_ITX_N1 DMI_MRX_ITX_P1 DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_MRX_ITX_N2 DMI_MRX_ITX_P2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_MRX_ITX_N3 DMI_MRX_ITX_P3
<6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6>
<26> PCIE_TX4<26> PCIE_TX4+
WPAN
<26> PCIE_RX4<26> PCIE_RX4+
PCIE_TXN3_C PCIE_TXP3_C
A
Non-iAMT
RP27 OC7# OC9# OC5# OC6# +3.3V_SUS 6 7 8 9 10 10P8R-10K 5 4 3 2 1
+3.3V_SUS
Express Card
PCIE_TXN4_C PCIE_TXP4_C
USB_OC0_1# USB_OC2_3# OC4# USB_OC8#
CLK_PCIE_ICH# <17> CLK_PCIE_ICH <17> 24.9/F 1 <27> <27> <27> <27> <27> <27> <27> <27> <24> <24> <33> <33> <26> <26> <37> <37> <27> <27> <25> <25> +1.5V_PCIE_ICH
DMI_ZCOMP DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBRBIAS# USBRBIAS
Place within 500mils of ICH8
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP SPI_CLK SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISO OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#
SPI
Layout Note: Place R313,R311 and R327 within 500 mils from ICH.
<28> ICH_EC_SPI_CLK
R313 1
2 15
ICH_EC_SPI_CLK_R ICH_SPI_CS# ICH_SPI_CS1#_R ICH_EC_SPI_DO_R USB_OC0_1# USB_OC2_3# OC4# OC5# OC6# OC7# USB_OC8# OC9#
C23 B23 E22 D23 F21 AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18
<28> ICH_EC_SPI_DO <28> ICH_EC_SPI_DIN
R311 1
2 15
<27> USB_OC0_1# +3.3V_ALW 5
B
<27> USB_OC2_3# R327 15
USB
U11 <30> SPI_CS0# R328 1 R93 1 15_NC 2 4 0 2
2 1 7SH08_NC
1
2
ICH_SPI_CS# <27> USB_OC8#
SIO_SPI_CS# <28>
ICH_USBP0ICH_USBP0+ ICH_USBP1ICH_USBP1+ ICH_USBP2ICH_USBP2+ ICH_USBP3ICH_USBP3+ ICH_USBP4ICH_USBP4+ ICH_USBP5ICH_USBP5+ ICH_USBP6ICH_USBP6+ ICH_USBP7ICH_USBP7+ ICH_USBP8ICH_USBP8+ ICH_USBP9ICH_USBP9+
USB[1B] USB[1A] USB[2B] USB[2A] 3rd MINI CARD CAMERA Express Card BT USB[3A] WWAN USB
+3.3V_RUN PCI_SERR# 6 SB_WLAN_PCIE_RST# 7 PCI_TRDY# 8 SB_MCARD3_PCIE_RST#9 10 10P8R-8.2K RP31 PCI_PERR# PCI_IRDY# PCI_PIRQA# PCI_REQ0# 6 7 8 9 10 10P8R-8.2K 5 4 3 2 1 +3.3V_RUN
PCI Pullups
6 7 8 9 10
RP35 5 4 3 2 1 10P8R-8.2K RP34 5 4 3 2 1
+3.3V_RUN
PCI_STOP# PCI_FRAME# PCI_REQ1# +3.3V_RUN PCI_PIRQD# SB_NB_PCIE_RST# PCI_DEVSEL# +3.3V_RUN PCI_PIRQC# PCI_PLOCK# PCI_PIRQB#
B
ICH8M REV 1.0
WWAN Noise - ICH improvements
OC4# OC5# OC6# OC7# OC9# USB_OC8# USB_OC0_1# USB_OC2_3# C876 C871 C872 C873 C878 C874 C875 C877 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V
18
ICH_SPI_CS1#_R PCI_GNT0# 2 2
Boot BIOS Strap GNT0#
R292 1K_NC 1
SPI_CS1# No stuff Stuff No stuff
R304 1K 1
LPC PCI SPI
11 10 01
No stuff No stuff Stuff
1
Short F2 and F3 at the package and keep length to less than 500mils. Trace Impedance should be 60ohms +/- 15%.
2 R301 22.6/F
+3.3V_RUN
35
LOM 1394/MediaCard
REQ0 REQ1
GNT0 GNT1
PIRQB PIRQC PIRQD
Non-iAMT
C84 1 2 0.047U/10V
+3.3V_SUS
Add Buffers as needed for Loading and fanout concerns.
5 2
U10 4 PCI_RST# <20,35>
C
<20,35> PCI_AD[0..31]
U8B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD# ICH8M REV 1.0
PCI
C
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME#
2
A4 D7 E18 C18 B19 F18 A11 C10 C17 E15 F16 E17 C8 D9 G6 D16 A7 B7 F10 C16 C9 A17
PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# SB_WWAN_PCIE_RST# SB_LOM_PCIE_RST#
PCI_REQ0# <35> PCI_GNT0# <35> PCI_REQ1# <20> PCI_GNT1# <20> SB_WWAN_PCIE_RST# SB_LOM_PCIE_RST# PCI_C_BE0# PCI_C_BE1# PCI_C_BE2# PCI_C_BE3# <20,35> <20,35> <20,35> <20,35>
PCI_RST#_G
1 7SH32
<25> SB_NB_PCIE_RST# C357 1 2 R307 1K_NC 1 PCI_PLTRST#
+3.3V_SUS
5 2
0.047U/10V
U28 4 PLTRST# <6,28>
PCI_IRDY# PCI_RST#_G PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
1 7SH32
PCI_IRDY# <20,35> PCI_PAR <20,35> PCI_DEVSEL# <20,35> PCI_PERR# <20,35> PCI_PLOCK# PCI_SERR# <20,35> PCI_STOP# <20,35> PCI_TRDY# <20,35> PCI_FRAME# <20,35> CLK_PCI_ICH <17> ICH_PME# <29>
A16 away override strap. SB_NB_PCIE_RST# Low = A16 swap override enabled. High = Default.
+3.3V_SUS C355 1 2 5 2 2 PCI_PLTRST# 4 1 7SH32 2 1 PLTRST1# <24,25,26> R310 10 0.047U/10V SB_MCARD3_PCIE_RST# R291 SB_WWAN_PCIE_RST# R314 SB_WLAN_PCIE_RST# R300 SB_LOM_PCIE_RST# R324 SB_NB_PCIE_RST# R302 2 2 2 2 2 1 1 1 1 1 20K_NC 20K 20K_NC 20K 20K_NC CLK_PCI_ICH U27
AG24 PCI_PLTRST# B10 CLK_PCI_ICH G7
D
BIOS should not enable the internal GPIO pull up resistor.
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 F8 G11 F12 B3 SB_MCARD3_PCIE_RST# SB_WLAN_PCIE_RST# SB_NB_PCIE_RST# PCIE_MCARD2_DET# SB_MCARD3_PCIE_RST# <24> SB_WLAN_PCIE_RST# <24> SB_NB_PCIE_RST# <6> PCIE_MCARD2_DET# <25> C417 9P/50V
D
<35> PCI_PIRQB# <20> PCI_PIRQC# <20> PCI_PIRQD# PCI_PIRQB: for LOM PCI_PIRQC: for Media Card PCI_PIRQD: for 1394
PCI_PIRQA# F9 PCI_PIRQB# B5 PCI_PIRQC# C5 PCI_PIRQD# A10
Interrupt I/F
1
35
Reserved for EMI. Place resister and cap close to ICH.
DELL CONFIDENTIAL/PROPRIETARY
Title ICH8-M (USB,DMI,PCIE,PCI) Size Date: Document Number M-08 Tuesday, March 06, 2007
7
Rev 0.1 Sheet 12
8
of
51
1
2
3
4
5
6
1
2
3
4
5
6
7
8
GG request
Place these close to ICH7.
ICH_SMBDATA R518 2 ICH_SMBCLK R519 2
A
1 0_NC 1 0_NC
AMT_SMBDAT AMT_SMBCLK
+3.3V_SUS R247 R273 R271 R255 R252 R261 2 2 2 2 2 2 1 1 1 1 1 1
9
Non-iAMT
10/1 TDC request
+3.3V_RUN
CLK_ICH_48M 1
A
+3.3V_SUS RP28
Non-iAMT
U8C 1 2 4 4P2R-2.2K ICH_SMBDATA ICH_SMBCLK <24,25,26> ICH_SMBCLK <24,25,26> ICH_SMBDATA ICH_CL_RST1# T60 PAD T53 PAD ICH_SMBCLK ICH_SMBDATA ICH_CL_RST1# AMT_SMBCLK AMT_SMBDAT ICH_RI# T69 PAD <3,29> ITP_DBRESET# R234 8.2K CLKRUN# <6> PM_BMBUSY# RSVD_LPCPD# AJ26 AD19 AG21 AC17 AE19 AF17 F4 AD15 AG12 LOM_SMB_ALERT# AG22 AE20 AG18 CLKRUN# ICH_PCIE_WAKE# IRQ_SERIRQ RSV_THRM# IMVP_PWRGD T12 PAD AH11 AE17 AF12 AC13 AJ20 AJ22 SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 RI# SUS_STAT#/LPCPD# SYS_RESET# BMBUSY#/GPIO0 SMBALERT#/GPIO11 S4_STATE#/GPIO26 STP_PCI#/GPIO15 STP_CPU#/GPIO25 CLKRUN#/GPIO32 WAKE# SERIRQ THRM# VRMPWRGD TP7 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SPKR MCH_SYNC# TP3 ICH8M REV 1.0 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# AJ12 AJ10 AF11 AG11 AG9 G5 D3 AG23 AF21 AD18 AH27 AE23 AJ14 AE21 C2 AH20 AG27 E1 E3 AJ25 F23 AE18 F22 AF19 D24 AH23 AJ23 AJ27 AJ24 AF22 AG19 PCIE_MCARD3_DET# ME_EC_ALERT WOL_EN R227 2 ICH_CL_PWROK RSV_SIO_SLP_M# RSV_ICH_CL_CLK1 RSV_ICH_CL_DATA1 CL_VREF0 CL_VREF1 ICH_LAN_RST# ICH_RSMRST# ICH_BATLOW# SIO_S4_STATE# ICH_PWRGD DPRSLPVR R270 2 CLK_ICH_14M CLK_ICH_48M ICH_SUSCLK CLK_ICH_14M <17> CLK_ICH_48M <17> R262 8.2K
1 2 CLK_ICH_14M 1 R254 10_NC 1 2 2 C377 4.7P/50V_NC PAD T71 SIO_SLP_S3# <28> PAD T52 SIO_SLP_S5# <28> PAD T49 ICH_PWRGD <6,38> DPRSLPVR <6,45> 8.2K 1 +3.3V_SUS 2 C412 4.7P/50V_NC
1 3
+3.3V_RUN 2
15
<28> LOM_SMB_ALERT# <17> H_STP_PCI# <17> H_STP_CPU#
1
SYS GPIO Power MGT
1
Clocks SATA GPIO
SMB
PWROK DPRSLPVR/GPIO16 BATLOW# PWRBTN# LAN_RST# RSMRST# CK_PWRGD CLPWROK SLP_M#
B
R233 10_NC 2
2
10K_NC ICH_CL_RST1# 10K AMT_SMBCLK 10K AMT_SMBDAT 10K ICH_RI# 10K SIO_EXT_SCI# 1K ICH_PCIE_WAKE#
R297 10_NC
<20,28,35> CLKRUN# <29> ICH_PCIE_WAKE# <20,28> IRQ_SERIRQ T56 PAD <28,38,45> IMVP_PWRGD
B
ICH_PWRGD DPRSLPVR WOL_EN ICH_RSMRST# ICH_LAN_RST#
R260 2 R232 1 R249 1 R21 2
1 10K 2 100K 2 100K 1 10K 1 1M 1 1M 1 10K
Option to " Disable " clkrun. Pulling it down will keep the clks running.
SIO_PWRBTN# <28> ICH_LAN_RST# ICH_RSMRST# <28> CLK_PWRGD <17> ICH_CL_PWROK PAD T9 <6,28>
36
<24> USB_MCARD1_DET#
GPIO MISC Controller Link
T10 <29> SIO_EXT_WAKE# <28> SIO_EXT_SMI# 14<28> SIO_EXT_SCI# <24> PCIE_MCARD1_DET# USB_MCARD1_DET# T81 <25> USB_MCARD2_DET# <24> USB_MCARD3_DET# <23> IDE_RST_MOD# <17> SATA_CLKREQ# <18> PLTRST_DELAY# 30<24> WPAN_RADIO_DIS_MINI# 26 <33> CCD_VDD_ON <32> SPKR <6> MCH_ICH_SYNC# R241 2 <11> ICH_RSVD
35
15
USB_IDE# AJ8 RSVD_GPIO6 AJ9 PAD SIO_EXT_WAKE# AH9 SIO_EXT_SMI# AE16 SIO_EXT_SCI# AC19 PCIE_MCARD1_DET# AG8 R547 1 AH12 2 4.7K AE11 PAD USB_MCARD2_DET# AG10 USB_MCARD3_DET# AH25 AD16 AG13 PLTRST_DELAY# AF9 AJ11 CCD_VDD_ON AD10 SPKR 1 0 MCH_ICH_SYNC#_R AD9 AJ13 AJ21
R246 2 R305 2 R511 2
Non-iAMT
ICH_CL_PWROK PLTRST_DELAY#
CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST# MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9
CL_CLK0 <6> PAD T58 CL_DATA0 <6> PAD T4 PAD T50
9/26 Add PD 10K
ICH_CL_RST0# <6> PCIE_MCARD3_DET# <24> PAD T11 PAD T6 10/1 TDC PAD T55 8.2K 1
C
request
C
R258 2
1 100K_NC CCD_VDD_ON
26
9
+3.3V_SUS
53
+3.3V_SUS +3.3V_RUN R243 2 R510 2 1 10K 1 10K SIO_EXT_SMI# LOM_SMB_ALERT# 2 +3.3V_RUN
Non-iAMT
+3.3V_RUN 2
+3.3V_ALW 2
SMbus address D2
2 4 R267 1K_NC
Non-iAMT
1 CL_VREF0 1 RP16 4P2R-2.2K
R296 3.24K/F 1 CL_VREF1 1 R299 453/F 2 1 C365 0.1U/10V_NC 2
R240 3.24K/F_NC
15
1
+3.3V_RUN R84 1 2.2K_NC IMVP_PWRGD
These are for backdrive issue.
2 SPKR Q8 1 1 3
1
2
C416 0.1U/10V
R239 453/F_NC
No Reboot strap. SPKR Low = Default. High = No Reboot.
<24,25,26> ICH_SMBDATA
2
2N7002W-7-F +3.3V_RUN
+3.3V_RUN
D
R277 R245 R266 R274 R540
2 2 2 2 1
1 1 1 1 2
10K 10K_NC 10K 10K 100K
RSV_THRM# MCH_ICH_SYNC#_R IRQ_SERIRQ RSVD_GPIO6 WPAN_RADIO_DIS_MINI#
+3.3V_RUN <24,25,26> ICH_SMBCLK 2 3
2
Q6 1 2N7002W-7-F
2
3
MEM_SDATA <15>
D
MEM_SCLK <15>
30
1
R25 8.2K USB_IDE#
DELL CONFIDENTIAL/PROPRIETARY
Title ICH8-M (PM,GPIO,SMB,CL) Size Date: Document Number M-08 Tuesday, March 06, 2007
7
9/20 Delete R258
Rev 0.1 Sheet 13
8
of
51
1
2
3
4
5
6
1
2
3
4
5
6
7
8
+RTC_CELL 1 2 2 C374 1U/10V C384 0.1U/10V C380 0.1U/10V U8F AD25 A16 T7 G4 AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 +VCCSATPLL R29 0 1 2 +VCCSATPLL_L L11 10uH/100MA +1.5V_RUN 1 AJ6 AE7 AF7 AG7 AH7 AJ7 AC1 AC2 AC3 AC4 AC5 1 C389 1U/10V AC10 AC9 AA5 AA6 G12 G17 H7 +1.5V_RUN AC7 AD7 D1 VCCRTC V5REF[1] V5REF[2] V5REF_SUS VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCCSATAPLL VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_