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A
B
C
D
E
MYALL2 Block Diagram
CLK GEN. IDT CV125
4
Project Code
TV Out
PCB
4
Intel Mobile CPU Yonah 478 Celeron M
14
91.4G901.001 06203-MP
CRT LCD
3
G792
19
4~5
14
FSB 400/533/667 MHz
DDR II SO-DIMM 1
11 ~ 12 RAM BUS 533/667 MHz
13
CPU DC/DC ISL6262 37 ~ 38
INPUTS OUTPUTS
DDR II SO-DIMM 2
11 ~ 12
3
Calistoga 945PM / 940GML
6 ~ 10 DMI 100 MHz
PEG
Nvidia G72M-V
46 ~ 48 , 51 ~ 55
VRAMx4
49 ~ 50
VCC_CORE DCBATOUT 0.844~1.3V 27A
PCI BUS
TI PCI7412
24 ~ 25
PWR SW CP2211 25
SYSTEM DC/DC PCMCIA SLOT 27 Card Reader26
MAX8744
INPUTS DCBATOUT OUTPUTS
3D3V_S5 5V_S5
35
3
a. Line In b. Mic In c. INT Mic
Codec
ALC883
29 28
HDA
1394
d. Line Out e. INT.SPKR
29
OP AMP G1421B MODEM MDC Card
Intel 82801 GBM ICH7-M Mini-PCI
30
26
APL5331-KAC APL5912-KAC APL5308-25AC 40 INPUTS OUTPUTS
1D5V_S5 1D8V_S3 3D3V_S5 3D3V_S0 1D05V_S0 1D5V_S0 1D5V_S5 2D5V_S0
TV & Video-In WIRELESS TXFM
29
30 30
2
21
PCIE x 1
LAN
RTL8111B
22 ~ 23
23
RJ45
23
APW7057-KC TPS51100DGQ APL5331-KAC 41 INPUTS OUTPUTS
5V_S5 5V_S5 5V_S5 1D8V_S0 3D3V_S5 1D8V_S3 0D9V 1D2V_S0
2
MINI CARD
PCIE x 1
LPC BUS
26 SATA
DEBUG CONN34
15 ~ 18
SIO
NS87381
32
KBC KB3910
31 X BUS
CHARGER ISL6255
INPUTS
42
OUTPUTS
BT+ 16.8V 3A
1
FIR
PCB Layer Stackup
1
32
BIOS
34
Touch INT. KB CIR Pad 33 33 33
DCBATOUT
xa
L1: Signal 1 L2: VCC L3: Signal 2 L4: Signal 3 L5: GND L6: Signal 4
A
PATA
USB
Date: Tuesday, April 11, 2006
B C D
Sheet
E
1
he
MYALL2
in
Size
Document Number
f@
21
13
BLOCK DIAGRAM
ho
Rev
24 ~ 25
20
20
Title
tm
MP
of 57
SATA
HDD
CDROM
MINI USB BlueTooth
USB 4 Port21
CAMERA
ai
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
l.c
om
Wistron Corporation
A
B
ICH7-M EDS 17837 1.5V1
C
D
E
ICH7M Integrated Pull-up and Pull-down Resistors
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#,
954305D 27Mhz/LCDCLK Spread and Frequency Selection Table
SS3 Byte9 bit 7 0 0 0 0 0 SS2 bit6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 bit5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 bit4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Spread Amount% -0.50 Down -1.00 Down -1.50 Down -2.00 Down -0.75 Down -1.25 Down -1.75 Down page 3
Calistoga Strapping Signals and EDS 17050 0.71 Configuration page 7
Pin Name CFG[2:0] Strap Description FSB Frequency Select 001 = FSB533 011 = FSB667 others = Reserved CFG[4:3] CFG5 CFG6 CFG7 CPU Strap Reserved Reserved DMI x2 Select Reserved 0 = Reserved 1 =Mobile CPU(Default) 0 = DMI x2 1 = DMI x4 (Default) Configuration
ICH7 internal 20K pull-ups LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0]
4
LDRQ[0], LDRQ[1]/GPIO[41], PWRBTN#, TP[3] DD[7], DDREQ ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, EE_CS,SPI_ARB, SPI_CLK, SPKR, USB[7:0][P,N] SATALED# LAN_CLK ICH7 internal 15K pull-downs ICH7 internal 11.5K pull-downs
4
0 ICH7 internal 20K pull-downs 0 0 1 1 1 ICH7 internal 15K pull-up ICH7 internal 100K pull-down 1 1 1 1
-2.25 Down +-0.25 Center
CFG8 CFG9 PCI Express Graphics Lane Reversal Reserved XOR/ALL Z test straps 00 = Reserved 01 = XOR mode enabled 10 = All Z mode enabled 11 = Normal Operation (Default) Reserved 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 0 = All R-comp Disable 1 = Normal Operation (Default) 0 = 1.05V (Default) 1 = 1.5V 0 = Normal operation (Default):lane Numbered in order 1 =Reverse Lane,4->0,3->1 ect... 0 = Only SDVO or PCIE x1 is operational (Default) 1 =SDVO and PCIE x1 are operating simultaneously via the PEG port 0 = No SDVO Card present (Default) 1= SDVO Card present 0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order
+-0.5 Center +-0.75 Center CFG[11:10] +-1.0 Center +-0.25 Center +-0.5 Center +-0.75 Center CFG[15:14] CFG[13:12]
3
ICH7M IDE Integrated Series Termination Resistors
DD[15:0], DIOW#, DIOR#, DREQ, approximately 33 ohm DDACK#, IORDY, DA[2:0], DCS1#, DCS3#, IDEIRQ
Reserved FSB Dynamic ODT Global R-comp Disable (All R-comps) VCC Select DMI Lane Reversal
1
+-1.0 Center CFG16
3
PCI Routing
IDSEL 7412 22 21
CFG17 page 16 CFG18
ICH7M Functional Strap Definitions
Signal ACZ_SDOUT Usage/When Sampled XOR Chain Entrance/ PCIE Port Config bit1, Rising Edge of PWROK Comment
page 16
MiniPCI
INT -> PIRQ A->G, B->B, C->F, D->G A/C -> E B/D -> E
REQ/GNT 0 1
CFG19
CFG20
SDVO/PCIE Concurrent SDVO Present
Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h) Sets bit0 of RPC.PC(Config Registers:Offset 224h) This signal should not be pull high. This signal should not be pull low. This signal should not be pull low. Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
SDVOCRTL _DATA
NOTE: All strap signals are sampled with respect to the leading edge of the Calistoga GMCH PWORK in signal.
ACZ_SYNC EE_CS EE_DOUT
PCIE bit0, Rising Edge of PWROK. Reserved Reserved Reserved Top-Block Swap Override. Rising Edge of PWROK.
2
GNT2# GNT3#
2
GNT5#/ GPIO17#, GNT4#/ GPIO48 DPRSLPVR GPIO25 INTVRMEN
Boot BIOS Destination Selection. Rising Edge of PWROK.
Reserved Reserved. Rising Edge of RSMRST#. Integrated VccSus1_05 VRM Enable/Disable. Always sampled. Reserved XOR Chain Selection. Rising Edge of PWROK. Reserved No Reboot. Rising Edge of PWROK.
This signal should not be pull high. This signal should not be pull low. Enables integrated VccSus1_05 VRM when sampled high Requires an external pull-up resistor. TBD, Chapter 8. This signal should not be pull low. If sampled high, the system is strapped to the "No Reboot" mode(ICH7 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit. This signal should not be pull low unless using XOR Chain testing.
LINKALERT# REQ[4:1]#
1
SATALED# SPKR
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number
TP3
XOR Chain Entrance. Rising Edge of PWROK.
Reference MYALL2
Sheet 2 of Rev
MP
57
Date: Friday, March 24, 2006
A
B
C
D
E
3D3V_S0 3D3V_S0 R448 0R0603-PAD 1 2 3D3V_CLKPLL_S0 R204 0R0603-PAD 1 2 R437 0R0603-PAD 2 1
3D3V_S0 C652 SC1U6D3V2ZY-GP
3D3V_48MPWR_S0
3D3V_CLKGEN_S0
1
1
1
1
1
1
1
1
1
1
C647 SCD1U16V2ZY-2GP
C626 SC1U6D3V2ZY-GP
C633 SC4D7U10V5ZY-3GP
C636 SCD1U16V2ZY-2GP
C655 SCD1U16V2ZY-2GP
C654 SCD1U16V2ZY-2GP
C653 SCD1U16V2ZY-2GP
C637 SCD1U16V2ZY-2GP
C625 SCD1U16V2ZY-2GP
1 2
C632 SCD1U16V2ZY-2GP
4
2
2
2
2
2
2
2
2
2
4
3D3V_S0
1
R426 10KR2J-3-GP DREFSSCLK_1 DREFSSCLK#_1 SS_SEL
4 3
1 RN67 2 SRN33J-5-GP-U 1 RN68 2 SRN33J-5-GP-U 2 RN73 1 SRN33J-5-GP-U 2 RN71 1 SRN33J-5-GP-U 1 RN69 2 SRN33J-5-GP-U
DREFSSCLK 7 DREFSSCLK# 7 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 CLK_PCIE_ICH 16 CLK_PCIE_ICH# 16 CLK_PCIE_LAN 22 CLK_PCIE_LAN# 22 CLK_PCIE_SATA 15 CLK_PCIE_SATA# 15
2
1
H/L: 100/96MHz
R427 DY 10KR2J-3-GP 31 PCLK_KBC 25 32 34 30 16 PCLK_PCM PCLK_SIO PCLK_FWH PCLK_MINI CLK_ICHPCI R451 2 R441 2 R432 2 R438 2 R434 2 R205 2 R433 2
U41
CLK_MCH_3GPLL_1 4 CLK_MCH_3GPLL_1# 3
1 33R2J-2-GP 1 1 1 1 1 1
22R2J-2-GP 33R2J-2-GP 22R2J-2-GP 33R2J-2-GP 33R2J-2-GP 10KR2J-3-GP
PCLKCLK0 PCLKCLK2 PCLKCLK3 SS_SEL ITP_EN
56 3 4 5 9 8 55
PCI0 PCI1 PCI2 PCI3 PCIF1/SEL100/96# PCIF0/ITP_EN PCI_STOP# SCL SDA DOT96 DOT96# XTAL_IN XTAL_OUT REF IREF VTT_PWRGD#/PD VSS_PCI VSS_PCI VSS_REF VSS_CPU VSSA VSS48 VSS_SRC
LVDS LVDS# SRC1 SRC1# SRC2 SRC2# SRC3 SRC3# SRC4 SRC4# SRC5 SRC5# SRC6 SRC6# CPU2_ITP/SRC7 CPU2_ITP#/SRC7# CPU0 CPU0# CPU1 CPU1# CPU_STOP# FSC/TEST_SEL FSB/TEST_MODE USB48/FSA VDD_SRC VDD_SRC VDD_PCI VDD_PCI VDD_REF VDD_CPU VDDA VDD48 VDD_SRC
71.00125.A0W
17 18 19 20 22 23 24 25 26 27 31 30 33 32 36 35 44 43 41 40 54 53 16 12 34 21 7 1 48 42 37 11 28
DREFSSCLK_1 DREFSSCLK#_1 CLK_MCH_3GPLL_1 CLK_MCH_3GPLL_1# CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# CLK_PCIE_LAN_1 CLK_PCIE_LAN_1# CLK_PCIE_SATA_1 CLK_PCIE_SATA_1# CLK_PCIE_MINI_12 CLK_PCIE_MINI_12# CLK_PCIE_PEG_1 CLK_PCIE_PEG_1# CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# CLK_MCH_BCLK_1 CLK_MCH_BCLK_1# CPU_SEL2 CPU_SEL1 CLK48 3D3V_CLKGEN_S0
CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# CLK_PCIE_LAN_1 CLK_PCIE_LAN_1# CLK_PCIE_SATA_1 CLK_PCIE_SATA_1#
3 4 3 4 4 3
2
16 PM_STPPCI#
H/L : CPU_ITP/SRC7
46 47
RN66 SRN33J-5-GP-U 1 4 2 3 DREFCLK_1 DREFCLK#_1
3
PCLK_FWH & PCLK_PCM need equal length
11,18 SMBC_ICH 11,18 SMBD_ICH 7 7 DREFCLK DREFCLK#
CLK_PCIE_MINI_12 CLK_PCIE_MINI_12# CLK_PCIE_PEG_1 CLK_PCIE_PEG_1# CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# CLK_MCH_BCLK_1 CLK_MCH_BCLK_1#
3 4 3 4 3 4 3 4
2 RN78 1 SRN33J-5-GP-U 2 RN77 G72 1 SRN33J-5-GP-U 2 RN75 1 SRN33J-5-GP-U 2 RN76 1 SRN33J-5-GP-U
2
CLK_PCIE_MINI2 26 CLK_PCIE_MINI2# 26 CLK_PCIE_PEG 46 CLK_PCIE_PEG# 46 CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 PM_STPCPU# 16 CPU_SEL2 4,7 CPU_SEL1 4,7 CLK48_ICH 16 CLK48_CARDBUS CPU_SEL0 4,7
3
C648 SC27P50V2JN-2-GP 1 2
14 15 50 49 52 39 10 2 6 51 45 38 13 29
When use UMA RN9 DUMMY
C640 SC27P50V2JN-2-GP 1 2
GEN_XTAL_IN GEN_XTAL_OUT_R X4 X-14D31818M-31GP 32 CLK14_SIO 82.30005.831 16 CLK_ICH14
1
R444 2 R452 2 R453 2 R450 2
1 0R0603-PAD 1 22R2J-2-GP 1 22R2J-2-GP 1 475R2F-L1-GP
GEN_XTAL_OUT GEN_REF GEN_IREF
2
37
CLK_EN# 3D3V_S0
2
R435 10KR2J-3-GP 1
R436 22R2J-2-GP 2 R428 22R2J-2-GP 2 R429 2K2R2J-2-GP 2
1 1 1
CPU_SEL0
25
FSC
3D3V_CLKPLL_S0 3D3V_48MPWR_S0 0 0 0 0 1 1 1 1 1D05V_S0
FSB
0 0 1 1 0 0 1 1
FSA
0 1 0 1 0 1 0 1
CPU
266M 133M 200M 166M 333M 100M 400M Reserved
FSB
X 533M X 667M X X X X
2
2
IDTCV125PAG-GP RN63 SRN49D9F-GP 4 3
DREFSSCLK# DREFSSCLK
1 2
2
2
DREFCLK# DREFCLK
1 2
RN62 SRN49D9F-GP 4 3 CPU_SEL0 RN72 SRN49D9F-GP 1 4 2 3 RN65 SRN49D9F-GP 3 4
R573 DY 1K74R2F-GP
R574 DY 1K74R2F-GP
2
R575 DY 1K74R2F-GP CPU_SEL2 R577 DY 1K74R2F-GP
1
1
CPU_SEL1 R576 DY 1K74R2F-GP
CLK_CPU_BCLK CLK_CPU_BCLK#
RN79 SRN49D9F-GP 1 4 2 3 RN80 SRN49D9F-GP 4 3
2
2
CLK_PCIE_LAN CLK_PCIE_LAN#
2
R578 DY 1K74R2F-GP
1
1
PCLK_SIO CLK_ICH14
1
EC50 1 EC55 1 EC46 1 EC51 1 EC53 1 EC45 1 EC47 1
2 SC10P50V2JN-4GP 2 SC10P50V2JN-4GP 2 SC10P50V2JN-4GP 2 SC10P50V2JN-4GP 2 SC10P50V2JN-4GP 2 SC10P50V2JN-4GP 2 SC10P50V2JN-4GP
DY DY DY DY DY DY DY
CLK_MCH_BCLK CLK_MCH_BCLK#
1 2
CLK_PCIE_SATA CLK_PCIE_SATA#
2 1
om
Size Document Number
PCLK_MINI PCLK_PCM PCLK_KBC CLK_ICHPCI CLK48_ICH
1
1
EMI
CLK_MCH_3GPLL CLK_MCH_3GPLL#
2 1
RN64 SRN49D9F-GP 3 4
CLK_PCIE_MINI2 CLK_PCIE_MINI2#
1 2
RN82 SRN49D9F-GP 4 3
he
Clock Generator ICS954305D
Rev
MYALL2
Date: Thursday, March 30, 2006
A B C D
xa
Title
in
f@
ho
CLK_PCIE_PEG CLK_PCIE_PEG#
RN81 G72 SRN49D9F-GP 1 4 2 3
CLK_PCIE_ICH CLK_PCIE_ICH#
RN74 SRN49D9F-GP 1 4 2 3
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
tm
Wistron Corporation
ai
l.c
MP
3 of 57 Sheet
E
A
B
C
D
E
H_DINV#[3..0] H_DSTBN#[3..0] TP24 TPAD30 U34A 6
4
H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] 6
6 6 6
4
1D05V_S0
H_DSTBP#[3..0] H_D#[63..0]
H_A#[31..3]
H_A#[31..3]
CONTROL
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
6 6
H_ADSTB#0 H_REQ#[4..0]
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] RSVD[11]
ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK#
1
R101 56R2J-4-GP
H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 D21 A24 A25 C7
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# H_RS#0 H_RS#1 H_RS#2
H_ADS# H_BNR# H_BPRI#
6 6 6
ADDR GROUP 0 ADDR GROUP 0
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6
2
H_BREQ#0 6 H_IERR# H_INIT# 15 H_LOCK# 6 H_CPURST# 6 H_RS#[2..0]
Place testpoint on H_IERR# with a GND 0.1" away
U34B 6 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
2
3
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 6 H_ADSTB#1 15 H_A20M# 15 H_FERR# 15 H_IGNNE# 15 H_STPCLK# 15 H_INTR 15 H_NMI 15 H_SMI# TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TP34 TP31 TP33 TP32 TP26 TP25 TP28 TP29 TP16 TP13
THERM
Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 A6 A5 C4 D5 C6 B4 A3 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 B25
HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
H_HIT# H_HITM# TP48 TP49 TP43 TP42 TP40 TP41 TP47 TP35 TP39 TP38 TP46 TP10
6 6 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 H_THERMDC
XDP/ITP SIGNALS
1D05V_S0 6 H_DSTBN#0 6 H_DSTBP#0 6 H_DINV#0
2
C160 SC2200P50V2KX-2GP
DATA GRP 2
H_REQ#0 K3 H_REQ#1 H2 H_REQ#2 K2 H_REQ#3 J3 H_REQ#4 L5
RESET# RS[0]# RS[1]# RS[2]# TRDY#
H_TRDY# 6
H_THERMDA
R88 56R2J-4-GP
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26 AD26
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 BSEL[0] BSEL[1] BSEL[2]
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3]
AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R164 1 R172 1 R146 1 R176 1
DATA GRP 0
1
1
H CLK
BCLK[0] BCLK[1] RSVD[12]
A22 A21 T22 D2 F6 D3 C1 AF1 D22 C23 C24
R96 0R0402-PAD 1 2 PM_THRMTRIP-I# 19 CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 TP27 TPAD30 TP17 TPAD30 TP22 TPAD30 TP50 TP21 TP20 TP19 TPAD30 TPAD30 TPAD30 TPAD30 Layout Note: 0.5" max length. R189 2KR2F-3-GP
PM_THRMTRIP# should connect to ICH7 and Calistoga without T-ing ( No stub)
1D05V_S0
RESERVED
1
2
SC1KP16V2KX-GP 2 1
TPAD30
RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20]
R188 1KR2F-3-GP
6 6 6
H_DSTBN#1 H_DSTBP#1 H_DINV#1
1 2
CPU_GTLREF0 C258 R381 2 1TEST1 1KR2J-1-GP 1 2TEST2 R384 51R2F-2-GP CPU_SEL0 CPU_SEL1 CPU_SEL2
DATA GRP 3
2nd source: 62.10053.401
2
BGA479-SKT6-GPU1 62.10079.001
XDP_TDI R184 XDP_TMS XDP_TDO H_CPURST#
1
XDP_DBRESET# R90 XDP_TCK XDP_TRST#
ADDR GROUP 1 ADDR GROUP 1
3
PROCHOT# THERMDA THERMDC
CPU_PROCHOT# 37 H_THERMDA 19 H_THERMDC 19 PM_THRMTRIP-A# 7
THERMTRIP#
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
MISC
DATA GRP 1
C26 D25 B22 B23 C21
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
2
3,7 3,7 3,7
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
H_DPRSLP# 15,37 H_DPSLP# 15 H_DPWR# 6 H_PWRGD 15,19 H_CPUSLP# 6,15 PSI# 37 Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .
BGA479-SKT6-GPU1 1D05V_S0
1 1
R186 R185 1 R98
DY DY
150R2F-1-GP 2 39D2R3F-2-GP 2 54D9R2F-L1-GP
2
1
2 54D9R2F-L1-GP
3D3V_S0
1
2 150R2F-1-GP
1
1 R200 R201 1
2 27D4R2F-L1-GP 2 680R3F-GP
Title
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
All place within 2" to CPU
CPU (1 of 2)
Size Document Number Rev
MYALL2
Date: Thursday, March 30, 2006
A B C D
MP
4 of 57
Sheet
E
A
B
C
D
E
VCC_CORE_S0 VCC_CORE_S0
4
U34D
U34C
3
2
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26
CPU_V6
Layout Note 1D05V_S0
1 R170 2 0R0402-PAD 1
C245 SCD1U10V2KX-4GP
1D5V_VCCA_S0 L26
1D5V_S0 1D05V_S0
H_VID[6..0]
AD6 AF5 AE5 AF4 AE3 AF2 AE2 AF7 AE7
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
H_VID[6..0]
37
C553
SCD01U16V2KX-3GP VCC_CORE_S0
2
2
1 2 HCB1608KF121T30-GP 68.00230.041 C554 SC4D7U6D3V3KX-GP
C188 SCD1U10V2KX-4GP
C216 SCD1U10V2KX-4GP
C231 SCD1U10V2KX-4GP
C209 SCD1U10V2KX-4GP
C217 SCD1U10V2KX-4GP
C233 SCD1U10V2KX-4GP
C237 SC4D7U6D3V3KX-GP
C243 SC4D7U6D3V3KX-GP
R198 100R2F-L1-GP-U VCC_SENSE 37 VSS_SENSE 37
VCC_CORE_S0
BGA479-SKT6-GPU1
Layout Note:
1
1
1
1
1
1
C184 SCD1U10V2KX-4GP
C246 SCD1U10V2KX-4GP
C183 SCD1U10V2KX-4GP
C255 SCD1U10V2KX-4GP
C239 SC10U10V5ZY-1GP
C267 SC10U10V5ZY-1GP
1
R199 100R2F-L1-GP-U
VCCSENSE and VSSSENSE lines should be of equal length.
DY
C145 SC10U10V5ZY-1GP
Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.
1
A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24
4
3
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
BGA479-SKT6-GPU1
om
VCC_CORE_S0
1
CPU (2 of 2)
Size Document Number
he
xa
Title
in
f@
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ho
C192 SC10U10V5ZY-1GP
C189 SC10U10V5ZY-1GP
C146 SC10U10V5ZY-1GP
C268 SC10U10V5ZY-1GP
C266 SC10U10V5ZY-1GP SC10U10V5ZY-1GP
C147 SC10U10V5ZY-1GP
C585 SC10U10V5ZY-1GP
C269 SC10U10V5ZY-1GP
C559 SC10U10V5ZY-1GP
C148 SC10U10V5ZY-1GP SC10U10V5ZY-1GP
C190 SC10U10V5ZY-1GP
C191 SC10U10V5ZY-1GP
C242 SC10U10V5ZY-1GP
C241 SC10U10V5ZY-1GP
C240 SC10U10V5ZY-1GP SC10U10V5ZY-1GP
tm
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DY
DY
DY
DY
Wistron Corporation
ai
57
l.c
Rev
MYALL2
Date: Thursday, March 30, 2006
D
MP
5 of
Sheet
E
A
B
C
A
B
C
D
E
H_XRCOMP
1
R416 24D9R2F-L-GP 4 H_D#[63..0] H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING 3 CLK_MCH_BCLK 3 CLK_MCH_BCLK# U39A H_A#[31..3]
4
1D05V_S0
R415 54D9R2F-L1-GP
H_XSCOMP
1D05V_S0
R180 221R2F-2-GP
H_XSWING R183 100R2F-L1-GP-U
1
C249 SCD1U16V2ZY-2GP
H_VREF
H_YRCOMP
H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4 H_DBSY# 4 H_DEFER# 4 H_DPWR# 4 H_DRDY# 4 H_DINV#[3..0] H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#[3..0] H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#[3..0] H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
2
HOST
2
1
R192 200R2F-L-GP C262 SCD1U16V2ZY-2GP
R442 24D9R2F-L-GP
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_HIT# H_HITM# H_LOCK#
J7 W8 U3 AB10 K4 T7 Y5 AC4 K3 T6 AA5 AC5 D3 D4 B3
H_DINV#[3..0]
4
1
H_DSTBN#[3..0]
4
2
H_DSTBP#[3..0]
4
1D05V_S0
2
2
2
1
2
3
R430 54D9R2F-L1-GP
1
F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 E1 E2 E4 Y1 U1 W1 AG2 AG1
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING H_CLKIN H_CLKIN#
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF_0 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF_1
H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4
H_A#[31..3]
4
4
1
1
2
2
1D05V_S0
2
1
R196 100R2F-L1-GP-U
3
1
2
H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_REQ#[4..0] 4
2
H_YSCOMP
1D05V_S0
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_SLPCPU# H_TRDY#
D8 G8 B8 F8 A8 B4 E6 D6 E3 E7
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# 4,15 H_TRDY# 4
H_RS#[2..0]
4
1
R431 221R2F-2-GP
2
H_YSWING R440 100R2F-L1-GP-U
1
2
CALISTOGA C627 SCD1U16V2ZY-2GP
KI.94501.006
1
Place them near to the chip ( < 0.5")
2
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number
GMCH (1 of 5) MYALL2
Sheet
E
Rev
MP
6 of 57
Date: Thursday, March 30, 2006
A B C D
A
B
C
D
E
U39B 11 11 11 11 11 11 11 11
4
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# M_OCDCOMP0 M_OCDCOMP1
AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21 AL20 AF10 BA13 BA12 AY20 AU21
M_RCOMPN M_RCOMPP
SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3 SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_OCDCOMP_0 SM_OCDCOMP_1 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP# SM_RCOMP SM_VREF_0 SM_VREF_1 G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
11,12 11,12 11,12 11,12 11,12 11,12 11,12 11,12
RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN# SDVO_CTRLCLK SDVO_CTRLDATA LT_RESET# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18
KI.94501.006 CFG18 CFG19 CFG20 CFG3 CFG4
H32 T32 R32 F3 F7 AG11 AF11 H7 J19 K30 J29 A41 A35 A34 D28 D27 K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
for calistoga configuration
U39C TP36 31 BL_ON TPAD30 BL_ON LCTLA_CLK LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID LIBG L_LVBG GMCH_LCDVDD_ON
RSVD RSVD MUXING
13 CLK_DDC_EDID 13 DAT_DDC_EDID TPAD30 TP30 TPAD30 TP37 13 GMCH_LCDVDD_ON CPU_SEL0 3,4 CPU_SEL1 3,4 CPU_SEL2 3,4
D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 A33 A32 E27 E26 C37 B35 A37
L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LA_CLK# LA_CLK LB_CLK# LB_CLK
EXP_A_COMPI EXP_A_COMPO EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15 EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15 EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15 EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15
KI.94501.006 RN58 G72 SRN0J-6-GP 2 3 1 4 R408 G72 0R2J-2-GP 1 2 R195 G72 0R2J-2-GP 1 2 R409 G72 0R2J-2-GP 1 2 RN59 G72 SRN0J-6-GP 4 3
D40 D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40
R419 24D9R2F-L-GP 2 1 1D5V_PCIE_S0 PEG_RXN[15..0] PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP[15..0] PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 GTXN0 GTXN1 GTXN2 GTXN3 GTXN4 GTXN5 GTXN6 GTXN7 GTXN8 GTXN9 GTXN10 GTXN11 GTXN12 GTXN13 GTXN14 GTXN15 GTXP0 GTXP1 GTXP2 GTXP3 GTXP4 GTXP5 GTXP6 GTXP7 GTXP8 GTXP9 GTXP10 GTXP11 GTXP12 GTXP13 GTXP14 GTXP15 PEG_RXN[15..0] 46
4
R214DY R209 DY 11,12 M_ODT0 40D2R2F-GP 40D2R2F-GP 11,12 M_ODT1 11,12 M_ODT2 11,12 M_ODT3
DDR_VREF_S3
AV9 AT9 AK1 AK41 AF33 AG33 A27 A26 C40 D41 AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 AE37 AF41 AG37 AH41 AC37 AE41 AF37 AG41
1
C298 SCD1U16V2ZY-2GP
1
C649 SCD1U16V2ZY-2GP
13 GMCH_TXAOUT0+ 13 GMCH_TXAOUT1+ 13 GMCH_TXAOUT2+ 13 GMCH_TXBOUT013 GMCH_TXBOUT113 GMCH_TXBOUT2-
B37 B34 A36 G30 D30 F29
LA_DATA_0 LA_DATA_1 LA_DATA_2 LB_DATA#_0 LB_DATA#_1 LB_DATA#_2
CLK
3
3 CLK_MCH_3GPLL# 3 CLK_MCH_3GPLL 3 DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DREFCLK# DREFCLK DREFSSCLK# DREFSSCLK DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
PCI-EXPRESS
G28 PM_BMBUSY# 16 F25 PM_EXTTS#0 13 GMCH_TXBOUT0+ R2130R2J-2-GP DY H26 PM_EXTTS#1 13 GMCH_TXBOUT1+ G6 PM_THRMTRIP-A# 4 13 GMCH_TXBOUT2+ AH33 1 2 VGATE_PWRGD 16,37 R215 0R2J-2-GP AH34 1 2 R212 1 2 PWROK 16,19 100R2J-2-GP PLT_RST1# 16,18,22,26,31,32,34,46,51 TV_DACA TP45 TPAD30 H28 14 TV_DACA TV_DACB TP44 TPAD30 H27 14 TV_DACB TV_DACC K28 MCH_ICH_SYNC# 16 14 TV_DACC D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 3D3V_S0 B41 RN10 DY B2 SRN10KJ-5-GP AY41 AY1 4 1 AW41 3 2 AW1 A40 A4 14 GMCH_DDCCLK A39 14 GMCH_DDCDATA A3
R389 4K99R2F-L-GP R385 0R2J-2-GP R106 0R2J-2-GP R108 0R2J-2-GP
GRAPHICS
CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
13 13 13 13
GMCH_TXACLKGMCH_TXACLK+ GMCH_TXBCLKGMCH_TXBCLK+
1
1
LVDS LVDS
13 GMCH_TXAOUT013 GMCH_TXAOUT113 GMCH_TXAOUT2-
LA_DATA#_0 LA_DATA#_1 LA_DATA#_2
PEG_RXP[15..0] 46
CFG CFG
2
2
2
2
DDR
F30 D29 F28
LB_DATA_0 LB_DATA_1 LB_DATA_2
3
PM PM
MISC MISC
PEG_TXN[15..0]
A16 C18 A19 J20 B16 B18 B19
TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC
UMA 1 UMA 1 UMA 1 UMA 1
2 2 2 2
TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C248SCD1U10V2KX-5GP C610SCD1U10V2KX-5GP C254SCD1U10V2KX-5GP C615SCD1U10V2KX-5GP C259SCD1U10V2KX-5GP C618SCD1U10V2KX-5GP C263SCD1U10V2KX-5GP C620SCD1U10V2KX-5GP C272SCD1U10V2KX-5GP C622SCD1U10V2KX-5GP C278SCD1U10V2KX-5GP C628SCD1U10V2KX-5GP C281SCD1U10V2KX-5GP C631SCD1U10V2KX-5GP C286SCD1U10V2KX-5GP C638SCD1U10V2KX-5GP C251SCD1U10V2KX-5GP C608SCD1U10V2KX-5GP C253SCD1U10V2KX-5GP C612SCD1U10V2KX-5GP C257SCD1U10V2KX-5GP C617SCD1U10V2KX-5GP C261SCD1U10V2KX-5GP C619SCD1U10V2KX-5GP C271SCD1U10V2KX-5GP C621SCD1U10V2KX-5GP C275SCD1U10V2KX-5GP C624SCD1U10V2KX-5GP C279SCD1U10V2KX-5GP C630SCD1U10V2KX-5GP C283SCD1U10V2KX-5GP C635SCD1U10V2KX-5GP
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP[15..0] PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
PEG_TXN[15..0] 46
TV TV
NC NC DMI
14
GMCH_BLUE
3D3V_S0
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
14 GMCH_GREEN 14 GMCH_RED
GMCH_BLUE GMCH_BLUE# GMCH_GREEN GMCH_GREEN# GMCH_RED GMCH_RED# GMCH_DDCCLK GMCH_DDCDATA GMCH_HS CRT_IREF GMCH_VS
E23 D23 C22 B22 A21 B21 C26 C25 G23 J22 H23
PEG_TXP[15..0] 46
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC
VGA VGA
2
RN17
1 2
1D8V_S3
4 3
PM_EXTTS#0 PM_EXTTS#1 CALISTOGA 3D3V_S0 1
2
SRN10KJ-5-GP
1
2 R163DUMMY-R2 2 R161DUMMY-R2 2 R162DUMMY-R2 2 R157DUMMY-R2 2 R178DUMMY-R2 2 R187DUMMY-R2 2 R158DUMMY-R2 2 R156DUMMY-R2 2 R166DUMMY-R2 2 R179DUMMY-R2 2 R168DUMMY-R2 2 R167DUMMY-R2 2 R193DUMMY-R2 2 R203DUMMY-R2 2 R165DUMMY-R2 2 R202DUMMY-R2 2 R159DUMMY-R2 2 R197DUMMY-R2
14 GMCH_HSYNC 14 GMCH_VSYNC
R216 80D6R2F-L-GP
1 1 1
R107 UMA 0R2J-2-GP 1 2 GMCH_HS R109 UMA 0R2J-2-GP 1 2 GMCH_VS
CALISTOGA
2
M_RCOMPN M_RCOMPP R217 80D6R2F-L-GP
RN18 UMA SRN100KJ-6-GP 1D05V_S0 BL_ON 2 GMCH_LCDVDD_ON 1 R181 UMA 1K5R2F-2-GP 1 2 RN11 G72 SRN0J-6-GP 2 3 1 4
1
1 1 1
GMCH_RED# CFG5 CFG6 GMCH_BLUE CFG7 CFG8 CFG9 CFG10 GMCH_RED CFG11 CFG12 TV_DACA CFG13 CFG14 TV_DACB CFG15 CFG16 TV_DACC CFG17 R148 UMA 150R2F-1-GP 1 2
R152 0R2J-2-GP G72 1 2
GMCH_BLUE GMCH_GREEN
3 4
2
R151 0R2J-2-GP G72 GMCH_GREEN# 1 2 R149 0R2J-2-GP G72 1 2 R147 0R2J-2-GP UMA 1 2
LCTLA_CLK LCTLB_DATA
GMCH_RED 1D05V_S0 CRT_IREF
3 4
RN9 UMA SRN10KJ-5-GP 2 1
3D3V_S0
1 1
LIBG
R154 UMA 150R2F-1-GP GMCH_GREEN 1 2 R153 UMA 150R2F-1-GP 1 2 R413 UMA 150R2F-1-GP 1 2 R400 UMA 150R2F-1-GP 1 2 R398 UMA 150R2F-1-GP 1 2
CLK_DDC_EDID DAT_DDC_EDID
GMCH_BLUE#
RN16 UMA SRN10KJ-5-GP 3 2 4 1
When High 1K Ohm
1 1 1
TV_DACC
GMCH_VS GMCH_HS
GMCH_RED#
1
CFG6:
1
0=Moby Dick ,1=Calistoga (default)
1 1
R155 0R2J-2-GP UMA GMCH_GREEN# 1 2 R150 0R2J-2-GP UMA 1 2 R191 255R2F-L-GP UMA 1 2
TV_DACA TV_DACB
1 2
1D5V_S0
1
GMCH_BLUE#
TV_IREF TV_IRTNA
When Low choice lower than 3.5K Ohm
RN49 G72 SRN0J-6-GP 1 4 2 3 RN8 G72 SRN0J-6-GP 1 4 2 3 Title
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1 1 1
CRT_IREF
TV_IRTNB TV_IRTNC
GMCH (2 of 5)
Size Document Number Rev
MYALL2
Date: Thursday, March 30, 2006
A B C D E
MP
7 of 57
Sheet
he
xa
in
f@
ho
tm
ai
l.c
om
A
B
C
D
E
4
4
11 M_B_DQ[63..0] 11 M_A_DQ[63..0] M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 U39D
M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
U39E
3
2
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
CALISTOGA
SA_BS_0 SA_BS_1 SA_BS_2 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AU12 AV14 BA20 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 AW14 AK23 AK24 AY14
M_A_DM[7..0] M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS[7..0] M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 SA_RCVENIN# SA_RCVENOUT# TP54 TPAD30 TP53 TPAD30
M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12 M_A_CAS# 11,12 M_A_DM[7..0] 11
M_A_DQS[7..0] 11
M_A_A[13..0] 11,12
DDR
DDR
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#
SYSTEM
SYSTEM
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
M_A_DQS#[7..0]
M_A_DQS#[7..0] 11
M_A_A[13..0]
M_A_RAS# 11,12 M_A_WE# 11,12
Place Test PAD Near to Chip as could as possible
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
CALISTOGA
SB_BS_0 SB_BS_1 SB_BS_2 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AT24 AV23 AY28 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 AU23 AK16 AK18 AR27
M_B_DM[7..0] M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS[7..0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 SB_RCVENIN# SB_RCVENOUT#
M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12 M_B_CAS# 11,12 M_B_DM[7..0] 11
M_B_DQS[7..0] 11
B MEMORY
MEMORY
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#
A
3
M_B_DQS#[7..0]
M_B_DQS#[7..0] 11
M_B_A[13..0]
M_B_A[13..0] 11,12
M_B_RAS# 11,12 TP52 TPAD30 TP51 TPAD30 M_B_WE# 11,12
2
Place Test PAD Near to Chip ascould as possible
KI.94501.006
KI.94501.006
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GMCH (3 of 5)
Size Document Number Rev
MYALL2
Date: Thursday, March 30, 2006
A B C D
MP
8 of 57
Sheet
E
A
B
C
D
E
2D5V_S0
2D5V_S0
1
C588 SC4D7U6D3V3KX-GP
1
VCC_TXLVD
1
1 2 2 2 2
C591 SCD1U10V2KX-4GP R414 0R3-0-U-GP R190G72 0R2J-2-GP 1 2 R402 0R3-0-U-GP
UMA
1
UMA
U39H 1D05V_S0
2D5V_3GBG_S0
4
2D5V_S0
R410 0R0603-PAD 2 1
1
SC4D7U6D3V3KX-GP 2 1
SC4D7U6D3V3KX-GP 2 1
SC4D7U6D3V3KX-GP 2 1
2
C297
C294
SCD1U10V2KX-4GP 2 1
C592 SCD1U10V2KX-4GP
1D5V_S0
1D5V_PCIE_S0 R211 0R0805-PAD 1 2 C291
C289
1D5V_S0
R208 0R0603-PAD 1D5V_3GPLL_S0 2 1
1
C285 SC4D7U6D3V3KX-GP
2
2
C284
1
2D5V_3GBG_S0
AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41 F21 E21 G21
VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS VCCA_MPLL VCCA_TVBG VSSA_TVBG
2
VCCA_CRTDAC
SCD1U10V2KX-4GP 1D5V_DPLLA 1D5V_DPLLB 1D5V_HPLL_S0
2D5V_S0 1D5V_S0 L29
R613 UMA 0R3-0-U-GP 1 2 R401 G72 0R2J-2-GP 2 1 1D5V_S0
B26 C39 AF1
UMA
1 1
3
1 2 HCB1608KF121T30-GP 68.00230.041 2
1D5V_DPLLA C596 SC10U10V5ZY-1GP C597 SCD1U10V2KX-4GP
A38 R182 2 1 0R2J-2-GP UMA B39 C595UMA SCD1U10V2KX-4GP R138G72 1D5V_MPLL_S0 AF2 0R2J-2-GP H20 1 2 V_TVBG G20
L30
RN14 G72 SRN0J-6-GP 1 4 2 3 R134 1
2
1
2
C280 SCD1U10V2KX-4GP
C274 C288 SC2D2U6D3V3MX-1-GP SC4D7U10V5ZY-3GP
1
1
C260 UMA SCD1U10V2KX-4GP R403G72 1 0R3-0-U-GP VCC_TXLVD 2
H22 C30 B30 A30
VCCSYNC VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2 VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76
2
V_DACA V_DACB
UMA
1 1
1 2 HCB1608KF121T30-GP 68.00230.041 2
1D5V_DPLLB
2 0R2J-2-GP
1D5V_S0 R404 G72 0R3-0-U-GP 1
G72
V_DACC
2
C599 SC10U10V5ZY-1GP
C598 SCD1U10V2KX-4GP
E19 F19 C20 D20 E20 F20 AH1 AH2
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCD_TVDAC VCC_HV0 VCC_HV1 VCC_HV2 VCCD_QTVDAC VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
CALISTOGA
POWER
L38
1 2 HCB1608KF121T30-GP 68.00230.041 1
C644
1D5V_HPLL_S0
2
1
2
C643 R177 0R0603-PAD 2 1 1D5V_S0
1 R405 0R3-0-U-GP UMA
1D5V_TVDAC_S0 C247 SCD1U10V2KX-4GP
A28 B28 C28 D21 A23 B23 B25 H19
L34 1D5V_MPLL_S0 1 2 HCB1608KF121T30-GP SC10U10V5ZY-1GP SCD1U10V2KX-4GP 68.00230.041 C641 C639 SC10U10V5ZY-1GP SCD1U10V2KX-4GP
R406 0R0603-PAD 2 1 3D3V_S0
C587 SC10U10V5ZY-1GP
C593 SCD1U10V2KX-4GP
2
D9 UMA BAT54-4-GP 1D5V_S0
1 1 3 2
1D5V_S0
R194 0R0603-PAD 2 1
1D5V_QTVDAC_S0
C256 SCD1U10V2KX-4GP
R118 10R2J-2-GP
UMA
2
L14 UMA 2D5V_CRTDAC R133 UMA HCB1608KF121T30-GP 0R5J-6-GP 1 2 2 1 68.00230.041 VCCA_CRTDAC R132 G72 0R3-0-U-GP 1 2
2D5V_S0
1D5V_S0
C252 SCD1U10V2KX-4GP
1D5V_S0
D10 UMA BAT54-4-GP 1
2 1 3
3D3V_TVDAC R119 10R2J-2-GP
R130 UMA 0R3-0-U-GP V_DACA 1
1D5V_S0
2
1
R131 UMA 0R3-0-U-GP V_DACB 2 1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
UMA
2
L12 UMA HCB1608KF121T30-GP 1 2 68.00230.041 R129 UMA 0R3-0-U-GP V_DACC 2 1
om
KI.94501.006 Size Document Number
C228
C227 SCD1U10V2KX-4GP
C290
C293
C296
C292
SCD1U10V2KX-4GP
2
2
2
2
2
2
2
2
SC10U10V5ZY-1GP
he
C229 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
GMCH (4 of 5) MYALL2
Date: Friday, March 24, 2006 Sheet
E
xa
1
C214
Title
in
1
R128 0R3-0-U-GP UMA V_TVBG 2 1
C226
f@
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ho
3D3V_S0
Wistron Corporation
tm
2
Divide by Trace (Layout Rule approve)
UMA
ai
SCD1U10V2KX-4GP
AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12
AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
2
4
3
2
2
1
2
2
1
2
1
1
1
1 2
C600 SCD47U10V3ZY-GP
2
VCCP_GMCH_CAP3
2
2
1
2
1
2
1
2
1
1
1
1
1
1
2
C634 SCD47U10V3ZY-GP
1
C250 SCD22U16V3ZY-GP
VCCP_GMCH_CAP2 VCCP_GMCH_CAP1
1
l.c
Rev
MP
9 of 57
A
B
C
D
A
B
C
D
E
1D05V_S0
U39G
4
3
2
1
SCD1U10V2KX-4GP 2 1
SCD1U10V2KX-4GP 2 1
SCD1U10V2KX-4GP 2 1
SCD1U10V2KX-4GP 2 1
SCD1U16V2ZY-2GP 2 1
SCD1U16V2ZY-2GP 2 1
SCD1U16V2ZY-2GP 2 1
SCD1U10V2KX-4GP 2 1
C680
C299
C679
C302
C303
C301
C304
C677
SCD1U16V2ZY-2GP 2 1
AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110
VCC
VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107
AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1
AC41 AA41 W41 T41 VCC_NCTF0 P41 VCC_NCTF1 VSS_NCTF0 AE27 M41 VCC_NCTF2 VSS_NCTF1 AE26 J41 VCC_NCTF3 VSS_NCTF2 AE25 F41 VCC_NCTF4 VSS_NCTF3 AE24 AV40 VCC_NCTF5 VSS_NCTF4 AE23 AP40 VCC_NCTF6 VSS_NCTF5 AE22 AN40 VCC_NCTF7 VSS_NCTF6 AE21 AK40 VCC_NCTF8 VSS_NCTF7 AE20 AJ40 VCC_NCTF9 VSS_NCTF8 AE19 AH40 VCC_NCTF10 VSS_NCTF9 AE18 AG40 VCC_NCTF11 VSS_NCTF10 AC17 Y17 AF40 VCC_NCTF12 VSS_NCTF11 AE40 VCC_NCTF13 VSS_NCTF12 U17 B40 VCC_NCTF14 AY39 VCC_NCTF15 AW39 VCC_NCTF16 AV39 VCC_NCTF17 AR39 VCC_NCTF18 AN39 VCC_NCTF19 VCCAUX_NCTF0 AG27 AJ39 1D5V_S0 VCC_NCTF20 VCCAUX_NCTF1 AF27 AC39 VCC_NCTF21 VCCAUX_NCTF2 AG26 AB39 VCC_NCTF22 VCCAUX_NCTF3 AF26 AG25 AA39 VCC_NCTF23 VCCAUX_NCTF4 Y39 VCC_NCTF24 VCCAUX_NCTF5 AF25 W39 VCC_NCTF25 VCCAUX_NCTF6 AG24 V39 VCC_NCTF26 VCCAUX_NCTF7 AF24 AG23 T39 VCC_NCTF27 VCCAUX_NCTF8 R39 VCC_NCTF28 VCCAUX_NCTF9 AF23 P39 VCC_NCTF29 VCCAUX_NCTF10 AG22 N39 VCC_NCTF30 VCCAUX_NCTF11 AF22 M39 VCC_NCTF31 VCCAUX_NCTF12 AG21 L39 VCC_NCTF32 VCCAUX_NCTF13 AF21 J39 VCC_NCTF33 VCCAUX_NCTF14 AG20 H39 VCC_NCTF34 VCCAUX_NCTF15 AF20 AG19 G39 VCC_NCTF35 VCCAUX_NCTF16 F39 VCC_NCTF36 VCCAUX_NCTF17 AF19 D39 VCC_NCTF37 VCCAUX_NCTF18 R19 AT38 VCC_NCTF38 VCCAUX_NCTF19 AG18 AF18 AM38 VCC_NCTF39 VCCAUX_NCTF20 AH38 VCC_NCTF40 VCCAUX_NCTF21 R18 AG38 VCC_NCTF41 VCCAUX_NCTF22 AG17 AF38 VCC_NCTF42 VCCAUX_NCTF23 AF17 AE17 AE38 VCC_NCTF43 VCCAUX_NCTF24 C38 VCC_NCTF44 VCCAUX_NCTF25 AD17 AK37 VCC_NCTF45 VCCAUX_NCTF26 AB17 AH37 VCC_NCTF46 VCCAUX_NCTF27 AA17 AB37 VCC_NCTF47 VCCAUX_NCTF28 W17 AA37 VCC_NCTF48 VCCAUX_NCTF29 V17 Y37 VCC_NCTF49 VCCAUX_NCTF30 T17 R17 W37 VCC_NCTF50 VCCAUX_NCTF31 V37 VCC_NCTF51 VCCAUX_NCTF32 AG16 T37 VCC_NCTF52 VCCAUX_NCTF33 AF16 R37 VCC_NCTF53 VCCAUX_NCTF34 AE16 P37 VCC_NCTF54 VCCAUX_NCTF35 AD16 N37 VCC_NCTF55 VCCAUX_NCTF36 AC16 M37 VCC_NCTF56 VCCAUX_NCTF37 AB16 L37 VCC_NCTF57 VCCAUX_NCTF38 AA16 Y16 J37 VCC_NCTF58 VCCAUX_NCTF39 H37 VCC_NCTF59 VCCAUX_NCTF40 W16 G37 VCC_NCTF60 VCCAUX_NCTF41 V16 F37 VCC_NCTF61 VCCAUX_NCTF42 U16 D37 VCC_NCTF62 VCCAUX_NCTF43 T16 AY36 VCC_NCTF63 VCCAUX_NCTF44 R16 AW36 VCC_NCTF64 VCCAUX_NCTF45 AG15 AN36 VCC_NCTF65 VCCAUX_NCTF46 AF15 AH36 VCC_NCTF66 VCCAUX_NCTF47 AE15 AG36 VCC_NCTF67 VCCAUX_NCTF48 AD15 AC15 AF36 VCC_NCTF68 VCCAUX_NCTF49 AE36 VCC_NCTF69 VCCAUX_NCTF50 AB15 AC36 VCC_NCTF70 VCCAUX_NCTF51 AA15 C36 VCC_NCTF71 VCCAUX_NCTF52 Y15 B36 VCC_NCTF72 VCCAUX_NCTF53 W15 BA35 VCCAUX_NCTF54 V15 AV35 VCCAUX_NCTF55 U15 AR35 VCCAUX_NCTF56 T15 AH35 VCCAUX_NCTF57 R15 AB35 CALISTOGA KI.94501.006 AA35 Y35 W35 V35 T35 R35 P35 N35 C273 C276 C265 C287 C264 C270 C282 TC13 M35 ST220U2VBM-3GP SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP L35 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP J35 H35 G35 Place these Caps close VCC_0 ~ VCC_110 F35 D35 AN34 1D8V_S3
U39F
1D05V_S0
U39I
AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18
NCTF
VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96
CALISTOGA
VSS
VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179
AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23
U39J
AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11
VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272
CALISTOGA
VSS
VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360
J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
4
3
2
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
KI.94501.006
KI.94501.006 C295
1
ST220U2VBM-3GP 2 1
SC10U10V5ZY-1GP 2 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
TC5
DY
C678
DY
GMCH (5 of 5)
Size Document Number Rev
CALISTOGA KI.94501.006
B
MYALL2
Date: Friday, March 24, 2006 Sheet
E
MP
10 of 57
A
C
D
A
B
C
D
E
DM2 8,12 M_B_A[13..0] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13
8,12 M_A_A[13..0]
DM1 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13
4
8,12 8,12 8,12
M_B_BS#2 M_B_BS#0 M_B_BS#1 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 1 2 202
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 OTD0 OTD1 VREF VSS GND MH1
DDR2-200P-23-GP
RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GND MH2
108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 201 MH2 1
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SMBD_ICH_1 SMBC_ICH_1
M_B_RAS# 8,12 M_B_WE# 8,12 M_B_CAS# 8,12 M_CS2# 7,12 M_CS3# 7,12 M_CKE2 7,12 M_CKE3 7,12 M_CLK_DDR3 7 M_CLK_DDR#3 7 M_CLK_DDR2 7 M_CLK_DDR#2 7 M_B_DM[7..0] 8
8,12 8,12 8,12
M_A_BS#2 M_A_BS#0 M_A_BS#1 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 1 2 202
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF VSS GND
DDR2-200P-2-GP
/RAS /WE /CAS /CS0 /CS1 CKE0 CKE1 CK0 /CK0 CK1 /CK1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GND
108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 201
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SMBD_ICH_1 SMBC_ICH_1 3D3V_S0
M_A_RAS# 8,12 M_A_WE# 8,12 M_A_CAS# 8,12 M_CS0# 7,12 M_CS1# 7,12 M_CKE0 7,12 M_CKE1 7,12 M_CLK_DDR0 7 M_CLK_DDR#0 7 M_CLK_DDR1 7 M_CLK_DDR#1 7 M_A_DM[7..0]
4
8
8 M_A_DQ[63..0] SRN33J-5-GP-U RN20
8 M_B_DQ[63..0]
1 2
4 3
3D3V_S0
SMBD_ICH 3,18 SMBC_ICH 3,18
R251 10KR2J-3-GP 2 3D3V_S0
3
3
1D8V_S3
1D8V_S3
2
2
8 M_A_DQS[7..0]
8 M_B_DQS#[7..0]
8 M_A_DQS#[7..0]
8 M_B_DQS[7..0]
7,12 7,12 DDR_VREF_S3
M_ODT0 M_ODT1
7,12 7,12 DDR_VREF_S3
M_ODT2 M_ODT3
1 2
C321 SC4D7U6D3V3KX-GP
1
1
2
2
C380 SC4D7U6D3V3KX-GP
2
1
BC1
BC2
Title Size Date:
A B C D
Document Number
DDR2 Socket MYALL2
E
he
Rev
Thursday, March 30, 2006
Sheet
11
of
57
xa
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
MP
in
f@
Wistron Corporation
ho
High 9.2mm
tm
ai
62.10017.A71
l.c
1
SCD1U16V2ZY-2GP
High 5.2mm
1
om
MH1
SCD1U16V2ZY-2GP
62.10017.691
A
B
C
D
E
PARALLEL TERMINATION
DDR_VREF_S0
Decoupling Capacitor
DDR_VREF_S0
Put decap near power(0.9V) and pull-up resistor
RN30
4
1
1
1
1
1
1
1
1
1
1
C356 SCD1U16V2ZY-2GP
C397 SCD1U16V2ZY-2GP
C324 SCD1U16V2ZY-2GP
C379 SCD1U16V2ZY-2GP
C323 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C325 SCD1U16V2ZY-2GP
C352 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C326 SCD1U16V2ZY-2GP
C378 SCD1U16V2ZY-2GP
C392 SCD1U16V2ZY-2GP
1
8 7 6 5
1 2 3 4
SRN56J-2-GP
M_B_A12 M_B_A9
M_CKE2 7,11 M_B_BS#2 8,11
Put decap near power(0.9V) and pull-up resistor
4
C322 SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
2
2
1 1 1 1
2 R235 2 56R2J-4-GP R249 2 56R2J-4-GP M_A_A9 R234 2 56R2J-4-GP M_B_A8 R248 56R2J-4-GP
M_B_A5 M_B_A3 M_B_A1 M_B_A10
M_ODT1 7,11 M_ODT3 7,11
RN31
1
1
1
1
1
1
1
1
1
1
C393 SCD1U16V2ZY-2GP
C394 SCD1U16V2ZY-2GP
C396 SCD1U16V2ZY-2GP
C395 SCD1U16V2ZY-2GP
C351 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C376 SCD1U16V2ZY-2GP
C375 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C377 SCD1U16V2ZY-2GP
C353 SCD1U16V2ZY-2GP
C355 SCD1U16V2ZY-2GP
1 2
8 7 6 5
1 2 3 4
M_A_A[13..0] M_B_A[13..0]
M_A_A[13..0] 8,11 M_B_A[13..0] 8,11 C354 SCD1U16V2ZY-2GP
8 7 6 5
SRN56J-2-GP RN35 1 M_B_A13 2 3 4 SRN56J-2-GP RN34
2
2
2
2
2
2
2
2
2
M_ODT2 7,11 M_CS2# 7,11 M_B_RAS# 8,11
3
8 7 6 5
1 2 3 4
SRN56J-2-GP RN33
M_B_A0 M_B_A2 M_B_A4
M_B_BS#1 8,11 1D8V_S3
2
2
Place these Caps near DM1
1 1 1
C730 SC2D2U6D3V3MX-1-GP C731 SC2D2U6D3V3MX-1-GP C732 SC2D2U6D3V3MX-1-GP C733 SC2D2U6D3V3MX-1-GP
3
1
1 2
SCD1U16V2ZY-2GP
C734 SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP
8 7 6 5
1 2 3 4
SRN56J-2-GP RN32
M_B_A6 M_B_A7 M_B_A11 M_CKE3 7,11
2
2
2
1
1
1
C385 SCD1U16V2ZY-2GP
C386 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C387 SCD1U16V2ZY-2GP
SRN56J-2-GP
2
2
2
RN28
8 7 6 5
2
1 2 3 4
SRN56J-2-GP RN27
M_A_A13 M_ODT0 7,11 M_CS0# 7,11 M_A_RAS# 8,11
2
1
8 7 6 5
1 2 3 4
M_B_BS#0 8,11 M_B_WE# 8,11 M_CS3# 7,11 M_B_CAS# 8,11
2
C388
2
8 7 6 5
1 2 3 4
SRN56J-2-GP
M_A_A0 M_A_A2 M_A_A4
M_A_BS#1 8,11 1D8V_S3
Place these Caps near DM2
1 1 1 1
C768 SC2D2U6D3V3MX-1-GP C771 SC2D2U6D3V3MX-1-GP C769 SC2D2U6D3V3MX-1-GP C770 SC2D2U6D3V3MX-1-GP
RN23
1 2
C767 SC2D2U6D3V3MX-1-GP
8 7 6 5
1 2 3 4
SRN56J-2-GP RN21
M_A_BS#0 8,11 M_A_WE# 8,11 M_A_CAS# 8,11 M_CS1# 7,11
2
2
2
1
1
C342 SCD1U16V2ZY-2GP
C338 SCD1U16V2ZY-2GP
1 2
8 7 6 5
1 2 3 4
SRN56J-2-GP RN26
M_A_A12 M_A_A8
M_CKE0 7,11 M_A_BS#2 8,11
1
C337 SCD1U16V2ZY-2GP
2
C343 SCD1U16V2ZY-2GP
2
2
1
8 7 6 5
1 2 3 4
SRN56J-2-GP RN22
M_A_A6 M_A_A7 M_A_A11 M_CKE1 7,11
2
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
8 7 6 5
1 2 3 4
SRN56J-2-GP
M_A_A5 M_A_A3 M_A_A1 M_A_A10
DDR2 Termination Resistor
Size Document Number Rev
MYALL2
Date: Thursday, March 30, 2006
A B C D
MP
12 of 57
Sheet
E
LED
LCDVDD
D19 DY BAV99PT-GP-U 2
5V_S0 26,30 WLAN_LED# 31 BLT_LED#_1 WLAN_LED# BLT_LED#_1
R290 120R2F-GP 1 2
LED5 LED-YO-3-GP-U K A
3D3V_S0 5V_S0
Layout