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Compal confidential
IGL50/51 Schematics Document Mobile Yonah uFCPGA with Intel Calistoga_GM/PM+ICH7-M core logic
2006-05-15
REV:0.1
2
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Security Classification Issued Date 2005/03/10
Compal Secret Data
Deciphered Date 2006/03/10
Title
Compal Electronics, Inc.
Cover Sheet
R ev 0 .1 Sheet
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THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 1 of 48
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Compal confidential
File Name : LA-3061
ZZZ1
PCB
PCI-E x 16 VGA Sub BD
1
LVDS Panel Interface
V RAM 128/ 256MB
Thermal Sensor AD M1032
page 4
Mobile Yonah uFCBGA-479/uFCPGA-478 CPU
page 4, 5, 6
1
Fan Control Nvidia G7 2/G73M
page 4
H_A#(3..31) H_D#(0..63)
533/667MHz
FSB
Clock Generator I CS 954306
page 15
PCI-E x 16
page 18
Intel Calistoga GMCH
PCBGA 1466
page 7, 8, 9, 10,11,12
DDR2 -400/533/667
Dual Channel
BANK 0, 1, 2, 3
DDR2-SO-DIMM X2
page 13,14
LVDS Panel Interface page
2
16
Mini-PCIE Card CRT & TV OUT
page 17, 36
2
DMI
PCIE x3 LAN I/F
page 28
Intel ICH7-M
PCI BUS mBGA-652
page 19, 20, 21, 22
USB2.0 AC-LINK
New Card Connector x2 page 37
3.3V 33 MHz
USB conn X3
page 31, 37
10/100/1G LAN
RTL8110CL/SBL
page 27
3
CardBus Controller 1394+CARD
E NE CB1410
page 24
READER R5C832
page 26
LPC BUS
B T Conn
page 28
MO DEM A MOM page SubWoofer
29
3
page 31
RJ45 CONN
page 28
Slot 0
page 25
1394
page 26
3IN1 READER
page 38
ENE KB910/L
page 33
Audio AD1986A A MOM page 29 SATA HDD Connector x2
page 23
AMP & Audio Jack
page 30
RTC CKT.
page 20
SPR CONN.
*RJ45 CONN *MIC IN JACK *LINE OUT JACK *1394 CONN *SPDIF CONN *DC JACK *TVOUT CONN *USB CONN x1 *CIR x1
page 34
Int.KBD BIOS
page 32
Power On/Off CKT.
page 32
page 34
PATA CDROM Connector
page 23
T ouch Pad
4
DC/DC Interface CKT.
page 35
page 37
4
Power Circuit DC/DC
page 39~45
Security Classification Issued Date 2005/03/10
Compal Secret Data
Deciphered Date 2006/03/10
Title
Compal Electronics, Inc.
Block Diagram
R ev 0 .1 Sheet
E
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 2 of 48
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Power Block Diagram Of The IMVP6
RTCVREF
(3.3V)
B+ +5VALW
SPOK#
+VSB
+3VALW
MOS TP0610K +5VS MOS SI4800 +5VALW +VDDA
+CPU_CORE +VCCP
KB910L SB RTL8110SBL/CL CPU CPU NB EXPRESS CARD HDD ODD MDC APA2066 TPA0211 AD1986 USB PORT * 6
mA 160mA
VIN VIN Detector DC IN BATT+ BATT MOS AO4407
Regulator G920AT24 B+
MOS AO4916 PWM CONT. MAX8734AEE
SUSP
36A 2.5A 9.8A (14.7A) 1A 1.5A 1.8A 300mA 1A mA 70mA 3A
SI9182DH +3.3VS
Switch MOS AO4916
+3VALW Regulator APL5912-KAC +1.8V MOS U:SI4810B L:SI4810B PWM OZ813
OUT2 ON2 ON1 SYSON SUSP# SUSP# SUSP
+5VS
+2.5VS +0.9VS Regulator APL5331KAC +1.5VS MOS U:SI4810B L:SI4810B
OUT2 SUSP
MOS SI4800 +1.8VS MOS SI4800
+3VS
Charger MB39A126 +CPU_CORE
P.40
U:SI7840 X1 L:AO4410X2
VID[0..6]
OUT1
+1.05VS
MOS AO4916
PWM CONT. MAX8770GTL+
VCCP
PWM ISL6269CRZ
SUSP#
NB EXPRESS CARD CLK_GEN LCDVCC VGA CARD (G7XM) SB R5C832 BIOS ROM KB910L CB1410 VGA CARD (G7XM) NB
480mA 1A 200mA 1A 655mA 680mA mA 15mA 200mA mA 130mA (143mA)
1
PCI DEVICES
1
Voltage Rails
IDSEL# AD20 AD22 AD17 R E Q/GNT# 2 0 3 PIRQ PCI_PIRQA# PCI_PIRQG# PCI_PIRQF# S0 PCI_PIRQH# power plane +B LDO3 LDO5 +5VALW +3VALW +1.8V +5V
O MEANS ON X MEANS OFF +5VS +3VS +2.5VS +1.8VS +1.5VS +VGA_CORE +1.2VS +0.9VS +CPU_CORE +VCCP
EXTERNAL
CARD BUS CB1410 CARD READER & 1394 R5C832 L A N CONTROLLER RTL8110SBL/CL
+2.5VS
State S4 : STD S5 : SOFT OFF
+1.8V +1.8VS
DDR2_DIMM NB (667Mhz) GDDR2 VGA CARD (G7XM)
8A 3.1A 6A 4.06A
PCIE LANE
LANE 1 2 DEVICE Express Card Mini Card
USB
PORT 0 1 2 3 4 5 6 DEVICE LEFT SIDE BLUE TOOTH RIGHT SIDE JP810 RIGHT SIDE CMOS RIGHT SIDE
S1 S3 : STR S5 S4/AC S5 S4/ Battery only S5 S4/AC & Battery don't exist
O O O O O
O O O O
O O O
O O
X
ID
0 1 2 3 4 5 6 7
X X
BRD_ID
X X X
X X X X
R115(Rb) Vab
+0.9VREF +0.9VS
DDR2_DIMM GDDR2 DDR2_DIMM
10mA 1A 2A 40mA 8.9A(13.8A) 3.8A 1A 0.65A 2A
I2C / SMB Address
KB910/L (SM1-Pulled-Up 5V)
DEVICE AT24C16AN SMART BATTERY ADM1032AR G781-1 (RESERVED) ADDRESS R/W A3/A2 H 17/16 H 99/98 H 9B/9A D3/D2 H A1/A0 H A3/A2 H NC NC (3.3V) (3.3V) (3.3V) (2.5V) (2.5V)
R119(Ra)=100K Ohm
MB_ID
MB ID 0 1 P NAME IGL-50 IGL-51
MB REV#
R0.1 R0.2 R0.3 R1.0 (EVT) (DVT) (PVT) (MP)
+1.5V +1.5VS
SB NB SB MiniCard EXPRESS CARD VGA CARD (G7XM)
BOM Structure
MARK
@ EXP@ BT@ UMA@ VGA@ HGT30@ CB@ GIGA@ 10/100@
FUNCTION
NC FOR ALL PCIE-NEW CARD BLUE TOOTH Internal 945GM External G7xM SUBWOOFER HGT30 PCMCIA/CARD BUS 8110SBL(SCL)Giga LAN 8110CL 10/100Mb LAN
KB910/L (SM2-Pulled-Up 3.3V) G7xM (I2CC-Pulled-Up 3.3V) ICH7M SM Bus
ICS9LPR325AKLFT DDR II DIMM0 DDR II DIMM1 Express Card Mini-Express
0 8.2K 18K 33K 56K 100K 200K NC
0V 0.25V 0.50V 0.82V 1.19V 1.65V 2.20V 3.30V
SUBWOOFER@
Security Classification Issued Date 2005/03/10
Compal Secret Data
Deciphered Date 2006/03/10
Title
Compal Electronics, Inc.
Notes List
R ev 0 .1 Sheet 3 of 48 , 08, 2006
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate:
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1
+ VCCP 7 H_ A# [3..31] H_ A #3 H_ A #4 H_ A #5 H_ A #6 H_ A #7 H_ A #8 H_ A #9 H_ A#10 H_ A#11 H_ A#12 H_ A#13 H_ A#14 H_ A#15 H_ A#16 H_ A#17 H_ A#18 H_ A#19 H_ A#20 H_ A#21 H_ A#22 H_ A#23 H_ A#24 H_ A#25 H_ A#26 H_ A#27 H_ A#28 H_ A#29 H_ A#30 H_ A#31 H _REQ#0 H _REQ#1 H _REQ#2 H _REQ#3 H _REQ#4 7 7
C
JP 1A
H_ D #[0..63] 7 I TP_TDI
This shall place near CPU R 98 1 56_0402_5% 2 R 97
D
7
H_ REQ#[0..4]
J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 K3 H2 K2 J3 L5 L2 V4
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#
YONAH
ADDR GROUP
DATA GROUP
REQ0# REQ1# REQ2# REQ3# REQ4# ADSTB0# ADSTB1#
H_ADSTB#0 H_ADSTB#1
H _ADSTB#0 H _ADSTB#1
15 C LK_CPU_BCLK 15 C LK_CPU_BCLK#
C LK_CPU_BCLK A22 C LK_CPU_BCLK# A21
BCLK0 BCLK1
HOST CLK
+ VCCP
1
7 7 7 7 7 7 R 84 7 56_0402_5% 7
2
H_ ADS# H_ B NR# H_ B PRI# H_ BR0# H_ D EFER# H_ D R D Y# H_ HIT# H_ HITM# H_LOCK# H_RESET#
7 7 7
H_ A DS# H_ B NR# H_ B PRI# H_ BR0# H_ D EFER# H_ D R D Y# H_ HI T# H_ HI TM# H_ IE RR# H _LOCK# H_RESET#
H1 E2 G5 F1 H5 F21 G6 E4 D20 H4 B1 F3 F4 G3 G2
ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET# RS0# RS1# RS2# TRDY#
CONTROL
H_ R S#[0..2]
7
H_ T R DY#
H_ RS#0 H_ RS#1 H_ RS#2 H_ T R DY#
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 J26 M26 V23 AC20 H23 M24 W24 AD23 G22 N25 Y25 AE24
H_ D#0 H_ D#1 H_ D#2 H_ D#3 H_ D#4 H_ D#5 H_ D#6 H_ D#7 H_ D#8 H_ D#9 H_ D#10 H_ D#11 H_ D#12 H_ D#13 H_ D#14 H_ D#15 H_ D#16 H_ D#17 H_ D#18 H_ D#19 H_ D#20 H_ D#21 H_ D#22 H_ D#23 H_ D#24 H_ D#25 H_ D#26 H_ D#27 H_ D#28 H_ D#29 H_ D#30 H_ D#31 H_ D#32 H_ D#33 H_ D#34 H_ D#35 H_ D#36 H_ D#37 H_ D#38 H_ D#39 H_ D#40 H_ D#41 H_ D#42 H_ D#43 H_ D#44 H_ D#45 H_ D#46 H_ D#47 H_ D#48 H_ D#49 H_ D#50 H_ D#51 H_ D#52 H_ D#53 H_ D#54 H_ D#55 H_ D#56 H_ D#57 H_ D#58 H_ D#59 H_ D#60 H_ D#61 H_ D#62 H_ D#63
ITP_TMS ITP_TDO ITP_BPM#5 ITP_TRST# ITP_TCK
1
2 2 2 2 2
56_0402_5% 56_0402_5% 56_0402_5% 56_0402_5% 56_0402_5%
ITP_DBRESET#
R 85
1
2 @ 200_0402_1%
ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4
P AD T13 P AD P AD P AD P AD P AD T17 T18 T20 T16 T19
R 101 1 R 103 1 R 95 R 96
1 1
D
Thermal Sensor G781F
+3VS U1 6 H_ T H ERMDA C 311
2 3 8 7
D+ DSCLK SDATA
G781F_SOP8
VDD1 ALERT# THERM# GND
1 6 4 5
2
C 310
1
0 . 1 U_0402_16V4Z
1
33 EC_SMB_CK2 33 E C_SMB_DA2
2
H_ T H ERMDC 2200P_0402_50V7K EC_SMB_CK2 E C_SMB_DA2
T HERM# 2 10K_0402_5%
1
R 226
+3VS
C
Address:100_1100
+5VS
+VSB
21 ITP_DBRESET# 7 H_ D B S Y# 20 H_DPSLP# 2 0,45 H_DPRSTP# 7 H_ D PW R# 45 H_ PROCHOT# + VCCP
1 R 83
2
20 H_ PW RGOOD 7 ,20 H_ C PUSLP#
ITP_DBRESET# C20 H_ D B SY# E1 H _DPSLP# B5 H _DPRSTP# E5 H_ DPW R# D24 ITP_BPM#4 AC2 ITP_BPM#5 AC1 H_ PROCHOT#D21 H_ PW RGOOD D6 H_ C PUSLP# D7 ITP_TCK AC5 I TP_TDI AA6 ITP_TDO AB3 TEST1 C26 TEST2 D25 ITP_TMS AB5 ITP_TRST# AB6 H_ T H ERMDA A24 H_ T H ERMDC A25 H_ T HERMTRIP# C7
68_0402_5%
DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT# PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#
MISC
DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#
H_ DSTBN#0 H_ DSTBN#1 H_ DSTBN#2 H_ DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_ D STBN#[0..3] 7 33 E N_ F AN1
P
B
3 2
+IN OUT -IN G 4
G
1
F AN1 _ON
2
ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3
AD4 AD3 AD1 AC4
BPM0# BPM1# BPM2# BPM3#
DINV0# DINV1# DINV2# DINV3#
0 . 0 1U_0402_25V4Z
8
1 2 5 6
H_ D INV #0 H_ D INV #1 H_ D INV #2 H_ D INV #3
1
2
H_ D INV#0 H_ D INV#1 H_ D INV#2 H_ D INV#3
7 7 7 7
C 303 1 0 U_1206_10V4Z
2
1 C 309
+3VS D Q19 SI3456BDV-T1-E3_TSOP6 S
B
3 4
R 222 10K_0402_5%
H_DSTBP#[0..3] 7
1
U1 5 A LM358A_SO8
JP2
1 1
2
F AN1 C305 10U_0805_10V4Z C307 1000P_0402_50V7K
R 218 100K_0402_5% R 219 150K_0402_5%
1
1
14 25 3
ACES_85205-0300
THERMAL
THERMDA DIODE THERMDC THERMTRIP#
TYCO_1-1674770-2_Yonah~D ME@
LEGACY CPU
STPCLK# SMI#
D5 A3
H_STPCLK# H_ S MI#
H_STPCLK# 20 H_ S MI# 20
2
R 71 R 74
1 1
2 @ 1K_0402_5% 2 51_0402_5%
A20M# FERR# IGNNE# INIT# LINT0 LINT1
A6 A5 C4 B3 C6 B4
H_ A 20M# H_ F ERR# H_ IGNN E# H_ INI T# H_ IN TR H _ NMI
H_ A20M# 20 H_ F ERR# 20 H_ IGNNE# 20 H_ INIT# 20 H_ INTR 20 H _ NMI 20
2
D 11 1 N4148_SOD80
1
2
2
7 ,20 H_ T HERMTRIP#
5 6
33 F AN_SPEED1
+IN OUT -IN
7
C 308 1000P_0402_50V7K
1
H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil
A
U1 5B LM358A_SO8
2
+ VCCP + VCCP
A
1
R 100 R 73 @ 56_0402_5% H _DPSLP# 1
2
2 2
@ 56_0402_5% R 99 H _DPRSTP# 1 2 @ 56_0402_5%
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
Title
Compal Electronics, Inc.
Yonah CPU in mFCPGA479
R ev 0 .1 Sheet
1
B E
H_ PROCHOT# 3 1 OCP# Q4 @ PMBT3904_SOT23
5
OCP#
21
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4 3 2
C
Size D ocum ent Num ber C ustom I GL 50/51 LA-3771 D ate: , 08, 2006 4 of 48
5
4
3
2
1
+ VCCP
D
+ CPU_CORE + CPU_GTLREF R 69 1K_0402_1% R 93 100_0402_1%
Length match within 25 mils The trace width 18 mils space 45 VC CSENSE 7 mils 45 VSSENSE
VC CSENSE +1.5VS + VCCP V SSENSE C 122
+CPU_CORE J P1B VC CSENSE V SSENSE JP1C
D
1
AF7 AE7 B26 K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21
VCCSENSE VSSSENSE VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP PSI# VID0 VID1 VID2 VID3 VID4 VID5 VID6 GTLREF BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
2
1
2
R 94 100_0402_1%
1
R 62 2K_0402_1%
2
1
1
C 132
YONAH
2
2
2
Close to CPU pin AD26 within 500mils.
Close to CPU pin within 500mils.
1 0 U_0805_10V4Z
0 . 0 1U_0402_25V4Z
45 45 45 45 45 45 45 45
H_ PSI# C P U_ VID0 C P U_ VID1 C P U_ VID2 C P U_ VID3 C P U_ VID4 C P U_ VID5 C P U_ VID6 + CPU_GTLREF
H_ P SI# C P U_ VID0 C P U_ VID1 C P U_ VID2 C P U_ VID3 C P U_ VID4 C P U_ VID5 C P U_ VID6
AE6 AD6 AF5 AE5 AF4 AE3 AF2 AE2 AD26
C
CPU_BSEL 133 166
CPU_BSEL2 0 0
CPU_BSEL1 0
CPU_BSEL0 1 1
1
15 15 15
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
C PU_BSEL0 C PU_BSEL1 C PU_BSEL2 C OMP0 C OMP1 C OMP2 C OMP3
B22 B23 C21 R26 U26 U1 V1 E7 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17 D2 F6 D3 C1 AF1 D22 C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25
+ CPU_CORE
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal.
B
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1
AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
YONAH
POWER, GROUND
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21
1
POWER, GROUNG, RESERVED SIGNALS AND NC
C
R102 27.4_0402_1%
R70 27.4_0402_1%
R72 54.9_0402_1%
R104 54.9_0402_1%
1
1
1
2
2
2
2
1
B
TYCO_1-1674770-2_Yonah~D ME@
TYCO_1-1674770-2_Yonah~D ME@
A
A
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
Title
Compal Electronics, Inc.
Yonah CPU in mFCPGA479
R ev 0 .1 Sheet
1
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C ustom I GL 50/51 LA-3771 D ate: , 08, 2006 5 of 48
5
4
3
2
1
D
+ CPU_CORE
D
1
Place these capacitors on L8 (North side,Secondary Layer) C 318 1 0 U_0805_6.3V6M
1
C 326 1 0 U_0805_6.3V6M
1
C 151 1 0 U_0805_6.3V6M
1
C 171 1 0 U_0805_6.3V6M
1
C 346 1 0 U_0805_6.3V6M
1
C184 1 0 U_0805_6.3V6M
2
2
2
2
2
2
+ CPU_CORE
1
Place these capacitors on L8 (North side,Secondary Layer) C 325 1 0 U_0805_6.3V6M
1
C 186 1 0 U_0805_6.3V6M
1
C 341 1 0 U_0805_6.3V6M
1
C 178 1 0 U_0805_6.3V6M
1
C 316 1 0 U_0805_6.3V6M
1
C 185 1 0 U_0805_6.3V6M
1
C 166 1 0 U_0805_6.3V6M
1
C342 1 0 U_0805_6.3V6M
2
2
2
2
2
2
2
2
+ CPU_CORE
1
Place these capacitors on L8 (Sorth side,Secondary Layer) C 183 1 0 U_0805_6.3V6M
1
C 170 1 0 U_0805_6.3V6M
1
C 334 1 0 U_0805_6.3V6M
1
C 319 1 0 U_0805_6.3V6M
1
C 172 1 0 U_0805_6.3V6M
1
C 333 1 0 U_0805_6.3V6M
1
C 181 1 0 U_0805_6.3V6M
1
C 176 2 2 U_0805_6.3V6M
2
2
2
2
2
2
2
2
C
C
+ CPU_CORE
1
Place these capacitors on L8 (Sorth side,Secondary Layer) C 150 1 0 U_0805_6.3V6M
1
C 165 1 0 U_0805_6.3V6M
1
C 345 1 0 U_0805_6.3V6M
1
C 173 1 0 U_0805_6.3V6M
1
C 179 1 0 U_0805_6.3V6M
1
C 177 2 2 U_0805_6.3V6M
1
C 317 1 0 U_0805_6.3V6M
1
C182 1 0 U_0805_6.3V6M
2
2
2
2
2
2
2
2
Mid Frequence Decoupling
+ CPU_CORE
C324 330U_V_2.5VK_R9
C180 330U_V_2.5VK_R9
C175 330U_V_2.5VK_R9
C339 330U_V_2.5VK_R9
C320 330U_V_2.5VK_R9
1
+
1
+
1
+
1
+
1
+
C343 330U_V_2.5VK_R9
1
+
North Side Secondary
South Side Secondary
B
ESR <= 1.5m ohm Capacitor > 1980uF
B
2
2
2
2
2
2
+ VCCP
1
C 109 2 2 0U_D2_4VM +
1
C 190 0 . 1 U_0402_16V4Z
1
C 136 0 . 1 U_0402_16V4Z
1
C 138 0 . 1 U_0402_16V4Z
1
C 137 0 . 1 U_0402_16V4Z
1
C 189 0 . 1 U_0402_16V4Z
1
C188 0 . 1 U_0402_16V4Z
2
2
2
2
2
2
2
Place these inside socket cavity on L8 (North side Secondary)
A
A
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
Title
Compal Electronics, Inc.
CPU Bypass capacitors
R ev 0 .1 Sheet
1
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C ustom I GL 50/51 LA-3771 D ate: , 08, 2006 6 of 48
5
4
3
2
1
U1 4
4
H_ D # [0..63] H_ D#0 H_ D#1 H_ D#2 H_ D#3 H_ D#4 H_ D#5 H_ D#6 H_ D#7 H_ D#8 H_ D#9 H_ D#10 H_ D#11 H_ D#12 H_ D#13 H_ D#14 H_ D#15 H_ D#16 H_ D#17 H_ D#18 H_ D#19 H_ D#20 H_ D#21 H_ D#22 H_ D#23 H_ D#24 H_ D#25 H_ D#26 H_ D#27 H_ D#28 H_ D#29 H_ D#30 H_ D#31 H_ D#32 H_ D#33 H_ D#34 H_ D#35 H_ D#36 H_ D#37 H_ D#38 H_ D#39 H_ D#40 H_ D#41 H_ D#42 H_ D#43 H_ D#44 H_ D#45 H_ D#46 H_ D#47 H_ D#48 H_ D#49 H_ D#50 H_ D#51 H_ D#52 H_ D#53 H_ D#54 H_ D#55 H_ D#56 H_ D#57 H_ D#58 H_ D#59 H_ D#60 H_ D#61 H_ D#62 H_ D#63
U1 4 A
H_ A#[3..31] 4
PM
VGA@ 21 21 21 21 D MI_TXN0 D MI_TXN1 D MI_TXN2 D MI_TXN3 D M I_TXN0 D M I_TXN1 D M I_TXN2 D M I_TXN3
U1 4B
Description at page15.
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 G_CLKP G_CLKN K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26
MC H_CLKSEL0 MC H_CLKSEL1 MC H_CLKSEL2 C F G3 P AD C F G4 P AD C F G5 C F G6 P AD C F G7 C F G8 P AD C F G9 C F G10 P AD C F G11 C F G12 C F G13 C F G14 C F G15 C F G16 C F G17 C F G18 C F G19 C F G20 MC H_CLKSEL0 15 MC H_CLKSEL1 15 MC H_CLKSEL2 15 T9 T3 C F G5 11 T10 C F G7 11 T7 C F G9 11 T5 C F G11 11 C F G12 11 C F G13 11 T2 T8 C F G16 11 T1 C F G18 11 C F G19 11 C F G20 11
D
C
+ VCCP
J13
+ H _VREF K13 H _XRCOMP E1 H _XSCOMP E2 H_ YR C OMP Y1 H_ YS COMP U1 + H _SW NG0 E4 + H _SW NG1 W1 R23 24.9_0402_1% R20 24.9_0402_1%
B
HVREF0 HVREF1 HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING
19 MC H_ IC H_ S YNC#
K28
ICH_SYNC#
RESERVED
2
2
F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
C LK
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14
H_ A #3 H_ A #4 H_ A #5 H_ A #6 H_ A #7 H_ A #8 H_ A #9 H_ A#10 H_ A#11 H_ A#12 H_ A#13 H_ A#14 H_ A#15 H_ A#16 H_ A#17 H_ A#18 H_ A#19 H_ A#20 H_ A#21 H_ A#22 H_ A#23 H_ A#24 H_ A#25 H_ A#26 H_ A#27 H_ A#28 H_ A#29 H_ A#30 H_ A#31
U1 4
AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 AE37 AF41 AG37 AH41 AC37 AE41 AF37 AG41 AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29
DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMITXP0 DMITXP1 DMITXP2 DMITXP3 SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CS0# SM_CS1# SM_CS2# SM_CS3# SM_OCDCOMP0 SM_OCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 SM_RCOMPN SM_RCOMPP SM_VREF0 SM_VREF1 PM_BMBUSY# PM_EXTTS0# PM_EXTTS1# PM_THERMTRIP# PWROK RSTIN#
D
GML
UMA_ GML@
21 21 21 21
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI
C FG
21 21 21 21
D MI_RXN0 D MI_RXN1 D MI_RXN2 D MI_RXN3
D MI _RXN0 D MI _RXN1 D MI _RXN2 D MI _RXN3
P AD P AD P AD
21 21 21 21
D MI_RXP0 D MI_RXP1 D MI_RXP2 D MI_RXP3
D M I_RXP0 D M I_RXP1 D M I_RXP2 D M I_RXP3
13 13 14 14 13 13 14 14 13 13 14 14 H_ADSTB#0 4 H_ADSTB#1 4 C L K_MCH_BCLK# 15 C L K_MCH_BCLK 15 H_ D STBN#[0..3] 4 13 13 14 14
M_ CLK_DDR0 M_ CLK_DDR1 M_ CLK_DDR2 M_ CLK_DDR3 M_ CLK_DDR#0 M_ CLK_DDR#1 M_ CLK_DDR#2 M_ CLK_DDR#3
M_ CLK_DDR0 M_ CLK_DDR1 M_ CLK_DDR2 M_ CLK_DDR3 M_ CLK_DDR#0 M_ CLK_DDR#1 M_ CLK_DDR#2 M_ CLK_DDR#3 D D R _ CKE0_DIMMA D D R _ CKE1_DIMMA D D R _CKE2_DIMMB D D R _CKE3_DIMMB
AG33 C L K_MCH_3GPLL AF33 C L K_MCH_3GPLL# A27 A26
C L K _MCH_DREFCLK# C L K _ MCH_DREFCLK
C L K_MCH_3GPLL 15 C L K_MCH_3GPLL# 15 C L K _MCH_DREFCLK# 15 C L K _MCH_DREFCLK 15 C L K _MCH_SSCDREFCLK# 15 C L K _MCH_SSCDREFCLK 15 MC H_CLKREQ# 15
D_REF_CLKN D_REF_CLKP D_REF_SSCLKN D_REF_SSCLKP CLK_REQ#
HOST
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1 HCLKN HCLKP HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDINV#0 HDINV#1 HDINV#2 HDINV#3 HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# HRS0# HRS1# HRS2#
D8 G8 B8 F8 A8 B9 C13 AG1 AG2 K4 T7 Y5 AC4 K3 T6 AA5 AC5 J7 W8 U3 AB10 B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3 B4 E6 D6
H _REQ#0 H _REQ#1 H _REQ#2 H _REQ#3 H _REQ#4
H_ REQ#[0..4] 4
C40 MC H _SSCDREFCLK# D41 MC H_ SSCDREFCLK H32
MC H_CLKREQ#
H _ADSTB#0 H _ADSTB#1 C L K_MCH_BCLK# C L K_MCH_BCLK H_ DSTBN#0 H_ DSTBN#1 H_ DSTBN#2 H_ DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
D D R _ CKE0_DIMMA D D R _ CKE1_DIMMA D D R _CKE2_DIMMB D D R _CKE3_DIMMB D D R _ C S0_DIMMA# D D R _ C S1_DIMMA# D D R _ CS2_DIMMB# D D R _ CS3_DIMMB#
DDR MUXING
D D R _ C S0_DIMMA# AW13 D D R _ C S1_DIMMA# AW12 D D R _ CS2_DIMMB# AY21 D D R _ CS3_DIMMB# AW21 M _OCDOCMP0 M _OCDOCMP1
AL20 AF10 BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41
H_DSTBP#[0..3] 4
+1.8V
13 13 14 14 R 29
M_ODT0 M_ODT1 M_ODT2 M_ODT3
M_ODT0 M_ODT1 M_ODT2 M_ODT3 S MR COMPN S MRCOMPP
R26 54.9_0402_1%
R27 54.9_0402_1%
1
1
H_ D INV #0 H_ D INV #1 H_ D INV #2 H_ D INV #3
1 1
2 80.6_0402_1% 2
80.6_0402_1% + D D R _MCH_REF
H_ D INV#0 H_ D INV#1 H_ D INV#2 H_ D INV#3
4 4 4 4
R 28
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13
A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1 T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35
C
H_RESET# H_ A DS# H_ T R DY# H_ DPW R# H_ D R D Y# H_ D EFER# H_ HI TM# H_ HI T# H _LOCK# H_ BR0# H_ B NR# H_ B PRI# H_ D B SY# H_ C PUSLP#
H_RESET# 4 2 2 1,45 D P RSLPVR H_ ADS# 4 H_ T R DY# 4 H_ DPW R# 4 H_ D R D Y# 4 1 9,23,28,37 PLT_RST# H_ DEFER# 4 H_ HITM# 4 H_ HIT# 4 H_LOCK# 4 H_ BR0# 4 H_ B NR# 4 H_ B PRI# 4 H_ D B SY# 4 H_ CPUSLP# 4 ,20
R 88 0_0402_5%
P M_ B MBUSY# G28 21 P M_ B MBUSY# PM_EXTTS#0 F25 1 3,14 PM_EXTTS#0 PM_EXTTS#1 1 H26 H_ T HERMTRIP# G6 4 ,20 H_ T HERMTRIP# IC H _POK AH33 21,33 IC H_POK PLTRST_R# 2 1 AH34 R 55 100_0402_1%
NC PM
B
C ALISTOGA_FCBGA1466~D UMA_ GM@
H_ RS#0 H_ RS#1 H_ RS#2 H_ R S#[0..2] 4
Layout Note: +DDR_MCH_REF trace width and spacing is 20/20.
+3VS +1.8V R 46 10K_0402_5% R 25 PM_EXTTS#0
1
2
2
1
C ALISTOGA_FCBGA1466~D UMA_ GM@
1
2
1
C16 0.1U_0402_16V4Z
Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20.
+ VCCP + VCCP 221_0603_1% 100_0402_1% 221_0603_1% +VCCP
100_0402_1% + D D R _MCH_REF @ PM_EXTTS#1
2
R 49 10K_0402_5%
2
1
1 1
R 21 100_0402_1% R 45 @ 40.2_0402_1% M _OCDOCMP0
2
1
1
2
2
1
R22
R30
R18
R 31 @ 40.2_0402_1% M _OCDOCMP1
1
2
1
A
2
2
+ H _SW NG0 + H _VREF 0.1U_0402_16V4Z C19 0.1U_0402_16V4Z
2
A
+ H _SW NG1 0.1U_0402_16V4Z C11
1
100_0402_1%
1
200_0402_1%
R24
R36
C26
1
R19
1
100_0402_1%
1
1
2
2
2
2
2
2
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
Title
Compal Electronics, Inc.
Calistoga (1/6)
R ev 0 .1 Sheet
1
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 7 of 48
5
4
3
2
1
D
D
U1 4D 13 13 13 D DR_A_BS#0 D DR_A_BS#1 D DR_A_BS#2 D DR_A_BS#0 D DR_A_BS#1 D DR_A_BS#2
U14E
AU12 AV14 BA20
SA_BS0 SA_BS1 SA_BS2
13 D D R _ A_DM[0..7]
D D R _A_DM0 D D R _A_DM1 D D R _A_DM2 D D R _A_DM3 D D R _A_DM4 D D R _A_DM5 D D R _A_DM6 D D R _A_DM7
AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
13 D D R _A_DQS[0..7]
DDR SYS MEMORY A
C
DDR SYS MEMORY B
D D R_A_DQS0 D D R_A_DQS1 D D R_A_DQS2 D D R_A_DQS3 D D R_A_DQS4 D D R_A_DQS5 D D R_A_DQS6 D D R_A_DQS7
AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
13 D D R _A_DQS#[0..7]
D D R_A_DQS#0 D D R_A_DQS#1 D D R_A_DQS#2 D D R_A_DQS#3 D D R_A_DQS#4 D D R_A_DQS#5 D D R_A_DQS#6 D D R_A_DQS#7
13 D D R _ A_MA[0..13]
D D R _A_MA0 D D R _A_MA1 D D R _A_MA2 D D R _A_MA3 D D R _A_MA4 D D R _A_MA5 D D R _A_MA6 D D R _A_MA7 D D R _A_MA8 D D R _A_MA9 D D R _A_MA10 D D R _A_MA11 D D R _A_MA12 D D R _A_MA13
AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
B
13 13 13
D D R _A_CAS# D D R _A_RAS# D D R_A_W E# T6 P AD T12 P AD
D D R _A_CAS# D D R _A_RAS# D D R_A_W E# S A_ R C V ENIN# S A_ RCVENOUT#
AY13 AW14 AY14 AK23 AK24
SA_CAS# SA_RAS# SA_WE# SA_RCVENIN# SA_RCVENOUT#
check layout
C ALISTOGA_FCBGA1466~D UMA_ GM@
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8
D D R _A_D0 D D R _A_D1 D D R _A_D2 D D R _A_D3 D D R _A_D4 D D R _A_D5 D D R _A_D6 D D R _A_D7 D D R _A_D8 D D R _A_D9 D D R _A_D10 D D R _A_D11 D D R _A_D12 D D R _A_D13 D D R _A_D14 D D R _A_D15 D D R _A_D16 D D R _A_D17 D D R _A_D18 D D R _A_D19 D D R _A_D20 D D R _A_D21 D D R _A_D22 D D R _A_D23 D D R _A_D24 D D R _A_D25 D D R _A_D26 D D R _A_D27 D D R _A_D28 D D R _A_D29 D D R _A_D30 D D R _A_D31 D D R _A_D32 D D R _A_D33 D D R _A_D34 D D R _A_D35 D D R _A_D36 D D R _A_D37 D D R _A_D38 D D R _A_D39 D D R _A_D40 D D R _A_D41 D D R _A_D42 D D R _A_D43 D D R _A_D44 D D R _A_D45 D D R _A_D46 D D R _A_D47 D D R _A_D48 D D R _A_D49 D D R _A_D50 D D R _A_D51 D D R _A_D52 D D R _A_D53 D D R _A_D54 D D R _A_D55 D D R _A_D56 D D R _A_D57 D D R _A_D58 D D R _A_D59 D D R _A_D60 D D R _A_D61 D D R _A_D62 D D R _A_D63
D D R _ A_D[0..63] 13 14 14 14 DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
AT24 AV23 AY28
SB_BS0 SB_BS1 SB_BS2
14 D D R _B_DM[0..7]
D D R_B_DM0 D D R_B_DM1 D D R_B_DM2 D D R_B_DM3 D D R_B_DM4 D D R_B_DM5 D D R_B_DM6 D D R_B_DM7
AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
14 D D R_B_DQS[0..7]
D DR_B_DQS0 D DR_B_DQS1 D DR_B_DQS2 D DR_B_DQS3 D DR_B_DQS4 D DR_B_DQS5 D DR_B_DQS6 D DR_B_DQS7
AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
14 D D R_B_DQS#[0..7]
D DR_B_DQS#0 D DR_B_DQS#1 D DR_B_DQS#2 D DR_B_DQS#3 D DR_B_DQS#4 D DR_B_DQS#5 D DR_B_DQS#6 D DR_B_DQS#7
14 D D R _ B_MA[0..13]
D D R_B_MA0 D D R_B_MA1 D D R_B_MA2 D D R_B_MA3 D D R_B_MA4 D D R_B_MA5 D D R_B_MA6 D D R_B_MA7 D D R_B_MA8 D D R_B_MA9 D D R_B_MA10 D D R_B_MA11 D D R_B_MA12 D D R_B_MA13
AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
14 14 14
D D R_B_CAS# D D R_B_RAS# D DR_B_W E# T4 P AD T11 P AD
D D R_B_CAS# D D R_B_RAS# D DR_B_W E# S B _ R C VENIN# S B _RCVENOUT#
AR24 AU23 AR27 AK16 AK18
SB_CAS# SB_RAS# SB_WE# SB_RCVENIN# SB_RCVENOUT#
check layout
C ALISTOGA_FCBGA1466~D UMA_ GM@
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3
D D R_B_D0 D D R_B_D1 D D R_B_D2 D D R_B_D3 D D R_B_D4 D D R_B_D5 D D R_B_D6 D D R_B_D7 D D R_B_D8 D D R_B_D9 D D R_B_D10 D D R_B_D11 D D R_B_D12 D D R_B_D13 D D R_B_D14 D D R_B_D15 D D R_B_D16 D D R_B_D17 D D R_B_D18 D D R_B_D19 D D R_B_D20 D D R_B_D21 D D R_B_D22 D D R_B_D23 D D R_B_D24 D D R_B_D25 D D R_B_D26 D D R_B_D27 D D R_B_D28 D D R_B_D29 D D R_B_D30 D D R_B_D31 D D R_B_D32 D D R_B_D33 D D R_B_D34 D D R_B_D35 D D R_B_D36 D D R_B_D37 D D R_B_D38 D D R_B_D39 D D R_B_D40 D D R_B_D41 D D R_B_D42 D D R_B_D43 D D R_B_D44 D D R_B_D45 D D R_B_D46 D D R_B_D47 D D R_B_D48 D D R_B_D49 D D R_B_D50 D D R_B_D51 D D R_B_D52 D D R_B_D53 D D R_B_D54 D D R_B_D55 D D R_B_D56 D D R_B_D57 D D R_B_D58 D D R_B_D59 D D R_B_D60 D D R_B_D61 D D R_B_D62 D D R_B_D63
D D R _B_D[0..63] 14
C
B
A
A
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
Title
Compal Electronics, Inc.
Calistoga (2/6)
R ev 0 .1 Sheet
1
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 8 of 48
5
4
3
2
1
D
D
U1 4C
+ 1.5VS_PCIE R 54 24.9_0402_1%
H27 H28
L VDSA0+ L VDSA1+ L VDSA2+ L VDSA0L VDSA1L VDSA2LVDSB0+ LVDSB1+ LVDSB2+ LVDSB0LVDSB1LVDSB2L VDSAC+ L V DSACLVDSBC+ L VDSBC-
SDVOCTRL_DATA SDVOCTRL_CLK LA_DATA0 LA_DATA1 LA_DATA2 LA_DATA#0 LA_DATA#1 LA_DATA#2 LB_DATA0 LB_DATA1 LB_DATA2 LB_DATA#0 LB_DATA#1 LB_DATA#2 LA_CLK LA_CLK# LB_CLK LB_CLK# LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL TVDAC_A TVDAC_B TVDAC_C TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC TV_DCONSEL1 TV_DCONSEL0
EXP_COMPI EXP_COMPO EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
D40 D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40
PEGCOMP
1
2
P EG_RXN[0..15] 18
38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
C
L VDSA0+ L VDSA1+ LVDSA2+ L VDSA0L VDSA1L VDSA2LVDSB0+ LVDSB1+ LVDSB2+ LVDSB0LVDSB1LVDSB2L VDSAC+ L VDSACLVDSBC+ L VDSBC-
B37 B34 A36 C37 B35 A37 F30 D29 F28 G30 D30 F29 A32 A33 E26 E27 D32 J30 H30 H29 G26 G25 F32 B38 C35 C33 C32 A16 C18 A19 1 J20 B16 B18 B19 J29 K30
P EG_RXN0 P EG_RXN1 P EG_RXN2 P EG_RXN3 P EG_RXN4 P EG_RXN5 P EG_RXN6 P EG_RXN7 P EG_RXN8 P EG_RXN9 P EG_RXN10 P EG_RXN11 P EG_RXN12 P EG_RXN13 P EG_RXN14 P EG_RXN15 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 C 153 C 124 C 142 C 115 C 155 C 126 C 148 C 117 C 157 C 128 C 140 C 119 C 159 C 130 C 144 C 121 C 152 C 123 C 141 C 114 C 154 C 125 C 147 C 116 C 156 C 127 C 139 C 118 C 158 C 129 C 143 C 120
PCI-EXPRESS GRAPHICS
LV DS
PEG_RXP[0..15] 18
16 GMC H_ENBKL
GMC H _ENBKL
C
16 GMC H_ L VDDEN
L D DC_CLK L D DC_DATA GMC H_ L VDDEN
2
R 53
1
1.5K_0402_1%
P EG_M_TXN[0..15] 18 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z PEG_M_TXN0 PEG_M_TXN1 PEG_M_TXN2 PEG_M_TXN3 PEG_M_TXN4 PEG_M_TXN5 PEG_M_TXN6 PEG_M_TXN7 PEG_M_TXN8 PEG_M_TXN9 PEG_M_TXN10 PEG_M_TXN11 PEG_M_TXN12 PEG_M_TXN13 PEG_M_TXN14 PEG_M_TXN15 PEG_M_TXP0 PEG_M_TXP1 PEG_M_TXP2 PEG_M_TXP3 PEG_M_TXP4 PEG_M_TXP5 PEG_M_TXP6 PEG_M_TXP7 PEG_M_TXP8 PEG_M_TXP9 PEG_M_TXP10 PEG_M_TXP11 PEG_M_TXP12 PEG_M_TXP13 PEG_M_TXP14 PEG_M_TXP15
2
R 207
2
R 208
2
R 209
TV_COMPS 1 UMA@ 150_0603_1% T V_ LUMA 1 UMA@ 150_0603_1% T V _CRMA 1 UMA@ 150_0603_1%
17 17 17
TV_COMPS T V_LUMA T V_CRMA
TV_COMPS T V_ LUMA T V _CRMA
TV
2 R 42
4.99K_0402_1%
17 17 17 17 17 17 17
3 VD DCCL 3 VD D CDA C R T _ VSYNC C R T _ HS YNC CRT_B C RT_G C RT_R
3 VD DCCL 3 VD D CDA C R T _ V SYNC C R T _ HS YNC CRT_B C RT_G C RT_R
C26 C25 H23 G23 E23 D23 C22 B22 A21 B21 J22
PEG_M_TXP[0..15] 18
DDCCLK DDCDATA VSYNC HSYNC BLUE BLUE# GREEN GREEN# RED RED# CRT_IREF
C RT
B
B
2
R 210
2
R 211
2
R 212
C RT_R UMA@ 150_0603_1% C RT_G 1 UMA@ 150_0603_1% CRT_B 1 UMA@ 150_0603_1%
1
2 R 47
1
255_0402_1%
C ALISTOGA_FCBGA1466~D UMA_ GM@ +2.5VS +3VS
R215 2.2K_0402_5%
R216 2.2K_0402_5%
1
1
1
R 214 1 2.2K_0402_5% @ 0_0402_5% UMA@
UMA@
1
R 217 2.2K_0402_5% UMA@
UMA@
2
R 709 S
2
2
2
D
L D DC_CLK
2
E D I D_CLK_LCD
3
1
A
2
Q18 BSS138_SOT23 UMA@ +2.5VS
E D ID_CLK_LCD 38
L D DC_DATA
2
G G
A
3
Q17 BSS138_SOT23 UMA@ S
1
D
E D I D_DAT_LCD
E D ID_DAT_LCD 38
Security Classification
1
@ 0_0402_5%
Compal Secret Data
2005/10/06 Deciphered Date 2006/10/06
Title
2
R 710
Compal Electronics, Inc.
Calistoga (3/6)
R ev 0 .1 Sheet
1
Issued Date
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 9 of 48
5
4
3
2
1
+ VCCP
2
D13
D
@
+2.5VS
D
1 1
CH751H-40_SC76
U1 4 H + VCCP
VCC_SYNC
+2.5VS
H22 B30 C30 A30 AB41 AJ41 L41 N41 R41 V41 Y41 AC33 G41 H41 E21 F21 G21 B26 C39 AF1 A38 B39 AF2 H20 G20 E19 F19 C20 D20 E20 F20 AH1 AH2 A28 B28 C28 D21 H19 A23 B23 B25 AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14
1
2
R221 @ 10_0402_5%
+1.5VS
D12 @ CH751H-40_SC76
1
+
R220 @ 10_0402_5%
+3VS
2 2
C
C55 2200P_0402_50V7K
C297 2200P_0402_50V7K
C45 2200P_0402_50V7K
1
1
2
2
C296 0.47U_0603_16V4Z
M CH_A6
1
2
B
C299 0.1U_0402_16V4Z
1
C12 0.22U_0603_10V7K
MC H_D2 C10 0.47U_0603_16V4Z MCH_AB1
C98 10U_1206_6.3V6M
C104 0.1U_0402_16V4Z
C97 0.1U_0402_16V4Z
C67 0.1U_0402_16V4Z
2
1
2
1
1
1
1
C37 2200P_0402_50V7K
1
C301 0.1U_0402_16V4Z
AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1
VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51 VTT52 VTT53 VTT54 VTT55 VTT56 VTT57 VTT58 VTT59 VTT60 VTT61 VTT62 VTT63 VTT64 VTT65 VTT66 VTT67 VTT68 VTT69 VTT70 VTT71 VTT72 VTT73 VTT74 VTT75 VTT76
C306 0.1U_0402_16V4Z +2.5VS +1.5VS_PCIE
VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC2 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_LVDS VSSA_LVDS
10U_1206_6.3V6M C105
1
C108 +
1
1
10U_1206_6.3V6M
W=40 mils
220U_D2_4VM C107
R57 0_0805_5%
2
2
1
+1.5VS
2
2
+1.5VS_3GPLL +2.5VS
2
2
1
2
L4 C72 2200P_0402_50V7K +2.5VS_CRT DAC F BM-11-160808-601-T_0603
C99 0.1U_0402_16V4Z
+2.5VS
C91 220U_D2_4VM
1 1
+1.5VS_DPLLA
L16 CHB1608U301_0603
+1.5VS_DPLLB +1.5VS 0.1U_0402_16V4Z
L5 CHB1608U301_0603
1
C71 0.1U_0402_16V4Z
2
+2.5VS 330U_V_2.5VK_R9 C82 0.1U_0402_16V4Z
2
1
2
1
+1.5VS
330U_V_2.5VK_R9 C101
close pin G41 CRTDAC: Route caps within 250mil of Alviso. Route FB within 3" of Calistoga
1
+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL
1
1
+
1
+
C300
C100
1
1
2
2
2
2
UMA@
2
2
UMA@
+2.5VS +2.5VS
C
P O W E R
VCCA_MPLL VCCA_TVBG VSSA_TVBG VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 VCCD_HMPLL0 VCCD_HMPLL1 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCD_TVDAC VCCDQ_TVDAC VCCHV0 VCCHV1 VCCHV2 VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31
+1.5VS_MPLL 0.01U_0402_25V4Z 0.1U_0402_16V4Z +3VS_TVBG C102 +3VS_T VDACA C304 +3VS_T VDACA +3VS_T VDACA R206 +3VS
C24 4.7U_0805_10V4Z
C50 2.2U_0805_16V4Z
2
C46 0.1U_0402_16V4Z
1
C54 0.1U_0402_16V4Z
+3VS_T VDACA +3VS_T VDACA +3VS_T VDACA
1
1
1
1
C58 0.1U_0402_16V4Z
1
1
0_0603_5%
1
1
2
2
2
2
2
2
2
2
close pin A38
+1.5VS +3VS_TVBG R205 C711 4.7U_0805_10V4Z +3VS
2
C63 2200P_0402_50V7K C49 0.1U_0402_16V4Z
1
0_0805_5%
+1.5VS_T VDAC
1
1
1
+3VS
2
2
2
1
C298 10U_1206_6.3V6M
C302 0.1U_0402_16V4Z
1
2
2
C94 0.22U_0603_10V7K
PCI-E/MEM/PSB PLL decoupling
+1.5VS_3GPLL R56 0_0603_5% +1.5VS +1.5VS_TVDAC R213 0_0603_5% +1.5VS
B
+1.5VS
1
2
1
2
1
1
2
1
2
2
2
2
2
2
2 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40
CALIST OGA_F CBGA1466~D UMA_GM@
@
@
+1.5VS_MPLL
R16 0_0603_5%
+1.5VS_HPLL +1.5VS
R17 0_0603_5%
+1.5VS
45mA Max.
0.1U_0402_16V4Z
2
10U_1206_6.3V6M
1
45mA Max.
0.1U_0402_16V4Z
2
10U_1206_6.3V6M
1
+1.5VS
1
C13
1
C8
1
C14
1
C9
2
A
2
2
2
A
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
T itle
Compal Electronics, Inc.
Calistoga (4/6)
Rev 0.1 Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL A ND TRA DE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DE P A RTME NT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number C ustom I G L 5 0/51 LA-3771 Date: , 08, 2006 10 of 48
5
4
3
2
1
Strap Pin Table
CFG[3:17] have internal pull up
+VCCP U1 4 F +1.5VS + VCCP U1 4G + 1.8V
CFG[19:18] have internal pull down
D
1
1
1
2
2
2
1
1
1
2
2
2
C
1
+
2
1
+
2
B
AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16
VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72 VCC100 VCC101 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC110
VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57 VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12
AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17
+ 1.8V
C93 0.47U_0603_16V4Z
+ VCCP
VCC_SM100 VCC_SM101 VCC_SM102 VCC_SM103 VCC_SM104 VCC_SM105 VCC_SM106 VCC_SM107
AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1
C15 0.47U_0603_16V4Z C17 0.47U_0603_16V4Z
C ALISTOGA_FCBGA1466~D UMA_ GM@
1
1
2
2
Place near pin AV1 & AJ1
AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99
P O W E R
VCC_SM0 VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4 VCC_SM5 VCC_SM6 VCC_SM7 VCC_SM8 VCC_SM9 VCC_SM10 VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15 VCC_SM16 VCC_SM17 VCC_SM18 VCC_SM19 VCC_SM20 VCC_SM21 VCC_SM22 VCC_SM23 VCC_SM24 VCC_SM25 VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36 VCC_SM37 VCC_SM38 VCC_SM39 VCC_SM40 VCC_SM41 VCC_SM42 VCC_SM43 VCC_SM44 VCC_SM45 VCC_SM46 VCC_SM47 VCC_SM48 VCC_SM49 VCC_SM50 VCC_SM51 VCC_SM52 VCC_SM53 VCC_SM54 VCC_SM55 VCC_SM56 VCC_SM57 VCC_SM58 VCC_SM59 VCC_SM60 VCC_SM61 VCC_SM62 VCC_SM63 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99
AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6
MC H_AT41 MC H_ AM41 C106 0.47U_0603_16V4Z C103 0.47U_0603_16V4Z
CFG[2:0] CFG5
1
011 001
= 667MT/s FSB = 533MT/s FSB
0 = DMI x 2 1 = DMI x 4 * (Default) 0 = Reserved 1 = Mobile Yonah CPU*(Default) 0 = Lane Reversal Enable 1 = Normal Operation (Default)* 0 = Reserved 1 = Calistoga 00 01 10 11 = = = =
D
1
CFG7 CFG9 CFG6 PSB 4X CLK Enable
C69 0.22U_0603_10V7K
C61 0.22U_0603_10V7K
C25 0.22U_0603_10V7K
2
2
*
Place near pin AT41 & AM41 CFG[13:12]
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation * (Default)
CFG16
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled * (Default) 10 = 1.05V* (Default) 01 = 1.5V 0 = Normal Operation * (Default) 1 = DMI Lane Reversal Enable 0 = No SDVO Device Present * (Default) 1 = SDVO Device Present 0 = Only PCIE or SDVO is operational. * (Default) 1 = PCIE/SDVO are operating simu.
C
C48 10U_1206_6.3V6M
C95 10U_1206_6.3V6M
C31 1U_0603_10V4Z
CFG10 CFG18 CFG19 SDVO_CTRLDATA
P O W E R
1
C21
1
C20
1
C86
1
C47
2
2
2
2
CFG20 (PCIE/SDVO select)
C27 0.47U_0603_16V4Z
C18 220U_D2_4VM
1
2
7 7
C F G5 C F G7 C F G9 C F G11 C F G12 C F G13 C F G16
R 32 R 40 R 37 R 35 R 34 R 38 R 33
1 1 1 1 1 1 1
2
@ 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2 @ 2 @ 2 @ 2 @ 2 @ 2
Place near pin BA23
C44 10U_1206_6.3V6M C78 10U_1206_6.3V6M C59 @ 220U_D2_4M_R45
7 7 7
1
+ 7 7
1
1
C79 @ 220U_D2_4VM
@ 2.2K_0402_5%
2
2
2
+3VS
B
1
7 7 7
C F G18 C F G19 C F G20
R 48 R 50 R 51
1 1 1
2 @ 1K_0402_5% 2 @ 1K_0402_5% 2 @ 1K_0402_5%
2
Place near pin BA15
A
C ALISTOGA_FCBGA1466~D UMA_ GM@
A
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
Title
Compal Electronics, Inc.
Calistoga (5/6)
R ev 0 .1 Sheet
1
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 11 of 48
5
4
3
2
1
U 14I
U1 4 J
D
C
B
AC41 AA41 W41 T41 P41 M41 J41 F41 AV40 AP40 AN40 AK40 AJ40 AH40 AG40 AF40 AE40 B40 AY39 AW39 AV39 AR39 AN39 AJ39 AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39 H39 G39 F39 D39 AT38 AM38 AH38 AG38 AF38 AE38 C38 AK37 AH37 AB37 AA37 Y37 W37 V37 T37 R37 P37 N37 M37 L37 J37 H37 G37 F37 D37 AY36 AW36 AN36 AH36 AG36 AF36 AE36 AC36 C36 B36 BA35 AV35 AR35 AH35 AB35 AA35 Y35 W35 V35 T35 R35 P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34 AK34 AG34 AF34
VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99
P O W E R
VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199
AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21
AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11 J11 D11 B11 AV10 AP10 AL10 AJ10
VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS265 VSS264 VSS263 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279
P O W E R
VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS292 VSS291 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360
AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1
D
C
B
C AL ISTOGA_FCBGA1466~D UMA_ GM@
A
C ALISTOGA_FCBGA1466~D UMA_ GM@
A
Security Classification Issued Date 2005/10/06
Compal Secret Data
Deciphered Date 2006/10/06
Title
Compal Electronics, Inc.
Calistoga (6/6)
R ev 0 .1 Sheet
1
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 12 of 48
5
4
3
2
1
8 D D R_A_DQS#[0..7] 8 D D R _A_D[0..63] 8 D D R _ A_DM[0..7] 8 D D R _A_DQS[0..7]
Layout Note: +DDR_MCH_REF trace width and spacing is 20/20.
+ 1.8V
+1.8V
+ 1.8V + D D R_MCH_REF1 JP 3 2.2U_0805_16V4Z 0.1U_0402_16V4Z + D D R _MCH_REF1 14
D D R _A_D4 D D R _A_D1 D D R_A_DQS#0 D D R_A_DQS0 D D R _A_D2 D D R _A_D3 D D R _A_D8 D D R _A_D14
8 D D R _ A_MA[0..13]
R 86 100_0402_1% 14 + D D R_MCH_REF1 + D D R_MCH_REF1 C149 0.1U_0402_16V4Z
1
2
D
Layout Note: Pla c e near JP41
1
R 87 100_0402_1% D D R_A_DQS#1 D D R_A_DQS1 D D R _A_D9 D D R _A_D15
2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
R13 10K_0402_5%
D D R _A_D6 D D R _A_D0 D D R _A_DM0 D D R _A_D5 D D R _A_D7 D D R _A_D13 D D R _A_D12 D D R _A_DM1 M_ CLK_DDR0 M_ CLK_DDR#0 D D R _A_D11 D D R _A_D10
1
1
C145
C134
1
2
2
D
M_ CLK_DDR0 7 M_ CLK_DDR#0 7
+1.8V D D R _A_D16 D D R _A_D17 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 2.2U_0805_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z D D R_A_DQS#2 D D R_A_DQS2 C83 D D R _A_D18 D D R _A_D19 D D R _A_D29 D D R _A_D24 D D R _A_DM3 1 4,33 EC_P80_DATA D D R _A_D26 D D R _A_D27
C
2
D D R _A_D20 D D R _A_D21 PM_EXTTS#0 7 ,14
1
1
1
1
1
1
1
1
1
D D R _A_DM2 D D R _A_D23 D D R _A_D22 D D R _A_D28 D D R _A_D25 D D R_A_DQS#3 D D R_A_DQS3 D D R _A_D31 D D R _A_D30 D D R _ CKE1_DIMMA
C89
C87
C28
C92
C30
C85
C57
C43
2
2
2
2
2
2
2
2
2
7 D D R _ CKE0_DIMMA 1 4,33 EC_P80_CLK 8 D DR_A_BS#2
D D R _ CKE0_DIMMA
D D R _ C KE1_DIMMA 7
C
D DR_A_BS#2 D D R _A_MA12 D D R _A_MA9 D D R _A_MA8 D D R _A_MA5 D D R _A_MA3 D D R _A_MA1 D D R _A_MA10 D DR_A_BS#0 D D R_A_W E# D D R _A_CAS# D D R _ C S1_DIMMA# M_ODT1 D D R _A_D37 D D R _A_D36 D D R_A_DQS#4 D D R_A_DQS4 D D R _A_D35 D D R _A_D32 D D R _A_D40 D D R _A_D44 D D R _A_DM5 D D R _A_D41 D D R _A_D46
Layout Note: Pla c e one cap close to every 2 pullup resistors terminated to +0.9VS
D D R _A_MA11 D D R _A_MA7 D D R _A_MA6 D D R _A_MA4 D D R _A_MA2 D D R _A_MA0 D DR_A_BS#1 D D R _A_RAS# D D R _ C S0_DIMMA# M_ODT0 D D R _A_MA13 D DR_A_BS#1 8 D D R _A_RAS# 8 D D R _ C S0_DIMMA# 7 M_ODT0 7
+0.9VS
8 8
D DR_A_BS#0 D D R_A_W E#
8 D D R _A_CAS# 7 D D R _ C S1_DIMMA# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 7 M_ODT1
1
1
1
1
1
1
1
1
1
1
1
1
1
D D R _A_D39 D D R _A_D38 D D R _A_DM4 D D R _A_D34 D D R _A_D33 D D R _A_D45 D D R _A_D43
B
2
C74
2
C66
2
C60
2
C51
2
C42
2
C34
2
C40
2
C53
2
C64
2
C77
2
C39
2
C70
2
C33
B
D D R_A_DQS#5 D D R_A_DQS5 D D R _A_D47 D D R _A_D42 D D R _A_D52 D D R _A_D53 M_ CLK_DDR1 M_ CLK_DDR#1 D D R _A_DM6 D D R _A_D51 D D R _A_D55 D D R _A_D57 D D R _A_D56 D D R_A_DQS#7 D D R_A_DQS7 D D R _A_D62 D D R _A_D63 M_ CLK_DDR1 7 M_ CLK_DDR#1 7
+0.9VS RP1 D D R_A_W E# D D R _A_CAS# D D R _ C S1_DIMMA# M_ODT1 R P2
1 2 3 4
8 7 6 5
8 7 6 5
1 2 3 4
D D R _A_RAS# D D R _ C S0_DIMMA# M_ODT0 D D R _A_MA13
Layout Note: P l ace t hese r esi st or cl osel y JP41,all t r ace l engt h M ax=1.5"
D D R _A_D49 D D R _A_D48
D D R_A_DQS#6 D D R_A_DQS6 D D R _A_D54 D D R _A_D50 D D R _A_D61 D D R _A_D60 D D R _A_DM7 D D R _A_D59 D D R _A_D58 14,15 C LK_SMBDATA 1 4,15 CLK_SMBCLK C LK_SMBDATA CLK_SMBCLK +3VS C7
56_0804_8P4R_5%
56_0804_8P4R_5% R P6
56_0402_5% D DR_A_BS#0 R 39 D D R _A_MA10 R 43
1 1
2 2
56_0402_5%
5 6 7 8
4 3 2 1
D DR_A_BS#1 D D R _A_MA0 D D R _A_MA2 D D R _A_MA4
56_0804_8P4R_5% R P7 D D R _A_MA1 D D R _A_MA3 D D R _A_MA5 D D R _A_MA8
A
RP9
56_0804_8P4R_5% R P10 D D R _A_MA9 D D R _A_MA12 D DR_A_BS#2 D D R _ CKE0_DIMMA
56_0804_8P4R_5% 0 . 1 U_0402_16V4Z
F OX_ASOA426-M2RN-7F ME@
R15 10K_0402_5%
4 3 2 1
5 6 7 8
5 6 7 8
4 3 2 1
D D R _A_MA6 D D R _A_MA7 D D R _A_MA11 D D R _ CKE1_DIMMA
1
1
A
2
4 3 2 1
5 6 7 8
Top side
Security Classification Issued Date 2005/10/06
2
2
SO-DIMM A
2006/10/06
56_0804_8P4R_5%
Compal Secret Data
Deciphered Date
Title
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
R ev 0 .1 Sheet
1
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size D ocum ent Num ber C u stom I G L50/51 LA-3771 D ate: , 08, 2006 13 of 48
5
4
3
2
1
8 D D R_B_DQS#[0..7] 8 D D R _B_D[0..63] 8 D D R _B_DM[0..7] 8 D D R_B_DQS[0..7] 8 D D R _ B_MA[0..13] D D R_B_D0 D D R_B_D1 D DR_B_DQS#0 D DR_B_DQS0
D
+ 1.8V
+1.8V
+ D D R_MCH_REF1 J P4 2.2U_0805_16V4Z 0.1U_0402_16V4Z
+ D D R_MCH_REF1 13
Layout Note: Pla c e near JP42
D D R_B_D2 D D R_B_D3 D D R_B_D8 D D R_B_D9 D DR_B_DQS#1 D DR_B_DQS1 D D R_B_D10 D D R_B_D11
+ 1.8V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
D D R_B_D5 D D R_B_D4 D D R_B_DM0 D D R_B_D6 D D R_B_D7 D D R_B_D12 D D R_B_D13 D D R_B_DM1 M_ CLK_DDR3 M_ CLK_DDR#3 D D R_B_D14 D D R_B_D15
1
C146
1
C135
2
2
D
M_ CLK_DDR3 7 M_ CLK_DDR#3 7
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_