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Compal Confidential
2 2




ICL50/51, ICK70/71 Schematics Document
Intel Merom Processor with Crestline(PM965/GM965) + DDRII + ICH8M
(With ATI MXM/B)

3 2007-4-20 3




REV:1A




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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/04/04 Deciphered Date 2008/04/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICL50/ICK70 M/B LA-3551P Schematic
Date: Monday, April 23, 2007 Sheet 1 of 48
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A B C D E




Compal Confidential
Intel Merom Processor Thermal Sensor Clock Generator
Fan Control
Model Name : ICL50/51, ICK70/ICK71 page 36
ADM1032 ICS9LPRS365
uPGA-478 Package page 4 page 16
File Name : LA-3551P
(Socket P) page 4,5,6
1 1
FSB
H_A#(3..35) 667/800MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 18 page 18 page 19

LVDS Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Crestline
Dual Channel BANK 0, 1, 2, 3 page 14,15
DVI LVDS SDVO
1.8V DDRII 533/667
uFCBGA-1299
PCI-Express page 7,8,9,10,11,12,13


MXM II VGA/B
DMI C-Link USB conn x2 Bluetooth CMOS
page 17
USB port 0, 2 Conn Camera
PCI-Express
2
Intel ICH8-M 3.3V 48MHz USB
2




3.3V 24.576MHz/48Mhz HD Audio
PCI BUS
3.3V 33 MHz 3.3V ATA-100 IDE
IDSEL:AD20 BGA-676
(PIRQA#,
S-ATA
New Card MINI Card x2 LAN(GbE) GNT#2, page 20,21,22,23
REQ#2)
Socket WLAN, TV-Tuner BCM5787M CDROM MDC 1.5 HDA Codec
page 29 page 28 page 26 ALC268
Card Reader port 0, 1 Conn. 24
page
Conn 33
page page 34
R5C833
page 25

RJ45 SATA HDD
page 26
Conn. page 24
1394 5 in 1 Audio AMP
Conn. socket page 35
page 25 page 25 LPC BUS
3 3
Phone Jack x3
BTN/B Conn. ENE KB926 page 35
RTC CKT. page 30
page 32
page 33



Power On/Off CKT. LED/B Conn. Touch Pad Int.KBD
page 32 page 32 page 32
page 33


USB&TV/B Conn. EC I/O Buffer BIOS
DC/DC Interface CKT. page 32 page 32
USB port 4, 6
page 37 page 29

CIR
Power Circuit DC/DC AUDIO/B Conn. page 29
4
page 38,39,40,41 w/Woofer(ICK70) 4
42,43,44,45 page 35



Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICL50/ICK70 M/B LA-3551P Schematic
Date: Thursday, April 19, 2007 Sheet 2 of 48
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail for SB ON ON X 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW 5V always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VS 5V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VSB VSB always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
2 2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 Discrete PM@
1394/Card Reader AD16 0 PIRQE
1 0.2 UMA GM@
PIRQG
2 0.3
3 1.0
4 1A
5
6
7


EC SM Bus1 address EC SM Bus2 address
3 3
Device Address Device Address
Smart Battery 0001 011X b ADI ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b
GMT G781-1 1001 101X b




ICH8M SM Bus address
Device Address

Clock Generator 1101 001Xb
(ICS9LPRS365)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICL50/ICK70 M/B LA-3551P Schematic
Date: Monday, April 23, 2007 Sheet 3 of 48
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H_A#[3..35]
7 H_A#[3..35]
H_REQ#[0..4]
7 H_REQ#[0..4]
H_RS#[0..2]
7 H_RS#[0..2]
JP22A
H_A#3 J4 H1 H_ADS# 7
A[3]# ADS#




ADDR GROUP 0
H_A#4 L5 E2 H_BNR# 7
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# 7 D
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 A[12]#




CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# 21
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 7
7 H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# 7
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# 7
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# 7
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 7
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4
ADDR GROUP 1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#



XDP/ITP SIGNALS
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
H_A#23 A[22]# BPM[3]#
U1 A[23]# PRDY# AC2
H_A#24 R4 AC1 XDP_BPM#5
H_A#25 A[24]# PREQ# XDP_TCK
T5 A[25]# TCK AC5
C H_A#26 T3 AA6 XDP_TDI C
H_A#27 A[26]# TDI
W2 A[27]# TDO AB3
H_A#28 W5 AB5 XDP_TMS
H_A#29 A[28]# TMS XDP_TRST#
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# XDP_DBRESET# 22
H_A#31 A[30]# DBR#
V4 A[31]#
H_A#32 W3 +1.05VS
H_A#33 A[32]#
AA4 A[33]# THERMAL
H_A#34 AB2
H_A#35 A[34]# H_PROCHOT#
AA3 A[35]# PROCHOT# D21
V1 A24 THERMDA
7 H_ADSTB#1 ADSTB[1]# THERMDA
B25 THERMDC XDP_TDI R59 1 2 150_0402_1%
THERMDC
21 H_A20M# A6 A20M#
ICH




21 H_FERR# A5 FERR# THERMTRIP# C7 H_THERMTRIP# 8,21 left NC if no ITP
21 H_IGNNE# C4 IGNNE# XDP_TMS R63 1 2 39_0402_1% 39Ohm
21 H_STPCLK# D5 STPCLK#
C6 H CLK XDP_BPM#5 R46 1 2 54.9_0402_1%
21 H_INTR LINT0
21 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 16
21 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 16
M4 H_PROCHOT# R114 2 1 56_0402_5%
RSVD[01]
N5 RSVD[02]
T2 H_IERR# R113 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
RESERVED




B2 RSVD[05] Layout Note:
C3 RSVD[06]
D2 THERMDA&THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
B
D22 RSVD[08] THERMDA_R&THERMDC_R Trace / Space = 10 / 10 mil XDP_TRST# R57 649_0402_1% B
D3 RSVD[09] 2 1
F6 RSVD[10] XDP_TCK R37 1 2 27_0402_5%


Merom Ball-out Rev 1a
CONN@


+3VS
C485
0.1U_0402_16V4Z
1 2


BSEL2 BSEL1 BSEL0 BCLK THERMDA 1 2
R546 0_0402_5% U21
0 1 0 200 1 VDD SCLK 8 EC_SMB_CK2 30
1
C484 THERMDA_R 2 7
D+ SDATA EC_SMB_DA2 30
0 1 1 166 2200P_0402_50V7K THERMDC_R 3 D- ALERT# 6
2
4 THERM# GND 5
THERMDC 1 2
R547 0_0402_5%
ADM1032ARMZ_MSOP8
A A
For Next Generation CUP (45nm)



Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/12/25 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (1/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICL50/ICK70 M/B LA-3551P Schematic
Date: Monday, April 23, 2007 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1




H_D#[0..63] JP22C
H_D#[0..63] 7
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JP22B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12
H_D#3 G22 V26 H_D#35 A15 AC13
D[3]# D[35]# VCC[006] VCC[073]




DATA GRP 0
H_D#4 F23 V23 H_D#36 A17 AC15
H_D#5 D[4]# D[36]# H_D#37 VCC[007] VCC[074]
G25 D[5]# D[37]# T22 A18 VCC[008] VCC[075] AC17
H_D#6 E25 U25 H_D#38 A20 AC18
H_D#7 D[6]# D[38]# H_D#39 VCC[009] VCC[076]
E23 D[7]# D[39]# U23 B7 VCC[010] VCC[077] AD7
H_D#8 K24 Y25 H_D#40 B9 AD9




DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[011] VCC[078]
G24 D[9]# D[41]# W22 B10 VCC[012] VCC[079] AD10
H_D#10 J24 Y23 H_D#42 B12 AD12
H_D#11 D[10]# D[42]# H_D#43 VCC[013] VCC[080]
J23 D[11]# D[43]# W24 B14 VCC[014] VCC[081] AD14
H_D#12 H22 W25 H_D#44 B15 AD15
H_D#13 D[12]# D[44]# H_D#45 VCC[015] VCC[082]
F26 D[13]# D[45]# AA23 B17 VCC[016] VCC[083] AD17
H_D#14 K22 AA24 H_D#46 B18 AD18
H_D#15 D[14]# D[46]# H_D#47 VCC[017] VCC[084]
H23 D[15]# D[47]# AB25 B20 VCC[018] VCC[085] AE9
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 C9 VCC[019] VCC[086] AE10
7 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 7 C10 VCC[020] VCC[087] AE12
7 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 7 C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]




DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14
H_D#22 D[21]# D[53]# H_D#54 VCC[029] VCC[096]
L22 D[22]# D[54]# AD20 D15 VCC[030] VCC[097] AF15
H_D#23 M23 AE22 H_D#55 D17 AF17
H_D#24 D[23]# D[55]# H_D#56 VCC[031] VCC[098]
P25 D[24]# D[56]# AF23 D18 VCC[032] VCC[099] AF18
C H_D#25 P23 AC25 H_D#57 E7 AF20