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A B C D E
Compal confidential Block Diagram
Model Name : CY23 LA-1281 Rev:2.0
1 1
INTEL FC-PGA370
APICCLK
CRT
om
HCLK_CPU
Connector Page 2,3
page 14
HA#(3..31) HD#(0..63) Y1
14.318MHZ
TV_OUT 14MOSC
Connector Twister PN-133T
HCLK_NB
Clock Generator 14MCRT/14.3M_TV
.c
page 13 PCLK_NB
PCLK_1394
(VT8606)PCIGNT#/PCIREQ#
DCLKWR
ICS 9248-195
page 11 PCLK_PCM
page 4,5,6 PIRQA# DCLKO
op
PCLK_MINI
CLK_SDRAM0
MA(0..13)
TFT Panel
MD(0..63)
CLK_SDRAM2,3
Interface
2 2
page 14
pt
On Board
AD(0..31)
Memory Damping 64/128MB SO-DIMM 0
Resistor (Bank 2,3)
page 6 (Bank 0) page 8
La
PCLK_SB
page 7
PCI BUS
ia
USB Port 0,1
Mini PCI CardBus FIR DIRECT
IEEE 1394 VT686B 48MHZ
CD-PLAY
Socket OZ6933
as
PIRQB#/PIRQD#
PIRQC#
GNT#2/REQ#2 AC97 page 25
page 9,10
14MOSC
FUNCTION
GNT#0/REQ#0
GNT#1/REQ#1
PIRQA#/PIRQB#
GNT#3/REQ#3
AD24
Interface IDE CHANNEL 1 page 18
page 23 AD27/AD28 page 15 AD15 page 29
page 27
3
ah S A ( 0..15)
Pull Up/Down 3
Slot 0& 1 Slot 0 S D ( 0..15) Resistor
page 29
page 16 ISA BUS IDE Damping page 12
Power On/Off Resistor
Reset Circuit
.R
page 17
page 28
KeyBoard
87570 IDE Connector PIO
w
page 20 page 24
(FDD/HDD/CR-ROM)
DC/DC Interface
RTC Battery page 19
w
page 22
I/O Buffer KBD
w
page 21 page 21
4 4
Power Circuit BIOS Touch Pad
DC/DC page 21 page 26
page
30,31,32,33 Compal Electronics , Inc.
Title
T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC,M/BLA-1281
PROPRIETARY NOTE T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B 2A
401202
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月04, 2002 Sheet 1 of 34
A B C D E
A B C D E
+5VS
HA#[3..31] HD#[0..63]
4 HA#[3..31] U38A HD#[0..63] 4
1
HA#3 AK8 W1 HD#0 R90
HA#4 A3# D0# HD#1 200
AH12
FC-PGA2 T4
1
HA#5 AH8 A4# D1# N1 HD#2 C79
HA#6 AN9 A5# D2# M6 HD#3 .1UF
HA#7 AL15 A6# D3# U1 HD#4
A7# D4#
2
2
HA#8 AH10 S3 HD#5 1617VCC
HA#9 A8# D5# HD#6
AL9 T6
HA#10 AH6 A9# D6# J1 HD#7 U6
VCMOS VCMOS +3VS HA#11 AK10 A10# D7# S1 HD#8 C80 1 16 from 87570
1
4 4
HA#12 AN5 A11# D8# P6 HD#9 2 NC NC 15
HA#13 AL7 A12# D9# Q3 HD#10 2200PF THERMDA 3 VCC STBY 14
A13# D10# DXP SMBCLK SMC 18,20,24
HA#14 AK14 M4 HD#11 THERMDC 4 13
2
2
HA#15 AL5 A14# D11# Q1 HD#12 5 DXN NC 12
2
2
A15# D12# NC SMBDATA SMD 18,20,24
R64 R67 R73 HA#16 AN7 L1 HD#13 6 11
A16# D13# ADD1 ALERT
om
1.5K 1.5K 10K HA#17 AE1 N3 HD#14 7 10
HA#18 Z6 A17# D14# U3 HD#15 8 GND ADD0 9
HA#19 A18# D15# HD#16 GND NC
AG3 H4
HA#20 AC3 A19# D16# R4 HD#17 MAX1617 ATF# 21
1
21
1
HA#21 AJ1 A20# D17# P4 HD#18
HA#22 AE3 A21# D18# H6 HD#19
FERR#1.5 3 1 HA#23 AB6 A22# D19# L3 HD#20
FERR# 9 A23# D20#
HA#24 AB4 G1 HD#21
1
1
HA#25 AF6 A24# D21# F8 HD#22 R89 R96
HA#26 Y3 A25# D22# G3 HD#23 1K
Q5 A26# D23# 1K
HA#27 AA1 REQUEST DATA K6 HD#24
.c
HA#28 AK6 A27# D24# E3 HD#25 1 2 PWRGD_CPU 1 2
PHASE PHASE 9,27,32 VR_POK +2.5V_CLK
FDV301N HA#29 A28# D25# HD#26 R27 180
Z4 SIGNALS SIGNALS E1
2
2
HA#30 AA3 A29# D26# F12 HD#27 D7 1 2
HA#31 AD4 A30# D27# A5 HD#28 RB751V R395 @1.8K
X6 A31# D28# A3 HD#29 +5VS CPU_IO
A32# D29#
op
AC1 J3 HD#30
A33# D30# HD#31
W3 C5
AF4 A34# D31# F6 HD#32
A35# D32# C1 HD#33
HREQ#0 AK18 D33# C7 HD#34
4 HREQ#0 REQ0# D34#
HREQ#1 AH16 B2 HD#35 BREQ0# 8 1 HA#5 8 1 HD#39 1 8 HD#1 8 1
4 HREQ#1 REQ1# D35#
HREQ#2 AH18 C9 HD#36 RS#2 7 2 HA#13 7 2 HD#36 2 7 HD#5 7 2
4 HREQ#2 REQ2# D36#
3 HREQ#3 AL19 A9 HD#37 DBSY# 6 3 HA#10 6 3 HD#37 3 6 HD#8 6 3 3
4 HREQ#3 REQ3# D37#
pt
HREQ#4 AL17 D8 HD#38 DRDY# 5 4 HA#12 5 4 HD#38 4 5 HD#17 5 4
4 HREQ#4 REQ4# D38#
AN23 D10 HD#39
RP# D39# C15 HD#40 RP2 RP6 RP43 RP25
ADS# D40# HD#41 @8P4R-56 @8P4R-56 @8P4R-56 @8P4R-56
AN31 D14
4 ADS# ADS# D41# D12 HD#42 HA#16 8 1 HD#27 1 8 HD#0 8 1
D42# A7 HD#43 HA#15 7 2 HD#42 2 7 HD#4 7 2
D43#
La
AK24 A11 HD#44 HA#28 6 3 HD#45 3 6 HD#15 6 3
AL11 AERR# ERROR D44# C11 HD#45 HA#31 5 4 HD#44 4 5 HD#6 5 4
AP0# D45# RP26
AN13 SIGNALS A21 HD#46 IGNNE# 1 8
AP1# D46# VCMOS
V4 A15 HD#47 A20M# 2 7 RP14 RP44 RP24
B36 BERR# D47# A17 HD#48 INTR 3 6 @8P4R-56 @8P4R-56 @8P4R-56
AE35 BINIT# D48# C13 HD#49 NMI 4 5 HA#19 8 1 HD#40 1 8 HD#12 8 1
IERR# D49# C25 HD#50 HA#25 7 2 HD#41 2 7 HD#10 7 2
BREQ0# D50# HD#51 8P4R-150 HA#22 HD#49 HD#9
AN29 A13 6 3 3 6 6 3
4 BREQ0# BR0# D51#
ia
BPRI# AN17 D16 HD#52 PRDY# 1 2 HA#17 5 4 HD#51 4 5 HD#18 5 4
4 BPRI# BPRI# D52#
BNR# AH14 ARBITRATION A23 HD#53 R151 150
4 BNR# BNR# D53#
LOCK# AK20 PHASE C21 HD#54 SLP# 1 2 RP20 RP45 RP28
4 HLOCK# LOCK# D54#
X2 SIGNALS C19 HD#55 R54 150 @8P4R-56 @8P4R-56 @8P4R-56
BR1#/RSVD* D55# HD#56 CPUINIT# HA#23 HD#48 HD#14
C27 1 2 8 1 1 8 8 1
HIT# AL25 D56# A19 HD#57 R61 150 HA#24 7 2 HD#63 2 7 HD#2 7 2
4 HIT#
as
HITM# AL23 HIT# SNOOP PHASE D57# C23 HD#58 STPCLK# 1 2 HA#20 6 3 HD#52 3 6 HD#3 6 3
4 HITM# HITM# D58#
DEFER# AN19 SIGNALS C17 HD#59 R53 150 HA#27 5 4 HD#47 4 5 HD#11 5 4
4 DEFER# DEFER# D59# A25 HD#60 FLUSH# 1 2
D60# HD#61 R57 150 RP19 RP46 RP27
G33 A27
E37 BP2# RESPONSE D61# E25 HD#62 SMI# 1 2 @8P4R-56 @8P4R-56 @8P4R-56
C35 BP3# D62# F16 HD#63 R47 150 HA#30 8 1 HD#46 1 8 HD#13 8 1
PHASE
E35 BPM0# D63# PREQ# 1 2 HA#29 7 2 HD#55 2 7 HD#20 7 2
BPM1# SIGNALS
HTRDY# AN25 R127 330 HA#18 6 3 HD#57 3 6 HD#7 6 3
2 4
4
4
HTRDY#
RS#0
RS#1
RS#0
RS#1
AH26
AH22
TRDY#
RS0#
ah DEP0#
C33
C31
HA#26 5 4 HD#59 4 5 HD#16 5 4 2
RS#2 AK28 RS1# DEP1# A33 CPURST# 1 2 RP22 RP47 RP31
4 RS#2 RS2# DEP2#
AC37 A31 R26 56.2_1% CPU_IO @8P4R-56 @8P4R-56 @8P4R-56
RSP# DEP3# E31 ADS# 1 2 HREQ#2 8 1 HD#50 1 8 HD#19 8 1
A20M# DEP4# R7 @56.2_1% HREQ#0 HD#58 HD#24
AE33 C29 7 2 2 7 7 2
3 A20M# A20M# DEP5#
FERR#1.5 AC35 PC E29 HREQ#4 6 3 HD#53 3 6 HD#30 6 3
IGNNE# AG37 FERR# DEP6# A29 BPRI# 5 4 HD#54 4 5 HD#22 5 4
3 IGNNE# COMPATIBILITY
.R
PWRGD_CPU AK26 IGNNE# DEP7#
PWRGOOD SIGNALS
SMI# AJ35 AL27 DBSY# RP9 RP48 RP30
9 SMI# SMI# DBSY# DBSY# 4
AN27 DRDY# @8P4R-56 @8P4R-56 @8P4R-56
DRDY# DRDY# 4
AN37 RS#1 8 1 HD#61 1 8 HD#43 1 8
1 8 AN35 TDO DIAGNOSTIC HLOCK# 7 2 HD#56 2 7 HD#34 2 7
2 7 AK32 TDI HREQ#3 6 3 HD#62 3 6 HD#32 3 6
& TEST
3 6 AN33 TMS DEFER# 5 4 HD#60 4 5 HD#28 4 5
TRST# SIGNALS
w
4 5 PWRGD_CPU AL33
6 BSEL0 TCK
PREQ# J37 J33 RP10 RP49 RP42
6,11 BSEL1 PREQ# PICCLK APICCLK 11
RP98 PRDY# A35 L35 @8P4R-56 @8P4R-56 @8P4R-56
PRDY# PICD1 VCMOS
2 1 R6 1K 8P4R-1K AJ33 J35 R117 150 RS#0 8 1 HA#4 8 1 HD#31 1 8
+3VS 2 1 R5 1K