Text preview for : ACER ASPIRE 5738.pdf part of Acer Aspire 5738 Aspire 5738
Back to : ACER ASPIRE 5738.pdf | Home
5
4
3
2
1
JV50 Block Diagram
D
Project code: 91.4CG01.001 PCB P/N : 48.4CG01.0SA REVISION : 08245-SA
SYSTEM DC/DC
ISL62392
INPUTS
5V_S5(6A) 3D3V_S5(7A) DCBATOUT 5V_AUX_S5 3D3V_AUX_S5
42 OUTPUTS
CLK GEN.
ICS9LPRS365B
3
Mobile CPU
Penryn
4, 5
SMSC
EMC2102
34
TOP GND S S
PCB STACKUP
SYSTEM DC/DC
L1 L2 L3 L4 L5 L6
TPS51124
INPUTS
DCBATOUT
43 OUTPUTS
D
1D05V_S0(9A) 1D5V_S3(12A)
HOST BUS
667/800/[email protected]
VRAM 64MbX16X4 512M
GND BOTTOM
RT9026
1D5V_S3
44
DDR_VREF_S3 (1.2A)
DDR3
800/1066 16,17 MHz
Cantiga
AGTL+ CPU I/F DDR Memory I/F INTEGRATED GRAHPICS LVDS, CRT I/F
PCIex16
VGA
N10M-GE-1
52~57
HDMI
20 RT9018
1D5V_S3
44
1D1V_S0(2A)
DDR3
800/1066 16,17 MHz
LCD
18
6,7,8,9,10,11
CRT
19
TPS51117
DCBATOUT FBVDD(4A)
45
X4 DMI 400MHz
C-Link0 USB
CardBus
RTS5159
31
MS/MS Pro/xD /MMC/SD
CHARGER
ISL88731A INPUTS 47 OUTPUTS
C
C
ICH9M
LINE IN
29
6 PCIe ports PCI/PCI BRIDGE ACPI 2.0 4 SATA 12 USB 2.0/1.1 ports ETHERNET (10/100/1000MbE)
DCBATOUT
BT+
Giga LAN
BCM5764 25
LAN
TXFM
26
RJ45
26
CPU DC/DC
ISL6266A INPUTS
DCBATOUT
41 OUTPUTS
VCC_CORE 38A
Int MIC
18
Codec
ALC888S
27
AZALIA
High Definition Audio LPC I/F Serial Peripheral I/F Matrix Storage Technology(DO) Active Managemnet Technology(DO)
New Card
32
PWR SW TPS2231 32
VGA_CORE
RT8202A INPUTS
DCBATOUT
MIC In
29
47 OUTPUTS
VGA_CORE 13A
PCIe
Mini 1 Card Wire LAN 33 Mini 2 Card 33 3G card
INT.SPKR
1.5W
12,13,14,15
OP AMP
MAX9789A
30
GFXCORE
ISL6263A 46 OUTPUTS
VCC_GFXCORE (7A)
B
B
29
LPC BUS LINE OUT
29
INPUTS
SATA
USB
Mini USB Blue Tooth 23
RJ11
MODEM MDC Card
30
HDD SATA 21
Camera
USB 4 Port
24
Winbond
WPCE773 35
KBC
SPI BIOS
DCBATOUT
(2MB)
36 MEDIA KEY 38
LPC
DEBUG 36 CONN.
SATA
ODD SATA 22
Finger Printer
37
Touch Pad 37
INT. KB 35
A
A
JV50
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
BLOCK DIAGRAM
Size A2 Date:
5 4 3 2
Document Number
Rev
JV50
Thursday, January 08, 2009
1
SB
Sheet 1 of 60
A
Signal HDA_SDOUT Usage/When Sampled XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK PCIE config1 bit0, Rising Edge of PWROK. PCIE config2 bit2, Rising Edge of PWROK. Reserved ESI Strap (Server Only) Rising Edge of PWROK Comment
B
page 92
ICH9M Functional Strap DefinitionsRev.1.5 ICH9 EDS 642879
ICH9M Integrated Pull-up and Pull-down Resistors
ICH9 EDS 642879
C
E CantigaDchipset and ICH9M I/O controller Hub strapping configuration
Montevina Platform Design guide 22339 Rev.1.5
Pin Name CFG[2:0] Strap Description FSB Frequency Select Configuration 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved page 218
0.5
Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h) This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high. ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile. Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.
SIGNAL
CL_CLK[1:0] CL_DATA[1:0] CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK# GPIO[20] GPIO[49] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED#
SPI_CS1#/GPIO58/CLGPIO6 GNT[3:0]#/GPIO[55,53,51]
Resistor Type/Value
PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K
The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller
4
HDA_SYNC GNT2#/ GPIO53 GPIO20 GNT1#/ GPIO51
CFG[4:3] CFG8 CFG[15:14] CFG[18:17] CFG5 CFG6
Reserved
4
DMI x2 Select iTPM Host Interface Intel Management engine Crypto strap
0 = DMI x2 1 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) 0 = Transport Layer Security (TLS) cipher suite with no confidentiality 1 = TLS cipher suite with confidentiality (default) 0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order 0 = Enable (Note 3) 1= Disabled (default) 00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enabled (Note 3) 11 = Disabled (default) 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 0 = Normal operation(Default): Lane Numbered in Order
GNT3#/ GPIO55
Top-Block Swap Override. Rising Edge of PWROK.
CFG7
CFG9
PCIE Graphics Lane
GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI
Boot BIOS Destination Selection 0:1. Rising Edge of PWROK. Integrated TPM Enable, Rising Edge of CLPWROK
PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K
L_DDC_DATA Local Flat Panel (LFP) Present SDVO_CTRLDATA SDVO Present CFG20 CFG19 DMI Lane Reversal CFG16 FSB Dynamic ODT CFG10 CFG[13:12] PCIE Loopback enable XOR/ALL
3
GPIO49 SATALED# SPKR
DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK. applications and required to be high for mobile applications. PCI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK. Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit. This signal should not be pull low unless using XOR Chain testing. Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister.
3
1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1) Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe 0 = Only Digital Display Port or PCIE is operational (Default) 1 =Digital display Port and PCIe are operting simulataneously via the PEG port 0 =No SDVO Card Present (Default) 1 = SDVO Card Present 0 = LFP Disabled (Default) 1= LFP Card Present; PCIE disabled
SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]
TP3
XOR Chain Entrance. Rising Edge of PWROK. Flash Descriptor Security Override Strap Rising Edge of PWROK
GPIO33/ HDA_DOCK _EN#
2
NOTE: 1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
2
1
JV50
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size A3 Date: Document Number Rev
JV50
Thursday, January 08, 2009 Sheet 2 of 60
SB
A
B
C
D
E
A
B
C
D
E
3D3V_S0
SB 1202
1 R554 2 0R0603-PAD 3D3V_VDD48_S0 1 1 1
3D3V_S0 1D05V_S0
SB 1202
1 1 1 1 1 SCD1U16V2ZY-2GP SC4D7U6D3V3KX-GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C450 C417 C435 C444 C436
SB 1202
1 SCD1U16V2ZY-2GP C416
SB 1202
1 1 1 1 1 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C430 C419 C445 C448 C454
SB 1202
1 2 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C418
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C456 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
C457
C455
DY
2
SC1U16V3ZY-GP
DY
2
DY
2
DY
2
DY
2
DY
2
2
2
2
2
2
2
2
4
SB 1202
3D3V_VDD48_S0 1D05V_S0
2
4
3D3V_S0 3D3V_S0
4 16 9 46 62 23
GEN_XTAL_OUT X5 X-14D31818M-35GP
2
DIS
2 PCLKCLK4 1
VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO
VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3
R260 10KR2J-3-GP
SB 1202
C453 SC33P50V2JN-3GP 1 2
19 27 43 52 33 56
CL=20pF±0.2pF
1
U24
82.30005.891
R254 10KR2J-3-GP 1 2 C452 SC33P50V2JN-3GP 4,7 31 CPU_SEL0 CLK48_5158E GEN_XTAL_IN 3 2 1 X1 X2
CPUT0 CPUC0 CPUT1_F CPUC1_F CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8
61 60 58 57 54 53 51 50 48 47 41 42 40 39 37 38 34 35 31 32 28 29 24 25 20 21 DREFSSCLK_1 DREFSSCLK_1# DREFCLK_1 DREFCLK_1# 3D3V_S0 CR#_H CR#_G
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13 CLK_PCIE_NEW 32 CLK_PCIE_NEW# 32 CLK_PCIE_PEG 52 CLK_PCIE_PEG# 52 CLK_PCIE_LAN 25 CLK_PCIE_LAN# 25
CPU NB SB DMI NEWCARD GPU LAN
3
UMA
2
R251 2 R253 2
1 2K2R2J-2-GP CLK48 1 33R2J-2-GP
17
USB_48MHZ/FSLA SRCT7/CR#_F SRCC7/CR#_E PCI_STOP# CPU_STOP# SRCT6 SRCC6 SRCT10 SRCC10 SRCT11/CR#_H SRCC11/CR#_G SRCT9 SRCC9 PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN SRCT4 SRCC4 SRCT3/CR#_C SRCC3/CR#_D SRCT2/SATAT SRCC2/SATAC FSLB/TEST_MODE REF0/FSLC/TEST_SEL NC#55 GND GNDSRC GNDSRC GNDSRC GNDCPU GND GND48 GNDPCI GNDREF 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 SRCT0/DOTT_96 SRCC0/DOTC_96
3D3V_S0 5 6 7 8
RN48 4 3 2 1 SRN10KJ-6-GP RN46 PCLKCLK2 CPU_SEL2_R PCLKCLK5 3D3V_S0 C451 2
13 PM_STPPCI# 13 PM_STPCPU#
45 44
modify by RF
15,16,17 SMBC_ICH 15,16,17 SMBD_ICH 7 6 63 1 8 10 11 12 13 14 SCLK SDATA CK_PWRGD/PD#
3
4,7
CPU_SEL2
DY
1
13 CLK_PWRGD
13
CLK_ICH14 CLK48_ICH 35 PCLK_KBC 13 PCLK_ICH
13
1 2 3 4
8 CPU_SEL2_R 7 CLK48 6 PCLKCLK4 5 PCLKCLK5
10KR2J-3-GP 2R249
SC47P50V2JN-3GP 36,51 PCLK_FWH
SRN33J-7-GP
PCLKCLK0 PCLKCLK1 R255 2 1 33R2J-2-GP PCLKCLK2 1PCLKCLK3 TPAD14-GP TP158 PCLKCLK4 -1 PCLKCLK5
DY
CLK_PCIE_MINI1 33 CLK_PCIE_MINI1# 33 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 CLK_PCIE_MINI2 33 CLK_PCIE_MINI2# 33 CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12
WLAN NB CLK 3G SB SATA GPU
-1
CLK_ICH14 PCLK_FWH PCLK_ICH PCLK_KBC CLK48_ICH 1 EC25 1 EC24 1 EC23 1 EC39 1 EC48 2 SC33P50V2JN-3GP 2 SC33P50V2JN-3GP 2 SC33P50V2JN-3GP 2 SC33P50V2JN-3GP 2 SC33P50V2JN-3GP 55 4,7 CPU_SEL1 CPU_SEL2_R 64 5
-1
4 3 4 3
DIS
1 RN42 2 SRN33J-5-GP-U 1 RN44 2 SRN0J-6-GP
VGA_XIN1 52 OSC_SPREAD DREFCLK 7 DREFCLK# 7
52
NB NB
2
GND
UMA
1 2
18 15 1
22 30 36 49 59 26
2
65
ICS9LPRS365BKLFT-GP-U
4 RN76 3 SRN0J-6-GP
71.09365.A03
4 3 2 1
DREFSSCLK 7 DREFSSCLK# 7 VGA_XIN1 1 EC68 DY OSC_SPREAD 1 EC69 DY 2
EMI capacitor for Antenna team suggestion
UMA
RN47 SRN10KJ-6-GP
-1
SC33P50V2JN-3GP 2 SC33P50V2JN-3GP
ICS9LPRS365YGLFT setting table PIN NAME DESCRIPTION PCI0/CR#_A
Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed 13 7 25 33 SATACLKREQ# CLK_MCH_OE# LAN_CLKREQ# WLAN_CLKREQ# 1 2 3 4
DY
RN45 8 7 6 5 PCLKCLK0 PCLKCLK1 CR#_H CR#_G 5 6 7 8
DY
SEL2 SEL1 SEL0 FSC FSB FSA 1 0 0 0 0
JV50
CPU
100M 133M 166M 200M 266M
FSB
X 533M 667M 800M 1067M
1
SRN470J-3-GP
PIN NAME SRCC3/CR#_D SRCC7/CR#_E
DESCRIPTION
Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6 Byte 6, bit 6 0 = SRC7 enabled (default) 1= CR#_F controls SRC8 Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10
C D
PCI1/CR#_B PCI2/TME
1
0 0 1 1 0
1 1 1 0 0
PCI3 PCI4/27M_SEL PCI_F5/ITP_EN SRCT3/CR#_C
A
0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# 0 =SRC8/SRC8# 1 = ITP/ITP# Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair
B
SRCT7/CR#_F SRCC11/CR#_G SRCT11/CR#_H
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Clock Generator
Size Date: Document Number Rev
JV50
Thursday, January 08, 2009 Sheet
E
SB
3 of 60
A
B
C
D
E
6
H_A#[35..3]
H_A#[35..3] H_DINV#[3..0] CPU1A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 1 OF 4 ADS# BNR# BPRI# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM#0 1 XDP_BPM#1 1 XDP_BPM#2 1 XDP_BPM#3 1 XDP_BPM#4 1 XDP_BPM#5 1 XDP_TCK 1 XDP_TDI 1 XDP_TDO 1 XDP_TMS 1 XDP_TRST# 1 XDP_DBRESET# 1 H_RS#0 H_RS#1 H_RS#2 1 TP74 TPAD14-GP 6 6 6 1D05V_S0 Place testpoint on H_IERR# with a GND 0.1" away R88 56R2J-4-GP 2 H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] 6 6 6 6
4
4
6 6
H_ADSTB#0 H_REQ#[4..0]
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 KEY_NC
H_ADS# H_BNR# H_BPRI#
ADDR GROUP 0 ADDR GROUP 0
CONTROL
DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM#
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6 H_IERR# H_INIT# 12
1
C104 1
DY
2
SC47P50V2JN-3GP CPU1B 6 2 OF 4 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R71 1 R67 1 R57 1 R60 1 2 2 2 2 27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_LOCK# 6 H_CPURST# 6,51 H_RS#[2..0]
modify by RF
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL0 BSEL1 BSEL2 BGA479-SKT6-GPU7
H_TRDY# H_HIT# H_HITM# TP28 TP27 TP26 TP32 TP29 TP30 TP34 TP50 TP31 TP49 TP33 TP88
6 6 6 H_THERMDA 1 C116 SC2200P50V2KX-2GP
XDP/ITP SIGNALS
3
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
2
TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP
H_THERMDC 1D05V_S0
DY
Close to NB
1 R89 68R2-GP 6 H_DSTBN#0 6 H_DSTBP#0 6 H_DINV#0 CPU_PROCHOT#_R 41
DATA GRP2
DATA GRP0
2
ADDR GROUP 1 ADDR GROUP 1
3
1 R97 2 DY 0R2J-2-GP C90 1
THERMAL
PROCHOT# THRMDA THRMDC THERMTRIP# D21 A24 B25 C7 CPU_PROCHOT#_1 H_THERMDA 34 H_THERMDC 34
SC47P50V2JN-3GP 2
6 12 12 12 12 12 12 12
H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#
DY
modify by RF
PM_THRMTRIP-A# 7,12,39 PM_THRMTRIP# ICH9 and MCH PH @ page48 should connect to without T-ing
HCLK
BCLK0 BCLK1
A22 A21
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3
1D05V_S0 2 6 6 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
RESERVED
1 1
Layout Note: "CPU_GTLREF0" 0.5" max length.
1KR2F-3-GP R312 SC1KP50V2KX-1GP 2 1
CPU_GTLREF0
2
R309 2KR2F-3-GP 2
DY
C526TPAD14-GP TP87 TPAD14-GP TP25 TPAD14-GP TP180 3,7 3,7 3,7 CPU_SEL0 CPU_SEL1 CPU_SEL2
TPAD14-GP TP97
1
RSVD_CPU_11
B1
AD26 TEST1 C23 TEST2 D25 1RSVD_CPU_12 C24 TEST4 AF26 1RSVD_CPU_13 AF1 1RSVD_CPU_14 A26 B22 B23 C21
MISC
DATA GRP3
DATA GRP1
BGA479-SKT6-GPU7
62.10079.001 2nd = 62.10053.401
C102
DY
1D05V_S0 1 DY R119 2 TEST1 1KR2J-1-GP Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .
XDP_TMS XDP_TDI XDP_BPM#5 XDP_TDO H_CPURST#
1
R54 R55 R46 R47
1 1 1 1
2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP
1 DY 2 TEST2 R114 1KR2J-1-GP C525 2 DY TEST4 1 SCD1U10V2KX-4GP
Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals
R113 1
DY DY
2 51R2F-2-GP 3D3V_S0 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# H_INIT# H_CPURST# 1 1 1 1 1 1 1 TP76 TP95 TP114 TP81 TP78 TP92 TP86 TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP JV50
1
XDP_DBRESET#
R105 1
2 1KR2J-1-GP
DY
XDP_TCK XDP_TRST# R32 R33 1 1 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Place these TP on button-side, easy to measure.
CPU (1 of 2)
Size Date: Document Number Rev
All place within 2" to CPU
JV50
Thursday, January 08, 2009 Sheet
E
SC100P50V2JN-3GP 2
1
ICH
2
H_DPRSTP# 7,12,41 H_DPSLP# 12 H_DPWR# 6 H_PWRGD 12,39,51 H_CPUSLP# 6 H_PSI# 41
SB
4 of 60
A
B
C
D
A
B
C
D
E
VCC_CORE
VCC_CORE
SB 1209
1 1 1 1 1 1 1 1 1 1 1 1 1 C89 SC10U6D3V5MX-3GP C88 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C53 SC10U6D3V5MX-3GP C50 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C51 SC10U6D3V5MX-3GP C52 SC10U6D3V5MX-3GP C553 SC10U6D3V5MX-3GP C538 SC10U6D3V5MX-3GP C552 SC10U6D3V5MX-3GP C539 SC10U6D3V5MX-3GP C548 SC10U6D3V5MX-3GP C547 SC10U6D3V5MX-3GP C536 SC10U6D3V5MX-3GP 1 2 C537 SC10U6D3V5MX-3GP
1
1
1
1
C86
C56
C85
C55
1 2
C87 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VCC_CORE VCC_CORE
4
DY
DY
DY
DY
DY
DY
2
CPU1D A4 A8 A11 A14 A16 A19 A23 TP_AF2_CPU AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4 OF 4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 TP_AE26_CPU 1 TP_A2_CPU A2 1 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 TP_A25_CPU 1 AF25
4
CPU1C A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
3 OF 4 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCCSENSE VSSSENSE AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7 1 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 H_VID[6..0] VCC_CORE 1 41 2
TPAD14-GP TP23
1
1D05V_S0
SB 1208
3
3
1
1
1
1
1
1D05V_S0_CPU 2 1D05V_S0 G2 1 2 GAP-CLOSE-PWR C57 SCD1U10V2KX-4GP C58
C67
C75
C79
C80
C83 SC4D7U6D3V3KX-GP
1 2
C84 SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
2
2
2
DY
DY
1
1 2
SCD1U10V2KX-4GP
2
layout note: "1D5V_VCCA_S0" as short as possible
1D5V_S0 1D5V_VCCA_S0 FCM1608KF-1-GP 1 2 L18 C6062nd = 68.00248.061 SC10U6D3V5MX-3GP
1
C603 SCD01U16V2KX-3GP
2
1
2
R25 100R2F-L1-GP-U
2
2
VCC_SENSE
41
VSS_SENSE 41 Layout Note:
R24 100R2F-L1-GP-U BGA479-SKT6-GPU7 2 VCCSENSE and VSSSENSE lines should be of equal length.
TP174 TPAD14-GP TP98 TPAD14-GP
Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.
TP181 TPAD14-GP
BGA479-SKT6-GPU7
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (2 of 2)
Size Date:
A B C D
Document Number
Rev
JV50
Thursday, January 08, 2009 Sheet
E
SB
5 of 60
5
4
3
2
1
NB1A 4 H_D#[63..0] H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
1 OF 10 H_A#[35..3] H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3 H_DPWR# 4 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4 H_A#[35..3] 4
1D05V_S0
D
H_SWING routing Trace width and Spacing use 10 / 20 mil H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )
1
D
1 R381 221R2F-2-GP 2 1 R382 100R2F-L1-GP-U 2
H_SWING C619 SCD1U10V2KX-4GP
C
2
C
H_RCOMP routing Trace width and Spacing use 10 / 20 mil
1 R380 2 H_RCOMP 24D9R2F-L-GP
HOST
H_DINV#[3..0] H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#[3..0] H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#[3..0] H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
H_DINV#[3..0]
4
Place them near to the chip ( < 0.5")
H_DSTBN#[3..0]
4
B
H_DSTBP#[3..0]
4
B
1D05V_S0 2 H_SWING H_RCOMP R370 1KR2F-3-GP 1 H_AVREF SCD1U16V2ZY-2GP 4,51 H_CPURST# 4 H_CPUSLP# C5 E3 C12 E11 A11 B11 1 C614 H_SWING H_RCOMP H_CPURST# H_CPUSLP# H_AVREF H_DVREF CANTIGA-GM-GP-U-NF
H_REQ#[4..0]
4
H_RS#[2..0]
4
1 R389 2KR2F-3-GP 2
71.CNTIG.00U
2
A
JV50
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:
5 4 3 2
Document Number
Cantiga (1 of 6) JV50
Sheet
1
Rev
SB
6 of 60
Thursday, January 08, 2009
5
4
3
2
1
1D05V_S0
NB1B
2 OF 10 NB1C 3 OF 10
2
R196 C270
1
49D9R2F-GP
Close to GMCH as 500 mils.
modify by RF
PEG_RXN[15..0] 52
D
RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24
DDR CLK/ CONTROL/COMPENSATION
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 B31 B2 M1 AY21
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_RCOMPP M_RCOMPN SM_RCOMP_VOH SM_RCOMP_VOL 16 16 17 17 16 16 17 17 16 16 17 17
16 16 17 17 16 16 17 17
18 35
L_BKLTCTL GMCH_BL_ON
LCTLA_CLK LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID
L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
SC47P50V2JN-3GP
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
PEG_CMP
2
1
DY
PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 PEG_TXN0_L PEG_TXN1_L PEG_TXN2_L PEG_TXN3_L PEG_TXN4_L PEG_TXN5_L PEG_TXN6_L PEG_TXN7_L PEG_TXN8_L PEG_TXN9_L PEG_TXN10_L PEG_TXN11_L PEG_TXN12_L PEG_TXN13_L PEG_TXN14_L PEG_TXN15_L PEG_TXP0_L PEG_TXP1_L PEG_TXP2_L PEG_TXP3_L PEG_TXP4_L PEG_TXP5_L PEG_TXP6_L PEG_TXP7_L PEG_TXP8_L PEG_TXP9_L PEG_TXP10_L PEG_TXP11_L PEG_TXP12_L PEG_TXP13_L PEG_TXP14_L PEG_TXP15_L
18 CLK_DDC_EDID 18 DAT_DDC_EDID
18 GMCH_LCDVDD_ON TPAD14-GP TP189 R183 1 2 0R0402-PAD
GMCH_LCDVDD_ON LIBG 1 L_LVBG LVDS_VREF
D
RSVD
RESERVED#B31 RESERVED#B2 RESERVED#M1 RESERVED#AY21
18 GMCH_TXACLK18 GMCH_TXACLK+ 18 GMCH_TXBCLK18 GMCH_TXBCLK+ 18 GMCH_TXAOUT018 GMCH_TXAOUT118 GMCH_TXAOUT2-
BG23 BF23 BH18 BF18
RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18
SM_PWROK DDR_VREF_S3_1
39
18 GMCH_TXAOUT0+ 18 GMCH_TXAOUT1+ 18 GMCH_TXAOUT2+
0.75V
DDR2 : connect to GND SM_REXT R444 499R2F-2-GP 1 2 DDR3_DRAMRST# DDR3_DRAMRST# DREFCLK 3 DREFCLK# 3 DREFSSCLK 3 DREFSSCLK# 3 CLK_MCH_3GPLL CLK_MCH_3GPLL# 3 3
18 GMCH_TXBOUT018 GMCH_TXBOUT118 GMCH_TXBOUT2-
16,17
C335 SCD1U10V2KX-4GP
PCI-EXPRESS
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
18 GMCH_TXBOUT0+ 18 GMCH_TXBOUT1+ 18 GMCH_TXBOUT2+
2
GRAPHICS
LVDS LVDS
PEG_RXP[15..0]
52
1
CLK
TV_DACA TV_DACB TV_DACC
F25 H25 K25 H24
TVA_DAC TVB_DAC TVC_DAC TV_RTN
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
3,4 3,4 3,4 CPU_SEL0 CPU_SEL1 CPU_SEL2
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43
DMI_TXN0 13 DMI_TXN1 13 DMI_TXN2 13 DMI_TXN3 13 DMI_TXP0 13 DMI_TXP1 13 DMI_TXP2 13 DMI_TXP3 13 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 13 13 13 13 13 13 13 13 19 GMCH_BLUE GMCH_BLUE GMCH_GREEN GMCH_RED
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
C
1D5V_S3 CFG9
3D3V_S0
R443 80D6R2F-L-GP
M_RCOMPP
CFG16
GRAPHICS VID
R193 1
DY
2 4K02R2F-GP
CFG20
M_RCOMPN
R385 1 R556 1
DY DY
2 2K21R2F-GP 2 2K21R2F-GP
CFG9
R442 80D6R2F-L-GP 13 PM_SYNC# 4,12,41 H_DPRSTP# 16,17 PM_EXTTS#0 13,34 PWROK
1
CFG20
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C220 C648 C654 C228 C233 C658 C237 C239 C265 C264 C269 C660 C671 C666 C680 C679 C213 C647 C651 C222 C229 C663 C234 C245 C259 C253 C266 C657 C667 C664 C672 C686
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
PEG_TXN[15..0]
52
TV TV
C
DMI
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
E28 G28 J28 G29
PEG_TXP[15..0]
52
CRT_BLUE CRT_GREEN CRT_RED
19 GMCH_GREEN 19 GMCH_RED
CFG
VGA VGA
CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
1
19 GMCH_DDCCLK 19 GMCH_DDCDATA 19 GMCH_HSYNC 19 GMCH_VSYNC GFX_VID[4..0] 46
GMCH_DDCCLK GMCH_DDCDATA 1 R189 2 GMCH_HS 0R0402-PAD 1 R188 2GMCH_VS 0R0402-PAD
H32 J32 J29 E29 L29
2
1
CFG16
SB 1202
13,25,31,32,33,35,36,51,52
PLT_RST1#
2
100R2J-2-GP
1
R203
R29 B7 PM_EXTTS#0 N33 PM_EXTTS#1 P32 AT40 RSTIN# AT11 NB_THERMTRIP# T20 PM_DPRSLPVR_MCH R32 1
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4
R161
UMA
CRT_IREF 2 1K02R2F-1-GP CANTIGA-GM-GP-U-NF
FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm
71.CNTIG.00U SB 1202
PEG_TXN0_L PEG_TXP0_L
2
GFX_VR_EN
C34
GFXVR_EN 1D05V_S0
CRT_IREF routing Trace width use 20 mil
2
PM
UMA 1 UMA 1 UMA 1 UMA 1 UMA 1 UMA 1 UMA 1 UMA 1
2 C600 2 C605 2 C596 2 C598 2 C589 2 C592 2 C568 2 C561
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_TXN0_L_1 PEG_TXP0_L_1
UMA 1
2
4 RN82 3 SRN0J-10-GP-U 4 RN83 3 SRN0J-10-GP-U 4 RN84 3 SRN0J-10-GP-U 3 RN85 4 SRN0J-10-GP-U
HDMI_DATA2- 20,55 HDMI_DATA2+ 20,55
ME
DY
SB 1202
4,12,39 PM_THRMTRIP-A#
B
1 R192
2
SCD1U10V2KX-4GP
0R0402-PAD
0R0402-PAD
MISC
13,41 PM_DPRSLPVR
1 R195
2
PM_DPRSLPVR_MCH
HDA
NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47
CANTIGA-GM-GP-U-NF
2
MCH_CLVREF
1
C324 SC100P50V2JN-3GP
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AH37 AH36 AN36 AJ35 AH34
CL_CLK0 13 CL_DATA0 13 PWROK 13,34 CL_RST#0 13
R201 1KR2F-3-GP
PEG_TXN1_L PEG_TXP1_L
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_TXN1_L_1 PEG_TXP1_L_1
UMA 1
2
HDMI_DATA1- 20,55 HDMI_DATA1+ 20,55
DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN#
N28 M28 G36 E36 K36 CLK_MCH_OE# H36 B12
for HDMI port C
GMCH_HDMI_CLK 20 GMCH_HDMI_DATA 20 CLK_MCH_OE# 3 MCH_ICH_SYNC# 13
C288
1
1
PEG_TXN2_L PEG_TXP2_L R200 499R2F-2-GP
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_TXN2_L_1 PEG_TXP2_L_1
UMA 1
2
HDMI_DATA0- 20,55 HDMI_DATA0+ 20,55
2
PEG_TXN3_L PEG_TXP3_L
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_TXN3_L_1 PEG_TXP3_L_1
UMA 2
1
HDMI_CLK- 20,55 HDMI_CLK+ 20,55
MCH_TSATN#
FOR Cantiga:500 ohm Teenah: 392 ohm
2
B
NC NC
1 2
MCH_TSATN# GFXVR_EN
R555 PEG_RXP3
1
UMA HDMI_DETECT#_L 2
R61
1
UMA 2
HDMI_DETECT#
20
0R2J-2-GP
0R2J-2-GP
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
B28 B30 B29 C29 A28
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
R419
1
2
33R2J-2-GP RN36
UMA
ACZ_SDIN3
ACZ_SDIN3
12
RN30
HDA_BCLK HDA_SYNC HDA_RST# HDA_SDO
1 2 3 4
8 7 6 5
ACZ_BIT_CLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAOUT_R
71.CNTIG.00U
1D05V_S0
ACZ_BIT_CLK 12 ACZ_SYNC_R 12 ACZ_RST#_R 12 ACZ_SDATAOUT_R
GMCH_RED GMCH_GREEN GMCH_BLUE 12
1 2 3 4
8 7 6 5
SRN150F-1-GP
UMA
SRN33J-4-GP 1D5V_S3 R445 1KR2F-3-GP
UMA/DIS FOR Discrete change RN to 0 ohm (66.R0036.A8L)
1
EC21DY
RN32 GMCH_BL_ON GMCH_LCDVDD_ON
2 1
3 4
SRN100KJ-6-GP
2
R387 56R2J-4-GP
1
SM_RCOMP_VOH
UMA
1
1
C756
1
C759 SC2D2U6D3V3MX-1-GP
2
2
R441 3K01R2F-3-GP
2 HDA_BCLK SC12P50V2JN-3GP 5 6 7 8
LIBG RN31
UMA
1
R384
2
2K37R2F-GP
SCD01U16V2KX-3GP
SM_RCOMP_VOL
2
1
C757
1
4 3 2 1
SRN75J-1-GP
TV_DACC TV_DACB TV_DACA
2
CRT_IREF
DIS
1
R162 RN33
2
0R2J-2-GP
C760 SC2D2U6D3V3MX-1-GP
A
GFXVR_EN
46
2
2
R446 1KR2F-3-GP
UMA/DIS
SCD01U16V2KX-3GP
GMCH_VS GMCH_HS
2 1
3 4
SRN0J-10-GP-U
DY
1
3D3V_S0 RN34 LCTLA_CLK LCTLB_DATA
R178 100KR2F-L1-GP
FOR Discrete,change to 0 ohm (66.R0036.A8L)
DIS
A
2
1
layout take note
UMA
1 2
4 3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
SRN10KJ-5-GP RN35 PM_EXTTS#0 PM_EXTTS#1
4 3
1 2
Size SRN10KJ-5-GP Date: Document Number
Cantiga (2 of 6)
Rev
JV50
Thursday, January 08, 2009
1
SB
Sheet 7 of 60
5
4
3
2
5
4
3
2
1
16 M_A_DQ[63..0]
D
C
M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
NB1D AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 CANTIGA-GM-GP-U-NF
4 OF 10 SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 BB20 BD20 AY20 17 M_B_DQ[63..0] M_A_BS#0 16 M_A_BS#1 16 M_A_BS#2 16 M_A_RAS# 16 M_A_CAS# 16 M_A_WE# 16 M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
NB1E SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 CANTIGA-GM-GP-U-NF
5 OF 10 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# BC16 BB17 BB33 AU17 BG16 BF14 M_B_BS#0 17 M_B_BS#1 17 M_B_BS#2 17 M_B_RAS# 17 M_B_CAS# 17 M_B_WE# 17
D
M_A_DM[7..0] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DQS[7..0] M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
M_A_DM[7..0]
16
M_B_DM[7..0] SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS[7..0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
M_B_DM[7..0]
17
A
M_A_DQS[7..0]
16
B
M_B_DQS[7..0]
17
MEMORY
M_A_DQS#[7..0]
M_A_DQS#[7..0]
16
MEMORY
M_B_DQS#[7..0]
M_B_DQS#[7..0]
17
SYSTEM
M_A_A[14..0]
16
SYSTEM
M_A_A[14..0]
M_B_A[14..0]
M_B_A[14..0]
17
C
DDR
B
DDR
B
71.CNTIG.00U
71.CNTIG.00U
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga (3 of 6)
Size Date:
5 4 3 2
Document Number
Rev
JV50
Thursday, January 08, 2009 Sheet
1
SB
8 of 60
5
4
3
2
1
7 OF 10 1D5V_S3 NB1G
VCC_GFXCORE
D
SCD47U6D3V2KX-GP
2
2
2
2
2
2
2
2
2
2
2
Coupling CAP
POWER
VCC GFX NCTF
BA36 BB24 BD16 BB21 AW16 AW13 AT13
VCC_GFXCORE
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
2
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
C
VCC SM LF
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
1D05V_S0
DIS
1
R438
FOR VCC CORE
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32
NB1F
6 OF 10
2
0R5J-1-GP
DIS
1
R439
2 1 1 1 1 1 1
C291 C287 C274 C249 C281 SCD22U10V2KX-1GP C280 SCD1U10V2KX-4GP
1
0R5J-1-GP
C284 SCD1U10V2KX-4GP
POWER
DY
DY
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
2
2
2
2
2
2
D
Coupling CAP 370 mils from the Edge
VCC SM
VCC_GFXCORE
-1
-1
SB 1202
1
C612 SC10U6D3V5MX-3GP
1
C289 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
1
1
1
1
1
1
1
1
1
1
1
TC18 ST220U2D5VBM-2GP
C292
C277
C273
C276
C282
C302
C285
C275
1 2
C286
C271 SC1U10V3ZY-6GP
C279 SCD1U10V2KX-4GP
1
C278 SCD1U10V2KX-4GP
2
DY
VCC CORE
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
DY
UMA
UMA
DY
UMA
DY
DY
UMA
DY
UMA
UMA
UMA
UMA
1D05V_S0
Place on the Edge
Coupling CAP
1D5V_S3
1
1
1
1
1
1
1
1
C361
C367
C359
C349
C323
C308
C348
TC22 ST330U2D5VBM-GP
2
2
2
2
2
2
2
DY
DY
DY
80.3371V.12L
Place on the Edge
VCC GFX
SB 1202
C298
C340
SC1U10V3KX-3GP
C320
C350 SCD1U10V2KX-4GP
C290 SCD1U10V2KX-4GP
C347 SCD22U10V2KX-1GP
C329 SCD22U10V2KX-1GP
B
SC1U10V3KX-3GP
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH 1 1 1 1 1
2
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
1
1
VCC NCTF
FOR VCC SM
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
C
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD47U16V3ZY-3GP
46 VCC_AXG_SENSE 46 VSS_AXG_SENSE
2
2
2
2
2
2
CANTIGA-GM-GP-U-NF
U60(ISL6263ACRZ-T-GP) place near Cantiga
71.CNTIG.00U
place near Cantiga
A
2
VCC_AXG_SENSE VSS_AXG_SENSE
AJ14 AH14
VCC_AXG_SENSE VSS_AXG_SENSE
B
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga (4 of 6)
Size Document Number Rev
JV50
Date:
5 4 3 2
SB
Sheet 9 of 60
Thursday, January 08, 2009
1
5
4
3
2
1
5V_S0
C250 SC4D7U6D3V3KX-GP 2 1
C267 SC4D7U6D3V3KX-GP 2 1
C670 SC4D7U6D3V3KX-GP
C268 SCD47U6D3V2KX-GP
2
2
2
NC#4
G9091-330T11U-GP BC2
UMA
1
1
2
D
UMA
UMA
2
2
3D3V_S0_DAC SCD1U10V2KX-4GP 1 R374 2 0R0603-PADC625 SCD01U16V2KX-3GP
5mA
1 1 C207
VCCA_DAC_BG VSSA_DAC_BG
CRT
74.09091.J3F
M_VCCA_DAC_BG
2
BC1 SC1U16V3ZY-GP
VCCA_CRT_DAC VCCA_CRT_DAC
DY
A25 B25
2
1 2 3 SC1U16V3ZY-GP
VIN GND EN
VOUT
5 4 C141 SC22U6D3V5MX-2GP
UMA
UMA
1
R379 0R2J-2-GP
DY
B27 A26
DY
2
2
2
M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL
L48 AD1 AE1 J48 J47
VCCA_HPLL VCCA_MPLL VCCA_LVDS VSSA_LVDS
PLL
1
1
C622
C624
1
2 R371 1 0R0603-PAD
65mA
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP 2 2
VCCA_DPLLB
VTT
1D05V_S0
UMA
UMA
R168 0R2J-2-GP
M_VCCA_DPLLA
F47
VCCA_DPLLA
M_VCCA_DPLLA R390 0R2J-2-GP
1
UMA DY
2 1D5V_S0 M_VCCA_DPLLB
A LVDS
2
1
1
1
2 R399 1 0R0603-PAD
65mA
SC10U6D3V5MX-3GP
1
C642
C644
R400 0R2J-2-GP
1 R421 2 0R0603-PAD
VCCA_PEG_BG C704 SCD1U10V2KX-4GP
AD48
VCCA_PEG_BG
DY
UMA
2 1D05V_S0 2 R447 1 0R0603-PAD
50mA 1D05V_RUN_PEGPLL AA48
1D05V_SM C309 SC1U10V3KX-3GP C305 SC1U10V3KX-3GP 1 1 1 C306 AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
A PEG
DY
2
2
2
1D05V_S0
VCCA_PEG_PLL VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
322mA
U12 1 1 1 SC1U10V3KX-3GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP C616 C251 C272
I=1A
VIN VOUT GND 3 2 1 3D3V_S0 1D8V_NB_S0 2 2 C119 SC1U10V2ZY-GP 1 C100 SC1U10V2ZY-GP 1
C
1D05V_S0 1
C
480mA
R430 0R0603-PAD 1D05V_SUS_MCH_PLL2
C755
C753
C754
C752
POWER
A SM
2
2
1
1
1
1
2
DY
DY
DY
DY
G1117-18T63UF-GP
74.G1117.B3C UMA
2
2
2
2
2
2
DY
FCM1608KF-1-GP 1 2 L22
DY
2
UMA
UMA
2
24mA
M_VCCA_HPLL SC4D7U6D3V3KX-GP SC10U6D3V5MX-3GP 1 C687 1 1D05V_S0 C692 SCD1U10V2KX-4GP
2nd = 68.00248.061
2 FCM1608KF-1-GP 1 2 L21
2
1
1
1
1
2 R202 1 0R0603-PAD
1D05V_SM_CK C294 C295 C313 C293 AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCC_AXF VCC_AXF VCC_AXF B22 B21 A21
1D5V_SUS_SM_CK
1D5V_S3
AXF
24mA 139.2mA
C697 SCD1U10V2KX-4GP 1
200mA
SCD1U10V2KX-4GP C750 1 1 1 SC4D7U6D3V3KX-GP C751 C758
2 R448 1 0R0603-PAD
M_VCCA_MPLL 1 C694
DY
DY
DY
SB 1202
2
2
2
2
DY
2
A CK
120ohm 100MHz 2nd = 68.00248.061
2
DY
2
3D3V_S0_DAC 1 R377 2 0R0603-PAD 2 R386 1 0R2J-2-GP DY 1D5V_S0 3D3V_S0_DAC_1
SM CK
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
BF21 BH20 BG20 BF20
2
1D8V_TXLVDS_S0
2
1D8V_NB_S0
1D05V_S0 L20
B
119mA
1 SC1U10V3KX-3GP C634
TV
2
1
68.00217.521
220ohm 100MHz
2
C691 SCD1U10V2KX-4GP
VCC_HV VCC_HV VCC_HV VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_DMI VCC_DMI VCC_DMI VCC_DMI
HV
2
1
2 FCM1608CF-221T02-GP
1D05V_RUN_PEGPLL
B24 A24
VCC_TX_LVDS VCCA_TV_DAC VCCA_TV_DAC
K47 C35 B35 A35 V48 U48 V47 U47 U46 AH48 AF48 AH47 AG47
3D3V_HV_S0
106mA
UMA
UMA
2 R396 1 0R0603-PAD R398 0R2J-2-GP
1
1
2
C636 SC27P50V2JN-2-GP
13.2mA
2 BAT54-5-GP
83.BAT54.D81
1
DY
SB 1208
C621 SCD1U10V2KX-4GP
1D8V_TXLVDS_S0
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
1 2
C263 SCD1U10V2KX-4GP
1
1
1
1
C206
C617
C662 SC2D2U6D3V3MX-1-GP 2 1
1
U13
Imax = 300 mA UMA
3D3V_S0_DAC 3D3V_S0_DAC 2 R378 1 0R0603-PAD
1D05V_S0
73mA
SCD01U16V2KX-3GP 1 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
3D3V_CRTDAC_S0
NB1H
8 OF 10
852mA
D
1D05V_S0 D5 1 3 1D05V_HV_S0 2 3D3V_S0 1 R106 10R2J-2-GP 3D3V_HV_S0
1 R376 2 0R0603-PAD
HDA
1
1
1 R375 2 0R0603-PAD C205 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP
VCC_HDA
A32
VCC_HDA
1D05V_S0 SC10U6D3V5MX-3GP
1782mA
SC4D7U6D3V3KX-GP 1 1 C283 2 2
SB 1202
SCD1U10V2KX-4GP C678 C678 1
PEG
UMA
1D5V_S0
2
1D5VRUN_TVDAC 1D5VRUN_QDAC
M25 L28 AF1
VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS VCCD_LVDS
D TV/CRT
DY
2
C739
2
1
R383 0R2J-2-GP
C675
1D05V_SUS_MCH_PLL2
2
2
1
1
1
1
1
1
1 R156 2 0R0603-PAD
C715 C174 SCD1U10V2KX-4GP
1
1D5VRUN_TVDAC C243 SCD01U16V2KX-3GP
58.7mA
157.2mA
C690 2
DMI
VTTLF
LVDS
SB 1202
2
DY
2
2
2
2
VTTLF VTTLF VTTLF
C676 SCD47U6D3V2KX-GP
C650 SCD47U6D3V2KX-GP
L6
A
1D8V_NB_S0 1 R153 2 0R0603-PAD R159 0R2J-2-GP 1D8V_SUS_DLVDS 1 1
1
1
1
68.00206.041
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C247 SCD01U16V2KX-3GP
C188 SCD1U10V2KX-4GP 2
60.3mA
2
C235 SCD1U10V2KX-4GP
C175
C186
1
1D5VRUN_QDAC 1 2 PBY160808T-181Y-GP
UMA
71.CNTIG.00U SB 1202
R167 0R2J-2-GP
1 2
1 2
1 2
C620 SCD47U6D3V2KX-GP
CANTIGA-GM-GP-U-NF
1
2
2
2
2
2
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
50mA
UMA
UMA
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
SC2D2U6D3V3MX-1-GP
SCD1U10V2KX-4GP 1D05V_RUN_PEGPLL SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
DY
SC1KP50V2KX-1GP C635
DY
B
SC10U6D3V5MX-3GP
DY
DY
1D05V_S0
AA47 M38 L37
456mA
C712 VTTLF1 VTTLF2 VTTLF3
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C732
C722
A8 L1 AB2
DY
A
DY
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
180ohm 100MHz
UMA
UMA
UMA
DIS
Cantiga (5 of 6)
Size Date: Document Number Rev
JV50
Thursday, January 08, 2009 Sheet
1
SB
10 of 60
5
4
3
2
5
4
3
2
1
NB1I AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
9 OF 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6 BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
NB1J VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
10 OF 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 NCTF_VSS_SCB#BH48 BH1 NCTF_VSS_SCB#BH1 A48 NCTF_VSS_SCB#A48 C1 NCTF_VSS_SCB#C1 NCTF_VSS_SCB#A3 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 1 1 1 1 1 TP201 TP202 TP188 TP190 TP187 TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP
D
D
VSS
VSS
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
C
B
VSS NCTF
B
NCTF TEST PIN: A3,C1,A48,BH1,BH48
VSS SCB
NCTF_VSS_SCB#BH48 NCTF_VSS_SCB#BH1 NCTF_VSS_SCB#A48 NCTF_VSS_SCB#C1 NCTF_VSS_SCB#A3 NC#E1 NC#D2 NC#C3 NC#B4 NC#A5 NC#A6 NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48
A
NC
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
Cantiga (6 of 6)
Size Date: Document Number Rev
JV50
Thursday, January 08, 2009 Sheet
1
SB
11 of 60
5
4
3
2
5
4
3
2
1
SB 1202
C386 1 2 SC7P50V2DN-2GP
RTC_X1
3
4 1 R215 10MR2J-L-GP 1 2
3D3V_AUX_S5 2
D12 RTC_AUX_S5 SC1U16V3ZY-GP 1 3
X4 X-32D768KHZ-40GPU
82.30001.841
2
D
D
1 RTC_BAT_R BAS40CW-GP
C402 2
SB 1202
C385 1 2 SC7P50V2DN-2GP RTC_X2 RTC_RST# SRTC_RST# INTRUDER# 1 1 C396 SC1U16V3ZY-GP INTVRMEN C23 C24 A25 F20 C22 B22 A22 E25 TPAD14-GP TP204 1TP_LAN_RSTSYNC C13 F14 G13 D14 SB1A RTCX1 RTCX2 1 OF 6 FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M# K5 K4 L6 K2 K3 J3 J1 N7 AJ27 AJ25 AE23 AJ26 AD22 AF25 AE22 AG25 L3 AF23 AF24 AH27 AG26 AG27 AH11 AJ11 AG12 AF12 AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7 SATARBIAS 2 24D9R2F-L-GP 1 R194
B
RTC1 PWR GND NP1 NP2 BAT-CON2-1-GP-U RTC_BAT 1 2 NP1 NP2 1 R228
RTC LPC
1
LPC_LFRAME# LDRQ0# 3D3V_LDRQ1_S0 1 1
35,36,51 R413 56R2J-4-GP R424 56R2J-4-GP
2
G17 GAP-OPEN
R230 C397 1MR2J-1-GP SC1U16V3ZY-GP SC1U16V3ZY-GP
INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC
TP200 TPAD14-GP TP144 TPAD14-GP 2 1D05V_S0 H_DPRSTP# H_PWRGD 1
DY
1
2 1KR2J-1-GP
RN39 SRN20KJ-GP-U 2 1 1
3 4 2
RTCRST# SRTCRST# INTRUDER#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
35,36,51 35,36,51 35,36,51 35,36,51
1D05V_S0
1D05V_S0
DY
2
2
62.70001.011
1
KA20GATE 35 H_A20M# 4 H_DPRSTP# H_FERR#_R H_PWRGD H_PWRGD H_IGNNE# 4,39,51 4
LAN / GLAN CPU
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GLAN_DOCK#/GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
DPRSTP# DPSLP# FERR# CPUPWRGD IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#
H_DPRSTP# 4,7,41 H_DPSLP# 4
1 2
4 3 SRN56J-4-GP
H_FERR#
4 2
C683
1 C706 2 SC47P50V2JN-3GP
RN71
2
SC47P50V2JN-3GP
close to SB1
1D5V_S0
C
GLAN_COMP place within 500 mil of ICH9M
HDMI_EN 1 R213 2 GLAN_COMP 24D9R2F-L-GP ACZ_BIT_CLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAIN0 ACZ_SDATAIN1 ACZ_SDIN2 ACZ_SDIN3 ACZ_SDATAOUT_R 1HDA_DOCK_RST#
D13 D12 E13 B10 B28 B27 AF6 AH4 AE7 AF4 AG4 AH3 AE5 AG5 AG7 AE8 AG8
DY
DY
modify by RF
C381 SC47P50V2JN-3GP 1
H_INIT# 4 H_INTR 4 KBRCIN# 35 H_NMI 4 H_SMI# 4 H_STPCLK# 4 H_THERMTRIP_R ICH_TP8 1 TP195 TPAD14-GP 1 1 R410 R411 1 2 56R2J-4-GP 2 54D9R2F-L1-GP
modify by RF
1D05V_S0
C
DY
7 ACZ_BIT_CLK 7 ACZ_SYNC_R 7 ACZ_RST#_R 27 30 52 7 ACZ_SDATAIN0 ACZ_SDATAIN1 ACZ_SDIN2 ACZ_SDIN3
2
PM_THRMTRIP-A# 4,7,39 Layout note: R373 needs to placed within 2" of ICH9, R379 must be placed within 2" of R373 w/o stub
IHDA
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT
PECI SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS
DY
C673
SC47P50V2JN-3GP
7 ACZ_SDATAOUT_R TPAD14-GP TP197 38 3D3V_S5 1 MEDIA_LED#
DY
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED#
modify by RF
HDD ODD
HDMI_EN
SATA
21 21 21 21 22 22 22 22
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1
AJ16 AH16 AF17 AG17 AH13 AJ13 AG14 AF14
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP ICH9M-GP-NF
CLK_PCIE_SATA# CLK_PCIE_SATA
3 3
R218 10KR2J-3-GP
B
2
Place within 500 mils of ICH9 ball
2
1
1D05V_S0 2 1 RN70 SRN10KJ-5-GP
3D3V_S0
R217 10KR2J-3-GP
71.ICH9M.00U DY
DY
2
H_INIT#_G RN37 R414 3D3V_S0 1 2 MEDIA_LED# 10KR2J-3-GP 1 EC22DY 1 EC45DY 1 EC46DY ACZ_BTCLK_MDC SC12P50V2JN-3GP ACZ_BITCLK_AUDIO SC22P50V3JN-GP 2 ACZ_BITCLK_GPU SC22P50V3JN-GP 2 2 30 30 30 30 ACZ_BTCLK_MDC ACZ_SYNC_MDC ACZ_RST#_MDC ACZ_SDATAOUT_MDC 1 2 3 4 8 7 6 5 SRN33J-4-GP RN68 8 7 6 5 SRN33J-4-GP RN69 8 7 6 5 ACZ_BIT_CLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAOUT_R H_INIT#
DY
E
B
C FWH_INIT# Q14 MMBT3904-4-GP
3 4
1
TP116 TPAD14-GP
RTC_AUX_S5 1
27 27 27 27
ACZ_BITCLK_AUDIO ACZ_SYNC_AUDIO ACZ_RST#_AUDIO ACZ_SDATAOUT_AUDIO
1 2 3 4
ACZ_BIT_CLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAOUT_R
84.T3904.C11
A
R229 330KR2F-L-GP INTVRMEN 52 52 52 52 ACZ_BITCLK_GPU ACZ_SYNC_GPU ACZ_RST#_GPU ACZ_SDATAOUT_GPU 1 2 3 4 2
JV50
A
integrated VccSus1_05,VccSus1_5,VccCL1_5
ACZ_BIT_CLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAOUT_R Title Size Date: Document Number
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
INTVRMEN LAN100_SLP
High=Enable High=Enable
Low=Disable Low=Disable
DIS
integrated VccLan1_05VccCL1_05
SRN33J-4-GP
ICH9-M (1 of 4) JV50
Sheet
1
Rev
SB
12 of 60
Thursday, January 08, 2009
5
4
3
2
5
4
3
2
1
SB1C SB1B D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3 J5 E1 J6 C4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD# ICH9M-GP-NF
C
3 OF 6 RN72 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# S4_STATE#/GPIO26 AH23 AF19 AE21 AD20 H1 AF3 P1 C16 E16 G17 PM_SLP_S5# 1 C10 S4_STATE#1 G20 M2 B13 R3 D20 D22 R5 R6 B16 F24 B19 F22 C19 C25 A19 F21 D18 A16 ICH_GPIO24 1 C18 SUSPWRACK C11 AC_PRESENT ICH_GPIO9 1 C20 1 100KR2J-1-GP R220 CL_VREF0_ICH 1 R227 453R2F-1-GP
C
2 OF 6 REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# F1 G4 B6 A7 F13 F12 E6 F6 D8 B4 D6 A5 D3 E3 R1 C6 E4 C2 J4 A4 F5 D7 C14 D4 R2 PCI_IRDY# PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# PLT_RST#_R 1 2 R216 0R0402-PAD PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3
15,25,32,33 15,25,32,33
SMB_CLK SMB_DATA
PCI
SMB
G16 A13 SMB_LINK_ALERT# E17 C17 B18 PM_RI# TPAD14-GP TP199 F19
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1 RI# SUS_STAT#/LPCPD# SYS_RESET# PMSYNC#/GPIO0 SMBALERT#/GPIO11
SATA GPIO
SATA0GP SATA1GP ICH_GPIO36 ICH_GPIO37 CLK_ICH14 CLK48_ICH 3 3 34
5 6 7 8
4 3 2 1 SRN10KJ-6-GP
1PM_SUS_STAT# R4 DBRESET# G19 M6 SMB_ALERT# A17 A14 E19 L4 E20 M5 AJ23 D21 A20
Clocks
PM_SUS_CLK
D
PCI_GNT#0 and SPI_CS1# have weak internal Pull up
7
PM_SYNC#
PM_SLP_S3# 32,34,35,39,43,46 PM_SLP_S4# 32,35,39,43,44 TP203 TPAD14-GP TP207 TPAD14-GP PWROK 7,34 PM_DPRSLPVR 7,41
D
SYS GPIO Power MGT
3 3
PM_STPPCI# PM_STPCPU#
STP_PCI# STP_CPU# CLKRUN# WAKE# SERIRQ THRM# VRMPWRGD SST TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 ENERGY_DETECT/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 SPKR MCH_SYNC# TP3 PWM0 PWM1 PWM2 ICH9M-GP-NF
PWROK DPRSLPVR/GPIO16 BATLOW# PWRBTN# LAN_RST# RSMRST# CK_PWRGD CLPWROK SLP_M# CL_CLK0 CL_CLK1
35 PM_CLKRUN# 25,32 PCIE_WAKE# 35 INT_SERIRQ 34 THRM# 34,41 VGATE_PWRGD 3D3V_S0 PLT_RST1# 7,25,31,32,33,35,36,51,52 1 10KR2J-3-GP 10KR2J-3-GP R404 35 35 2 1 C388 2 SC100P50V2JN-3GP 1 DY 2 ICH_TP7 0R2J-2-GP R221 TPAD14-GP TP193 1FP_ID 35 EC_TMR ECSCI#_1 ECSWI#
PM_DPRSLPVR_1 PM_BATLOW#_R PWRBTN#_ICH
R211 2 100R2J-2-GP 1 R212 1 2 DY 100KR2J-1-GP D8 BAS16-1-GP 1 3
PM_PWRBTN#
35,51
RSMRST#_SB
83.00016.B11
2 CLK_PWRGD PWROK 3 3D3V_S0
SB 1202
PCLK_ICH 3
3
SATACLKREQ# TPAD14-GP TP198 TPAD14-GP TP194
MISC GPIO Controller Link
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
Interrupt I/F
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
CL_CLK0 CL_DATA0
7 7
2
R226 3K24R2F-GP 2 RN73 USB_OC#0 USB_OC#1 USB_OC#3 8 7 6 5 1 2 3 4 SRN10KJ-6-GP C409 SCD1U10V2KX-4GP 2 2 1 3D3V_S5
H4 K6 F2 G2
INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
G78
TPAD14-GP TP196 TPAD14-GP TP122
CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# CL_RST1# GPIO24/MEM_LED GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT GPIO9/WOL_EN
71.ICH9M.00U
1
CL_RST#0
7